DesignCon 2002

Figure 15: VerifEye contour BER diagram with 3 ps of RJ introduced into the system with 5 taps of
FFE at the receiver.
VerifEye BER results for the final pre-layout channel (Figure 13) that included the SMP
connector and an additional four 50 mil via stubs are shown in Figure 16. This shows that
additional equalization was required to achieve an acceptable system BER; this required
the inclusion of DFE into the receiver along with FFE. The final design showed 8 taps of
FFE and 3 taps of DFE at the receiver were required to equalize the system channel.
A B
Figure 16: A- VerifEye contour BER plot for Figure 13 yielding BERs up to 1x10
bathtub
-12 . B- VerifEye
BER curve shown up to a BER of 1x10 -12 . Both A and B plots are using 8 taps of FFE and 3
taps of DFE at the receiver.
Post-Layout Analysis
The Allegro CAD design was translated into an Ansoft Neutral File format (.anf) using
Ansoft links. The translated PWB layout was then imported into Ansoft’s SIwave fullwave
package and PWB extractor tool. The package and PWB extractor tool was used to
create a Touchstone S-parameter file that included the exact layout of each lane analyzed.
A differential pair for the 10 Gb/s (5 GHz) lane is shown in Figure 17 for the Blade and
switch cards.