DesignCon 2002

Discrete
Time
1.5
1
0.5
0
-0.5
-1
Input
Output (Equalized)
-1.5
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
Output
Waveform
Feedback
Taps
K
T T
ff1 ff2 ff3 ffn
fbm fb2
fb1
T
SUM
T
T
T
Decision
Forward
Taps
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
20 40 60 80 100 120 140 160
Output
Bits
Figure 9: FFE/DFE Architecture implemented within QuickEye and VerifEye.
The new statistical simulation tools allow the user to determine the number of taps
required for equalizing the channel based on the architecture shown above. The tap
weights may be entered manually or calculated by the software. The input of the
equalizer quantizes the waveform in UI-spaced time slots and passes the voltage
amplitudes through the FFE delays and taps. Currently a zero forcing function has been
implemented to determine the optimum sampling point for the bits along with the tap
weights. At each unit interval (UI) a decision is made between a binary 1 or 0 or (1 and
-1) and that decision is fed back through the feedback delays and taps. The current output
of the equalizer is the sum of both the forward and reverse weighted amplitudes stored in
the UI-spaced taps.
Figure 10: Graphical user interface used for setting up equalization within QuickEye and VerifEye.
Pre-Layout Analysis
Prior to the task of designing and laying out high-speed channels, simulation analysis is
required and performed to determine an acceptable system level performance which is
typically defined by many standards to be a BER = 1x10 -12 at a minimum. Simulation