PV Intern - Cadence

Cadence 2013 校园招聘职位
Cadence(Nasdaq: CDNS)是全球领先的 EDA (Electronic Design Automation) 软件开
发商以及电子设计自动化解决方案提供商.我们的产品涵盖了电子设计的整个流程,包括
系统级设计,功能验证,IC 综合及布局布线,模拟、混合信号及射频 IC 设计,全定制集
成电路设计,IC 物理验证,PCB 设计和硬件仿真建模等。全球知名半导体与电子系统公
司均将 Cadence 软件作为其全球设计的标准。公司网站 www.cadence.com.cn
欢迎软件工程、计算机科学、微电子、集成电路、数学等相关专业的 2013 年及之前毕业
的硕士生和博士生投递 CV 至 job_china@cadence.com,简历命名:姓名-学校-专业-学历-
投递职位名称,对职位有任何疑问,也可发邮件至该信箱,我们 HR 同事会及时给你回复
并尽快安排面试。
R&D(prefer Ph.D)
1.Senior Software Engineer –Placement (Location:SH)
Position Description:
1.The primary responsibility is designing, developing, troubleshooting and debugging software p
rograms on Unix/Linux platforms.
2.Will be involved in placement development for Encounter.
Position Requirements:
1.The candidate should have strong software programming skill with C/C++ and EDA backend kn
owledge.
2.Strong interest and understanding of complex software development in UNIX platformare req
uired.
3.Background on numerical analysis and non linear programming,numerical solver, Optimization
4.(Optional) Familiarity with optimization algorithms, including CG, quasi-Newton, Nesterov, etc.
5.Good verbal and written presentation are must.
6.Minimum master degrees in EE or CS.
2. Senior Software Engineer for Floorplan (Location:SH)
Position Description:
1.The candidate will be a member of the Encounter floorplan team in Shanghai, to work on the
development and maintenance of manual Floorplan project.
2.The responsibilities include the develop of new features and products, and support other
teams in Encounter product lines.
3.The candidate must be comfortable working with existing code as well as developing new
functionality to address new requirements, and be working closely with local/remote team
members, and be also strong technical support to team.
Position Requirements:

1.Candidate must be an expert in software engineering methods and committed to high quality
of development work.
2.The individual must be team-oriented, possess good communication skills, self-motivated,
able to work independently and working with a team from multiple remote sites.
3.Candidate must be able to develop detailed technical specification as well as the ability to
scope efforts required.
4.The candidate must be also smart to capture new EDA technologies, and switch among
different areas successfully.
5.Advanced developing and debugging software in UNIX & LINUX environments, familiar with
gnu c/c++, gdb etc..
6.Strong problem-solving, architecture, algorithmic.
7.Familiar with interpreted language such as TCL is a plus.
8.Knowledge of Digital Physical Design flow such as Floorplan/Placement/Routing/CTS is a plus.
3. Senior Software Engineer for Encounter Hier Solution Team(Location:SH)
Position Description:
1.The candidate will be a member of the Encounter Hier Solution team in Shanghai, to work on
the development and maintenance of Hier Solution project.
2.The responsibilities include development of new features and products, and support other
teams in Encounter product lines.
3.The candidate must be comfortable working with existing code as well as developing new
functionality to address new requirements, and be working closely with local/remote team
members, and be also strong technical support to team.
Position Requirements:
1.Candidate must be an expert in software engineering methods and committed to high quality
of development work.
2.The individual must be team-oriented, possess good communication skills, self-motivated,
able to work independently and working with a team from multiple remote sites.
3.Candidate must be able to develop detailed technical specification as well as the ability to
scope efforts required.
4.The candidate must be also smart to capture new EDA technologies, and switch among
different areas successfully.
5.Advanced developing and debugging software in UNIX & LINUX environments, familiar with
gnu c/c++, gdb etc..
6.Strong problem-solving, architecture, algorithmic.
7.Familiar with interpreted language such as TCL is a plus.
8.Knowledge of Timing analysis is a plus.
4. Senior software engineer (Database development for Encounter platform)
(Location:SH)
Position Description:
1. The candidate will be responsible for the development and maintenance of Database of
Encounter platform in Cadence. The engineer works with engineers in Shanghai and US.
(NOTE: The database is a specific designed one for back-end EDA tools, NOT a general relational
database with SQL)

Position Requirements:
1. Programming skill on Linux/Unix platform is must.
2. Deep understanding on Linux OS
3. Strong C/C++ language coding skill.
4. Having Sound experience in software development projects and a strong background in data
structures, algorithms and program design.
5. Tcl programming skill is a plus.
6. Multiple thread programming experience is a plus.
7. EDA software development experience or IC design knowledge is a plus.
8. Strong desires to learn and explore new technologies and is able to demonstrate good
analysis and problem solving skills
9. Good English communication skill, both oral and written.
5. Senior Software Engineer - Characterization RD (Location: BJ)
Position Description:
The positions are for a developer who will be responsible for designing, implementing, and
maintaining library characterization and validation software for use with standard cells, memory
and macro blocks, and IO cells.
Position Requirements:
1.The candidates should have two or more years of experiences in developing EDA software.
2.Must be proficient in C, C++, TCL, and development in Linux/Unix.
3.Knowledge on semiconductor device is strong plus.
4.Experience with SPICE or SPICE-like circuit simulation is important.
5.Knowledge of Verilog and VHDL is also highly desirable.
6.Have a good understanding of library characterization, IP design, static timing analysis, power
analysis, and signal integrity analysis flows.
7.Minimum Education Required / Minimum Experience Required : MS, EE, CS, Math or Physics 2
8. Preferred Education / Preferred Experience: Ph.D. , EE, CS, Math or Physics 3-5
6. Senior Software Engineer (Location: BJ)
Position Description:
-The position is for analog circuit simulation engineer responsible for designing, implementing
and maintaining device compact models in SPICE-like circuit simulation software for use with
analog, RF and mixed signal circuit simulators. The engineer will be responsible for leading
multiple development efforts through the development process, including writing specifications
based on marketing and product requirements, designing and implementing product
improvements and fixes, and working with a cross-functional team to ensure the software is
tested, integrated and documented. The engineer must be proficient in C/C++ Unix
development, and have a thorough knowledge of device physics, device compact models. The
engineer must have a proven ability to learn from and work with an engineering and crossfunctional
team to deliver innovative products in a production environment.
Position Requirements:
1.Well devices physics, device compact models;
2.Familiar with matrix solver & mathematic calculation;
3.Familiar with Spice, Spectre format & usage;

4.Skilled in C++ programming, familiar with development under Linux/Unix environment;
5.Be familiar with Analog-signal design is a plus;
6.Good English communication skill both verbally and writing;
7.Good problem solving skill and team work spirit;
7. Senior Software Engineer - Cadence Virtuoso Environment (Location: BJ)
Position Description:
The Cadence Virtuoso platform powers all of the latest design innovations in consumer, mobile
and enterprise electronics worldwide. We are looking for an exceptional senior software
engineer to join our team and contribute to the continued growth and success of the company’s
flagship product. In this high-impact career opportunity, you will lead design and development
of cutting-edge features of some of our most exciting new products, with an emphasis on circuit
simulator integration in the Virtuoso ADE/ADE XL environment. You will contribute both
individually and as a technical lead, working with a cross-functional team in Beijing and San Jose
to ensure that our software is developed, tested, and documented with high quality.
Position Requirements:
1.Exceptional C++ programming and familiarity with Linux/Unix development.
2.Experience with GUI frameworks, such as Qt.
3.Strong scripting language skills in one or more of: Python, Perl, Lisp, Tcl.
4.Proficiency with build and version-control systems.
5.Excellent written and oral English communication skills.
Preferred Skills
6.Coursework or work experience in electronic circuit design.
7.Exposure to the Cadence Virtuoso environment or other electronic design platforms.
Education
8.B.S. in engineering, computer science or related field. Graduate degree preferred.
8. Senior Software Engineer, Simulation Integration(Location: BJ)
Position Description:
World’s leading design companies rely on Cadence technologies to deliver the latest design
innovations in consumer, mobile and enterprise electronics. We are looking for exceptional
software engineers to join our team and contribute to the continued growth and success of the
company’s flagship products, such as Virtuoso Spectre and Virtuoso ADE. In this high-impact
career opportunity, you will develop cutting-edge features of some of our most exciting new
products, with an emphasis of scripting language development and GUI integration. You will
work with a cross-functional team in Beijing and San Jose to ensure that our software is
developed, tested, and documented with high quality.
Position Requirements:
1.Strong C++ programming and familiarity with development under Linux/Unix environment
2.Experience with GUI frameworks, such as Qt.
3.Strong scripting language skills in one or more of: Python, Perl, Lisp, Tcl
4.Proficiency with build and version-control systems.
5.Good English communication skill both verbally and writing.
6.Good problem solving skill and team work spirit.

Preferred Skills
1.Experience in the use of parser generators, such as Antlr or Yacc/Lex
2.Exposure to circuit simulators, such as SPICE, HSPICE and Spectre.
3.Coursework or work experience in analog, RF or mixed-signal circuit design
Education
1.B.S. in engineering, computer science or related field.
9. Software engineer for Virtuoso ADE XL (Location: BJ)
Position Description:
Custom digital and analog circuit designers must generate and interpret large amounts of
complex simulation data. Virtuoso ADE XL accelerates design by enabling setup reuse,
parallelizing compute-intensive simulation, and through extensive post-processing and
visualization capabilities. We are seeking a talented software developer to improve simulation
throughput and data visualization.
Position Requirements
1.Demonstrated proficiency in C++ and general software development skills
2.BS in Computer Science or Computer Engineering required.
3.XML, SQL, GUI (Qt specifically), and distributed processing experience a plus.
4.Experience with Cadence Virtuoso or analog circuit design is a plus.
SOC R&D
1.Design Engineer – Analog circuit Engineer (Location: SH)
Position Description:
1.In charge of analog and mixed-signal circuit design.
2.Hands-on experience conducting design analysis and recommending appropriate solutions
3.Architecture study, modeling and verification.
4.Specific duties include:
- Analog circuit simulation, layout guidance, test chip measurement and debug
-Excellent analytical and problem-solving skills. Quick learner-able to learn and apply technical
and complex topics.
-Excellent communication skills and the uncanny ability in a cooperative team environment are
required.
5.Self-motivated, result-oriented, can take ownership and follow-through on tasks.
Position Requirements:
Essential Qualifications:
1.Master or PHD degree, major in Micro-Electronics, Electronic Engineering or equivalent
2.Ability to work effectively alone or as well as in a team.
3.Essential that the individual demonstrates strong communication, verbal and written
4.Requires good communication skills in English.
Desirable Qualifications:

1.Knowledge of one of key Analog IC design areas and their architectures/applications:
Data Converters; PLL's; Oscillators; Low Noise Design; RF IC building blocks
2.Solid understanding of IC design technology and process/methodology in IC design solutions
3.Familiar with Cadence analog and mixed-signal EDA tools is a plus
2.Design Engineer – Algorithm & Architecture Engineer (Location: SH)
Position Description:
1.In charge of SoC Spec definition, whole chip or complex IP architecture design.
2.Algorithm study, modeling and verification.
Specific duties include:
- Owning the IC micro-architecture, package and test platform development
- Proficiency in logic design, simulation
3.Excellent analytical and problem-solving skills. Quick learner-able to learn and apply technical
and complex topics.
4.Excellent communication skills and the uncanny ability in a cooperative team environment are
required.
5.Self-motivated, result-oriented, can take ownership and follow-through on tasks.
Position Requirements:
Essential Qualifications:
1.Master or PHD degree
2.Major in Micro-Electronics, Electronic Engineering, Computer Science, Information Technology,
3.Mathematics, Physical or equivalent
4.Ability to work effectively alone or as well as in a team.
5.Essential that the individual demonstrates strong communication, verbal and written
6.Requires good communication skills in English.
Desirable Qualifications:
1.Solid Hardware, Software and Embedded System knowledge
2.Knowing ARM-based SOC design architecture, Knowing AMBA bus. Be familiar with CPU/DSP
architecture.
3.Knowledge of USB2.0/3.0, PCI/PCIE, HDMI, Display Port
3.Design Engineer – Digital Backend Engineer (Location: SH or BJ)
Position Description:
1.In charge of IP and SoC physical implementation, Place & Routing for IP, ASIC, Mixed-signal
Chip and SOC chips.
2.HDL language Knowledge, like verilog or vhdl is necessary.
3.Perl/tcl/csh, UNIX, Linux experience are plus.
4.Excellent analytical and problem-solving skills. Quick learner-able to learn and apply technical
and complex topics.
5.Excellent communication skills and the uncanny ability in a cooperative team environment are
required.
6.Self-motivated, result-oriented, can take ownership and follow-through on tasks.

Position Requirements:
Essential Qualifications:
1.Master degree or above
2.Major in Micro-electronics, Electronic Engineering, Computer Science, Information Technology
or equivalent
3.Ability to work effectively alone or as well as in a team.
4.Essential that the individual demonstrates strong communication, verbal and written
5.Requires good communication skills in English.
Desirable Qualifications:
1.Tapeout experience or EDA tools experience
4.Design Engineer – Digital Frontend Engineer (Location: SH or BJ)
Position Description:
1.In charge of IP and SOC logic design, verification and Implementation.
2.Daily duties include: Digital IC micro-architecture, RTL coding, Logic Synthesis, Function
Verification, DFT, and Static Timing Analysis.
3.HDL language Knowledge, like verilog or vhdl is necessary.
4.C/C++/perl/tcl/csh, UNIX, Linux experience are plus.
5.Excellent analytical and problem-solving skills. Quick learner-able to learn and apply technical
and complex topics.
6.Excellent communication skills and the uncanny ability in a cooperative team environment are
required.
7.Self-motivated, result-oriented, can take ownership and follow-through on tasks.
Position Requirements:
Essential Qualifications:
1.Master degree or above
2.Major in Micro-electronics, Electronic Engineering, Computer Science, Information Technology
3.or equivalent
4.Ability to work effectively alone or as well as in a team.
5.Essential that the individual demonstrates strong communication, verbal and written
6.Requires good communication skills in English.
Desirable Qualifications:
1.Good at any following skill sets: ASIC design, FPGA design, Computer architecture, SOC design
2.based on ARM/MIPS.
3.Experience of USB2.0/3.0, PCIE,HDMI, Display Port
PE
1. Senior/Principal Product Engineer – Characterization (Location: BJ)
Position Description:
1.The Altos Product Engineer (PE) works with key customers to understand their library
characterization challenges, maps

2.Customer needs into product requirements, and collaborate with the R&D and PV
organization to ensure that the product
3. Implementation addresses the customers real needs.
4.The Altos PE plays a pivotal role in defining and deploying Cadence’s library characterization
products and solutions at key customersthat enables them to do characterization at a very high
performance & efficiency.
5.This position requires problem discovery and analysis at customer site, assessment of possible
solutions, collaborating with RD and customer to develop and test the solution, and managing
it’s deployment at the customer site.
Position Requirements:
1.The candidate should possess minimum a Bachelors technical degree and 3-5 years of industry
experience
2.Minimum 3 years hands-on, expertise on library characterization, IP design, static timing
analysis, power analysis, and signal integrity analysis flows.
3.Hands on Design experience using Verilog, VHDL
4.Experience with SPICE or SPICE-like circuit simulation is strong plus
5. Knowledge on semiconductor device is strong plus.
6.Knowledge on competitor characterization flow and tools is a plus
7.Highly technical & hands on engineer with an ability to partner with key customers and
provide expert support to field application engineers.
8.The candidate must be able to drive R&D and Application engineers and have passion to make
customers successful.
9.He/She must be willing to travel worldwide in order to work closely with customers in any part
of the world.
10.Passionate about adopting and promoting new technologies and making customers
successful.
11.Successful in building and delivering training content on rolling out new
products/methodologies
12.Very good communication skills and a strong desire for working in a global environment with
customers Developers, marketing and sales.
13.English fluency is a must, Korean speaking language is a plus
PV Intern
1. PV Intern for STA (Static Timing Analysis) (Location: SH)
Position Description:
This intern will work in Encounter Common Timing Engine Product Validation team. The
responsibilities include:
1. Assist in Cadence STA product and engine's developement and validation
2. validate comprehensive STA testcases for Encounter Digital Impelementation System and
Encoutner Tming System
3. Develope and maintain system and infrastructure for high productivity and efficiency with
various scripting and system developement techniques

Position Requirements:
1.MS or excellent undergraduate
2.Digital IC design knowledge is necessary, statistic timing analysis knowledge is a strong plus
3.Unix System knowledge, vi/TCL/TK/CSH/Perl will be plus.
4.Good communication in English and Chinese, good confidence and self-motivation.
5.Commitment to work as intern for at least 6 months
2. PV Intern for GPS (Global Physical Synthesis) (Location: SH)
Position description:
1.This intern will work in ICD (P&R) Product Validation team. The responsibilities include:
2.Assist in Cadence GPS product and engine's development and validation
3.Validate comprehensive GPS test cases for Encounter Digital Implementation System
4.Develop and maintain system and infrastructure for high productivity and efficiency with
various scripting and system development techniques
Position Requirements:
1.MS or excellent undergraduate, Strong perl programming experience.
2.IC design knowledge is necessary, statistic timing analysis knowledge is a strong plus
3.Unix System knowledge, vi/TCL/TK/CSH will be plus.
4.Good communication in English and Chinese, good confidence and good self-motivation.