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Stencil codes 199
Implementation Issues
Many simulation codes may be formulated naturally as stencil codes. Since computing time and memory
consumption grow linearly wth the number of array elements, parallel implementations of stencil codes are of
paramount importance to research. [6] This is challenging since the computations are tightly coupled (because of the
cell updates depending on neighboring cells) and most stencil codes are memory bound (i.e. the ratio of memory
accesses and calculations is high). [7] Virtually all current parallel architectures have been explored for executing
stencil codes efficiently [8] ; at the moment GPGPUs have proven to be most efficient. [9]
Libraries
Due to both, the importance of stencil codes to computer simulations and their high computational requirements,
there are a number of efforts which aim at creating reusable libraries to support scientists in implementing new
stencil codes. The libraries are mostly concerned with the parallelization, but may also tackle other challenges, such
as IO, steering and checkpointing. They may be classified by their API.
Patch-Based Libraries
This is a traditional design. The library manages a set of n-dimensional scalar arrays, which the user code may access
to perform updates. The library handles the synchronization of the boundaries (dubbed ghost zone or halo). The
advantage of this interface is that the user code may loop over the arrays, which makes it easy to integrate legacy
codes [10] . The disadvantage is that the library can not handle cache blocking (as this has to be done within the
loops [11] ) or wrapping of the code for accelerators (e.g. via CUDA or OpenCL). Notable implementations include
Cactus [12] , a physics problem solving environment, and waLBerla [13] .
Cell-Based Libraries
These libraries move the interface to updating single simulation cells: only the current cell and its neighbors are
exposed to the user code, e.g. via getter/setter methods. The advantage of this approach is that the library can control
tightly which cells are updated in which order, which is useful not only to implement cache blocking, [9] but also to
run the same code on multi-cores and GPUs. [14] This approach requires the user to recompile his source code
together with the library. Otherwise a function call for every cell update would be required, which would seriously
impair performance. This is only feasible with techniques such as class templates or metaprogramming, which is also
the reason why this design is only found in newer libraries. Examples are Physis [15] and LibGeoDecomp [16] .
References
[1] Roth, Gerald et al. (1997) Proceedings of SC'97: High Performance Networking and Computing. Compiling Stencils in High Performance
Fortran. (http:/ / citeseer. ist. psu. edu/ viewdoc/ summary?doi=10. 1. 1. 53. 1505)
[2] Sloot, Peter M.A. et al. (May 28, 2002) Computational Science - ICCS 2002: International Conference, Amsterdam, The Netherlands, April
21-24, 2002. Proceedings, Part I. (http:/ / books. google. com/ books?id=qVcLw1UAFUsC& pg=PA843& dq=stencil+ array&
sig=g3gYXncOThX56TUBfHE7hnlSxJg#PPA843,M1) Page 843. Publisher: Springer. ISBN 3540435913.
[3] Fey, Dietmar et al. (2010) Grid-Computing: Eine Basistechnologie für Computational Science (http:/ / books. google. com/
books?id=RJRZJHVyQ4EC& pg=PA51& dq=fey+ grid& hl=de& ei=uGk8TtDAAo_zsgbEoZGpBQ& sa=X& oi=book_result& ct=result&
resnum=1& ved=0CCoQ6AEwAA#v=onepage& q& f=true).
Page 439. Publisher: Springer. ISBN 3540797467
[4] Yang, Laurence T.; Guo, Minyi. (August 12, 2005) High-Performance Computing : Paradigm and Infrastructure. (http:/ / books. google.
com/ books?id=qA4DbnFB2XcC& pg=PA221& dq=Stencil+ codes& as_brr=3& sig=H8wdKyABXT5P7kUh4lQGZ9C5zDk) Page 221.
Publisher: Wiley-Interscience. ISBN 047165471X
[5] Micikevicius, Paulius et al. (2009) 3D finite difference computation on GPUs using CUDA (http:/ / portal. acm. org/ citation.
cfm?id=1513905) Proceedings of 2nd Workshop on General Purpose Processing on Graphics Processing Units ISBN: 978-1-60558-517-8
[6] Datta, Kaushik (2009) Auto-tuning Stencil Codes for Cache-Based Multicore Platforms (http:/ / www. cs. berkeley. edu/ ~kdatta/ pubs/
EECS-2009-177. pdf), Ph.D. Thesis