System-on-Chip Design Flow

26.03.2003 

<strong>System</strong>-on <strong>System</strong> on-Chip Chip Design Flow 

Prof. Jouni Tomberg 

Tampere University of Technology 

Institute of Digital and Computer <strong>System</strong>s 

jouni.tomberg@tut.fi 

Jouni Tomberg / TUT 1

SoC - How and with whom? 

• SoC Players 

• Markets 

• Flows 

• Bottlenecks 

• IP and platform metrics 

26.03.2003 Jouni Tomberg / TUT 2

Definitions 

• Frontend design 

– Design from system level to cell library level netlist 

• Backend design 

– Design from netlist level to Placed & Routed production 

ready database 

• ASIC flow 

– Netlist handoff to ASIC vendor (takes care of the backend) 

• COT (Customer Owned Tooling) flow 

– P&R database handoff to foundry (takes care of the 

production) 


SoC Players 

Customer 

(end user) 

IC's 

IP provider 

Requirement specification 

Production 

requirements 

ASIC vendor 

or 

Foundry 

Standard 

function 

blocks 

Netlist or 

P&R 

database 

Design 

Service 

provider 

Physical 

backannotation 


Need for <strong>System</strong> Level Design 


Market Segments 


Design Productivity Gap 


Typical Design Flow Tasks 

Implement 

Verify 

Models/IP 

<strong>System</strong>/ 

Algorithm 

Define <strong>System</strong> 

Create/select 

Algorithms 

Filter design 

Protocol 

Development 

Verify system 

function 

Verify Algorithm 

performance 

<strong>System</strong> Simulation 

HW/SW Coverification 

<strong>System</strong> model 

components 

<strong>System</strong> environments 

Reference Kits 

Behavioral 

Create behavioral 

description 

Code generation 

Wordlength optimizatiuon 

Architectural Tradeoffs 

Partitioning 

Verify behavioral 

description (function 

and performance) 

Simulation 

Testbench Generation 

HW/SW Coverifiication 

Behavioral models 

RAM Models 

Part models 

Bus Models 

Cores 

26.03.2003 Jouni Tomberg / TUT 8 

RTL 

Create RTL 


Behavioral Synthesis 

Code generation 

Design Planning 

Verify RTL 


(function and 

performance) 


Power Analysis 

RTL quality analysis 

Emulation 

RTL models 

RAM models 

Part models 

Bus Models 

Cores (functional & 

timing Models) 

Gate-level 

Create Netlist 

Optimize Netlist 

Logic Synthesis 

Datapath Synthesis 

Test Synthesis 

Power Optimization 

Retiming 

Verify Netlist 

(function and 

performance) 


Equivalence Checking 

Static Timing Analysis 

Power Analysis 

Test Analysis/ATPG 

Gate models 

Bus Models 

Synthesis/simulation 

libraries 

Transistor/ 

Physical 

Create physical 

representation 

Place & Route 

Clock-tree synthesis 

Power Routing 

Transistor Optimization 

Verify physical 

design 

DRC, LVS 

Power analysis 

Rail analysis 

Static Timing analysis 

Parasitic Extraction 

Physical/transistor 

models 

Std Cell libraries 

Gate Array libraries

Design Flows 

Design Flows 

Source: T. Moxon / EEDesign, 2.1.2002 


ASIC design flow interfaces 

DESIGN TEAM CUSTOMER ASIC VENDOR 

Requirement spec 

Data sheet for acceptance 

Verification for acceptance 

(modeler/testbench/simul.results) 

Technical info for quotation 

Library & tools 

Netlist, test vectors, arch.plan 

Backannotation from P&R 

Acceptance for prototype production (sign off) 

ASIC quotation 

Prototype ASICs (/risk production) 

Prototype acceptance 

Mass production ASICs 


Importance of Specification 


Design Bottlenecks * Source EETIMES EDA 2000 Survey 

Simulation/Design Verification 51% 

Design Creation 

Place & Route 

Post Layout Optimization 

Parasitic Extraction 

<strong>System</strong> or <strong>System</strong>-on-Chip 

Layout Versus Schematic(LVS) 

Design Rule Check (DRC) 

Static Timing Analysis 

Synthesis 

Delay Calculation 

26.03.2003 Jouni Tomberg / TUT 12 

17% 

17% 

17% 

16% 

15% 

13% 

26% 

32% 

32% 

Base = 545 

0% 10% 20% 30% 40% 50% 60% 

50 -70 % of project effort devoted to design verification!

Verification Importance 


Project Scheduling 

• External constraints 

– Targeted market entry 

– ASIC vendor 

• Layout generation (P&R) 

• Mask producing 

• Prototype processing 

• Prototype acceptance 

• Volume production starting delay 

• Design constraints 

– Design team experience 

– Design tools / flows, vendor libraries, IP provider quality 

– <strong>System</strong> specification iterations 

– Design complexity 

– Verification complexity 

– Production test complexity 


Differencies between SoC and SoPC 

design flows 

• SoPC is a FPGA technology based user programmable 

solution 

– P&R and programming done by the user (vs. backend flow in 

SoC) 

• No delay on prototype production 

• No delay on mass production start 

• No NRE (production start) costs 

– Production tests done by the IC vendor 

• Design resource and time savings in the design flow 

– Quick and cheap modifications 

• On the other hand certain limitations on performance, 

integration capacity and mass production costs exists 

compared to SoC 


Platform Based Design 

• A platform should consist of a basic set of 

integrated technologies that defines how the 

system should function. 

• Design platform / Verification platform 

• Generic platform 

– CPU, memory and standard peripheral fucntions 

• Application specific platform 

– Generic platform plus pre-integrated pre integrated IP blocks for 

the given application 


Platform drivers 

Source: B. Altizer, L. Cooke, and G. Martin / EEDesign 7.11.2002 


Platform Advantages 

• Reduce integration risk by insuring that all IP works 

together 

• Reduce licensing and contractual negotiation time 

per project 

• Reduce cost by allowing efficient reuse in multiple 

designs 

• It is estimated that in the near future each SoC 

design will consist of 10 to 15 different IP blocks 

from 6 to 8 IP vendors 

– Suppose 6 to 8 weeks per IP vendor for evaluation, 

negotiation and integration of IP into the system 

=> with 8 different IP vendors this means 64 weeks of 

”hidden” cost 


IP Market Dynamics 

• Design dynamics (Dataquest 2002) 

– 30% of a designs are composed of reused circuitry 

– 12% of reused circuit is from outside sources 

=> 3.6% of circuitry is from third parties 

• Contractual and legal issues 

– Legal issues remain a huge bottleneck in the IP purchase process 

• rights, responsibility, guarantee, business model 

– VCX trying to address this bottleneck (with standard Ts &Cs) 

• Evaluation of IP 

– Deciding if a core is viable is biggest technical challenge in IP IP 

acquisition 

process. 

– Opportunities in IP evaluation services 

• Perceived instability of vendors.. 

– Most IP vendors are small and vulnerable 

– Partnerships and alliance can help to resolve perceived volatility volatility 

• Software replacing hardware 

– Proliferation of processors in ICs 

– Resulting in more functions being implemented in software 

– SW/HW co-design! co design! 


IP Market Metrics 

46%CAGR 

75% License Revenue 25% Royalty Revenue 


Conclusions 

• The main players in the SoC design flow are Design 

team, IP provider, IC vendor (or Backend team + 

Foundry) 

• Efficient SoC design flow is based on IP reuse and 

platform based design 

• The major bottlenecks are in the test and verification 

area 

• The system level (specification, HW/SW co-design) co design) 

and layout level links to RTL design play also an 

important role in a fluent design flow

System-on-Chip Design Flow

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