3U CompactPCI®/Express Core™ 2 Duo SBC - The Simon Group

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PowerPC and Nios-based 16 MEN 3U CompactPCI and CompactPCI Express F12N – 3U CompactPCI ® MPC5200B SBC ■ -bit/ -MHz cPCI system slot, HP ■ MPC 00B / 8 MHz ■ FPGA 18,7 LEs (approx. ,000 gates) ■ Up to 6 MB on-board DDR SDRAM ■ Up to 8 MB boot Flash, NAND Flash ■ MB SRAM, 16 MB graphics memory ■ Dual Fast Ethernet, COM, USB (front) ■ Dual CAN bus controller ■ FPGA for user-defined I/O functions ■ MENMON BIOS for PowerPC ® cards ■ - 0 to +8 °C with qualified components CPU ■ PowerPC ® ■ MPC5200B ■ Up to 400MHz Memory ■ 2x16KB L1 data and instruction cache integrated in MPC5200 ■ Up to 256MB SDRAM system memory ■ Soldered ■ DDR ■ 64MHz memory bus frequency ■ Up to 1GB soldered NAND Flash (and more), FPGA-controlled ■ 16MB additional SDRAM, FPGA-controlled, e.g. for video data and NAND Flash firmware ■ Up to 8MB boot Flash ■ 2MB GoldCap-backed SRAM, or: 128KB non-volatile FRAM ■ Serial EEPROM 8kbits for factory settings PowerPC® MPC5200B Multifunction external bus Boot Flash SRAM/ FRAM SDRAM Main EEPROM RTC Watchdog Ethernet 10/100Base-T RS232 COM1 CAN bus SDRAM Additional PCI-104 P1 FPGA F F USB 1.1 F NAND Flash B CAN bus B PCI-to-PCI Bridge I/O Mass Storage ■ Parallel IDE (PATA) ■ One IDE port via 44-pin on-board connector ■ FPGA-controlled ■ PIO mode 0 support ■ Up to 1GB soldered ATA NAND Flash (and more), FPGA-controlled I/O ■ USB ■ One USB 1.1 port ■ Series A connector at front panel ■ OHCI implementation ■ Data rates up to 12Mbits/s ■ Ethernet ■ Two 10/100Base-T Ethernet channels ■ One channel FPGA-controlled ■ Two RJ45 or one D-Sub conn. at front panel ■ One RS232 UART (COM1) ■ RJ45 or D-Sub connector at front panel F Front panel B On-board SA SA Ethernet 10/100Base-T CompactPCI® J1/J2 I/O Connector P2 Option: Busless F F IDE GPIO COM10 F B B B SA F ■ Data rates up to 115.2kbits/s ■ 512-byte transmit/receive buffer ■ Handshake lines: CTS, RTS ■ One UART (COM10) ■ Accessible via I/O connector ■ Physical interface at front panel using SA-Adapter via 10-pin ribbon cable on I/O connector ■ RS232..RS485, isolated or not: for free use in system (e. g. cable to front) ■ Data rates up to 115.2kbits/s ■ 16-byte transmit/receive buffer ■ Handshake lines: CTS, RTS; DCD, DSR, DTR; RI ■ CAN bus ■ Two CAN bus channels ■ 2.0 A/B CAN protocol ■ Data rates up to 1 Mbit/s ■ Connection via on-board connectors ■ External transceivers using SA-Adapters ■ GPIO ■ 36 GPIO lines; FPGA-controlled ■ Connection via on-board I/O connector ■ Further I/O depending on FPGA configuration Front Connections (Standard) ■ One USB 1.1 (Series A) ■ Two Ethernet (RJ45) ■ One RS232 UART (RJ45) FPGA ■ Standard factory FPGA configuration: ■ Main bus interface ■ 16Z070_IDEDISK - IDE contr. for NAND Flash ■ 16Z043_SDRAM - Additional SDRAM controller (16MB) ■ 16Z023_IDENHS - IDE controller (PIO mode 0; non-hot-swap) ■ 16Z087_ETH - Ethernet contr. (10/100Base-T) ■ 16Z025_UART - UART contr. (controls COM10) ■ 16Z034_GPIO - GPIO controller (40 lines, 5 IP cores) ■ The FPGA offers the possibility to add customized I/O functionality. See FPGA. Miscellaneous ■ Real-time clock with GoldCap backup ■ Power supervision and watchdog ■ Reset button, GPIO-controlled ■ Three user LEDs, GPIO-controlled; 1 FPGA power status LED CompactPCI ® Bus ■ Compliance with CompactPCI ® Core Specification PICMG 2.0 R3.0 ■ System slot ■ 32-bit/32-MHz PCI-to-PCI bridge ■ V(I/O): +3.3V or +5V (Universal Board) PXI ■ Four trigger lines compliant with PXI Specification R1.0
F206N – 3U CompactPCI ® Nios ® II Slave Board ■ -bit/ -MHz CompactPCI ® ■ Peripheral slot function ■ FPGA 1 ,000 LEs (approx. 1 ,000 gates) ■ Nios ® II soft processor ■ MB SDRAM, MB Flash ■ Flexible FPGA-Flash structure ■ Open platform FPGA development package ■ Support of Wishbone and Avalon ® bus ■ - 0 to +8 °C with qualified components CPU ■ Nios ® II soft processor, 33MHz Memory ■ 512 bytes instruction cache and 512 bytes data cache integrated in Nios ® II ■ 32MB SDRAM system memory ■ Soldered ■ 133MHz memory bus frequency ■ 2MB boot Flash I/O ■ One RS232 UART (COM10) ■ D-Sub connector at front panel ■ Data rates up to 115kbits/s ■ 60-byte transmit/receive buffer ■ Handshake lines: full support ■ For debugging ■ Three 10-pin connectors ■ For FPGA-controlled functions ■ For use of SA-Adapters ■ One receptacle for direct SA-Adapter connection at the front ■ Two receptacles for direct connection of long SA-Adapters at the front ■ Two optional plugs for on-board connection via ribbon cable ■ Different physical layers through SA-Adapters : RS232, RS422, RS485, TTY, Ethernet, CAN bus, binary I/O, audio, PS/2 ■ One optional 40-pin plug connector ■ For FPGA-controlled functions ■ For use of SA-Adapters ■ For on-board connection via ribbon cable ■ Different physical layers through SA- Adapters : RS232, RS422, RS485, TTY, Ethernet, CAN bus, binary I/O, audio, PS/2 FPGA ■ Standard factory FPGA configuration: ■ Nios ® II soft processor ■ 16Z014_PCI - PCI to Wishbone interface ■ 16Z052_GIRQ - Global Interrupt Contr. (Nios ® ) ■ 16Z052_GIRQ - Global Interrupt Contr. (CPU) ■ 16Z069_RST - Reset Controller ■ 16Z043_SDRAM - SDRAM controller (32MB) ■ 16Z045_FLASH - Flash interface ■ 16Z025_UART - UART contr. (contr. COM10) ■ The FPGA offers the possibility to add customized I/O functionality. See website. Miscellaneous ■ Four user LEDs, FPGA-controlled ■ Local PCI Bus ■ 32-bit/33-MHz, 3.3V V(I/O) ■ Compliant with PCI Specification 2.2 CompactPCI ® Bus ■ Compliance with CompactPCI ® Core Specification PICMG 2.0 R3.0 ■ Peripheral slot ■ 32-bit/33-MHz PCI ■ V(I/O): +3.3V ■ Only one slot required on 3U cPCI ® backplane ■ More supplementary CompactPCI ® slots required depending on SA-Adapters Electrical Specifications ■ Supply voltage/power consumption: ■ +5V (-3%/+5%), current depends only on mounted SA-Adapters ■ +3.3V (-3%/+5%), 500mA typ. ■ MTBF: 308,000h @ 40°C (derived from MIL-HDBK-217F) FPGA F Front Panel Nios® II GPIO for LEDs IP Core IP Core IP Core Avalon® Bus SA- Adapter Wishbone to Avalon® Bridge Avalon® to Wishbone Bridge Wishbone Bus Optional 40-pin plug (can be assembled on request) SA- Adapter MEN 3U CompactPCI and CompactPCI Express SA- Adapter PCI Slave Flash Interface SDRAM Interface B IP Core UART COM10 IP Core SA- Adapter Compact PCI J1 2 MB boot Flash 32MB SDRAM 10-pin receptacle B 10-pin receptacle B B B B On Board SA- Adapter SA- Adapter SA- Adapter SA- Adapter Optional 10-pin plugs (can be assembled on request) F F PowerPC and Nios-based 17
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Page 3 and 4: Contents 4 Intel ® -based 3U Compa
Page 5 and 6: F18 - 3U CompactPCI ® /Express Cor
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Page 11 and 12: F603 - 3U CompactPCI ® Side Card U
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Page 23 and 24: F206 - 3U CompactPCI ® Octal UART
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Page 27 and 28: F205/F204 - 3U CompactPCI ® /PXI
Page 29 and 30: Individual Solutions 4U 84HP Compac
Page 31 and 32: Standard CompactPCI ® Desktop - 3
Page 35 and 36: CompactPCI ® Express Rack 0701-004

3U CompactPCI®/Express Core™ 2 Duo SBC - The Simon Group

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