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COMPACTPCI
Data transmission with CompactPCI
Serial enables new applications
By Martin Traut, Schroff/Pentair
CompactPCI Serial
(PICMG CompactPCI-S.0) is
the successor to CompactPCI.
This standalone specification
is based on pure serial
architecture and offers data
transmission speeds up to
32 GB/s. The application
bandwidth is therefore
even greater than
with CompactPCI.
n To avoid presenting a sharp edge to CompactPCI,
a sub-specification to the CompactPCI
base specification, CompactPCI PlusIO
(PICMG 2.30), was developed. This allows a
soft migration from CompactPCI. CompactPCI
PlusIO defines a unified pin-out on the P2
connector of the 32-bit CompactPCI system
slot on which the four new serial buses, PCIe,
GbE, SATA and USB are defined. It is thus
possible to create hybrid CompactPCI/CompactPCI
Serial systems. The CPU addresses
the parallel CompactPCI slots in the system
on the P1 connector, while the P2 area is connected
to the fast CompactPCI Serial slots. As
a result the transfer rate is increased above
that of the parallel bus by a factor of 300. Instead
of the roughly 150 connections of CompactPCI,
with CompactPCI Serial there are
more than 360, of which 340 are high-speed
connections. System components such as slow
I/O boards can remain on CompactPCI. As a
result, only special boards that require one of
the new protocols or more bandwidth need to
be converted to the new technology.
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Schroff has developed backplanes and complete
systems for both specifications. The backplanes
available include, for example, 8-slot hybrid
backplanes with three CompactPCI peripheral
slots, one CompactPCI PlusIO system slot and
four CompactPCI Serial peripheral slots. These
backplanes are available in two versions - with
and without rear I/O on the CompactPCI
Serial slots.
They represent the maximum configuration
for hybrid systems and can thus be used in all
possible applications. Other backplanes with
fewer slots are currently in preparation, such
as a 5-slot version. Likewise for CompactPCI
Serial, Schroff has also first developed backplanes
for the maximum configuration with
nine slots, one system slot and eight peripheral
slots. This again allows the widest range of applications
to be accommodated. There are
even different backplane versions in which
PCIe, USB and SATA are provided in single
star in all cases. One version also features a
single star for gigabit Ethernet, while the other
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June 2011 14
Figure 1. Hybrid
CompactPCI/CompactPCI
Serial system
version has full-mesh wiring in the GbE area
and is thus best suited for building processor
farms or clusters. Both of these versions are
available with or without rear I/O.
CompactPCI Serial backplanes have twice the
number of signals and less space between
connectors, and thus offer a high performance
density. The signal lines are thus necessarily
very close to one another, and excessive
crosstalk can occur. Crosstalk, like reflections,
contributes to noise and jitter. The skill of the
designer is in reaching the optimum compromise
between performance density and the
number of layers, while generally reducing
impedance discontinuities. 3D modelling of
the circuit board elements and simulation of
the complete transmission channel to determine
the bit error rate is a very helpful method
of designing boards and backplanes at the
first draft with a sufficiently low bit-error
rate. The mechanical construction of CompactPCI
Serial systems matches that of
Schroff’s 8-slot 3+1 CompactPCI system with