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ATCA, MTCA & AMC Figure 3. Example of a large industrial control system in customized ATCA form factor Figure 3 shows an industrial control system that consists of custom ATCA I/O blades. The I/O blades are grouped into clusters with each cluster serving one particular set of I/O devices such as sensors, scanners, or cameras. The blades have an AMC bay supporting one or more AMC CPUs per cluster. Note that the CPU AMC used could be any one of many standard off-the-shelf processor AMCs, such as the GE Intelligent Platform ASLP11. This CPU enumerates the PCIe tree of a particular I/O cluster. Considering a 14-slot ATCA chassis, up to four such I/O clusters can be interconnected using one I/O blade as a main PCIe switch. All PCIe connections are via a customized Zone 1 and Zone 2 backplane. If more compute power is needed, a standard off-the- shelf ATCA SBC, such as the GE A10200 dual Westmere blade, can be added to the system. Most SBCs on the market route PCIe to the Zone 3 connector for connectivity to a RTM; this connection can be reused by creating a custom Zone 3 backplane. Note that in figure 3, only one custom ATCA blade design is needed. To further cost-optimize a blade, implementers can take advantage of the fact that there are pin-compatible PCIe switches supporting different numbers of ports. Once again, this implementation takes advantage of PCIe features, such as non-transparent ports and high performance. A gen 3 x8 PCIe port can support up to 64 Gbits/s throughput, which excluding overheads still delivers approximately 54 Gbits/s effective data throughput with only a couple of hundred nanoseconds latency and very low CPU utilization. Portable systems, be it a medical scanner (ultrasound, etc.) or industrial tester, require a compact and flexible form factor. Such systems, being portable in nature, also depend on shock and vibration immunity. Typically, a portable scanner consists of two distinct elements: an acquisition subsystem consisting of sensors or cameras, their interface card, and a processing element, and a display subsystem consisting of a CPU and high-performance graphic cards and displays. Both subsystems need to be in-
terconnected via a high-performance bus. An example of this type of implementation is shown in figure 4. This implementation is based on the MicroTCA form factor and uses standard off-the-shelf components. Here the MCH functions as the main switching resource, hosting both PCIe and Gigabit Ethernet switches. Some MCHs available today implement the PCIe switch via two interconnected but distinct silicon devices. This architecture opens up a unique opportunity to partition the MTCA system into two subsystems, both interconnected by a high-performance PCIe interface via a non-transparent port. Following this concept, the image acquisition subsystem consists of an FPGA that provides the interface to sensors or cameras. A dedicated CPU controls the FPGA board. This CPU can be easily scaled to be multiple CPUs forming a high-performance computing cluster. If a Windows operating system is used, the Network Direct Driver will enable easy creation of such clusters. Yet another CPU forms a user interface and display subsystem that controls one, or optionally two, high-performance VGA cards, for instance GE Telum 3001. Note that two VGA ATCA, MTCA & AMC Figure 4. Example of a portable medical or industrial tester implementation using the MTCA form factor www.embedded-control-europe.com/bas-magazine www .embedded-control-europe.com/bas-magazine cards can be teamed up to share graphical processing resources using, for example, a Cross- FireX feature. The two subsystems are interconnected via the high-performance PCIe interface enabling fast and efficient image transfer from the acquisition subsystem to the display subsystem. An advantage of this type of system is that it is built completely using off-the-shelf components, with no customization. Although most AMCs today are still gen 1 PCIe, gen 2 and gen 3 devices are entering the market. The PCIe interconnect has come a long way since it was first introduced to connect a CPU to an I/O device. Today, with gen 3 devices entering the market, it supports staggering data throughput with extremely low latency and CPU overhead. Being the native built-in interface in most processors, PCIe presents the most efficient and lowest cost connectivity option. Although PCIe has limitations and does not fit all applications, new functionality dramatically increases the range of possibilities. Features, such as a non-transparent port, and software drivers like the Windows Network Direct driver, enable new topologies and usage models, simplifying application software development. n FREE SUBSCRIPTION to boards & solutions the european embedded computing magazine 13 June 2011
Page 1: COVER STORY Multi-core processors a
Page 4: CONTENTS Viewpoint 3 ATCA, MTCA & A
Page 7 and 8: Fi Figure 11: Si Simplified plif if
Page 9 and 10: n ELMA: 12-slot xTCA system with re
Page 11: Figure 1. CPU-to-CPU connectivity u
Page 15 and 16: an integrated 1U fan drawer. Fitted
Page 18 and 19: COMPACTPCI A straightforward x86 em
Page 20 and 21: PCI EXPRESS Using PCI Express as hi
Page 22 and 23: PCI EXPRESS Figure Fig ig igu gure
Page 24 and 25: EMBEDDED COMPUTING Figure Fig ig ig
Page 26 and 27: EMBEDDED COMPUTING A new processor
Page 28 and 29: EMBEDDED COMPUTING hundreds of othe
Page 30 and 31: PRODUCT NEWS n VIA: Mini-ITX board
Page 32 and 33: PRODUCT NEWS n NEXCOM: rugged trans
Page 34: PRODUCT NEWS n DDC: avionics 1553/4

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