C Thermo

5
5
L0D[0:3]
L4D[0:3]
D[0:15]
A[0:7]
4
4
3
D D
C C
SPI_CLK+
SPI_CLK-
SPI_MOSI+
SPI_MOSI-
/SPI_SEL+
/SPI_SEL-
B B
SPI_MISO+
SPI_MISO-
5V_RAW
5V_RAW_RTN
SPORT_CLK+
SPORT_CLK-
SPORT_DT+
SPORT_DT-
SPORT_FS+
SPORT_FS-
EL_CLK_422+
EL_CLK_422-
EL_DATA_422+
EL_DATA_422-
EL_SYNC_422+
EL_SYNC_422-
SCAN_LED+
SCAN_LED-
/SYS_RST+
/SYS_RST-
5V_RAW
A A
ALL OFF-SHT NETS:
PORTS UP TO BLKS
ON SHT _1_
+5V_ANA, BOARD-WIDE
----------------> +5V D, BOARD-WIDE
----------------> +3.3V D, BOARD-WIDE
----------------> AGND, BOARD-WIDE
----------------> DGND, BOARD-WIDE
TO/FROM
DSP BLOCKS
sht 1, 12
SCAN_SP0_TCLK
SCAN_SP0_DT
SCAN_SP0_TFS
TO/FROM
CPU BLOCKS
sht 1, 18
TO/FROM
CPU SERIAL
TO/FROM
FPGA
BLOCKS
sht 1, 08
2
2
THIS DOCUMENT CONTAINS PROPRIETARY INFORMATION OF THERMO ELECTRON AND IS TENDERED SUBJECT TO THE CONDITIONS THAT
THE INFORMATION: (A) BE RETAINED IN CONFIDENCE. (B) NOT BE REPRODUCED OR COPIED IN WHOLE OR IN PART AND (C) NOT BE USED OR
INCORPORATED IN ANY PRODUCT, EXCEPT UNDER AN EXPRESS WRITTEN AGREEMENT WITH THERMO ELECTRON CORPORATION.
REV BRIEF DESCRIPTION OF CHANGE ECO
DATE BY APPR.
- SEE PAGE 1
SCAN_SP0_TCLK
SCAN_SP0_DT
SCAN_SP0_TFS
TO/FROM
FPGA
BLOCKS
sht 1, 08
MALDI_SP2
MALDI_SP
MALDI_RST
MALDI_FIRE
PB8
PD23
PB14
PC11
Inst_Spares
SEE sht: 06_Inst_Control_Spares_Foldr _
Inst_Control_Shield
SEE sht: 07_MALDI_&_Shield_Foldr
_
MALDI_SP2
MALDI_SP
MALDI_RST
MALDI_FIRE
PB8
PD23
PB14
PC11
02-Inst Control Top
Thermo
ELECTRON CORPORATION
Title
1
Size Document Number Rev
C
97055-91010
355 River Oaks Pkwy, San Jose, CA 95134-1991
SCH, PCB, DIGITAL BOARD, LTQ
Date: Wednesday, March 09, 2005 Sheet of
1
2 27
B