C Thermo

5
5
4
4
3
D D
L0D[0..3]
L0ACK
L0CLK
L4D[0..3]
L4ACK
L4CLK
/HBR
DA[0:31]
DD[0:31]
CLK_DSP1
CLK_DSP2
PA10
/HBG
L0D[0..3]
C C
/BUF_SYS_RST_PB
/PORESET
/SRESET
/SYS_RST
L4D[0..3]
R/W
DD[0:31]
/HBG
REDY
R/W
B B
PPC_A[6:29]
PPC-to-DSP ==>
PPC_D[0:31]
/CS2
/CS3
/CS4
/CS5
/CS6
/CS7
DSP/MS2
DSP/MS1
DSP/MS0
PPC_A[6:29]
PPC_D[0:31]
/SYS_RST
DA[0:31]
/SRESET
S/IRQ2
ACK
DSP/MS3
DSP/MS1
DSP/MS0
S/IRQ2
ACK
DSP/MS3
DSP/MS1
STMEXP
DSP/RD
DSP/WR
REDY DSP/MS2
/BUF_SYS_RST_PB
ACQU_SP1_DR
ACQU_SP1_RFS
ACQU_SP1_RCLK
/IRQ5
AFG2
/CS6
/CS7
/HBR
PA6
PGPL4
CLK_CPLD
/BUF_DATA_OUT_EN
DATA_CLKAB
STORE_DATA_A_TO_B
DACBUS_XLAT_DIR
/DACBUS_XLAT_OE
BUF_DATA_DIR
A A
ALL OFF-SHT NETS:
PORTS UP TO BLKS
ON SHT _1_
L0D[0..3]
L0ACK
L0CLK
L4D[0..3]
L4ACK
L4CLK
/HBG
/HBR
JTAG
LED's
TP's
DSP_Chips
SEE sht: 13_DSP_Chips_Foldr
_
ACQU_SP1_DR
ACQU_SP1_RFS
ACQU_SP1_RCLK
DA[0..31] STMEXP
DSP/RD
DD[0..31]
DSP/WR
DSP/MS2
CLK_DSP1
CLK_DSP2
PA10
/BUF_SYS_RST_PB
/PORESET
/SRESET
/SYS_RST
/IRQ5
AFG2
/CS6
/CS7
S/IRQ2
ACK
DSP/MS3
DSP/MS1
DSP/MS0
REDY
AFG0
AFG1
A/IRQ2
DSP
Bridge
in SRAM
Sheet
to
ELECTROMETER
/IRQ6 = AFG2
3
MALDI_SP2
MALDI_SP
MALDI_FIRE
SYNC4_DIG.ONLY goes to FPGA --<
STORE_DATA_A_TO_B
DACBUS_XLAT_DIR
/DACBUS_XLAT_OE
BUF_DATA_DIR
DD[0:31]
LAT_DD[0:15]
2
DSP_DAC_Bus
2
THIS DOCUMENT CONTAINS PROPRIETARY INFORMATION OF THERMO ELECTRON AND IS TENDERED SUBJECT TO THE CONDITIONS THAT
THE INFORMATION: (A) BE RETAINED IN CONFIDENCE. (B) NOT BE REPRODUCED OR COPIED IN WHOLE OR IN PART AND (C) NOT BE USED OR
INCORPORATED IN ANY PRODUCT, EXCEPT UNDER AN EXPRESS WRITTEN AGREEMENT WITH THERMO ELECTRON CORPORATION.
REV BRIEF DESCRIPTION OF CHANGE ECO
DATE BY APPR.
- SEE PAGE 1
{Input to
FPGA}
HYB_FLAG0
HYB_FLAG1
/DSP_IRQ2
HYB_RST
RDY_OUT
START_OUT
START_DIGIN
D[0:15]
A[0:7]
RESET_PB
DDS1+
DDS1-
DDS2+
DDS2-
DDS3+
DDS3-
SEE sht: 17_DSP_DDS_Foldr
_
WFM+
WFM-
SEE sht: 16_DSP_WFM/SRAM_Foldr _
SCANTEXP
/DSPRD
/DSPWR
/MS2
DAC_SYNC1
HYB_FLAG0
HYB_FLAG1
/DSP_IRQ2
HYB_RST
RDY_OUT
START_OUT
START_DIGIN
D[0:15]
DA[0:31] A[0:7]
/BUF_SYS_RST_PB
DSP_WFM/SRAM
DD[0..31]
SEE sht: 14_DSP_SRAM_Foldr
_ SEE sht: 15_DSP_DAC_Bus_Foldr
_
DSP/RD
DSP/RD
DSP/WR
DA[0..31]
DSP/WR
/CS2
/CS3
/CS4
/CS5
/CS6
/CS7
DSP/MS2
DSP/MS1
DSP/MS0
PPC_A[6:29]
PPC_D[0:31]
/SRESET
/SYS_RST
PGPL4
/HBR
DATA_CLKAB
STORE_DATA_A_TO_B
DACBUS_XLAT_DIR
/DACBUS_XLAT_OE
BUF_DATA_DIR
PA6
CLK_CPLD
/BUF_DATA_OUT_EN
MALDI_SP2
MALDI_SP
MALDI_FIRE
DSP_DDS
SPI_BOARDS_MISO
RESET_PB
DDS1+
DDS1-
DDS2+
CLK_DDS_X3 DDS2-
LAT_DD[0:15]
DDS3+
DDS3-
WFM+
WFM-
SCANTEXP
/DSPRD
/DSPWR
/MS2
DAC_SYNC1
HYB_FLAG0
HYB_FLAG1
/DSP_IRQ2
HYB_RST
RDY_OUT
START_OUT
START_DIGIN
SPI_BOARDS_MISO
D[0:15]
A[0:7]
RESET_PB
DDS1+
DDS1-
DDS2+
DDS2-
DDS3+
DDS3-
WFM+
WFM-
Thermo
ELECTRON CORPORATION
Title
1
Size Document Number Rev
C
DAC bus cntl
out to j200
to J200,
IO Brd
97055-91010
to j200,
Hyb sigs
12-DSP Top
355 River Oaks Pkwy, San Jose, CA 95134-1991
SCH, PCB, DIGITAL BOARD, LTQ
Date: Wednesday, March 09, 2005 Sheet of
1
12 27
B