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5<br />
5<br />
4<br />
4<br />
3<br />
D D<br />
CPU_Clk_Pwr_Rst<br />
SEE sht: 23_CPU_Clk_Pwr_Rst_Foldr _<br />
/PORESET<br />
CLKDRAM1<br />
CLKDRAM2<br />
PPC_D[0:63]<br />
PPC_D[0:63] /CS1<br />
/CS1<br />
/CS1<br />
/CS2<br />
/CS2<br />
PPC_D[0:31]<br />
PPC_A[6:29]<br />
PPC_D[0:31]<br />
PGPL[0:3]<br />
PPC_A[6:29]<br />
PPC_D[0:31]<br />
PGPL[0:3]<br />
PPC_A[6:29]<br />
/CS3<br />
/CS4<br />
/CS5<br />
/CS6<br />
/CS7<br />
/PBS[0:7]<br />
/CS3<br />
/CS4<br />
/CS5<br />
/CS6<br />
/CS7<br />
/PBS[0:7]<br />
DACs<br />
SRAM1<br />
SRAM2<br />
S-DSP<br />
A-DSP<br />
M-SDRAM<br />
/CS4<br />
/CS5<br />
/CS6<br />
/CS7<br />
/CS3<br />
smc1<br />
smc2<br />
PD8<br />
PD9<br />
PA9<br />
PA8<br />
PD8<br />
PD9<br />
PA9<br />
PA8<br />
RS485+<br />
RS485+<br />
R/W<br />
/IRQ5<br />
AFG2<br />
/IRQ7<br />
/HRESET<br />
CLK_CPU<br />
MODCK[1:3]<br />
C C<br />
SW1<br />
SP1<br />
COP<br />
MODCK[1:3]<br />
PA31<br />
PA30<br />
PA29<br />
PA28<br />
PA27<br />
PA26<br />
PA25<br />
PA24<br />
PA23<br />
PA22<br />
PA21<br />
PA20<br />
PA19<br />
PA18<br />
PA17<br />
PA16<br />
PA15<br />
PA14<br />
PA13<br />
PA12<br />
PA11<br />
MODCK2<br />
MODCK3<br />
/PBS[0:7]<br />
PGPL[0:3]<br />
MODCK[2:3]<br />
PPC_A[10:31]<br />
PPC_D[0:63]<br />
B B<br />
PA[11:31]<br />
CLK_DDS_X3<br />
CLK_CPLD<br />
CLK_FPGA<br />
PA10<br />
PA6<br />
PA2<br />
PA1<br />
TS169<br />
PA[3:5]<br />
CLK_DSP2<br />
CLK_DSP1<br />
PA10<br />
PA9<br />
PA8<br />
PA7<br />
PA6<br />
PA2<br />
PA1<br />
PA0<br />
PA5<br />
PA4<br />
PA3<br />
M-SDRAM<br />
/SRESET<br />
/PORESET<br />
/SYS_RST<br />
PA[0:31]<br />
PA[11:31]<br />
DSP<br />
AFG2 = /IRQ6<br />
PB[18:31]<br />
R/W<br />
PGPL4<br />
/IRQ5<br />
AFG2<br />
PC2<br />
PB31<br />
PB30<br />
PB29<br />
PB28<br />
PB27<br />
PB26<br />
PB25<br />
PB24<br />
PB23<br />
PB22<br />
PB21<br />
PB20<br />
PB19<br />
PB18<br />
TS74<br />
TS73<br />
/SYS_RST<br />
PB17<br />
PB16<br />
PB13<br />
PB11<br />
PB10<br />
PB9<br />
PB7<br />
PB6<br />
PB5<br />
PB4<br />
SRAM<br />
DSP<br />
DSP<br />
PB[4:31]<br />
/SRESET<br />
/PORESET<br />
PC[18:19]<br />
PC31<br />
PC30<br />
PC29<br />
PC28<br />
PC27<br />
PC26<br />
PC25<br />
PC24<br />
PC23<br />
PC22<br />
PC21<br />
PC20<br />
PC17<br />
PC16<br />
PC15<br />
PC14<br />
PC13<br />
PC12<br />
PC11<br />
PC10<br />
PC9<br />
PC8<br />
PC7<br />
PC6<br />
PC5<br />
PC4<br />
PC3<br />
PC2<br />
PC1<br />
PC0<br />
PC19<br />
PC18<br />
A A<br />
ALL OFF-SHT NETS:<br />
PORTS UP TO BLKS<br />
ON SHT _1_<br />
MODCK[1:3]<br />
/SRESET<br />
/HRESET<br />
/PORESET<br />
CLK_CPU<br />
CLK_DSP2<br />
CLK_DSP1<br />
CLKDRAM1<br />
CLKDRAM2<br />
CLK_DDS_X3<br />
CLK_CPLD<br />
CLK_FPGA<br />
TS113<br />
/SYS_RST<br />
CLKDRAM1<br />
CLKDRAM2<br />
/PBS[0:7]<br />
PGPL[0:3]<br />
MODCK[2:3]<br />
CPU_Memory<br />
SEE sht: 20_CPU_Memory_Foldr<br />
_<br />
TS87<br />
TS116<br />
TS114<br />
TS122<br />
TS215<br />
TS212<br />
TS216<br />
TS213<br />
/CS0<br />
/CS1<br />
PPC_A[10:31]<br />
PPC_D[0:63]<br />
R/W<br />
PGPL4<br />
/IRQ5<br />
AFG2<br />
/IRQ7<br />
PC2<br />
MODCK[1:3]<br />
/SRESET<br />
/HRESET<br />
3<br />
PC[0:31]<br />
PC[0:31]<br />
/IRQ2<br />
/PORESET<br />
SEE sht: 19_CPU_Main_Foldr<br />
_<br />
CLK_CPU<br />
/SYS_RST<br />
/CS0<br />
/CS1<br />
TS23<br />
TS30<br />
TS33<br />
TS38<br />
TS42<br />
TS41<br />
TS45<br />
TS43<br />
TS58<br />
TS55<br />
TS67<br />
TS70<br />
TS72<br />
TS90<br />
TS89<br />
TS93<br />
TS112<br />
TS119<br />
TS111<br />
TS217<br />
TS172<br />
TS173<br />
TS171<br />
TS167<br />
CPU_Main<br />
PPC_A[10:31]<br />
/IRQ0<br />
/IRQ1<br />
/IRQ2<br />
PD7<br />
PD7<br />
PD[17:19]<br />
TS97<br />
TS88<br />
TS96<br />
TS98<br />
TS95<br />
TS117<br />
FROM CPM<br />
PIN PD7,<br />
/SUICIDE_OUT<br />
TS29<br />
TS37<br />
TS39<br />
TS46<br />
TS174<br />
TS170<br />
TS168<br />
PB8<br />
PD23<br />
PB14<br />
PC11<br />
MALDI_RST<br />
PD16<br />
PD31<br />
PD29<br />
PD28<br />
PD27<br />
PD26<br />
PD25<br />
PD24<br />
PD23<br />
PD22<br />
PD21<br />
PD20<br />
PD19<br />
PD18<br />
PD17<br />
PD15<br />
PD14<br />
PD13<br />
PD12<br />
PD11<br />
PD10<br />
PD9<br />
PD8<br />
PD7<br />
PD6<br />
PD5<br />
PD4<br />
MISO<br />
PD11<br />
PD[4:31]<br />
PD16<br />
2<br />
/IRQ0<br />
/IRQ1<br />
2<br />
THIS DOCUMENT CONTAINS PROPRIETARY INFORMATION OF THERMO ELECTRON AND IS TENDERED SUBJECT TO THE CONDITIONS THAT<br />
THE INFORMATION: (A) BE RETAINED IN CONFIDENCE. (B) NOT BE REPRODUCED OR COPIED IN WHOLE OR IN PART AND (C) NOT BE USED OR<br />
INCORPORATED IN ANY PRODUCT, EXCEPT UNDER AN EXPRESS WRITTEN AGREEMENT WITH THERMO ELECTRON CORPORATION.<br />
REV BRIEF DESCRIPTION OF CHANGE ECO<br />
DATE BY APPR.<br />
- SEE PAGE 1<br />
scc2<br />
scc4<br />
scc1<br />
PB12<br />
PD26<br />
PB15<br />
PC28<br />
/IRQ7<br />
PA[3:5]<br />
PD21<br />
PD20<br />
PD22<br />
PD29<br />
PD30<br />
PD31<br />
PA[11:31]<br />
PC[20:21]<br />
PB[18:31]<br />
PC[18:19]<br />
/IRQ2<br />
PA[0:31]<br />
PB[4:31]<br />
PB12<br />
PD26<br />
PB15<br />
PC28<br />
PD21<br />
PD20<br />
PD22<br />
<strong>Thermo</strong><br />
ELECTRON CORPORATION<br />
Title<br />
1<br />
1<br />
PC[0:31]<br />
PD[4:31]<br />
RS485-<br />
Size Document Number Rev<br />
C<br />
97055-91010<br />
RJ45-SCC1<br />
RJ11-SCC3<br />
RJ11-SCC2<br />
485-D9 SCC4<br />
RJ11-SMC1<br />
RJ11-SMC2<br />
PD29<br />
PD30<br />
PD31<br />
SEE sht: 21_CPU_Serial_Foldr<br />
_<br />
PA[11..31]<br />
PC[20..21]<br />
CPU_first_100bT<br />
LEDs<br />
RJ45<br />
/IRQ7<br />
SEE sht: 24_CPU_first_100bT_Foldr<br />
_<br />
PA[3:5]<br />
PB[18..31]<br />
PC[18:19]<br />
CPU_Serial<br />
CPU_second_100bT<br />
RS485-<br />
LEDs<br />
RJ45<br />
/IRQ2<br />
SEE sht: 25_CPU_second_100bT_Foldr _<br />
PA[0:31]<br />
CPU_CPM/PIO<br />
SEE sht: 22_CPU_CPM/PIO_Foldr<br />
_<br />
PB[4:31]<br />
PC[0:31]<br />
PD[4:31]<br />
18-CPU Top<br />
355 River Oaks Pkwy, San Jose, CA 95134-1991<br />
SCH, PCB, DIGITAL BOARD, LTQ<br />
18 27<br />
Date: Wednesday, March 09, 2005 Sheet of<br />
B