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5 5 4 4 3 D D TB4 TB3 TB1 TB2 PA[11..31] PC[20..21] PA22 PA23 PA24 PA25 -> TX PA28 PA13 PA18 PA19 PA20 PA21 PA29 PA31 PA30 PA27 PA26 PC20 PA17 PA16 PA15 PA14 PA12 FDE C C /IRQ7 RX
5 5 4 4 3 D D C C B B A A 3 +5V FPGA Rpull-up
Page 1 and 2:
X Y Y X 90 o S3 S3 S3 Line Voltage
Page 3 and 4:
SPI,VacOK, SYSRst, HVCTRL 5 5 4 4 3
Page 5 and 6:
5 * ONLY +5.5 VCC USED ON THIS PAGE
Page 7 and 8:
3 of 4 PWR REG, CONN 5 5 4 4 3 D D
Page 9:
5 5 4 4 3 3 2 1 THIS DOCUMENT CONTA
Page 12 and 13:
10 10 9 9 8 8 7 7 6 J J I I H H G G
Page 14 and 15:
10 10 9 9 8 8 7 7 6 J J I I H H G G
Page 16 and 17:
5 5 4 4 3 D D C C J1 CON6 1 2 3 4 5
Page 18:
5 5 4 4 3 3 2 2 1 THIS DOCUMENT CON
Page 21 and 22:
5 5 4 4 3 D D J1 CON6 1 2 3 4 5 6 Y
Page 26 and 27:
A A B TP107 THIS DOCUMENT CONTAINS
Page 28 and 29: A A B +5V +5V C144 .01UF D D 1DIR S
Page 30 and 31: 5 5 4 4 3 D CANARY_LED_FPGA_OUT [4]
Page 32 and 33: A Digital Valve Section A B +24V-AU
Page 34 and 35: A A B +11.75V +11.75V 4 SPARE GAS P
Page 36 and 37: A 4 TC- IS ALUMEL TC+ IS CHROMEL [1
Page 38 and 39: A A B ( 17.8 to 14.7 KHz ) +5V +15V
Page 40 and 41: A A -13.4V 8 4 B 6 6 C55 + + 1K .01
Page 42 and 43: 5 5 4 4 3 +5V [18] /INJECT_WASTE_LE
Page 44 and 45: +60V A TP69 +24V-AUX +24V-AUX A B 4
Page 46 and 47: +5V D A A SHUTDOWN_BUF B 2DIR 4 [5]
Page 48 and 49: 5 5 4 4 3 D CANARY_LED_FPGA_OUT [4]
Page 50 and 51: A A B 4 4 FROM FPGA SECTION Digital
Page 52 and 53: A A +11.75V B 4 7 + 5 4 - 6 +11.75V
Page 54 and 55: A A B 4 4 TC- IS ALUMEL TC+ IS CHRO
Page 56 and 57: A A B 4 4 3 3 +15VIN_IG C85 10uF 25
Page 58 and 59: A A -13.4V B 4 4 [11] [10] [12] [13
Page 60 and 61: [18] [18] +5V +5V 5 5 D D 4 4 3 D D
Page 75 and 76: 5 5 4 4 ACQU_SP1_DR ACQU_SP1_RFS AC
Page 77: 5 5 4 4 3 D D MALDI CABLE CONNECTOR
Page 81 and 82: 5 5 4 4 3 D D C C +3.3V VDDL ( ~ 2.
Page 83 and 84: PA[0:31] 5 5 4 4 3 D D TS211 TS214
Page 85 and 86: 5 5 PPC_D[0:63] PPC_A[10:31] MODCK[
Page 87 and 88: 5 RC RC24 D 6 RC 5 RC 100pF-47ohm R
Page 89 and 90: 5 5 4 4 3 D D CLK_DDS_X3 DDS1_/WR D
Page 91 and 92: 5 5 4 4 3 D D CLK_FPGA /SRESET /SYS
Page 93 and 94: 5 5 4 4 3 D D IO_DIR IO_DIR 0 free
Page 95 and 96: 5 5 4 4 3 D D L0D[0..3] L0ACK L0CLK
Page 97 and 98: 5 SCAN_SP0_DT U25-1 DS90LV047A U27B
Page 99 and 100: 5 5 4 4 L0D[0..3] L4D[0..3] 3 D D
Page 101 and 102: 5 5 4 4 3 3 2 2 1 1 D D C C B B A A
Page 103 and 104: 5 5 4 4 3 D TURBO POWER +24V Tgnd J
Page 105: 5 5 4 4 3 3 2 2 1 1 D D C C B B A A
Page 113 and 114: 5 4 3 2 1 D +5V (NOT LOADED) +/SYS_
Page 115 and 116: 5 +3.3V 4 3 D +3.3V +3.3V D D D (3.
Page 117 and 118: 5 4 3 2 1 D C B A [2,10] [3] [3,10]
Page 119 and 120: 5 5 +150V -150V 4 4 3 D [6] LT_FRON
Page 121 and 122: [5] FOUT_GT[0..11] FOUT_GT[0..11] 5
Page 123 and 124: 5 5 4 4 3 R102 ENABLE TP13 /FORCE_8
Page 125 and 126: 5 5 4 4 3 D D C 10K C ENABLE TTL LE
Page 127 and 128: 5 4 3 [19] [19] 10K R348 ANALOG_IN1
Page 129 and 130:
5 4 8 4 - + 3 +13.4V -2.5V_REF2 "8K
Page 131 and 132:
5 P. C. B. TOP COVER TABLE OF CONTE
Page 133 and 134:
5 4 CONNECTOR- SPI AND CONTROL 5 4
Page 135 and 136:
5 LENS D-C FROM ANALOG BOARD 5 4 4
Page 137 and 138:
5 5 4 4 3 D D (CONFIG DONE) IO_TDO
Page 139 and 140:
5 PAGE 9 LOCAL POWER & UNUSED FPGA
Page 141 and 142:
FROM PAGE 5 P-5, P-5, M1_DC M0_DC 5
Page 143 and 144:
5 5 4 4 3 D D P-4,15,17, +15V C C +
Page 145 and 146:
5 SIGNAL READBACKS MUX P-4,11,12, +
Page 147 and 148:
5 5 4 P-4,13,15, +15V +13V_RDBK P-4
Page 149 and 150:
5 AUXILIARY AC SIGNAL "WAMP" FROM A
Page 151 and 152:
5 +5VISOL_EXT +5ISOL (2/3A) 1 2 (5/
Page 153 and 154:
5 5 4 4 3 D D TP61 1 1 2 1 2 1 2 2
Page 155 and 156:
5 5 4 4 3 D D (2/2A) (2/2A) AUXIN-
Page 157 and 158:
(4/3B,8/1A,8/1A) +18VLOCAL 5 5 4 4
Page 159 and 160:
5 5 4 4 3 D D GND GND VCC_UNF CLK-
Page 161 and 162:
5 5 4 4 3 D +5V D AGND [2,3] [3] DA
Page 163 and 164:
5 5 +15V 4 4 3 - SEE PAGE 1 D +VDF
Page 165 and 166:
AGND 2 5 C37 1 100nF +5V 4 3 2 D [4
Page 168 and 169:
5 5 4 4 CPU/Digital PCB L0_D[0..7]
Page 170 and 171:
5 5 4 4 3 D D GND_EARTH J16 J15 C 1
Page 172 and 173:
5 5 Source PCB 4 4 3 D D J1 A1 1 A2
Page 189:
THIS DOCUMENT CONTAINS PROPRIETARY
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