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5<br />
5<br />
4<br />
4<br />
ACQU_SP1_DR<br />
ACQU_SP1_RFS<br />
ACQU_SP1_RCLK<br />
L0D[0:3]<br />
L0ACK<br />
L0CLK<br />
3<br />
D D<br />
L4ACK<br />
DDS1+<br />
DDS1-<br />
DDS2+<br />
DDS2-<br />
WFM+<br />
WFM-<br />
L4D[0:3]<br />
L4CLK<br />
D[0:15]<br />
A[0:7]<br />
/DSPWR<br />
/MS2<br />
DAC_SYNC1<br />
SCANTEXP<br />
DDS3+<br />
DDS3-<br />
/DSPRD<br />
C C<br />
D9-ELEC<br />
J24 SRC<br />
J200<br />
J-PWR BENCH<br />
SEE sht: 02_Inst_Control_Top_Foldr _<br />
Inst_Control_Top<br />
HYB_FLAG1<br />
HYB_FLAG0<br />
/DSP_IRQ2<br />
HYB_RST<br />
B B<br />
Sht ---<br />
=========<br />
3 200 pin CONN<br />
4 Diff ICs<br />
5 Power<br />
7 spare<br />
ACQU_SP1_DR<br />
ACQU_SP1_RFS<br />
ACQU_SP1_RCLK<br />
L0D[0:3]<br />
L0ACK<br />
L0CLK<br />
L4D[0:3]<br />
L4ACK<br />
L4CLK<br />
D[0:15]<br />
A[0:7]<br />
/DSPRD<br />
/DSPWR<br />
/MS2<br />
DAC_SYNC1<br />
SCANTEXP<br />
DDS1+<br />
DDS1-<br />
DDS2+<br />
DDS2-<br />
DDS3+<br />
DDS3-<br />
WFM+<br />
WFM-<br />
HYB_FLAG1<br />
HYB_FLAG0<br />
/DSP_IRQ2<br />
HYB_RST<br />
START_OUT<br />
RDY_OUT<br />
START_DIGIN<br />
RESET_PB<br />
----------------> +5V_ANA, BOARD-WIDE<br />
----------------> +5V D, BOARD-WIDE<br />
----------------> +3.3V D, BOARD-WIDE<br />
----------------> AGND, BOARD-WIDE<br />
----------------> DGND, BOARD-WIDE<br />
RS485+<br />
RS485-<br />
PB8<br />
PD23<br />
PB14<br />
PC11<br />
PD[17:19]<br />
MALDI_SP2<br />
MALDI_SP<br />
MALDI_RST<br />
MALDI_FIRE<br />
/SYS_RST<br />
SPI_BOARDS_MISO<br />
SCAN_SP0_TCLK<br />
SCAN_SP0_DT<br />
SCAN_SP0_TFS<br />
{SCC3 -<br />
MALDI<br />
RS232,<br />
SHT 7}<br />
MALDI_SP2<br />
MALDI_SP<br />
MALDI_FIRE<br />
to DIFF.<br />
ICs<br />
PD[17:19]<br />
MALDI_RST<br />
/SYS_RST<br />
PB8<br />
PD23<br />
PB14<br />
PC11<br />
SPI_BOARDS_MISO<br />
SCAN_SP0_DT<br />
START_OUT<br />
RDY_OUT<br />
START_DIGIN<br />
RESET_PB<br />
SCAN_SP0_TCLK<br />
SCAN_SP0_TFS<br />
/SYS_RST<br />
/BUF_DATA_OUT_EN<br />
PD[17:19] PD[17:19]<br />
A A<br />
SCAN_LED<br />
SCAN_LED<br />
MALDI_SP2<br />
MALDI_SP<br />
MALDI_FIRE<br />
ACQU_SP1_DR<br />
ACQU_SP1_RFS<br />
ACQU_SP1_RCLK<br />
L0D[0..3]<br />
L0ACK<br />
L0CLK<br />
L4D[0..3]<br />
L4ACK<br />
L4CLK<br />
D[0:15]<br />
A[0:7]<br />
DDS1+<br />
DDS1-<br />
WFM+<br />
WFM-<br />
/SYS_RST<br />
/DSPRD<br />
/DSPWR<br />
/MS2<br />
DAC_SYNC1<br />
SCANTEXP<br />
DDS2+<br />
DDS2-<br />
DDS3+<br />
DDS3-<br />
/SYS_RST<br />
HYB_FLAG1<br />
HYB_FLAG0<br />
/DSP_IRQ2<br />
HYB_RST<br />
START_OUT<br />
RDY_OUT<br />
START_DIGIN<br />
RESET_PB<br />
MALDI_SP2<br />
MALDI_SP<br />
MALDI_FIRE<br />
SPI_BOARDS_MISO<br />
SPI_BOARDS_MISO<br />
SCAN_SP0_TCLK<br />
SCAN_SP0_DT<br />
SCAN_SP0_TFS<br />
SCAN_LED<br />
/BUF_DATA_OUT_EN<br />
/BUF_DATA_OUT_EN<br />
3<br />
/SRESET<br />
/SRESET<br />
/SRESET<br />
DSP_Top<br />
DSP/MS1<br />
DSP/MS3<br />
ACK<br />
S/IRQ2<br />
DSP/MS1<br />
DSP/MS3<br />
ACK<br />
S/IRQ2<br />
DSP/MS1<br />
DSP/MS3<br />
ACK<br />
S/IRQ2<br />
FPGA_Top<br />
Sht ----<br />
======<br />
9 config<br />
10 global<br />
11 D I/O<br />
JTAG<br />
LED's<br />
TP's<br />
SEE sht: 12_DSP_Top_Foldr<br />
_<br />
R/W<br />
Sht ---<br />
==========<br />
13 BOTH DSPs<br />
14 SRAM<br />
15 DAC BUF<br />
16 WFM/SRAM<br />
17 DDS x3<br />
PA10<br />
PPC_D[0:31]<br />
PPC_A[6:29]<br />
/PORESET<br />
STAT LED's<br />
STAT TP's<br />
SEE sht: 08_FPGA_Top_Foldr<br />
_<br />
PA6<br />
/CS2<br />
/CS3<br />
/CS4<br />
/CS5<br />
/CS6<br />
/CS7<br />
/IRQ5<br />
AFG2<br />
PGPL4<br />
R/W<br />
PA1<br />
PA2<br />
PC2<br />
CLK_CPLD<br />
CLK_DSP1<br />
CLK_DSP2<br />
CLK_DDS_X3<br />
PD[17:19]<br />
CLK_FPGA<br />
/IRQ0<br />
/IRQ1<br />
/CS1<br />
/CS2<br />
/CS3<br />
PD16<br />
CANARY<br />
LED<br />
2<br />
2<br />
THIS DOCUMENT CONTAINS PROPRIETARY INFORMATION OF THERMO ELECTRON AND IS TENDERED SUBJECT TO THE CONDITIONS THAT<br />
THE INFORMATION: (A) BE RETAINED IN CONFIDENCE. (B) NOT BE REPRODUCED OR COPIED IN WHOLE OR IN PART AND (C) NOT BE USED OR<br />
INCORPORATED IN ANY PRODUCT, EXCEPT UNDER AN EXPRESS WRITTEN AGREEMENT WITH THERMO ELECTRON CORPORATION.<br />
REV BRIEF DESCRIPTION OF CHANGE ECO<br />
DATE BY APPR.<br />
A<br />
RELEASE TO PRODUCTION 10656 10/30/03 M.S.<br />
B BOM CHANGE 15151 01/19/05 M.G.<br />
ENGR<br />
MFG<br />
PA10<br />
PA6<br />
1ST USE<br />
N7695835<br />
PPC_D[0:31]<br />
PPC_A[6:29]<br />
CLK_CPLD<br />
CLK_DSP1<br />
CLK_DSP2<br />
CLK_DDS_X3<br />
CLK_FPGA<br />
(BOOTFLASH)<br />
PD16<br />
DRN M.S.<br />
CHK<br />
BY<br />
MISO<br />
DSN J.GABEL<br />
Orig dwn<br />
by J. Gabel<br />
/SYS_RST<br />
RS485+<br />
RS485-<br />
/SRESET<br />
PD[17:19]<br />
DATE<br />
10.30.03<br />
1.01.02<br />
1.01.02<br />
LTQ Endeavor<br />
PCB Title:<br />
C<br />
Size<br />
PA10<br />
PA6<br />
/CS4<br />
/CS5<br />
/CS6<br />
/CS7<br />
/IRQ5<br />
AFG2<br />
R/W<br />
CODE IDENT DWG NO<br />
PLOTTED:<br />
Wednesday, March 09, 2005<br />
1<br />
SEE sht: 18_CPU_Top_Foldr<br />
_<br />
PGPL4<br />
PPC_D[0:31]<br />
PPC_A[6:29]<br />
PA1<br />
PA2<br />
PC2<br />
/PORESET<br />
CLK_CPLD<br />
CLK_DSP1<br />
CLK_DSP2<br />
CLK_DDS_X3<br />
/SYS_RST<br />
RS485+<br />
RS485-<br />
MALDI_RST<br />
PB8<br />
PD23<br />
PB14<br />
PC11<br />
/SRESET<br />
PD[17:19]<br />
CLK_FPGA<br />
/IRQ0<br />
/IRQ1<br />
/CS1<br />
/CS2<br />
/CS3<br />
PD16<br />
01-Top Hierarchy<br />
<strong>Thermo</strong> 355 RIVER OAKS PARKWAY, SAN JOSE, CA. 95134<br />
ELECTRON CORPORATION<br />
SCH, PCB, DIGITAL BOARD, LTQ<br />
Software version used = OrCAD rev. 10.0<br />
<br />
CPU_Top<br />
Sht ---<br />
========<br />
19 CPU MAIN<br />
20 SDRAM<br />
21 SERIAL<br />
22 CPM<br />
23 CLK...<br />
24 FCC1<br />
25 FCC2<br />
97055-91010<br />
Sheet 1 of 27<br />
1<br />
RJ45-SCC1<br />
RJ11-SCC3<br />
RJ11-SCC2<br />
485-D9 SCC4<br />
RJ11-SMC1<br />
RJ11-SMC2<br />
SW1<br />
SP1<br />
COP<br />
E#1,<br />
#2<br />
LEDs<br />
RJ45<br />
Rev.<br />
B
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