Create successful ePaper yourself
Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.
A<br />
INTERLOCKS_ACTIVE+<br />
A<br />
B<br />
HV_ON+<br />
INTERLOCKS_ACTIVE-<br />
HV_ON-<br />
/VACUUM_OK+<br />
/VACUUM_OK-<br />
SPI_MISO+<br />
4 4<br />
SCAN+<br />
SPI_MISO_FPGA_OUT<br />
/SYS_RESET+<br />
SPI_MISO-<br />
[5]<br />
SCAN-<br />
/SYS_RESET-<br />
SPI_MOSI+<br />
+5V<br />
/SPI_SEL+<br />
SPI_MOSI-<br />
/SPI_SEL-<br />
SPI_CLK+<br />
SPI_MISO+<br />
SPI_CLK-<br />
SPI_MISO-<br />
+5V<br />
D<br />
SRC_BD_CONFIG_DONE+<br />
D<br />
TXD/RXD-<br />
SRC_BD_CONFIG_DONE-<br />
/SPI_MISO_ENABLE<br />
TXD/RXD+<br />
[4]<br />
/VACUUM_OK+<br />
2<br />
DO(+) /VACUUM_OK_FPGA_IN<br />
+5V<br />
/VACUUM_OK-<br />
DI [5,14]<br />
3<br />
DO(-)<br />
1<br />
2<br />
DO(+)<br />
DI<br />
3<br />
DO(-)<br />
U1A<br />
1<br />
2<br />
U30A<br />
DS26C31TM<br />
C164<br />
.01UF<br />
R137<br />
2<br />
4 4<br />
6 6<br />
8 8<br />
10 10<br />
12 12<br />
14 14<br />
16 16<br />
18 18<br />
20 20<br />
22 22<br />
24 24<br />
1 1<br />
3 3<br />
5 5<br />
7 7<br />
9 9<br />
11 11<br />
13 13<br />
15 15<br />
17 17<br />
19 19<br />
21 21<br />
23 23<br />
C184<br />
.01UF<br />
CON24<br />
FLAT CBL CONN.<br />
/TURBO_AT_SPEED<br />
1 2 TURBO_AT_SPD_FPGA_IN [5]<br />
D<br />
+5V<br />
TXD/RXD+<br />
100 74AHCT14<br />
TXD/RXD-<br />
+5V<br />
3 TXD/RXD_REF_GND<br />
SRC_BD_CONFIG_DONE+ 6<br />
3<br />
DO(+)<br />
C118<br />
SRC_BD_CONFIG_DONE_BUF<br />
SRC_BD_CONFIG_DONE-<br />
DI [3]<br />
.01UF<br />
5<br />
DO(-)<br />
U9A<br />
/SPI_SEL+<br />
D<br />
DS26C32ATM<br />
/SPI_SEL+ 2<br />
RI(+)<br />
3 /SPI_SEL_FPGA_IN<br />
/SPI_SEL-<br />
[5]<br />
1<br />
RI(-)<br />
PUP1<br />
/SPI_SEL-<br />
7<br />
2<br />
U1B<br />
DS26C31TM<br />
2<br />
4 4<br />
6 6<br />
8 8<br />
10 10<br />
12 12<br />
14 14<br />
16 16<br />
18 18<br />
20 20<br />
1 1<br />
3 3<br />
5 5<br />
7 7<br />
9 9<br />
11 11<br />
13 13<br />
15 15<br />
17 17<br />
19 19<br />
R44<br />
301<br />
CON20<br />
FLAT CBL CONN.<br />
+5V<br />
SPI<br />
J2<br />
J6<br />
SPI_CLK+<br />
SPI_CLK-<br />
16 1 /SPI_SEL+<br />
1K<br />
15 2 SPI_CLK+<br />
14 3 SPI_MOSI+<br />
SCAN+<br />
D<br />
13 4 /SYS_RESET+<br />
PUP3<br />
12 5 /SPI_SEL-<br />
10<br />
SPI_CLK-<br />
RI(+)<br />
11 6<br />
+5V<br />
R51<br />
11<br />
SCAN_FPGA_IN<br />
SPI_MOSI-<br />
[5]<br />
10 7<br />
9<br />
/SYS_RESET-<br />
301<br />
RI(-)<br />
9 8<br />
U21C<br />
2 2<br />
SCAN-<br />
D<br />
TURBO<br />
RP2<br />
D<br />
742-163-R102CT-ND<br />
CONNECTOR TO<br />
ANALYZER CONTROL BD<br />
Interface Connector Section 1<br />
10K<br />
Contact closure if<br />
turbo is at speed<br />
R139<br />
/SYS_RESET+<br />
/SYS_RESET-<br />
SPI_MOSI+<br />
HV_ON+<br />
1<br />
R92<br />
HV_ON+<br />
HV_ON-<br />
2<br />
1<br />
RI(+)<br />
RI(-)<br />
3 HV_ON_FPGA_IN [5]<br />
1<br />
HV_ON-<br />
SPI_MOSI-<br />
B<br />
D<br />
U36A<br />
R14<br />
301<br />
301<br />
R95<br />
1K<br />
R91<br />
1K<br />
R45<br />
301<br />
R15<br />
301<br />
D<br />
+5V<br />
R242<br />
+5V +5V<br />
1K<br />
PUP3<br />
SPI_CLK+<br />
SPI_CLK-<br />
SPI_MOSI+<br />
SPI_MOSI-<br />
/SYS_RESET+<br />
/SYS_RESET-<br />
+5V<br />
D<br />
6<br />
7<br />
10<br />
9<br />
PUP3<br />
14<br />
15<br />
PUP3<br />
C140<br />
.01UF<br />
EN1<br />
4<br />
EN1<br />
4<br />
RO<br />
12<br />
EN2<br />
RI(+)<br />
RI(-)<br />
EN1<br />
4<br />
RO<br />
12<br />
EN2<br />
+5V<br />
RI(+)<br />
RI(-)<br />
EN1<br />
4<br />
RO<br />
12<br />
EN2<br />
+5V<br />
RO<br />
12<br />
EN2<br />
+5V<br />
5<br />
U9C<br />
DS26C32ATM<br />
RI(+)<br />
RI(-)<br />
EN1<br />
4<br />
RO<br />
12<br />
EN2<br />
PUP2<br />
SPI_CLK<br />
U9B<br />
DS26C32ATM<br />
11<br />
13<br />
SPI_MOSI<br />
/SYS_RESET<br />
U9D<br />
DS26C32ATM<br />
U21A<br />
DS26C32ATM<br />
C<br />
C<br />
[3]<br />
[3]<br />
[4]<br />
+5V<br />
SCAN SIGNAL DRIVES<br />
THE FRONT PNL 'SCAN'<br />
LED THROUGH THE FPGA<br />
INTERLOCKS_ACTIVE+<br />
INTERLOCKS_ACTIVE-<br />
C105<br />
.01UF<br />
R93<br />
301<br />
R94<br />
1K<br />
EN2<br />
12<br />
EN2<br />
12<br />
EN2<br />
12<br />
+5V<br />
R52<br />
1K<br />
R96<br />
1K<br />
EN1<br />
4<br />
EN1<br />
4<br />
EN1<br />
4<br />
R50<br />
PUP1<br />
INTERLOCKS_ACTIVE+<br />
INTERLOCKS_ACTIVE-<br />
D<br />
DS26C31TM<br />
D<br />
+5V<br />
+5V<br />
D<br />
R237<br />
1K<br />
PUP2<br />
D<br />
PUP2<br />
6<br />
7<br />
RI(+)<br />
RI(-)<br />
EN1<br />
4<br />
EN1<br />
4<br />
RO<br />
12<br />
EN2<br />
+5V<br />
RO<br />
12<br />
EN2<br />
+5V<br />
+5V<br />
C143<br />
.01UF<br />
5<br />
R245<br />
1K<br />
+5V<br />
DS26C32ATM<br />
+5V<br />
INTERLOCKS_ACTIVE_FPGA_IN<br />
U21B<br />
DS26C32ATM<br />
[5]<br />
E<br />
<strong>Thermo</strong> 355 River Oaks Pkwy, San Jose, CA 95134-1991<br />
ELECTRON CORPORATION<br />
Title<br />
SCHEM, PCB, SOURCE<br />
Size B<br />
Document Number 70111-91050<br />
Rev<br />
F<br />
Date: Tuesday, August 30, 2005<br />
Sheet 2 of 18<br />
E
Change language