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A<br />
A<br />
B<br />
+3.3V<br />
+3.3V<br />
D<br />
+3.3V<br />
CONFIG_CLK<br />
4<br />
4 4<br />
/ALTERA_RESET<br />
DCLK<br />
CONFIG_DATA<br />
VCC2/SER_EN<br />
2<br />
DATA<br />
SRC_BD_CONFIG_DONE_FPGA_OUT<br />
9<br />
nCS<br />
D D<br />
D<br />
CONFIG_STATUS<br />
8<br />
OE<br />
(3.3 volt version)<br />
D<br />
D<br />
18<br />
VCC1 20<br />
GND 10<br />
nCASC 12<br />
R115<br />
EPC1441LC20<br />
10K<br />
C121<br />
.01uF R108<br />
1K R108<br />
10K<br />
R128<br />
1K<br />
Q11 1<br />
MMBT4403LT1<br />
Y11<br />
nCONFIG<br />
T3<br />
MSEL<br />
CONF_DONE 1K<br />
E18<br />
nSTATUS W11<br />
DCLK C10<br />
DATA B10<br />
R111<br />
1K<br />
U29-1<br />
E1<br />
nCE<br />
V18<br />
nCEO<br />
R111<br />
1K<br />
3<br />
VCC<br />
1<br />
GND GND<br />
S1<br />
KT11P2JM<br />
4<br />
RESET 2<br />
U7<br />
DS1233AZ-10<br />
+5V<br />
D<br />
+5V<br />
3<br />
[2]<br />
/SYS_RESET<br />
D<br />
+5V<br />
[3,6]<br />
SPICLK_BUF_FPGA_IN<br />
3<br />
+3.3V<br />
4<br />
VCC<br />
FPGA_CLK<br />
+5V<br />
D<br />
2<br />
GNDNC(OE)<br />
+5V<br />
+5V<br />
"SPI<br />
FPGA"<br />
DGND<br />
[5] CANARY_LED_FPGA_OUT<br />
/SHUTDOWN<br />
[3,17,18]<br />
+5V +5V<br />
+5V<br />
1<br />
OUT 3<br />
C129<br />
.01UF<br />
1<br />
1<br />
2<br />
U15A<br />
74HCT125<br />
2 3<br />
TP50<br />
PD2 1<br />
U29-5<br />
L3<br />
GLOB_IN1<br />
L1<br />
GLOB_IN2<br />
X1<br />
PD57 1<br />
L20<br />
GLOB_IN3<br />
K19<br />
GLOB_IN4<br />
D2<br />
C194<br />
.01uF<br />
EPF6024ABC256<br />
C152<br />
.01uF<br />
GRN LED<br />
20MHZ OSC<br />
14<br />
9<br />
10<br />
7<br />
U28C<br />
8<br />
74AHCT00<br />
2<br />
3<br />
3<br />
4 4<br />
5<br />
5 6 6<br />
7<br />
7<br />
8 8<br />
9<br />
9<br />
10 10<br />
J5<br />
R132<br />
10K<br />
3<br />
D1<br />
4<br />
D2<br />
6<br />
D3<br />
11<br />
D4<br />
13<br />
D5<br />
14<br />
D6<br />
Q1<br />
9<br />
CLK<br />
1<br />
CLR<br />
2<br />
Q2 5<br />
Q3 7<br />
Q4 10<br />
Q5 12<br />
Q6 15<br />
R1<br />
681<br />
U16<br />
74AHCT174<br />
R89<br />
SHUTDOWN<br />
[3,16,17]<br />
10K<br />
+5V<br />
+5V<br />
+5V<br />
[5]<br />
/SHUTDOWN_FPGA_OUT<br />
[3] GAS_PRS_CAL_EEPROM_CS_BUF<br />
1<br />
/CS<br />
2 GAS_PRS_CAL_EEPROM_DOUT_FPGA_IN<br />
2<br />
2<br />
[5]<br />
SOUT<br />
SPICLK_BUF_FPGA_IN<br />
3<br />
/WP<br />
[3,6]<br />
/SPI_MISO_ENABLE<br />
/SPI_MOSI_BUF_FPGA_IN<br />
D<br />
D<br />
[2]<br />
4<br />
[5]<br />
SPI_MISO_ENABLE_FPGA_OUT<br />
VSS SIN [3,5,6]<br />
D<br />
5<br />
SCLK 6<br />
/HLD 7<br />
VCC 8<br />
U28A<br />
14<br />
R246<br />
1<br />
R63<br />
3<br />
10K<br />
2<br />
U24<br />
10K<br />
7<br />
74AHCT00<br />
+<br />
C1<br />
C104<br />
U28B<br />
10uF 25V<br />
14<br />
4<br />
.1UF<br />
6<br />
5<br />
7<br />
NM25C020M8<br />
74AHCT00<br />
BR1<br />
+3.3V<br />
C26<br />
2.2uF 25V<br />
D<br />
+3.3V<br />
D<br />
C25<br />
.1UF<br />
+3.3V<br />
+3.3V<br />
R240<br />
1 3<br />
2 4<br />
D<br />
+3.3V +3.3V<br />
1<br />
D<br />
1<br />
PD23<br />
PD1<br />
PD3<br />
PD4<br />
1<br />
1<br />
1<br />
1<br />
EPF6024ABC256<br />
T17<br />
IO_TDO<br />
V1<br />
IO_TCK<br />
P3<br />
IO_TMS<br />
J3<br />
IO_TDI<br />
B<br />
U29-2<br />
EPF6024ABC256<br />
+3.3V<br />
SRC_BD_CONFIG_DONE_FPGA_OUT<br />
D<br />
TP40<br />
PD21<br />
EPF6024ABC256 std BGA pinout checked 12-29-99<br />
TP51<br />
TP39<br />
[3]<br />
C<br />
C<br />
U32<br />
+3.3V<br />
C170<br />
.01uF<br />
D<br />
/ATMEL_FPGA_PROG<br />
+3.3V<br />
2<br />
3<br />
D<br />
USED TO TRISTATE<br />
+3.3V ALTERA PART WHEN<br />
DOING IN-SITU<br />
PROGRAMMING OF<br />
BR2 ATMEL FPGA CONFIGURATION<br />
EEPROM.<br />
U29-3<br />
1<br />
DGND<br />
PD38 1<br />
PD37 1<br />
PD63 1<br />
C13<br />
IO_nRS<br />
B15<br />
IO_nWS<br />
A17<br />
IO_CS<br />
B17<br />
IO_nCS<br />
G17<br />
IO_CLKUSR<br />
G20<br />
IO_RDYnBSY<br />
J19<br />
IO_INIT_DONE<br />
C9<br />
DEV_CLRn<br />
A12<br />
DEV_OE<br />
EPF6024ABC256<br />
R252<br />
10K<br />
+3.3V<br />
C159<br />
.01UF<br />
D<br />
+3.3V<br />
C180<br />
.01UF<br />
C160<br />
.1UF<br />
C181<br />
.01UF<br />
C179<br />
.01UF<br />
C166<br />
.1UF<br />
C167<br />
.01UF<br />
C193<br />
.01UF<br />
C178<br />
.1UF<br />
<strong>Thermo</strong> 355 River Oaks Pkwy, San Jose, CA 95134-1991<br />
ELECTRON CORPORATION<br />
Title<br />
SCHEM, PCB, SOURCE<br />
1<br />
C166<br />
VCCINT1 PD9 1<br />
PD59 1<br />
C182<br />
.01UF<br />
.1UF<br />
D20<br />
VCCINT2 F3<br />
VCCINT3 K20<br />
VCCINT4<br />
A1<br />
GND1<br />
D4<br />
GND2<br />
D8<br />
GND3<br />
D13<br />
GND4<br />
L2<br />
VCCIO1<br />
D17<br />
GND5<br />
H4<br />
GND6<br />
H17<br />
GND7<br />
N4<br />
GND8<br />
D6<br />
VCCIO2 D11<br />
VCCIO3 D15<br />
VCCIO4 F4<br />
VCCIO5 F17<br />
VCCIO6 K4<br />
VCCIO7 L17<br />
VCCIO8 R4<br />
VCCINT5 T20<br />
VCCINT6 U1<br />
VCCIO9 R17<br />
VCCIO10 U6<br />
VCCIO11 U10<br />
VCCIO12 U15<br />
U29-4<br />
N17<br />
GND9<br />
U4<br />
GND10<br />
U8<br />
GND11<br />
U13<br />
GND12<br />
U17<br />
GND13<br />
EPF6024ABC256<br />
PD15 1<br />
C161<br />
.01UF<br />
C168<br />
.01UF<br />
C191<br />
.01UF<br />
C176<br />
.01UF<br />
C192<br />
.1UF<br />
C192<br />
PD39 1<br />
R250<br />
10K<br />
C165<br />
.01UF<br />
C169<br />
.01UF<br />
C177<br />
.01UF<br />
.1UF<br />
HEADER 5X2<br />
1 2<br />
D<br />
1 2<br />
D<br />
E<br />
Size<br />
B<br />
Document Number<br />
70111-91050<br />
Rev<br />
F<br />
Date: Tuesday, August 30, 2005<br />
Sheet 4 of 18<br />
E
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