5 DDS R-F FREQUENCY GENERATOR SERIAL DIRECT DIGITAL SYNTHESIZER 5 4 4 3 D D FULL SCALE ADJ R: IOUT(Full Scale)= 12.5x(Vrefin/Rset) P-7, DDSCLK_20MHZ_BUF P-8, SPI_DDS_CLOCK_FPGA_OUT_BUF P-8, SPI_DDS_DATA_FPGA_OUT_BUF P-3,4,6,7,8,9,15, DGND C C P-8, /SPI_DDS_FSYNC_FPGA_OUT_BUF FULL SCALE ADJ. 3.9K is min. DGND DGND DGND SWITCHED_RF_OSC 3.3MHz corner, 20 dB/decade. GCGND B B R177 1K 0805 R211 100 1206 C30 10pF 2.21K R282 GCGND BEGINS NEW WORD. "RF_OSC" TL15 GCGND 18-20 V P-P 40dB/decade after 3.6MHz R-F_OSC P-11, "Switched R-F Ref" GCGND TO FET DRIVERS A A 3 "GCGND" "EXT SINE IN" TL38 TL33 GCGND 3.6MHz corner, 20dB/decade. GCGND 2 8-10 Volts P-P+ 2.5 Volt Offset. "DDS BUF" TL14 EXTERNAL SINE REF INPUT 2 +5V=EXT SINE 0V =DDS OUT "SINE SEL" TL34 GCGND P-3, /TOP_COVER_RF_HV_ON C99 C35 1uF 0.1 50V +5VA_GC GCGND P-13, P-4,11,12,13, H-V SINE REF DISABLE P-11,12,13, -13V_GC GCGND C149 GCGND GCGND GCGND GCGND GCGND +5VA_GC "DDS" P-13, C38 .01UF "DGND" 0.0 R202 4MA MAX NOM R183 150 GCGND +13V_GC DDS_RF_DC -13V_GC P-11,12,13, P-11,12,13, DDS_RF_AC R284 10K 0.1 50V i2 R201 100 1206 R83 100 1206 GCGND GCGND 0.1 50V C97 GCGND GCGND +5VA_GC 16 14 nc c2 2 3 no c1 15 i1 1 C98 1uF IOUT ADG413BR U41A 14 1 FS ADJ 2 REFIN 3 REFOUT 6 MCLK 7 SCLK 8 SDATA FSYNC 9 FSEL 10 PSEL0 11 PSEL1 12 COMP 16 C34 .01UF U24 R175 1K 0805 C27 R176 1K 0805 10pF DDS R80 4.99K 0603 C102 .01UF AD9832BRU TSSOP16 TL16 R68 150 0.0 R81 TL17 0.0 R206 R70 100 1206 2 3 C95 0.1 50V - 1 + U19A AD826AR C148 0.1 50V 6 5 AD826AR 8 - + 4 7 U19B DVDD 4 5 DGND 13 AVDD AGND 15 TL36 TL37 R285 10K 8 4 6 no 11 nc U41B ADG413BR i2 8 c2 7 c1 10 i1 9 R290 10K "+5V" TL39 GCGND +5V P-3,4,6,7,8,9,15, DDS_RF_AC_SW 1 GCGND P-11,12,13, +13V_GC DDS R-F FREQUENCY GENERATOR <strong>Thermo</strong> 355 River Oaks Pkwy, San Jose, CA 95134-1991 ELECTRON CORPORATION Title Size Document Number Rev B C150 0.1 50V GND 5 VSS 4 VCC 12 VDD 13 SCH, TOP COVER BOARD C151 0.1 50V 97055-91040 D Date: Wednesday, July 27, 2005 Sheet 10 of 17 1
FROM PAGE 5 P-5, P-5, M1_DC M0_DC 5 M1_DC M0_DC 5 M1_DC_FILT 4 M0_DC_FILT 4 3 D D P-5, M00_DC M00_DC RFGND +13V_GC GCGND P-15, +36V_FUSED P-4, +36V FUSEHOLDER Q4 FH1 F1 CURRENT SENSE R R151 R152 1A SB C80 +36V_FUSED M1_BIAS_DC M0_BIAS_DC M00_BIAS_DC + C C 2.75 MHz NOM 10V P-P MAX P-10, R-F_OSC P-12, R-F_MOD_DRIVE REFERENCED TO GCGND -13V_GC 22p C37 +13V_GC C20 GCGND GCGND +36V_RET P-4,12,15, B + B CERFEED-4 ORIENTATION: VIEW FROM TOP OF PCB WITH PCB IN THE UPRIGHT POSITION. 3 4 GCGND -13V_GC GCGND RFGND +36V_RET +36V_RET A A 2 1 +36V_RET L6 100UH,choke .01UF, SMT, 1KV C24 RANGE = +/-150V RANGE = +/-150V 1K R69 1K R77 1K R45 1K R46 681 R47 0.1 50V C32 2 - 3 2 3 P-4,12,15, +36V_RET 22p C33 1K R73 1K R76 22p C17 7 - 4 7 4 1K R44 0.1 50V U10 6 AD847 0.1 50V C22 U20 6 AD847 "Q4_DRV" TL19 GCGND L4 100UH,choke GCGND 100UH,choke RANGE = +/-150V .01UF, SMT, 1KV R67 51.1 1/8W L5 "G" TL21 TL22 "S" R48 51.1 1/8W "Q3_DRV" TL26 P-4,10,12,13, GCGND TL18 "D" TL24 "D" TL25 "G" C19 C36 IRFR420A 1 Q3 0.1 50V 1 L3 100UH,choke RFGND L1 L2 100UH,choke 100UH,choke M00_DC_FILT 1 4 3 IRFR420A 4 3 .01UF, SMT, 1KV C16 1 STOFF1 ST-OFF, 6-32, 2-7/8" STOFF2 ST-OFF, 6-32, 2-7/8" -13V_GC .01UF C81 .01UF LOCATE CAPS AT T1 PRIMARY PIN 5 -13V_GC P-10,12,13, C26 2.2uF 50V CER NSCW1 Nylon Screw, 6-32, 1",PH,PN NSPCR1 Nylon Spacer, #6ID, 5/8" STOFF3 ST-OFF, 6-32, 2-7/8" STOFF4 ST-OFF, 6-32, 2-7/8" +13V_GC 7 M1 8 M0 9 M00 4 PR1 6 PR2 PCT 5 +13V_GC P-10,12,13, 3 C18 .01UF, SMT, 1KV T1 Top Cover Board Xfmr Top Cover Board XFMR 3RD HARMONIC FILTER C'S ARE DETERMINED BY PADDING REQMT'S. L'S ARE TUNED FOR 3RD. NSCW2 Nylon Screw, 6-32, 1",PH,PN NSPCR2 Nylon Spacer, #6ID, 5/8" NUT1 NUT, 6-32 NUT2 NUT, 6-32 C23 .01UF, SMT, 1KV M0P 2 M1P 3 M00P 1 M1N 10 M0N 11 M00N 12 RFGND TL20 TL23 C40 SAT 10p 2.5KV C44 CERFEED-4 ORIENTATION: VIEW FROM TOP OF PCB WITH PCB IN THE UPRIGHT POSITION. 3 4 2 1 CONNECTOR MOUNTED ON BOTTOM SIDE. M00_AC+ M0_AC+ M1_AC+ M1_AC- M0_AC- M00_AC- L9 33uH (SAT: Select at test) RFGND P-4,5,15, RFGND P-4,5,15, 2 3 3 2 2 2 4 4 3 4 J7 2 1 1 1 RFGND SIGNAL PAIR (SAT: Select at test) RFGND RFGND (Note: HV CAP (C41,C44,C49,C50) S/B installed vertically) SCW1 Screw, 6-32, 1/4",PH SCW3 Screw, 6-32, 1/4",PH SCW2 SCW4 Screw, 6-32, 1/4",PH Screw, 6-32, 1/4",PH NUT3 NUT, 6-32 CVR3 LCVR3 NUT4 XFMR Cover Label, HV NUT, 6-32 XFMR Cover 3 3 2 2 4 4 3 4 J8 2 1 1 1 C45 SAT 33uH 10p 2.5KV C41 CVR2 COVER C49 2.2p 2.5KV M00_AC+_DET RFGND 1 RFGND R-F GENERATOR M00_AC-_DET RFGND RF_DET_I+ P-12, +36V_RET P-4,12,15, CURRENT_SENSE_R P-12, <strong>Thermo</strong> 355 River Oaks Pkwy, San Jose, CA 95134-1991 ELECTRON CORPORATION Title Size Document Number Rev B g 2 g 1 g 1 g 2 L10 C50 2.2p 2.5KV COVER CVR1 CR2A 6 1 5 2 MA121CT C123 .01UF CR2B SCH, TOP COVER BOARD TOP VIEW MA121CT 6 1 4 3 CR2, CR3 Note reversed pinout! CR1A CR1B R236 82.5 6 1 5 2 MA121CT L7 47UH 97055-91040 D Date: Wednesday, July 27, 2005 Sheet 11 of 17 1 C115 .01UF
- Page 1 and 2:
X Y Y X 90 o S3 S3 S3 Line Voltage
- Page 3 and 4:
SPI,VacOK, SYSRst, HVCTRL 5 5 4 4 3
- Page 5 and 6:
5 * ONLY +5.5 VCC USED ON THIS PAGE
- Page 7 and 8:
3 of 4 PWR REG, CONN 5 5 4 4 3 D D
- Page 9:
5 5 4 4 3 3 2 1 THIS DOCUMENT CONTA
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10 10 9 9 8 8 7 7 6 J J I I H H G G
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10 10 9 9 8 8 7 7 6 J J I I H H G G
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5 5 4 4 3 D D C C J1 CON6 1 2 3 4 5
- Page 18:
5 5 4 4 3 3 2 2 1 THIS DOCUMENT CON
- Page 21 and 22:
5 5 4 4 3 D D J1 CON6 1 2 3 4 5 6 Y
- Page 26 and 27:
A A B TP107 THIS DOCUMENT CONTAINS
- Page 28 and 29:
A A B +5V +5V C144 .01UF D D 1DIR S
- Page 30 and 31:
5 5 4 4 3 D CANARY_LED_FPGA_OUT [4]
- Page 32 and 33:
A Digital Valve Section A B +24V-AU
- Page 34 and 35:
A A B +11.75V +11.75V 4 SPARE GAS P
- Page 36 and 37:
A 4 TC- IS ALUMEL TC+ IS CHROMEL [1
- Page 38 and 39:
A A B ( 17.8 to 14.7 KHz ) +5V +15V
- Page 40 and 41:
A A -13.4V 8 4 B 6 6 C55 + + 1K .01
- Page 42 and 43:
5 5 4 4 3 +5V [18] /INJECT_WASTE_LE
- Page 44 and 45:
+60V A TP69 +24V-AUX +24V-AUX A B 4
- Page 46 and 47:
+5V D A A SHUTDOWN_BUF B 2DIR 4 [5]
- Page 48 and 49:
5 5 4 4 3 D CANARY_LED_FPGA_OUT [4]
- Page 50 and 51:
A A B 4 4 FROM FPGA SECTION Digital
- Page 52 and 53:
A A +11.75V B 4 7 + 5 4 - 6 +11.75V
- Page 54 and 55:
A A B 4 4 TC- IS ALUMEL TC+ IS CHRO
- Page 56 and 57:
A A B 4 4 3 3 +15VIN_IG C85 10uF 25
- Page 58 and 59:
A A -13.4V B 4 4 [11] [10] [12] [13
- Page 60 and 61:
[18] [18] +5V +5V 5 5 D D 4 4 3 D D
- Page 75 and 76:
5 5 4 4 ACQU_SP1_DR ACQU_SP1_RFS AC
- Page 77 and 78:
5 5 4 4 3 D D MALDI CABLE CONNECTOR
- Page 79 and 80:
5 5 4 4 3 D D C C B B A A 3 +5V FPG
- Page 81 and 82:
5 5 4 4 3 D D C C +3.3V VDDL ( ~ 2.
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PA[0:31] 5 5 4 4 3 D D TS211 TS214
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5 5 PPC_D[0:63] PPC_A[10:31] MODCK[
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5 RC RC24 D 6 RC 5 RC 100pF-47ohm R
- Page 89 and 90: 5 5 4 4 3 D D CLK_DDS_X3 DDS1_/WR D
- Page 91 and 92: 5 5 4 4 3 D D CLK_FPGA /SRESET /SYS
- Page 93 and 94: 5 5 4 4 3 D D IO_DIR IO_DIR 0 free
- Page 95 and 96: 5 5 4 4 3 D D L0D[0..3] L0ACK L0CLK
- Page 97 and 98: 5 SCAN_SP0_DT U25-1 DS90LV047A U27B
- Page 99 and 100: 5 5 4 4 L0D[0..3] L4D[0..3] 3 D D
- Page 101 and 102: 5 5 4 4 3 3 2 2 1 1 D D C C B B A A
- Page 103 and 104: 5 5 4 4 3 D TURBO POWER +24V Tgnd J
- Page 105: 5 5 4 4 3 3 2 2 1 1 D D C C B B A A
- Page 113 and 114: 5 4 3 2 1 D +5V (NOT LOADED) +/SYS_
- Page 115 and 116: 5 +3.3V 4 3 D +3.3V +3.3V D D D (3.
- Page 117 and 118: 5 4 3 2 1 D C B A [2,10] [3] [3,10]
- Page 119 and 120: 5 5 +150V -150V 4 4 3 D [6] LT_FRON
- Page 121 and 122: [5] FOUT_GT[0..11] FOUT_GT[0..11] 5
- Page 123 and 124: 5 5 4 4 3 R102 ENABLE TP13 /FORCE_8
- Page 125 and 126: 5 5 4 4 3 D D C 10K C ENABLE TTL LE
- Page 127 and 128: 5 4 3 [19] [19] 10K R348 ANALOG_IN1
- Page 129 and 130: 5 4 8 4 - + 3 +13.4V -2.5V_REF2 "8K
- Page 131 and 132: 5 P. C. B. TOP COVER TABLE OF CONTE
- Page 133 and 134: 5 4 CONNECTOR- SPI AND CONTROL 5 4
- Page 135 and 136: 5 LENS D-C FROM ANALOG BOARD 5 4 4
- Page 137 and 138: 5 5 4 4 3 D D (CONFIG DONE) IO_TDO
- Page 139: 5 PAGE 9 LOCAL POWER & UNUSED FPGA
- Page 143 and 144: 5 5 4 4 3 D D P-4,15,17, +15V C C +
- Page 145 and 146: 5 SIGNAL READBACKS MUX P-4,11,12, +
- Page 147 and 148: 5 5 4 P-4,13,15, +15V +13V_RDBK P-4
- Page 149 and 150: 5 AUXILIARY AC SIGNAL "WAMP" FROM A
- Page 151 and 152: 5 +5VISOL_EXT +5ISOL (2/3A) 1 2 (5/
- Page 153 and 154: 5 5 4 4 3 D D TP61 1 1 2 1 2 1 2 2
- Page 155 and 156: 5 5 4 4 3 D D (2/2A) (2/2A) AUXIN-
- Page 157 and 158: (4/3B,8/1A,8/1A) +18VLOCAL 5 5 4 4
- Page 159 and 160: 5 5 4 4 3 D D GND GND VCC_UNF CLK-
- Page 161 and 162: 5 5 4 4 3 D +5V D AGND [2,3] [3] DA
- Page 163 and 164: 5 5 +15V 4 4 3 - SEE PAGE 1 D +VDF
- Page 165 and 166: AGND 2 5 C37 1 100nF +5V 4 3 2 D [4
- Page 168 and 169: 5 5 4 4 CPU/Digital PCB L0_D[0..7]
- Page 170 and 171: 5 5 4 4 3 D D GND_EARTH J16 J15 C 1
- Page 172 and 173: 5 5 Source PCB 4 4 3 D D J1 A1 1 A2
- Page 189: THIS DOCUMENT CONTAINS PROPRIETARY