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5<br />
READBACK CONTROL & BUFFERED FPGA SPARES<br />
5<br />
SPARE_FPGA_OUT_1<br />
4<br />
4<br />
3<br />
D D<br />
C C<br />
FPGA 14 OF 15<br />
IO161<br />
top<br />
C16<br />
IO162 B16<br />
IO163 A16<br />
IO164 C15<br />
IO165 D14<br />
IO166 A15<br />
IO167 C14<br />
IO168 B14<br />
IO169 A14<br />
IO170 B13<br />
IO171 A13<br />
IO172 D12<br />
IO173 C12<br />
IO174 B12<br />
IO175 B11<br />
IO176 C11<br />
IO177 A11<br />
IO178 A10<br />
IO179 D10<br />
IO180 A9<br />
U30-14<br />
EPF6024ABC256<br />
PS_MUX_EN_FPGA_OUT<br />
10K<br />
DGND<br />
R171<br />
SPARE_B16_FPGA_OUT<br />
LENS_MUX_EN_FPGA_OUT<br />
B B<br />
RDBK_MUX_ADDR0<br />
RDBK_MUX_ADDR1<br />
RDBK_MUX_ADDR2<br />
/RDBK_ADC_CS<br />
DGND<br />
DGND<br />
+5V<br />
+5V<br />
DGND<br />
DGND<br />
10K<br />
R172<br />
10K R178<br />
DGND<br />
10K R181<br />
U17A<br />
+5V<br />
20<br />
U17G<br />
+5V<br />
U21B 3 17<br />
74HCT541<br />
DGND<br />
FPGA 7 OF 15<br />
10K R203<br />
DGND<br />
+5V<br />
IO21<br />
center left<br />
HV_ON_FPGA_OUT<br />
HV_ON_FPGA_OUT_BUF P-3,<br />
DGND<br />
DGND<br />
+5V<br />
U21D<br />
5 15<br />
DGND<br />
74HCT541<br />
DGND<br />
10K R193<br />
/ALTERA_RESET P-7,<br />
+5V DDS CONTROL<br />
U21E<br />
SPI_DDS_DATA_FPGA_OUT 6 14<br />
SPI_DDS_DATA_FPGA_OUT_BUF P-10,<br />
DGND<br />
74HCT541 +5V<br />
10K R189<br />
U21F<br />
DGND<br />
7 13<br />
SPI_DDS_CLOCK_FPGA_OUT_BUF P-10,<br />
DGND<br />
74HCT541<br />
10K R188<br />
DGND<br />
+5V<br />
/SPI_DDS_FSYNC_FPGA_OUT<br />
/SPI_DDS_FSYNC_FPGA_OUT_BUF P-10,<br />
DGND<br />
10K R190<br />
DGND<br />
H2<br />
IO22 H1<br />
IO23 J4<br />
IO24 J2<br />
IO25 J1<br />
IO26 K2<br />
IO27 K3<br />
IO28 K1<br />
IO29 L4<br />
IO30 M1<br />
IO31 M2<br />
IO32 M3<br />
IO33 M4<br />
IO34 N1<br />
IO35 N2<br />
IO36 N3<br />
IO37 P1<br />
IO38 P2<br />
IO39 R1<br />
IO40 R2<br />
U30-7<br />
EPF6024ABC256<br />
U21C<br />
4 16<br />
74HCT541<br />
10K R194<br />
U21G<br />
8 12<br />
74HCT541<br />
10K R174<br />
10K R179<br />
10K R184<br />
U17H<br />
DGND<br />
2 18<br />
74HCT541<br />
R170<br />
DGND<br />
4.99K<br />
10<br />
19<br />
1<br />
C90<br />
0.1 50V<br />
U17C<br />
4 16<br />
74HCT541<br />
9 11<br />
74HCT541<br />
8 12<br />
74HCT541<br />
A A<br />
+5V<br />
READBACK CONTROL<br />
DGND<br />
+5V<br />
P-3,4,6,7,9,10,15,<br />
10K<br />
R173<br />
3 17<br />
U17D<br />
5 15<br />
74HCT541<br />
U17E<br />
6 14<br />
74HCT541<br />
U17F<br />
7 13<br />
74HCT541<br />
DGND<br />
/ALTERA_RESET<br />
U17B<br />
74HCT541<br />
3<br />
FPGA 8 OF 15<br />
IO42 P4<br />
IO43 R3<br />
IO44 T2<br />
IO45 U2<br />
IO46 T4<br />
IO47 U3<br />
IO48 V2<br />
IO49 W1<br />
IO50 V3<br />
IO51 W2<br />
IO52 Y1<br />
IO53 W3<br />
IO54 Y2<br />
IO55 W4<br />
IO56 V4<br />
IO57 U5<br />
IO58 Y3<br />
IO59 Y4<br />
IO60 V5<br />
IO41 T1<br />
U30-8<br />
EPF6024ABC256<br />
lower left<br />
PS_MUX_EN_FPGA_OUT_BUF P-15,<br />
LENS_MUX_EN_FPGA_OUT_BUF P-14,<br />
RDBK_MUX_ADDR0_BUF P-14,15,<br />
RDBK_MUX_ADDR1_BUF P-14,15,<br />
RDBK_MUX_ADDR2_BUF P-14,15,<br />
/RDBK_ADC_CS_BUF P-16,<br />
/RDBK_ADC_CONV_BUF P-16,<br />
/RDBK_ADC_BUSY_FPGA_IN P-16,<br />
DGND P-3,4,6,7,9,10,15,<br />
DGND<br />
2<br />
10K<br />
R212<br />
2<br />
+5V<br />
C39<br />
0.1 50V<br />
U21A<br />
2 18<br />
74HCT541<br />
20<br />
10<br />
19<br />
1<br />
DGND<br />
DGND DGND<br />
4.99K<br />
R207<br />
READBACK CONTROL & BUFFERED FPGA SPARES<br />
1<br />
<strong>Thermo</strong> 355 River Oaks Pkwy, San Jose, CA 95134-1991<br />
ELECTRON CORPORATION<br />
Title<br />
Size Document Number Rev<br />
B<br />
SCH, TOP COVER BOARD<br />
97055-91040 D<br />
Date: Wednesday, July 27, 2005<br />
Sheet 8 of 17<br />
1
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