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5<br />
5<br />
4<br />
4<br />
3<br />
D D<br />
(CONFIG DONE)<br />
IO_TDO<br />
C C<br />
P-3,<br />
FPGA SUPPORT<br />
+3.3V_FPGA<br />
R228<br />
10K<br />
/SYS_RESET_BUF<br />
B B<br />
+3.3V_FPGA<br />
C144<br />
.01UF<br />
D<br />
DGND<br />
D<br />
D<br />
DGND<br />
+3.3V_FPGA<br />
/ALTERA_RESET<br />
+3.3V_FPGA<br />
D<br />
DGND<br />
+3.3V_FPGA<br />
/ALTERA_RESET<br />
DGND<br />
/ALTERA_RESET<br />
+5V<br />
+5V<br />
DGND<br />
CONFIG_CLK<br />
CONFIG_DATA<br />
/CONFIG_DONE_ANA_CNTRL<br />
CONFIG_STATUS<br />
A A<br />
C122<br />
.01UF<br />
D<br />
+3.3V_FPGA<br />
D<br />
D<br />
C110<br />
.01UF<br />
FPGA 2 OF 15<br />
R223<br />
10K<br />
D<br />
1K R268<br />
1K R267<br />
/SYS_RESET= FALSE (1)<br />
WITH NO J1 CONNECTOR.<br />
THIS IS THE 3.3V<br />
VERSION OF THE<br />
DS1233 !!!<br />
C135<br />
.01UF<br />
1K R266<br />
IO_TDO T17<br />
IO_TCK V1<br />
IO_TMS P3<br />
IO_TDI J3<br />
U30-2<br />
EPF6024ABC256<br />
C136<br />
.01UF<br />
U27C<br />
74HCT125<br />
9 8<br />
10<br />
S1<br />
1 3<br />
PTS645TL50<br />
C114<br />
.01UF<br />
C119<br />
.01UF<br />
D16<br />
1K<br />
GRN LED1<br />
U27B<br />
74HCT125<br />
5 6<br />
4<br />
3.3 VOLTS<br />
3<br />
VCC<br />
1<br />
GND GND 4<br />
RESET 2<br />
U38<br />
DS1233AZ-10<br />
C111<br />
1K R265<br />
0.1 50V<br />
C127<br />
.01UF<br />
C108<br />
.01UF<br />
"ICP"<br />
R271<br />
R269<br />
10K<br />
+3.3V_FPGA<br />
FPGA<br />
RESET<br />
CIRCUITRY<br />
FPGA 3 OF 15<br />
U30-3<br />
C13<br />
IO_nRS<br />
B15<br />
IO_nWS<br />
A17<br />
IO_CS<br />
B17<br />
IO_nCS<br />
G17<br />
IO_CLKUSR<br />
G20<br />
IO_RDYnBSY<br />
J19<br />
IO_INIT_DONE<br />
10K R231 C9<br />
A12<br />
DEV_CLRn<br />
DEV_OE<br />
10K R221<br />
EPF6024ABC256<br />
FPGA 1 OF 15<br />
Y11<br />
nCONFIG<br />
T3<br />
MSEL<br />
CONF_DONE E18<br />
nSTATUS W11<br />
DCLK C10<br />
DATA B10<br />
U30-1<br />
E1<br />
nCE<br />
V18<br />
nCEO<br />
EPF6024ABC256<br />
EPF6024ABC256 STD BGA<br />
pinout checked 12-29-99<br />
P-6, CANARY_CLOCK_FPGA_OUT<br />
C113<br />
0.1 50V<br />
C130<br />
.01UF<br />
C131<br />
.01UF<br />
C109<br />
.01UF<br />
P-8, /ALTERA_RESET<br />
TO FPGA INPUT<br />
C121<br />
.01UF<br />
C129<br />
0.1 50V<br />
C120<br />
.01UF<br />
C46<br />
.01UF<br />
+5V<br />
DGND<br />
C128<br />
0.1 50V<br />
C112<br />
.01UF<br />
DGND<br />
C145<br />
0.1 50V<br />
J9<br />
C106<br />
0.1 50V<br />
+5V<br />
DGND<br />
1<br />
1 2 2<br />
3<br />
3 4 4<br />
5<br />
5 6 6<br />
7<br />
7 8 8<br />
9<br />
9 10 10<br />
HEADER 5X2(FPGA)<br />
CANARY CLOCK COUNTER<br />
DGND<br />
DGND<br />
CANARY CLOCK INDICATES<br />
'HEALTHY' FPGA.<br />
3<br />
DGND<br />
FPGA 4 OF 15<br />
VCCINT1 D20<br />
VCCINT2 F3<br />
VCCINT3 K20<br />
VCCINT4<br />
A1<br />
D4 GND1<br />
D8 GND2<br />
D13 GND3<br />
GND4<br />
L2<br />
VCCIO1<br />
D17<br />
H4 GND5<br />
H17 GND6<br />
N4 GND7<br />
GND8<br />
D6<br />
VCCIO2 D11<br />
VCCIO3 D15<br />
VCCIO4 F4<br />
VCCIO5 F17<br />
VCCIO6 K4<br />
VCCIO7 L17<br />
VCCIO8 R4<br />
VCCINT5 T20<br />
VCCINT6 U1<br />
VCCIO9 R17<br />
VCCIO10 U6<br />
VCCIO11 U10<br />
VCCIO12 U15<br />
U30-4<br />
N17<br />
U4 GND9<br />
U8 GND10<br />
U13 GND11<br />
U17 GND12<br />
GND13<br />
EPF6024ABC256<br />
+3.3V_FPGA"CONFIG<br />
DONE"<br />
14<br />
D17<br />
GRN LED1<br />
2 3<br />
LED\1206<br />
7<br />
U27A<br />
74HCT125<br />
VCC 16<br />
3<br />
D1<br />
4<br />
D2<br />
6<br />
D3<br />
11<br />
D4<br />
13<br />
D5<br />
14<br />
D6<br />
9<br />
CLK<br />
1<br />
CLR<br />
GND<br />
8<br />
1<br />
Q1 2<br />
Q2 5<br />
Q3 7<br />
Q4 10<br />
Q5 12<br />
Q6 15<br />
R272<br />
1K<br />
U31<br />
MC74AHCT174<br />
FPGA_REGISTER_INIT<br />
R214<br />
1K<br />
R208<br />
1K<br />
GOES TO +5V AFTER<br />
CANARY COUNT.<br />
U22<br />
SU22<br />
PLCC20 SKT<br />
DGND<br />
/SHUTDOWN_UNBUF P-6,<br />
+3.3V_FPGA<br />
PLCC20 SKT<br />
2<br />
+3.3V_FPGA<br />
DGND<br />
J6<br />
C137<br />
.01UF<br />
C100<br />
.01UF<br />
4<br />
DCLK<br />
2<br />
8<br />
DATA<br />
OE<br />
nCS<br />
9<br />
VCC2/SER_EN 18<br />
VCC1 20<br />
GND 10<br />
nCASC 12<br />
EPC1441LC20<br />
HEADER 5X2(FPGA)<br />
1<br />
1<br />
2 2<br />
3<br />
3<br />
4 4<br />
5<br />
5 6 6 8<br />
7<br />
7<br />
8 10<br />
9<br />
9<br />
10<br />
2<br />
P-3,<br />
SPI_CLOCK_FPGA_IN<br />
U30-5<br />
L3<br />
GLOB_IN1<br />
FPGA_REGISTER_INIT L1<br />
GLOB_IN2<br />
L20<br />
P-3,<br />
GLOB_IN3<br />
K19<br />
/SPI_SELECT_FPGA_IN<br />
GLOB_IN4<br />
EPF6024ABC256<br />
+5V<br />
X1<br />
4<br />
VCC<br />
2<br />
DGND<br />
+5V<br />
GND<br />
DGND DGND<br />
FPGA_CLK<br />
20MHZ CRYSTAL OSCILLATOR<br />
DGND<br />
MMBT4403LT1<br />
NC(OE) 1<br />
2<br />
Q2<br />
3<br />
OUT 3<br />
1<br />
R197<br />
1K<br />
/ATMEL_FPGA_PROG<br />
+5V<br />
1<br />
P-6,9,<br />
P-3,4,6,8,9,10,15,<br />
P-3,4,6,8,9,10,15,<br />
TF D TTL<br />
P-10,<br />
DDSCLK_20MHZ_BUF<br />
DGND<br />
ADD JUMPER TO PROGRAM PART<br />
JMPR PAIR IS USED TO TRISTATE THE<br />
ALTERA PART WHEN DOING IN-SITU<br />
PROGRAMMING OF ATMEL FPGA<br />
CONFIGURATION EEPROM.<br />
R198<br />
10K<br />
R248<br />
10K<br />
+3.3V_FPGA<br />
+5V<br />
DGND<br />
+3.3V_FPGA<br />
+5V<br />
DGND<br />
<strong>Thermo</strong> 355 River Oaks Pkwy, San Jose, CA 95134-1991<br />
ELECTRON CORPORATION<br />
Title<br />
Size Document Number Rev<br />
B<br />
FPGA 5 OF 15<br />
74HCT125<br />
12 11<br />
13<br />
U27D<br />
R222<br />
10K<br />
TP9<br />
1<br />
1 "JMP to PGM"<br />
TP10<br />
1<br />
1 "JMP to PGM"<br />
SCH, TOP COVER BOARD<br />
97055-91040 D<br />
Date: Wednesday, July 27, 2005<br />
Sheet 7 of 17<br />
1
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