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5<br />
5<br />
4<br />
4<br />
3<br />
D D<br />
+36V P-4,11,<br />
+36V_RET P-4,11,12,15,<br />
+5V P-3,4,6,7,8,9,10,15,<br />
DGND P-3,4,6,7,8,9,10,15,<br />
+15V P-4,13,15,17,<br />
AGND P-4,13,15,17,<br />
-15V P-4,13,15,17,<br />
RFGND P-4,5,11,15,<br />
P-4,14,15,16,17,<br />
RDBKGND<br />
GCGND<br />
P-4,10,11,12,13,<br />
CONNECTORS SHEETS 3-5 FPGA SHEETS 6-9<br />
R-F GENERATION SHEETS 10-13<br />
/SYS_RESET_BUF<br />
SPI_CLOCK_FPGA_IN<br />
/SPI_SELECT_FPGA_IN<br />
SPI_MOSI_FPGA_IN<br />
SPI_MISO+<br />
SPI_MISO-<br />
/SYS_RESET_BUF<br />
SPI_CLOCK_FPGA_IN<br />
/SPI_SELECT_FPGA_IN<br />
SPI_MOSI_FPGA_IN<br />
SPI_MISO+<br />
SPI_MISO-<br />
/SYS_RESET_BUF<br />
SPI_CLOCK_FPGA_IN<br />
/SPI_SELECT_FPGA_IN<br />
SPI_MOSI_FPGA_IN<br />
SPI_MISO+<br />
SPI_MISO-<br />
SPI_DDS_CLOCK_FPGA_OUT_BUF<br />
/SPI_DDS_FSYNC_FPGA_OUT_BUF<br />
SPI_DDS_DATA_FPGA_OUT_BUF<br />
DDSCLK_20MHZ_BUF<br />
SPI_DDS_CLOCK_FPGA_OUT_BUF<br />
/SPI_DDS_FSYNC_FPGA_OUT_BUF<br />
SPI_DDS_DATA_FPGA_OUT_BUF<br />
DDSCLK_20MHZ_BUF<br />
SPI_DDS_CLOCK_FPGA_OUT_BUF<br />
/SPI_DDS_FSYNC_FPGA_OUT_BUF<br />
SPI_DDS_DATA_FPGA_OUT_BUF<br />
DDSCLK_20MHZ_BUF<br />
+36V<br />
+36V_RET<br />
+5V<br />
DGND<br />
+15V<br />
AGND<br />
-15V<br />
RFGND<br />
RDBKGND<br />
GCGND<br />
HV_ON_FPGA_OUT_BUF<br />
/HV_ON_OVERRIDE_FPGA_OUT_BUF<br />
C C<br />
P-3,4,6,7,8,9,10,15,<br />
DGND<br />
/TOP_COVER_RF_HV_ON<br />
M1_DC<br />
M0_DC<br />
M00_DC<br />
OCT_RF_SET<br />
OCT_RF_SET_REF<br />
B B<br />
M00_DC_RDBK<br />
IM0_LENS_DC_RDBK<br />
M0_DC_RDBK<br />
IM1_LENS_DC_RDBK<br />
SPLIT_LENS_DC_RDBK<br />
SPLITLENS_GATE_RDBK<br />
M1_DC_RDBK<br />
FRONT_LENS_DC_RDBK<br />
BACK_LENS_DC_RDBK<br />
LENS_RDBK_LOCAL_REF<br />
P-3,4,6,7,8,9,10,15,<br />
+5V<br />
DGND<br />
P-3,4,6,7,8,9,10,15,<br />
SHEETS 14-17<br />
A A<br />
CONNECTOR & I/O<br />
HV_ON_FPGA_OUT_BUF<br />
/HV_ON_OVERRIDE_FPGA_OUT_BUF<br />
/TOP_COVER_RF_HV_ON<br />
M1_DC<br />
M0_DC<br />
M00_DC<br />
OCT_RF_SET<br />
OCT_RF_SET_REF<br />
M00_DC_RDBK<br />
IM0_LENS_DC_RDBK<br />
M0_DC_RDBK<br />
IM1_LENS_DC_RDBK<br />
SPLIT_LENS_DC_RDBK<br />
SPLITLENS_GATE_RDBK<br />
M1_DC_RDBK<br />
FRONT_LENS_DC_RDBK<br />
BACK_LENS_DC_RDBK<br />
LENS_RDBK_LOCAL_REF<br />
HV_ON_FPGA_OUT_BUF<br />
RDBK_MUX_ADDR2_BUF<br />
RDBK_MUX_ADDR1_BUF<br />
RDBK_MUX_ADDR0_BUF<br />
/HV_ON_OVERRIDE_FPGA_OUT_BUF<br />
LENS_MUX_EN_FPGA_OUT_BUF<br />
PS_MUX_EN_FPGA_OUT_BUF<br />
FPGA<br />
READBACKS<br />
READBACKS<br />
+5V<br />
DGND<br />
M00_DC_RDBK<br />
IM0_LENS_DC_RDBK<br />
M0_DC_RDBK<br />
IM1_LENS_DC_RDBK<br />
SPLIT_LENS_DC_RDBK<br />
SPLITLENS_GATE_RDBK<br />
M1_DC_RDBK<br />
FRONT_LENS_DC_RDBK<br />
BACK_LENS_DC_RDBK<br />
LENS_RDBK_LOCAL_REF<br />
/RDBK_ADC_CS_BUF<br />
/RDBK_ADC_CONV_BUF<br />
SPI_ADC_CLOCK_FPGA_OUT_BUF<br />
/RDBK_ADC_BUSY_FPGA_IN<br />
SPI_ADC_DATA_FPGA_IN<br />
SPI_ADC_DATA_FPGA_IN<br />
/RDBK_ADC_BUSY_FPGA_IN<br />
SPI_ADC_CLOCK_FPGA_OUT_BUF<br />
/RDBK_ADC_CONV_BUF<br />
/RDBK_ADC_CS_BUF<br />
PS_MUX_EN_FPGA_OUT_BUF<br />
LENS_MUX_EN_FPGA_OUT_BUF<br />
RDBK_MUX_ADDR0_BUF<br />
RDBK_MUX_ADDR1_BUF<br />
RDBK_MUX_ADDR2_BUF<br />
RF_LEVEL_RDBK<br />
RF_LEVEL_RDBK_REF<br />
RF_MOD_RDBK<br />
RF_MOD_RDBK_REF<br />
PRI_RF_AMPS_RDBK<br />
PRI_RF_AMPS_RDBK_REF<br />
+36V_FUSED<br />
+36V_RET<br />
+15V<br />
AGND<br />
-15V<br />
+5V<br />
DGND<br />
RFGND<br />
RDBKGND<br />
P-4,11,12,15,<br />
+36V_RET<br />
3<br />
+15V<br />
AGND<br />
-15V<br />
+5V<br />
DGND<br />
RFGND<br />
RDBKGND<br />
P-4,13,15,17,<br />
SPI_ADC_DATA_FPGA_IN<br />
/RDBK_ADC_BUSY_FPGA_IN<br />
SPI_ADC_CLOCK_FPGA_OUT_BUF<br />
/RDBK_ADC_CONV_BUF<br />
/RDBK_ADC_CS_BUF<br />
PS_MUX_EN_FPGA_OUT_BUF<br />
LENS_MUX_EN_FPGA_OUT_BUF<br />
P-4,13,15,17,<br />
P-4,13,15,17,<br />
P-3,4,6,7,8,9,10,15,<br />
P-3,4,6,7,8,9,10,15,<br />
P-4,5,11,15,<br />
P-4,14,15,16,17,<br />
RF_LEVEL_RDBK<br />
2<br />
RDBK_MUX_ADDR0_BUF<br />
RDBK_MUX_ADDR1_BUF<br />
RDBK_MUX_ADDR2_BUF<br />
RF_LEVEL_RDBK_REF<br />
RF_MOD_RDBK<br />
RF_MOD_RDBK_REF<br />
RF_AMPS_RDBK<br />
RF_AMPS_RDBK_REF<br />
+36V_FUSED<br />
2<br />
/TOP_COVER_RF_HV_ON<br />
M1_DC<br />
M0_DC<br />
M00_DC<br />
OCT_RF_SET<br />
OCT_RF_SET_REF<br />
MULTIPOLE R-F<br />
P-4,10,11,12,13,<br />
P-4,5,11,15,<br />
P-4,13,15,17,<br />
P-4,13,15,17,<br />
P-4,13,15,17,<br />
P-3,4,6,7,8,9,10,15,<br />
P-4,11,<br />
P-4,11,12,15,<br />
INTERCONNECTS<br />
1<br />
Date: Wednesday, July 27, 2005<br />
Sheet 2 of 17<br />
1<br />
GCGND<br />
RFGND<br />
-15V<br />
AGND<br />
+15V<br />
+5V<br />
+36V<br />
+36V_RET<br />
<strong>Thermo</strong> 355 River Oaks Pkwy, San Jose, CA 95134-1991<br />
ELECTRON CORPORATION<br />
Title<br />
Size Document Number Rev<br />
B<br />
RF_LEVEL_RDBK<br />
RF_LEVEL_RDBK_REF<br />
RF_MOD_RDBK<br />
RF_MOD_RDBK_REF<br />
GCGND<br />
RFGND<br />
-15V<br />
AGND<br />
+15V<br />
DGND<br />
+5V<br />
+36V<br />
+36V_RET<br />
+36V_FUSED<br />
PRI_RF_AMPS_RDBK<br />
PRI_RF_AMPS_RDBK_REF<br />
SCH, TOP COVER BOARD<br />
97055-91040 D
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