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5 5 +13.4V 4 4 3 D [19] [19] RF_SET_PT_RB 1M R3 RF_MOD_RB 1M R5 2 3 6 5 1 -13.4V +13.4V 7 -13.4V +13.4V RF_SETPT_RDBK U46A LT1014 RF_MOD_RDBK U46B 0 to 5v LT1014 [18] [18] [19] [19] +18V_RB 1M R18 -18V_RB 2 +18V_RDBK [18] 1 3 U36A V x 0.196 (5.5v nom) TLE2142 +13.4V -13.4V 6 -18V_RDBK [18] 7 5 H1 HEATSINK,PA94 1 2 LGND LGND D [19] RF_DET_RB 1M 11 12 10 -13.4V RF_DET_RDBK U46C LT1014 [18] 1M R20 U36B TLE2142 +13.4V V x 0.196 (-5.5v nom) H2 R7 +13.4V 4 1 [19] DET_TEMP_RB 15 14 16 DET_TEMP_RDBK [18] 1M R8 U46D LT1014 -13.4V Vout = 2 x (1.375v + (22.5mV/C) x T ) +13.4V -13.4V C C [19] +28V_V_RB 1M R9 2 3 1 -13.4V U45A LT1014 +28V_V_RDBK V x 0.258 ( 7.2V nom) [18] 3 2 [19] [6,18] [19] +28V_CURR_RB +2.5V_REF RF_TEMP +13.4V -13.4V +13.4V -13.4V +28V_CURR_RDBK 0v ~ 0 deg C B B 1 AD592 3 -15V RF GEN ASSY 1M R269 6 5 R252 10k R253 100K [15] 13 4 - + 13 4 - + 13 4 - + 13 4 - + 13 4 - + 13 4 - + 7 11 12 10V_REF 13 4 - + U45B LT1014 R254 100K 10 15 14 13 4 - + +13.4V 16 -13.4V [18] 6amp approx. = 5v RF_TEMP_RDBK [18] U45C LT1014 U45D LT1014 100mV/deg C R265 49.9 FS_CAL [18] 8 4 - + 8 4 - + A A 3 MISC. HARDWARE HEATSINK,PA85/19 2 2 1 <strong>Thermo</strong> 355 River Oaks Pkwy, San Jose, CA 95134-1991 ELECTRON CORPORATION Title SCH, PCB, ANALOG BORD, LT Size B Document Number 97055-91030 Rev B Date: Friday, April 07, 2006 Sheet 17 of 19 1
5 4 8 4 - + 3 +13.4V -2.5V_REF2 "8KV1 TO FRONT TP IRBK" "8KV1 VRBK" TO FRONT TP [5] [5] [5] [5] [5] MUX_A3_FPGA_OUT MUX_A2_FPGA_OUT MUX_A1_FPGA_OUT MUX_A0_FPGA_OUT MUX1_ENABLE_FPGA_OUT +13.4V -13.4V -13.4V +13.4V 2 1 3 LT1014 -13.4V U79A +13.4V -2.5V_REF2 R383 [6] D C [11,19] 8KV1_V_RDBK [11,19] 8KV1_I_RDBK [12] 8KV2_V_RDBK 8KV2_I_RDBK [12] [13,19] EMULT1_V_RDBK [14] EMULT2_V_RDBK [13] DYNODE_RDBK AMBIENT_TEMP_RBK [16] [15] WFRM_RFAMP_RDBK [17] RF_SETPT_RDBK [17] RF_MOD_RDBK RF_DET_RDBK [17] DET_TEMP_RDBK [17] +28V_V_RDBK [17] +28V_CURR_RDBK [17] RF_TEMP_RDBK [17] TO FRONT TP "EM1 VRBK TP31 MUX_A3_FPGA_OUT [5] MUX_A2_FPGA_OUT [5] MUX_A1_FPGA_OUT [5] MUX_A0_FPGA_OUT [5] MUX2_ENABLE_FPGA_OUT [5] [16] CAP_DC_RDBK [16] SKIMMER_DC_RDBK M00_DC_RDBK [16] [16] IM0_LENS_DC_RDBK [16] M0_DC_RDBK [16] IM1_LENS_DC_RDBK [16] M1_DC_RDBK FRONT_LENS_DC_RDBK [16] [16] -28VRF_RDBK +36VRF_RDBK [16] +13.4V -13.4V -13.4V +13.4V +13.4V -13.4V +13.4V -13.4V -13.4V 2 1 3 U85A TLE2142 +13.4V TP83 [5] /ADS7813_CS_FPGA_OUT [3] ADS7813_DATACLK_BUF [16] ANALOG_IN1_RET +13.4V +13.4V -13.4V +13.4V + -13.4V 6 0.0 C42 7 5 10uF 25V R386 U79B -13.4V LT1014 A_RBK Is = 7mA +5V_ADC A_RBK /ADS7813_BUSY_FPGA_IN [5] /ADS7813_CONV_FPGA_OUT [5] +5V_ADC ADS7813_DATA_FPGA_IN [5] 15 14 11 0.0 10 -2.5V_REF3 12 [6,10] D U79C -13.4V LT1014 -2.5V_REF [6] +2.5V_REF [6,17] +2.5V_REF2 +2.5V_REF2 [6] +13.4V 16 +2.5V_REF3 [6,10] U79D -13.4V LT1014 C [16] [8] ANALOG_IN2_RET R417 LT_FRT_DC_RB_RET C45 + TANT 1uF 25V B C166 .1UF TP38 [5] MUX_A3_FPGA_OUT [5] MUX_A2_FPGA_OUT TP42 [5] MUX_A1_FPGA_OUT [5] MUX_A0_FPGA_OUT MUX3_ENABLE_FPGA_OUT [5] [8] LT_FRONT_DC_RDBK [8] LT_CENTER_DC_RDBK [8] LT_BACK_DC_RDBK [8] BACK_LENS_DC_RDBK [16] TUBEGATE_RDBK SPLIT_LENS_DC_RDBK [16] SPLIT_LENS_GATE_RDBK [16] [16] SGATE-SDC [16] ANALOG_IN1+_RBK [16] ANALOG_IN2+_RBK [16] +5V_DAC_RDBK [16] -5V_DAC_RDBK [16] +5V_ADC_RBK OCT_RF_SET_RDBK [16] +18V_RDBK [17] -18V_RDBK [17] +13.4V -13.4V [8] [8] [16] A_RBK STRADDLES ARET TO A_RBK SPLIT PLANES LT_CNT_DC_RB_RET LT_BCK_DC_RB_RET SPDIF_RET 0.0 R415 LOCATE LOCATE CLOSE CLOSE TO TOPIN PIN 7 6 A_RBK 0.0 R394 A_RBK A_RBK SERIAL 16 BIT A/D CONVERTER -13.4V B 0.0 1000pF C152 R405 0.0 R380 0.0 R417 0.0 C253 .1UF 14 A3 15 A2 V+ 1 16 A1 18 EN 4 S16 NC1 3 NC2 13 GND TP46 12 17 A0 V- 27 5 S15 7 S13 9 S11 DOUT 28 S14 6 8 S12 10 S10 11 S9 20 S2 S3 21 S4 22 S5 25 S7 23 S8 0.0 R396 TP26 14 A3 15 A2 V+ 1 16 A1 18 EN 4 S16 NC1 3 NC2 13 GND TP47 TP81 6 7 5 U80B LT1014 R384 10K TP80 TP93 C252 .01UF TP44 NC3 2 26 24 U37 S6 19 S1 TP49 DG506 0.0 R416 R393 0.0 12 17 A0 V- 27 5 S15 7 S13 9 S11 DOUT 28 S14 6 8 S12 10 S10 11 S9 20 S2 S3 21 S4 22 S5 25 S7 23 S8 TP39 TP30 C169 .1UF C170 .1UF .1UF C250 .1UF C249 C163 .1UF TP36 TP41 NC3 2 26 24 S6 TP33 U35 TP32 19 S1 C164 .1UF .1UF C208 15 16 14 U80D LT1014 C251 .1UF .1UF .1UF C240 R385 10K 0.0 R378 C241 .1UF 10uF 25V C43 .1UF C242 1 R1IN VS 3 R2IN 4 R3IN 13 CS 2 GND 0.0 R397 R398 0.0 TP37 DG506 C44 TANT + 1uF 25V TP35 C165 .1UF R31 5.6 0.0 R414 R418 0.0 16 PWRD 15 BUSY 14 CONV 12 EXT_/INT 11 DATA 10 9 DATACLK REF 7 8 GND CAP 6 14 A3 15 A2 16 A1 18 EN V+ 1 4 S16 NC1 3 NC2 13 GND TP40 R277 511 R392 10K TP82 5 BUF ADS7813 U81 TP103 12 17 A0 V- 27 5 S15 7 S13 9 S11 DOUT 28 S14 6 8 S12 10 S10 11 S9 20 S2 S3 21 S4 22 S5 25 S7 23 S8 NC3 2 26 24 U39 S6 19 S1 DG506 TP27 .1UF C139 R413 0.0 R377 0.0 11 10 12 U80C LT1014 TP28 A TP23 TP21 TP22 TP24 [5] MUX_A3_FPGA_OUT [5] MUX_A2_FPGA_OUT [5] MUX_A1_FPGA_OUT [5] MUX_A0_FPGA_OUT [5] MUX4_ENABLE_FPGA_OUT [16] 5VPS_RBK [16] P15VPS_RBK [16] N15VPS_RBK [16] 24VPS_RBK [16] N28VPS_RBK [16] P36VPS_RBK -150VPS_V_RBK [16] +150VPS_V_RBK [16] TP34 TP29 14 A3 15 A2 16 A1 18 EN 4 S16 C167 .1UF V+ 1 NC1 3 NC2 13 C168 .1UF +13.4V -13.4V [19] R399 0.0 HELIUM_PRS_RB +13.4V -13.4V -2.5V_REF2 -2.5V_REF2 [6] [1,16] +2.5V_REF2 +2.5V_REF2 [6] -2.5V_REF3 +5V_ADC +5V_ADC READBACKS 6 7 5 U85B R419 TLE2142 10K +13.4V spare A [16] [16] [16] [17] -300VPS_V_RBK +300VPS_V_RBK 24V_TURBO_PS_RBK FS_CAL TP45 TP43 GND MULTIPLEXERS HELIUM_PRS_RDBK -2.5V_REF3 [6,10] +2.5V_REF3 +2.5V_REF3 [6,10] <strong>Thermo</strong> 355 River Oaks Pkwy, San Jose, CA 95134-1991 ELECTRON CORPORATION Title SCH, PCB, ANALOF BOARD, LT Size Document Number Rev B 97055-91030 B Date: Friday, April 07, 2006 Sheet 18 of 19 5 4 3 2 1 12 17 A0 5 S15 7 S13 9 S11 V- 27 DOUT 28 S14 6 8 S12 10 S10 11 S9 20 S2 S3 21 S4 22 S5 25 S7 23 S8 NC3 2 2 3 1M R400 U80A LT1014 1 R264 0.0 26 24 S6 U38 19 S1 DG506 13 4 - + 13 4 - + 13 4 - + + 2 13 4 - + 13 4 - + 13 4 - + 13 4 - + 13 4 - + 1 8 4 - +
Page 1 and 2:
X Y Y X 90 o S3 S3 S3 Line Voltage
Page 3 and 4:
SPI,VacOK, SYSRst, HVCTRL 5 5 4 4 3
Page 5 and 6:
5 * ONLY +5.5 VCC USED ON THIS PAGE
Page 7 and 8:
3 of 4 PWR REG, CONN 5 5 4 4 3 D D
Page 9:
5 5 4 4 3 3 2 1 THIS DOCUMENT CONTA
Page 12 and 13:
10 10 9 9 8 8 7 7 6 J J I I H H G G
Page 14 and 15:
10 10 9 9 8 8 7 7 6 J J I I H H G G
Page 16 and 17:
5 5 4 4 3 D D C C J1 CON6 1 2 3 4 5
Page 18:
5 5 4 4 3 3 2 2 1 THIS DOCUMENT CON
Page 21 and 22:
5 5 4 4 3 D D J1 CON6 1 2 3 4 5 6 Y
Page 26 and 27:
A A B TP107 THIS DOCUMENT CONTAINS
Page 28 and 29:
A A B +5V +5V C144 .01UF D D 1DIR S
Page 30 and 31:
5 5 4 4 3 D CANARY_LED_FPGA_OUT [4]
Page 32 and 33:
A Digital Valve Section A B +24V-AU
Page 34 and 35:
A A B +11.75V +11.75V 4 SPARE GAS P
Page 36 and 37:
A 4 TC- IS ALUMEL TC+ IS CHROMEL [1
Page 38 and 39:
A A B ( 17.8 to 14.7 KHz ) +5V +15V
Page 40 and 41:
A A -13.4V 8 4 B 6 6 C55 + + 1K .01
Page 42 and 43:
5 5 4 4 3 +5V [18] /INJECT_WASTE_LE
Page 44 and 45:
+60V A TP69 +24V-AUX +24V-AUX A B 4
Page 46 and 47:
+5V D A A SHUTDOWN_BUF B 2DIR 4 [5]
Page 48 and 49:
5 5 4 4 3 D CANARY_LED_FPGA_OUT [4]
Page 50 and 51:
A A B 4 4 FROM FPGA SECTION Digital
Page 52 and 53:
A A +11.75V B 4 7 + 5 4 - 6 +11.75V
Page 54 and 55:
A A B 4 4 TC- IS ALUMEL TC+ IS CHRO
Page 56 and 57:
A A B 4 4 3 3 +15VIN_IG C85 10uF 25
Page 58 and 59:
A A -13.4V B 4 4 [11] [10] [12] [13
Page 60 and 61:
[18] [18] +5V +5V 5 5 D D 4 4 3 D D
Page 75 and 76:
5 5 4 4 ACQU_SP1_DR ACQU_SP1_RFS AC
Page 77 and 78: 5 5 4 4 3 D D MALDI CABLE CONNECTOR
Page 79 and 80: 5 5 4 4 3 D D C C B B A A 3 +5V FPG
Page 81 and 82: 5 5 4 4 3 D D C C +3.3V VDDL ( ~ 2.
Page 83 and 84: PA[0:31] 5 5 4 4 3 D D TS211 TS214
Page 85 and 86: 5 5 PPC_D[0:63] PPC_A[10:31] MODCK[
Page 87 and 88: 5 RC RC24 D 6 RC 5 RC 100pF-47ohm R
Page 89 and 90: 5 5 4 4 3 D D CLK_DDS_X3 DDS1_/WR D
Page 91 and 92: 5 5 4 4 3 D D CLK_FPGA /SRESET /SYS
Page 93 and 94: 5 5 4 4 3 D D IO_DIR IO_DIR 0 free
Page 95 and 96: 5 5 4 4 3 D D L0D[0..3] L0ACK L0CLK
Page 97 and 98: 5 SCAN_SP0_DT U25-1 DS90LV047A U27B
Page 99 and 100: 5 5 4 4 L0D[0..3] L4D[0..3] 3 D D
Page 101 and 102: 5 5 4 4 3 3 2 2 1 1 D D C C B B A A
Page 103 and 104: 5 5 4 4 3 D TURBO POWER +24V Tgnd J
Page 105: 5 5 4 4 3 3 2 2 1 1 D D C C B B A A
Page 113 and 114: 5 4 3 2 1 D +5V (NOT LOADED) +/SYS_
Page 115 and 116: 5 +3.3V 4 3 D +3.3V +3.3V D D D (3.
Page 117 and 118: 5 4 3 2 1 D C B A [2,10] [3] [3,10]
Page 119 and 120: 5 5 +150V -150V 4 4 3 D [6] LT_FRON
Page 121 and 122: [5] FOUT_GT[0..11] FOUT_GT[0..11] 5
Page 123 and 124: 5 5 4 4 3 R102 ENABLE TP13 /FORCE_8
Page 125 and 126: 5 5 4 4 3 D D C 10K C ENABLE TTL LE
Page 127: 5 4 3 [19] [19] 10K R348 ANALOG_IN1
Page 131 and 132: 5 P. C. B. TOP COVER TABLE OF CONTE
Page 133 and 134: 5 4 CONNECTOR- SPI AND CONTROL 5 4
Page 135 and 136: 5 LENS D-C FROM ANALOG BOARD 5 4 4
Page 137 and 138: 5 5 4 4 3 D D (CONFIG DONE) IO_TDO
Page 139 and 140: 5 PAGE 9 LOCAL POWER & UNUSED FPGA
Page 141 and 142: FROM PAGE 5 P-5, P-5, M1_DC M0_DC 5
Page 143 and 144: 5 5 4 4 3 D D P-4,15,17, +15V C C +
Page 145 and 146: 5 SIGNAL READBACKS MUX P-4,11,12, +
Page 147 and 148: 5 5 4 P-4,13,15, +15V +13V_RDBK P-4
Page 149 and 150: 5 AUXILIARY AC SIGNAL "WAMP" FROM A
Page 151 and 152: 5 +5VISOL_EXT +5ISOL (2/3A) 1 2 (5/
Page 153 and 154: 5 5 4 4 3 D D TP61 1 1 2 1 2 1 2 2
Page 155 and 156: 5 5 4 4 3 D D (2/2A) (2/2A) AUXIN-
Page 157 and 158: (4/3B,8/1A,8/1A) +18VLOCAL 5 5 4 4
Page 159 and 160: 5 5 4 4 3 D D GND GND VCC_UNF CLK-
Page 161 and 162: 5 5 4 4 3 D +5V D AGND [2,3] [3] DA
Page 163 and 164: 5 5 +15V 4 4 3 - SEE PAGE 1 D +VDF
Page 165 and 166: AGND 2 5 C37 1 100nF +5V 4 3 2 D [4
Page 168 and 169: 5 5 4 4 CPU/Digital PCB L0_D[0..7]
Page 170 and 171: 5 5 4 4 3 D D GND_EARTH J16 J15 C 1
Page 172 and 173: 5 5 Source PCB 4 4 3 D D J1 A1 1 A2
Page 189:
THIS DOCUMENT CONTAINS PROPRIETARY
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