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5<br />
5<br />
+5V<br />
4<br />
4<br />
3<br />
D<br />
C73<br />
.01UF<br />
[6,19]<br />
EMULT1_OUTPUT_SET 10K<br />
D<br />
TP8<br />
-75ma<br />
[5] DYN_NEG_FPGA_OUT<br />
1=NEG 0=POS<br />
D<br />
14<br />
1<br />
2<br />
7<br />
U5A 3<br />
R98<br />
1K<br />
+5V<br />
0=NEG 1=POS<br />
(0=NEGATIVE, 1=POSITIVE)<br />
SET_DYNODE_POSITIVE<br />
[19]<br />
+5V<br />
D<br />
D<br />
U5C<br />
[3] ENABLE_EM1_PROTECT_BUF<br />
14<br />
14<br />
4<br />
9<br />
ENABLE_EMULT1_PROTECT<br />
TO ELECTRON<br />
U5B 6<br />
8<br />
[19]<br />
5<br />
10<br />
MULTIPLIER<br />
7<br />
7<br />
74AHCT00<br />
R89<br />
SUPPLY<br />
C C<br />
74AHCT00<br />
10K<br />
[3]<br />
[2,11,12,14]<br />
ENABLE<br />
TTL LEVELS DISABLE<br />
[3] EMULT1_ON_BUF<br />
DYN_ON_BUF<br />
HV_ENABLED<br />
10K R100<br />
R90<br />
D<br />
-13.4V<br />
10K<br />
B B<br />
TO 16<br />
BIT<br />
A/D<br />
TO 16<br />
BIT<br />
A/D<br />
1=SW ON HV OUTPUT<br />
0=SW OFF HV OUTPUT<br />
ENABLE<br />
[18,19]<br />
[18]<br />
OFF<br />
EMULT1_V_RDBK<br />
DYNODE_RDBK<br />
74AHCT00<br />
14<br />
4<br />
5<br />
7<br />
U6B<br />
6<br />
74AHCT00<br />
C72<br />
.01UF<br />
14<br />
12<br />
13<br />
7<br />
U5D<br />
11<br />
74AHCT00<br />
R22<br />
+13.4V<br />
0=HV ON<br />
1=HV OFF<br />
14<br />
1<br />
2<br />
7<br />
U6A<br />
0 to -2.5KV = 0 to -5V READBACK<br />
C133<br />
.1UF<br />
-13.4V<br />
C141 .1UF<br />
3<br />
74AHCT00<br />
14<br />
9<br />
10<br />
7<br />
7<br />
1<br />
U6C<br />
U23B<br />
TLE2142<br />
-13.4V<br />
8 4<br />
-<br />
+<br />
8<br />
6<br />
5<br />
+13.4V<br />
TP11<br />
1<br />
74AHCT00<br />
EMULT_DAC<br />
0 to -10V --> 0 to -2500v<br />
TP10<br />
1<br />
15KV_DYN_RDBK<br />
A A<br />
3<br />
1=ON<br />
0=OFF<br />
1=ON<br />
0=OFF<br />
+13.4V<br />
1=HV ON<br />
0=HV OFF<br />
1M<br />
R223<br />
1M<br />
R382<br />
DYNODE & MULTIPLIER #1 POWER SUPPLY CONTROL<br />
1<br />
U23A<br />
TLE2142<br />
8 4<br />
-<br />
+<br />
2<br />
3<br />
TP9<br />
1<br />
1M<br />
R234<br />
D<br />
1M<br />
R233<br />
TO FRONT TP<br />
"EM1_VSET"<br />
D<br />
2<br />
R99<br />
10K<br />
2<br />
D<br />
EMULT1_OUTPUT_SET [6,19]<br />
ENABLE_DYNODE<br />
ENABLE_EMULT1<br />
EMULT1_OUTPUT_V_RDBK<br />
15KV_DYN_RDBK<br />
[19]<br />
[19]<br />
[19]<br />
[19]<br />
1<br />
<strong>Thermo</strong> 355 River Oaks Pkwy, San Jose, CA 95134-1991<br />
ELECTRON CORPORATION<br />
Title<br />
SCH, PBC, ANALOG BOARD, LT<br />
Size B<br />
Document Number 97055-91030<br />
Rev<br />
B<br />
Date: Friday, April 07, 2006<br />
Sheet 13 of 19<br />
1
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