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5<br />

4<br />

3<br />

R96<br />

ENABLE<br />

TP7<br />

/FORCE_8KV1_ON<br />

10K<br />

+5V<br />

SOURCE COVER uSW<br />

CONTROLLED POWER<br />

TTL LEVELS DISABLE<br />

14<br />

ENABLE =1<br />

D<br />

[3] 8KV1_ON_BUF<br />

[2,12,13,14] HV_ENABLED<br />

14<br />

4<br />

5<br />

7<br />

U4B 6<br />

74AHCT00<br />

1<br />

2<br />

7<br />

U4A 3<br />

74AHCT00<br />

R439<br />

1K D18 "8KV EN"<br />

R97<br />

10K<br />

D<br />

8KV1_ENABLED [19]<br />

D<br />

"8KV1_VSET"<br />

GRN LED<br />

[6,19] 8KV1_V_SET<br />

CURRENT<br />

CONTROL<br />

0->10V=<br />

0->100uA<br />

POLARITY<br />

CONTROL<br />

C71<br />

C TTL1 = POS<br />

.01UF<br />

C<br />

TTL0 = NEG<br />

D<br />

14<br />

14<br />

[5]<br />

8KV1_POSITIVE_FPGA_OUT<br />

9<br />

10 U4C 8<br />

12<br />

13 U4D 11<br />

8KV1_POSITIVE [19]<br />

R88<br />

7<br />

7<br />

R87<br />

74AHCT00<br />

74AHCT00<br />

10K<br />

10K<br />

+13.4V<br />

D<br />

VOLTAGE<br />

READBACK<br />

0 to 8V =<br />

0 to 8KV<br />

[18,19] 8KV1_V_RDBK<br />

CURRENT<br />

READBACK<br />

0 to 10V =<br />

0 to 100uA<br />

8KV1_V_RDBK<br />

8KV1_V_SET<br />

B B<br />

[18,19] 8KV1_I_RDBK<br />

CONSTANT<br />

V/I MODE<br />

0=V MODE<br />

1=I MODE<br />

[5] 8KV1_IN_IMODE_FPGA_IN<br />

TO FRONT TP<br />

[6,19]<br />

0-10V DAC<br />

8KV1_I_SET<br />

CONSTANT CURRENT MODE<br />

TTL LEVELS<br />

0 to +8V=<br />

0 to 8KV<br />

8KV1_IN_IMODE_FPGA_IN<br />

R2<br />

10K<br />

0 to +10V=<br />

0 to 100uA<br />

D<br />

-13.4V<br />

CONSTANT VOLTAGE MODE<br />

3<br />

TO FRONT TP<br />

"8KV1_ISET"<br />

C137<br />

.01UF<br />

OPA2277<br />

1<br />

+ 3<br />

- 2<br />

U26A<br />

C142<br />

+<br />

4 8<br />

.01UF<br />

8KV1_I_RDBK<br />

U7A<br />

74AHCT08<br />

14<br />

1<br />

2<br />

7<br />

R6<br />

10K<br />

D<br />

R238 C145<br />

.01UF<br />

100k, 0.1%<br />

R101<br />

10K<br />

-13.4V<br />

-U26B -U26B<br />

7<br />

+13.4V<br />

8 4<br />

OPA2277<br />

D<br />

A A<br />

[2,12,13,14]<br />

[5]<br />

HV_ENABLED<br />

ENABLE_300VPS_FPGA_OUT<br />

14<br />

4<br />

5<br />

7<br />

U7B 6<br />

300VPS_EN<br />

[19]<br />

14<br />

9<br />

74AHCT08<br />

10<br />

7<br />

U7C 8<br />

<strong>Thermo</strong><br />

ELECTRON CORPORATION<br />

355 River Oaks Pkwy, San Jose, CA 95134-1991<br />

R92<br />

74AHCT08<br />

Title<br />

SCH, PCB, ANALOG BOARD, LT<br />

10K<br />

D<br />

Size Document Number B<br />

97055-91030<br />

Date: Friday, May 12, 2006<br />

Sheet 11 of<br />

Rev<br />

B<br />

19<br />

5<br />

4<br />

3<br />

2<br />

1<br />

+<br />

6<br />

5<br />

R227<br />

1M<br />

+5V<br />

8KV1_V_SET [6,19]<br />

8KV1_I_SET [6,19]<br />

8KV1_VOLTAGE_RDBK [19]<br />

C138<br />

.01UF<br />

8KV1_CURRENT_RDBK [19]<br />

8KV1_IS_IN_IMODE [19]<br />

2<br />

8KV Power Supply #1 Control<br />

1

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