Create successful ePaper yourself
Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.
5<br />
+3.3V<br />
4<br />
3<br />
D<br />
+3.3V<br />
+3.3V<br />
D D<br />
D<br />
(3.3 volt version)<br />
/ALTERA_RESET<br />
S1<br />
KT11P2JM<br />
CONFIG_CLK<br />
CONFIG_DATA<br />
ANALOG_BD_CONFIG_DONE<br />
CONFIG_STATUS<br />
+3.3V<br />
4<br />
DCLK VCC1<br />
20<br />
VCC2/SER_EN<br />
18<br />
2<br />
DATA<br />
9<br />
nCS GND<br />
8<br />
OE<br />
D<br />
D<br />
D<br />
D<br />
D<br />
SOCKET<br />
10<br />
nCASC 12<br />
10K<br />
R408<br />
1K<br />
EPC1441LC20<br />
R408<br />
3<br />
VCC<br />
1<br />
GND GND<br />
1K<br />
4<br />
RESET 2<br />
C272<br />
.01uF<br />
U88<br />
DS1233AZ-10<br />
R376<br />
1K<br />
R425<br />
1K R425<br />
Y11<br />
nCONFIG<br />
T3<br />
MSEL<br />
CONF_DONE 1K<br />
E18<br />
nSTATUS W11<br />
DCLK C10<br />
DATA B10<br />
U83-1<br />
E1<br />
nCE<br />
V18<br />
nCEO<br />
Q1 1<br />
MMBT4403LT1<br />
R426<br />
10K<br />
EPF6024ABC256<br />
/ATMEL_FPGA_PROG<br />
D<br />
C<br />
[2] /SYS_RESET<br />
+3.3V<br />
74HCT125<br />
2 3<br />
+5V<br />
TP70<br />
X1<br />
4<br />
VCC OUT<br />
3<br />
[3]<br />
[2]<br />
SPICLK_BUF_FPGA_IN<br />
/SPI_SEL_FPGA_IN<br />
FPGA_CLK<br />
U83-5<br />
L3<br />
GLOB_IN1<br />
L1<br />
GLOB_IN2<br />
L20<br />
GLOB_IN3<br />
K19<br />
GLOB_IN4<br />
+5V<br />
C261<br />
.01uF<br />
C<br />
R430<br />
+5V<br />
C260<br />
EPF6024ABC256 DGND<br />
681<br />
.01uF<br />
2<br />
GND NC(OE)<br />
1<br />
R421<br />
+5V<br />
D17<br />
D<br />
10K<br />
[5]<br />
GRN LED<br />
"SPI<br />
FPGA"<br />
CANARY_LED_FPGA_OUT<br />
3<br />
D1<br />
4<br />
D2<br />
6<br />
D3<br />
11<br />
D4<br />
13<br />
D5<br />
14<br />
D6<br />
9<br />
CLK<br />
1<br />
CLR<br />
Q1<br />
2<br />
Q2<br />
5<br />
Q3<br />
7<br />
Q4<br />
10<br />
Q5<br />
12<br />
Q6<br />
15<br />
U96<br />
14<br />
1<br />
2<br />
7<br />
U93A<br />
3 /SHUTDOWN [3]<br />
20MHZ OSC<br />
+5V<br />
+3.3V<br />
+<br />
C41<br />
10K<br />
B C282<br />
U93C<br />
B<br />
10uF 25V<br />
14<br />
9<br />
.1UF<br />
8 /SPI_MISO_ENABLE [2]<br />
74HCT125<br />
D<br />
D<br />
[5]<br />
/VOK_BYPASSED<br />
SPI_MISO_ENABLE_FPGA_OUT<br />
[2]<br />
/VOK_BYPASSED_FPGA_IN<br />
10<br />
5 6<br />
[5]<br />
7<br />
+3.3V<br />
C271<br />
2.2uF 25V<br />
D<br />
+3.3V<br />
D<br />
C273<br />
.1UF<br />
+5V<br />
U83-4<br />
R428<br />
+3.3V<br />
1 3<br />
2 4<br />
D<br />
+5V<br />
C283<br />
.01UF<br />
74AHCT174<br />
U95A<br />
1<br />
[5]<br />
/ALTERA_RESET [5]<br />
/SHUTDOWN_FPGA_OUT<br />
U83-3<br />
EPF6024ABC256 std BGA pinout checked 12-29-99<br />
14<br />
4<br />
5<br />
7<br />
U93B<br />
T17<br />
IO_TDO<br />
V1<br />
IO_TCK<br />
P3<br />
IO_TMS<br />
J3<br />
IO_TDI<br />
6<br />
74AHCT00<br />
74AHCT00<br />
U83-2<br />
EPF6024ABC256<br />
TP102<br />
TP101<br />
TP100<br />
TP95<br />
SHUTDOWN [3]<br />
74AHCT00<br />
A<br />
VCCINT1<br />
DGND<br />
+3.3V<br />
D<br />
+3.3V<br />
C235<br />
.01UF<br />
C263<br />
.01UF<br />
C264<br />
.01UF<br />
C248<br />
.1UF<br />
FPGA_1<br />
<strong>Thermo</strong> 355 River Oaks Pkwy, San Jose, CA 95134-1991<br />
ELECTRON CORPORATION<br />
Title<br />
SCH, PCB, ANALOG BOARD, LT<br />
A<br />
+3.3V +3.3V<br />
D<br />
Size Document Number B<br />
97055-910030<br />
Date: Friday, April 07, 2006<br />
Sheet 4 of<br />
Rev<br />
B<br />
19<br />
5<br />
4<br />
3<br />
2<br />
1<br />
D20<br />
VCCINT2 F3<br />
VCCINT3 K20<br />
VCCINT4<br />
L2<br />
A1<br />
GND1<br />
D4<br />
GND2<br />
VCCIO1<br />
D8<br />
GND3<br />
D13<br />
GND4<br />
D17<br />
GND5<br />
H4<br />
GND6<br />
H17<br />
GND7<br />
N4<br />
GND8<br />
D6<br />
VCCIO2 D11<br />
VCCIO3 D15<br />
VCCIO4 F4<br />
VCCIO5 F17<br />
VCCIO6 K4<br />
VCCIO7<br />
L17<br />
VCCIO8 R4<br />
VCCINT5 T20<br />
VCCINT6 U1<br />
VCCIO9 R17<br />
VCCIO10 U6<br />
VCCIO11 U10<br />
VCCIO12 U15<br />
N17<br />
GND9<br />
U4<br />
GND10<br />
U8<br />
GND11<br />
U13<br />
GND12<br />
U17<br />
GND13<br />
EPF6024ABC256<br />
R420<br />
10K<br />
C13<br />
IO_nRS<br />
B15<br />
IO_nWS<br />
A17<br />
IO_CS<br />
B17<br />
IO_nCS<br />
G17<br />
IO_CLKUSR<br />
G20<br />
IO_RDYnBSY<br />
J19<br />
IO_INIT_DONE<br />
C9<br />
DEV_CLRn<br />
A12<br />
DEV_OE<br />
R406<br />
EPF6024ABC256<br />
10K<br />
C265<br />
.01UF<br />
C268<br />
.01UF<br />
C259<br />
.1UF<br />
C266<br />
.01UF<br />
C267<br />
.01UF<br />
C275<br />
.01UF<br />
C274<br />
.1UF<br />
C236<br />
.01UF<br />
C258<br />
.01UF<br />
C237<br />
.01UF<br />
C254 C255<br />
.01UF .01UF<br />
C256<br />
.1UF<br />
C257<br />
.01UF<br />
D<br />
10K<br />
R447<br />
R446<br />
10K<br />
D<br />
14<br />
12<br />
13<br />
7<br />
1<br />
1<br />
3<br />
3<br />
5<br />
5<br />
7<br />
7<br />
9<br />
9<br />
U87<br />
J5<br />
10<br />
10<br />
8<br />
8<br />
6<br />
6<br />
4<br />
4<br />
2<br />
2<br />
+3.3V<br />
HEADER 5X2<br />
U93D<br />
11<br />
C270<br />
.01uF<br />
D<br />
74AHCT00<br />
+5V<br />
+3.3V<br />
2<br />
3<br />
2<br />
+3.3V<br />
1 2<br />
BR1<br />
USED TO TRISTATE<br />
ALTERA PART WHEN<br />
DOING IN-SITU<br />
PROGRAMMING OF<br />
ATMEL FPGA CONFIGURATION<br />
EEPROM.<br />
U95B<br />
4<br />
+3.3V<br />
R456<br />
1
Change language