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5<br />

4<br />

3<br />

2<br />

1<br />

D<br />

+5V (NOT LOADED)<br />

+/SYS_RST<br />

+MOSI<br />

+SPI_CLK<br />

/+SPI_SEL<br />

/-SPI_SEL<br />

-SPI_CLK<br />

-MOSI<br />

-/SYS_RST<br />

D<br />

[19] /+SPI_SEL<br />

U84A<br />

DS26C32ATM_<br />

+5V<br />

C239<br />

.01UF<br />

D<br />

[5] SPI_MISO_FPGA_OUT<br />

+5V<br />

U89A<br />

DS26C31TM_<br />

+MISO<br />

DO(+)<br />

2<br />

1<br />

DI<br />

-MISO<br />

DO(-)<br />

3<br />

/SPI_MISO_ENABLE<br />

[19]<br />

[19]<br />

[4]<br />

[5]<br />

[5]<br />

+5V_DAC<br />

/+LD_DAC_FOUT<br />

/-LD_DAC_FOUT<br />

+5V_DAC<br />

C243<br />

.01UF<br />

+5V_DAC<br />

16<br />

vp<br />

2<br />

RI(+)<br />

/LD_DAC_DBUF<br />

RO<br />

1<br />

RI(-)<br />

8<br />

gd<br />

[6,10]<br />

D<br />

[19] /-SPI_SEL<br />

/+SPI_SEL<br />

/-SPI_SEL<br />

2<br />

RI(+)<br />

1<br />

RI(-)<br />

3<br />

/SPI_SEL_FPGA_IN [4]<br />

D<br />

D<br />

TERMINATING RESISTORS NOT LOADED<br />

+5V_DAC<br />

PULLUP<br />

+5V_DAC<br />

TERMINATING RESISTORS NOT LOADED<br />

+5V<br />

[19] +SPI_CLK<br />

R423 +SPI_CLK<br />

301<br />

-SPI_CLK<br />

[19] -SPI_CLK<br />

R409<br />

1K<br />

6<br />

RI(+)<br />

7<br />

RI(-)<br />

+5V<br />

PUP3<br />

5 SPI_CLK<br />

U84B<br />

[3]<br />

[5]<br />

SRC_BD_HV_ON_FPGA_OUT<br />

SRC_BD_HV_ON+ [19]<br />

SRC_BD_HV_ON- [19]<br />

TO SOURCE BD TO CONNECT TO<br />

'HV_ON+' AND 'HV_ON-'<br />

[5]<br />

[5]<br />

+5V_DAC<br />

/+DAC_WR_FOUT<br />

/-DAC_WR_FOUT<br />

R401<br />

301<br />

+5V_DAC<br />

/DAC_WR_DBUF [6,10]<br />

TERMINATING RESISTORS NOT LOADED<br />

DS26C32ATM_<br />

PUP1 +5V<br />

TERMINATING RESISTORS NOT LOADED<br />

PULLUP<br />

PUP3<br />

+5V<br />

+5V<br />

C269<br />

U86B<br />

DS26C31TM<br />

+5V_DAC<br />

C [19] +MOSI<br />

.01UF<br />

DO(+)<br />

6<br />

7<br />

DI<br />

DO(-)<br />

5<br />

INTERLOCKS_ACTIVE+<br />

INTERLOCKS_ACTIVE-<br />

[19]<br />

[19]<br />

C<br />

R403<br />

301<br />

[19] -MOSI<br />

TERMINATING RESISTORS NOT LOADED<br />

+MOSI<br />

-MOSI<br />

SPI_MOSI [3]<br />

+5V<br />

PUP1 +5V<br />

TO SRC BD FPGA.<br />

RUNS BI-COLOR<br />

SYS LED<br />

+5V_DAC<br />

+5V_DAC<br />

[19] +/SYS_RST<br />

PUP3<br />

+5V<br />

[19] -/SYS_RST<br />

R402<br />

301<br />

+/SYS_RST<br />

-/SYS_RST<br />

/SYS_RESET [4]<br />

PULLUP<br />

SPARE<br />

TERMINATING RESISTORS NOT LOADED<br />

+5V_DAC<br />

3<br />

R389<br />

1K<br />

R33<br />

1K<br />

U82A<br />

DS26C32ATM_1<br />

0.0<br />

R410<br />

R395<br />

1K<br />

R407<br />

16<br />

vp<br />

6<br />

RI(+)<br />

RO<br />

7<br />

RI(-)<br />

8<br />

gd<br />

1K<br />

14<br />

RI(+)<br />

15<br />

RI(-)<br />

13<br />

U84D<br />

DS26C32ATM_<br />

5<br />

C276<br />

.01UF<br />

U86A<br />

DS26C31TM<br />

DO(+)<br />

2<br />

1<br />

DI<br />

DO(-)<br />

3<br />

U82B<br />

DS26C32ATM_1<br />

R429<br />

1K<br />

16<br />

vp<br />

10<br />

RI(+)<br />

RO<br />

9<br />

RI(-)<br />

R375<br />

1K<br />

8<br />

gd<br />

11<br />

RP11<br />

16<br />

1<br />

15<br />

2<br />

14<br />

3<br />

13<br />

4<br />

12<br />

5<br />

11<br />

6<br />

10<br />

7<br />

9<br />

8<br />

742-163-R102CT-ND<br />

R34<br />

301<br />

R390<br />

R422<br />

301<br />

1K<br />

U84C<br />

DS26C32ATM_<br />

10<br />

RI(+)<br />

9<br />

RI(-)<br />

11<br />

R391<br />

1K<br />

U82C<br />

DS26C32ATM_1<br />

R374<br />

301<br />

+5V<br />

PUP3<br />

B<br />

[19] /VAC_OK+<br />

[19] /VAC_OK-<br />

FROM SRC BD<br />

+5V<br />

/VAC_OK<br />

TL6<br />

1<br />

1<br />

2<br />

2<br />

[3] HV_ON_BUF<br />

VAC_OK_FPGA_IN [5]<br />

HV_ENABLED [11,12,13,14]<br />

GLOBAL ENABLE FOR EM/DYN,<br />

8KV POWER SUPPLY and LENs<br />

+5V_DAC<br />

+5V_DAC<br />

16<br />

vp<br />

14<br />

RI(+)<br />

RO<br />

15<br />

RI(-)<br />

B<br />

D<br />

+5V<br />

+5V<br />

PUP2<br />

TLOOP2<br />

D<br />

"VAC OK"<br />

/VOK_BYPASSED [4] From FPGA<br />

Power Splys<br />

8<br />

gd<br />

+5V_ADC<br />

PULLUP<br />

SPARE<br />

+5V_DAC<br />

D<br />

+5V<br />

+5V_ADC [1,16,18]<br />

+5V<br />

+5V_DAC<br />

DIGITAL TO ANALOG<br />

+5V<br />

+5V_DAC<br />

[1,6,10,16]<br />

INTERFACE DIFF DVRS<br />

D<br />

+5V<br />

A D<br />

PLACE ACROSS ARET - DGND SPLIT<br />

A<br />

D<br />

PUP2<br />

+5V<br />

+5V<br />

D<br />

PUP2<br />

+5V<br />

Differential Drivers / Receivers<br />

<strong>Thermo</strong><br />

ELECTRON CORPORATION<br />

Title<br />

355 River Oaks Pkwy, San Jose, CA 95134-1991<br />

SCH, PCB, ANALOG BOARD, LT<br />

13<br />

1K R442<br />

DS26C32ATM<br />

2<br />

RI(+)<br />

R451<br />

3<br />

1<br />

301<br />

RI(-)<br />

U90A<br />

R453<br />

14<br />

4<br />

5<br />

7<br />

U94B 6<br />

74AHCT00<br />

14<br />

9<br />

U94C 8<br />

10<br />

7<br />

74AHCT00<br />

14<br />

12<br />

U94D 11<br />

13<br />

7<br />

74AHCT00<br />

R388<br />

1K<br />

R373<br />

301<br />

U82D<br />

DS26C32ATM_1<br />

1K<br />

R372<br />

1K<br />

C280<br />

.01UF<br />

1K<br />

R460<br />

R454<br />

C279<br />

.01UF<br />

R444<br />

1K<br />

1K<br />

R452<br />

301<br />

R455<br />

6<br />

RI(+)<br />

7<br />

RI(-)<br />

5<br />

U90B<br />

DS26C32ATM<br />

R433<br />

301<br />

R434<br />

10<br />

RI(+)<br />

9<br />

RI(-)<br />

11<br />

U90C<br />

DS26C32ATM<br />

R32 0.0<br />

1K<br />

R443<br />

1K<br />

1K<br />

5<br />

RO<br />

4<br />

EN1<br />

12<br />

EN2<br />

RO<br />

4<br />

EN1<br />

12<br />

EN2<br />

SPARE<br />

RO<br />

4<br />

EN1<br />

12<br />

EN2<br />

RO<br />

4<br />

EN1<br />

12<br />

EN2<br />

RO<br />

4<br />

EN1<br />

12<br />

EN2<br />

RO<br />

4<br />

EN1<br />

12<br />

EN2<br />

4<br />

RO<br />

4<br />

EN1<br />

12<br />

EN2<br />

EN1<br />

4<br />

EN2<br />

12<br />

EN1<br />

4<br />

EN2<br />

12<br />

3<br />

D<br />

EN1<br />

4<br />

EN2<br />

12<br />

2<br />

EN1<br />

4<br />

EN2<br />

12<br />

EN1<br />

4<br />

EN1<br />

4<br />

EN2<br />

12<br />

EN1<br />

4<br />

Size<br />

B<br />

Document Number<br />

97055-91030<br />

Rev<br />

B<br />

Date: Friday, April 07, 2006<br />

Sheet 2 of 19<br />

1<br />

EN2<br />

12<br />

EN2<br />

12

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