30°C Power On 12 to 36 watts - for fanless sealed system design ...

Editorial 

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Martin Whitbread 


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E D A 

PUBLICATIONS 

Embedded System Engineering 

January-February 2006 

Editorial 

Embedded Software: The Works 04 

Instead of an editorial, we review a new book. 

News 

Industry 06 

A new GNU GPL, an Aardcase with a Were-Rabbit and flash memory trends. 

Chips 08 

Chip news includes a multi-colour, single package LED, a Dolby virtual speaker and low 

resistance power MOSFETS. 

Tools 10 

Oscilloscopes, ARM development for universities, MILs and ARINC and industry-specific 

platforms are in the tools news. 

Boards 12 

New board products include several CompactPCI SBCs, a mult -connection SoC module 

and sunlight readable LCDs. 

Application Focus: Consumer 

MP3 players 16 

Music database gets database software. 

MOST 18 

Intelligent network controllers. 

Buyer’s guide 

Eclipse for Embedded 19 - 33 

An overview of Eclipse and Eclipse tools. 

Technical Focus: RTOS 

● Measuring real-time performance 34 

● Minimising interrupt response time 36 

● Application portability across RTOSs 38 

● The fourth RTOS 40 

● Integrating XP and real-time 42 

● MILS: High-assurance security at an affordable cost 44 

Features 

● Continuous time delta sigma ADCs 46 

● Flash storage solutions 48 

Standards 

Standard or marketing document 50 

Our standard individual tries to disentangle international standards and marketing. 

Next Issue: Boards and modules, control and 

automation and a buyers guide to PC-104/Plus 

ESE Magazine Jan/Feb 06 

03

ESE Magazine Jan/Feb 06 

04 

Embedded Software: The 

Works – by Colin Walls 

Martin Whitbread 

Eclipse perspectives: 

showing the different 

views of the system 

#define RAM_SIZE 0x1000 

extern char RAM[RAM_SIZE]; 

COLIN WALLS has produced a very valuable document 

in the history of embedded system literature. Not a 

few books in the past have either been based on one academics 

limited experience or consist of an overview of 

the entire spectrum of products currently available. Neither of 

these is very useful to practitioners. The author here has constructed 

a document that is largely based on previously published 

papers that have been updated and linked into a narrative, 

with some interesting asides. The information comes 

across in an extremely useful format and although very occasionally 

some of the architectures mentioned might seem a little 

dated the actual technologies are very relevant. 

This book is not a “hard sell” for Accelerated Technology, 

where Colin Walls has worked for some time, but much more 

technical view of the whole field of embedded software. There is 

good stuff here, for electronic systems engineers faced with further 

involvement with software and for software engineers who 

are unlikely to have had the depth of experience that Colin has 

had. The topics covered range from an excellent introduction, 

which includes memory architecture, software migration and 

even USB. Design and development follows, with the increasingly 

important Eclipse IDE (more on that later) and designing with 

UML. This is followed by very useful sections on programming 

embedded systems, using C, C++ or an RTOS. Communications 

technologies are not neglected, the book finishes with 

Networking, including IPv6 and SNMP, and programmable logic. 

This book is accompanied by a CDROM containing text files 

of code and Power Point slides, for academic use. There are 

400 slides in all, quite enough for a program of teaching. As 

such it is a valuable resource for the few electronic engineering/embedded 

systems courses still running. As book, it is not a 

necessary, cover-to-cover read, the structure is such that you 

can dip in and out, by chapter or by section. The shear variety 

and range of the embedded systems industry, the different com- 

const char tests[] = { 0, 0xff, 0x55, 0xaa }; 

int ramtest() 

{ 

register int testnum, ramloc; 

register char save; 

} 

for (ramloc=0; ramloc

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Programmable Flash and on-chip JTAG-based debug in each device 

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06 

Industry 

Wireless design contest 

LANTRONIX is offering £7,000 in prizes for the 

best wirelessly network-enabled machines or 

devices, using a Lantronix WiPort 802.11b wireless 

embedded device server. Winners will be 

announced at the 2006 Embedded Systems 

Conference. 

www.lantronix.com/info/wirelesscontest 

Cell to 32 nanometres 

IBM, Sony Corporation and Toshiba, the team 

behind the “Cell” microprocessor design, and its 

underlying SOI (silicon-on-insulator) process technologies 

in 90 and 65 nanometre have begun a 

new, five-year phase of their joint technology development 

alliance. They plan to work together on fundamental 

research related to advanced process 

technologies at 32 nanometres and beyond. 

www.ibm.com/chips 

www.sony.net 

www.toshiba.co.jp/index.htm 

Multicore with T-Engine 

IGNIOS has demonstrated SystemWeaver integrated 

with a T-Engine. The SystemWeaver API 

allows application software to be written, via a T- 

Kernel adaptation layer, and compiled independently 

of the number of underlying processing 

resources. The SystemWeaver IP core then manages 

the dynamic run-time distribution of software 

across all available processing resources in a multicore 

Fujitsu MB87Q1100 device, delivering the 

full potential of the hardware to the application. 

www.ignios.com 

Multicore processor family 

P.A. Semi, a secretive start-up, has unveiled the 

PWRficient processor family. Based on the IBM 

Power Architecture the family is 64-bit, multicore 

and scalable. The first PWRficient processor, a 

dual-core chip running at 2GHz, dissipates 5-13 

watts (typical) depending upon the application. 

A modular architecture integrates cores, memory, 

south bridge, and high-speed I/O onto a single 

device. Target applications include high-performance 

computing, embedded datacom and telecom, 

storage, and embedded consumer applications. 

www.pasemi.com 

For a more detailed look at these stories please visit 

www.esemagazine.com 

Aardcase and the 

Were-Rabbit 

Part of the technology for creating 

“Wallace & Gromit: The Curse of the Were- 

Rabbit”, was Aardcase, a custom-developed 

computer. Capturing the images from 

up to 30 cameras directly to hard disc, it 

allows the animators to check the minute 

changes made from one frame the next in 

real time. 

Aardcase is a single board based PC with a passive 

backplane in a ruggedised 6U 19” rack mount 

case. The system includes a video capture PCI card, 

an optical drive for storing captured film, and two 

hard drives: video is stored on a high-performance 

SCSI drive while the operating system and software 

are held on a cost-effective ATA drive. 

www.sightsystems.co.uk 

Flash memory 

Spansion, which floated on NASDAQ in 

December, is going for the NAND portion of 

the cell phone market with its 90nm 

MirrorBit ORNAND family. 

The first product is 1Gb with a NAND interface. 

ORNAND combines the pricing of traditional 

NAND solutions with the reliability and highread 

performance of NOR Flash memory. 

Spansion plans to deliver complete memory 

subsystems of up to 3 gigabits to its customers 

GNU GPL revision 

THE FREE SOFTWARE Foundation and the 

Software Freedom Law Center are working 

on a revision of the GNU General Public 

License (GNU GPL). The first discussion draft 

was released for comment at the 

International Public Conference for GPLv3 at 

MIT on January 16 and 17, 2006. 

The last revision was more than 15 years 

ago and Gartner has predicted that by 2010 

more than 75 percent of IT organizations will 

have formal acquisition and management 

this year that include MirrorBit NOR, MirrorBit 

ORNAND and random-access memory (RAM) 

from leading RAM providers in Multi-chip 

Packages and Package-on-Package. (POP), solutions 

with the reliability and high-read performance 

of NOR Flash memory. 

Meanwhile Renesas has announced that it 

will be dropping development of AG-AND flash 

memory chips with capacities of 8G bit and 

beyond. It will continue to supply customers with 

existing flash memory products, mainly 1G bit 

and 4G bit products for applications, including 

flash cards for mobile and digital still cameras, 

and portable music players. 

Renesas also entered into supply and strategic 

collaboration agreements with M-Systems, where 

Renesas will supply advanced multi-level cell 

(MLC), high- performance AG-AND flash memory, 

while M-Systems will contribute flash controllers 

and the TrueFFS flash management technology. 

www.spansion.com 

www.renesas.com 

www.m-systems.com 

2006 technology 

trends 

Technology Futures, Inc. (TFI) list of significant 

technology trends for 2006 includes 

the democratisation of the Internet and the 

increased penetration of global broadband 

coverage to expand the Internet even more. 

This will lead to a greater threat to security and 

privacy extending to mobile devices and device-todevice 

networks. The digital home is entering the 

next level of acceptance, with the expansion of the 

electronic gaming and MP3 marketplace being a 

major driver. Public relations and marketing expenditures 

and projects will continue their shift to the 

public networks and the timeframe of the product 

life-cycle continues to decrease. 

www.tfi.com 

strategies 

dealing with 

Free Software. 

Publication of 

the second discussion 

draft is expected 

by summer 2006 and 

the final GPLv3 license is 

expected no later than spring 2007. 

http://gplv3.fsf.org

“The QNX Neutrino 

microkernel OS has 

the perfect DNA for 

multi-core processors” 

Dan Dodge. QNX CEO & CTO. 

Pioneer in distributed and multiprocessor computing. 

Introducing the QNX ® Momentics ® development suite 

Multi-Core Edition, the industry’s most comprehensive 

software platform for multi-core systems. Powered by the 

massively scalable QNX Neutrino ® RTOS, this fully integrated 

solution supports AMP, SMP, and BMP, a groundbreaking 

technology that simplifies code migration and future-proofs 

your designs for quad-core and beyond. It’s the latest 

innovation from QNX Software Systems, the undisputed 

leader in multiprocessing technology. 

Maximum Choice for Multi-Core 

Only QNX gives you the power to choose the best multiprocessing 

model for your multi-core design: 

Seamless resource sharing 

SMP BMP AMP 

Scalable beyond dual-core Limited 

Mixed OS environment 

Dedicated processor by function 

Inter-core messaging Fast Fast Slower 

Thread synchronization between cores 

Dynamic load balancing 

System-wide debug & optimization 

(OS primitives) (OS primitives) (application) 

Discover how Dan and the QNX team deliver the shortest 

migration path to multi-core. Call 1 800 676 0566 or 

visit www.qnx.com/innovate. 

QNX, Momentics, and Neutrino are trademarks or registered trademarks of QNX Software Systems GmbH & Co. KG and are used under 

license by QNX Software Systems International Corporation. All other trademarks belong to their respective owners. 301789 MC339.08 

QNX Unlocks the Power of Multi-Core 

Maximize performance. Eliminate complexity. 

Accelerate migration. Only QNX offers: 

■ Asymmetric Multiprocessing (AMP) for full 

developer control and fault tolerance 

■ Symmetric Multiprocessing (SMP) for maximum 

concurrency and scalability 

■ Bound Multiprocessing (BMP) for the fastest 

code migration and minimum design complexity 

■ Transparent Inter-Processor Communication 

(TIPC) protocol for seamless Linux connectivity 

■ System tracing tools for fast debugging and 

optimization of multi-core applications 

■ Off-the-shelf BSPs for multi-core platforms based 

on MIPS ® , PowerPC ® , and x86 architectures


08 

Chips 

Single chip MPEG4 

& JPEG Codec 

INTIME has announced 

the IME6500 single chip 

MPEG4-ASPL5/JPEG 

encoder and decoder. It has 

full TV resolution performance 

with lowest bit rate 

compression using multiple programmable filters. 

With a footprint of 17mm x 17mm and active 

power consumption of 300mW, the IME6500 is 

designed for consumer PVR, security, machine 

vision, medical equipment and CCTV markets. 

There are two reference designs available, a 

4-channel PCI interface module and a standalone 

4 channel digital video recorder. 

www.zilica.com 

65NM FPGAs 

XILINX is developing 65nm generation FPGAs 

with two existing foundry partners, Toshiba and 

UMC. In both cases the partnerships have seen 

prototype wafers with programmable logic circuitries 

and are exploring the possibilities of 45nm. 

www.toshiba.co.jp/index.htm 

www.xilinx.com 

www.umc.com 

883B FPGAS 

ACTEL has fully qualified MIL-STD 883B flashbased 

FPGAs. The ProASIC Plus B Flow family has 

qualified for use in high-reliability defence applications, 

such as military avionics and weapons 

systems. There are three devices ranging in density 

from 300,000 to 1-million system gates. 

www.actel.com 

FlexRay controllers 

FREESCALE is offering both integrated and 

stand-alone FlexRay controllers – the 

MC9S12XFR and MFR4300 – based on the latest 

FlexRay version 2.1 protocol. The MC9S12XFR 

integrates a FlexRay module with the 16-bit S12X 

core. The devices are intended for chassis control, 

body electronics and power train applications. 

www.freescale.com/flexray 


www.esemagazine.com 

Analogue front 

end for wireless 

authentication 

Microchip has announced a stand-alone, 

analog front end device for smart, low frequency 

(125kHz typical) sense-and-response 

applications such as hands-free access to 

vehicles or homes, low frequency sensor 

commands in tire pressure monitors and 

other wireless authentication applications. 

The MCP2030 AFE can be used alongside any 

Microchip’s PICs for passive access, intelligent 

transponder and smart sensing applications. 

Adjustable input sensitivity is 3 mVpp typical, 

modulation depth sensitivity options go to 8 percent 

and there are 3 input channels for reliable 3axis 

reception. Each channel of the AFE function is 

dynamically tuneable via the device’s SPI interface. 

An intelligent wake-up filter extends battery life. 

www.microchip.com 

Power MOSFETs 

Seventeen new power MOSFETs with onresistance 

values down to 3.7 milliohms in 

compact PowerPAK 1212-8 package have 

been released by Vishay. 

These TrenchFET Gen II are 3.3 mm by 3.3 mm 

by 1 mm with thermal resistance of 2° C per watt 

and are for synchronous rectification, synchro- 

Dolby virtual speaker 

MICRONAS’ new Multistandard Audio 

Processor family contains Dolby Virtual Speaker 

technology to provide surround sound from any 

audio source, whether stereo or 5.1 channels. 

The MSP-M/MAP-M are all-in-one TV 

audio processors, with both Dolby Virtual 

Speaker and Dolby Pro Logic II technologies. 

Designed for mid-range to high-end televisions, 

the chips can be included in flat-panel, 

projection or traditional CRT TVs. 

Dolby Virtual Speaker uses room-modelling 

techniques to create the illusion of five 

nous buck, and intermediate switching applications 

in point-of-load (POL) converters and highdensity 

dc-to-dc converters. 

The 12-V through 40-V single n-channel 

devices have on-resistance values ranging from 

3.7 milliohms to 10 milliohms at a 4.5-V gate 

drive and dual n-channel devices have on-resistance 

values down to 36 milliohms. Single-channel 

60-V devices have on-resistance values ranging 

from 135 milliohms to 435 milliohms at a 10- 

V gate drive. 

www.vishay.com 

Single package 

all-colour LED 

The programmable ACULED all-colour LED 

from PerkinElmer has three primary-coloured 

LEDs in a single package and can be programmed 

to display a wide variety of colours. 

Each LED has a separate anode and cathode 

and they are closely aligned for good quality 

white mix. A Lambertian emission ensures a 

homogenous optical luminance profile. 

It is for use in applications such as architectural, 

stage and automotive lighting. Operating 

and storage temperature is from -40 to +100ºC 

for both indoor and outdoor use and an evaluation 

kit is available. 

www.pacer-components.co.uk 

speakers from two, particularly useful for 

flat-screen TVs. 

www.micronas.com

AEC-6810 

Perfect Factory/Building Automation Platform 

❙ Fanless design with VIA Eden Processor 

❙ Operating Temperature: -15 to +60°C 

❙ Supports 4 COM/ 4 USB/ Audio/ TV-out 

❙ Factory Surveillance/ Production Line Tester/ 

❙ Building Automation/ Control Center 

t: 44 (0)1480 411600 

e: info@displaysolutions.ltd.uk 

Fanless Embedded Controller Series... 

...all on board at Display Solutions 

AEC-6840 

Superior Plant-wide Monitor Security Controller 

❙ Intel ® ULV Celeron ® 650/ 400MHz 

❙ Supports 4 COM/ USB 2.0/ Digital IO/ TV 

❙ Tuner/ Video Capture Function 

❙ Factory Automation/ e-learning Family/Security Installation 

AEC-6820 

Ideal Vehicle Control Equipment Platform 

❙ Supports 2 PCMCIA Slots for Expansion 

❙ Supports GSM/GPRS/GPS Applications 

❙ Operating Temperature: -15 to +70°C 

❙ Robust Vehicle/ GPS System/ Transportation Controller 

AEC-6850 

Digital Signage Controller 

❙ Intel ® Pentium ® M/ Celeron ® M Processor 

❙ Dual View/ 5.1CH Audio/ Card Reader/ USB/IEEE 1394 

❙ Outdoor Advertisement Player/ Advanced 

❙ Human-machine Interface 

www.displaysolutions.co.uk 

NEW! 

AEC - 6910 

AEC-6910 

Ideal for Digital Signage and multimedia advertising. 

Video Surveillance, Industrial Automation and Inspection 

❙ Intel Pentium M and Celeron up to 2.1GHz 

❙ Supports PCI, Mini-PCI, PCMCIA, CF 

❙ Add on cards for motion control, DVR, Data Acquisition, 

❙ 8-ch video capture 

AEC-6830 

Reliable 

Entertainment Application Unit 

❙ Intel ® ULV Celeron ® 650MHz 

❙ Dual View/ 6CH Audio/ TV-out/ DVI-out 

❙ Vehicle Multimedia System/ Audio & Video Playing 

NOW WITH 

TWO YEAR WARRANTY


10 

Tools 

FPGA development board 

THE RAGGEDSTONE1 is a low cost FPGA 

development PCB aimed at both the 

industrial/commercial and university/hobby markets 

from Enterpoint. 

It costs £50+VAT (which Enterpoint explains 

is less than a tank of petrol) and includes a 

Spartan-3 XC3S400 in a 456-pin BGA package. 

Options include packages ranging up to the 

XC3S2000. The full XC3S400 Spartan-3 I/O 

resources are available, giving 264 I/O. 

www.enterpoint.co.uk 

Distributed computing 

THE MATHWORKS’ new Distributed 

Computing Toolbox 2, designed to simplify the 

development of distributed computing applications, 

now offers support for third-party schedulers, 

and new interprocess communication 

capabilities for distributing and executing parallel 

algorithms in a cluster of computers using 

MATLAB. 

www.mathworks.co.uk 

OS migration path 

LYNUXWORKS has partnered with MapuSoft 

to provide embedded system developers with a 

migration path to the LynxOS RTOS. MapuSoft’s 

OS Changer and OS Abstractor can port large 

amounts of legacy code from an older operating 

system to LynxOS. 

www.lynuxworks.com 

www.mapusoft.com 

Eclipse: Eclipse tools are given an 

extended review in our buyers guide, 

following pafe 20. 


www.esemagazine.co.uk 

New ‘scopes (1) 

Tektronix has launched the DPO7000 Digital 

Phosphor Oscilloscopes (DPOs), which the 

company is calling the world’s first uncompromised 

performance oscilloscope. 

The 500 MHz DPO7054, 1 GHz DPO7104, and 

2.5 GHz DPO7254 models share a new platform 

that makes broad use of IBM 7HP silicon germanium 

(SiGe) technology for higher performance. The 

DPO7000 provides fast sample rates of 10 GS/s on 

four channels and real-time oversampling on four 

channels; up to 16X oversampling on one channel 

and 4X on four channels simultaneously. The 

DPO7054 and DPO7104 can support 40X oversampling 

on one channel and 10X on four channels 

simultaneously. They support deep record lengths 

to 200M while the DPO7254 supports 400M. All 

models include a 12.1 inch XGA display enabling 

engineers to see more information at once, and all 

models provide vertical accuracy of +/- 1%. 

Variable colour-graded persistence holds 

anomalies until the eye can see them, and the new 

models also include the MyScope user interface. 

www.tektronix.com 

Industry-specific platforms 

GREEN HILLS has introduced a family of 

industry-optimised software development 

platforms for medical, Software Defined 

Radio (SDR), wireless, industrial control, 

automotive and avionics devices. They 

include the core software and documentation 

required to develop and deploy a targeted 

device, accelerating time-to-market, reducing 

development risk, and enabling developers 

to focus on application-level innovation 

and differentiation. 

All Green Hills Platforms use the 

INTEGRITY RTOS, allowing developers to 

standardise on one RTOS. They are certified 

to the reliability, safety and security standards 

for each industry, including those specified 

by the NSA, FAA, FDA, IEEE and IEC. 

Each platform includes INTEGRITY and 

some optionally include the velOSity microkernel, 

the foundation of INTEGRITY. They 

have industry-specific middleware, such as 

Unit testing with 

hardware-in-the-loop 

Hitex has extended the Tessy software unit 

test tool with the new Tanto2-HIL “hardware-in-the-loop” 

system, so that embedded 

software testing can include the hardware 

environment and the physical interfaces 

of the application system. 

Tessy controls the generation and sampling 

of signals for the target hardware. The HIL system 

comes with a standard physical interface 

adapter to connect digital I/O signals. Customerspecific 

adapters will support analog or communication 

signals as well. The HIL system is able 

to generate and capture dynamic signals and signal 

sequences using the internal buffer memory 

of up to 1 GByte. 

www.hitex.co.uk 

New ‘scopes (2) 

Agilent Technologies has introduced the 

Infiniium 8000 Series of digital storage and 

mixed-signal oscilloscopes, which the 

company says combines superior signal 

viewing of the industry's deepest memory 

with advanced waveform analysis. 

The MegaZoom technology allows designers 

of embedded systems to capture analog and digital 

signals over long time spans, view critical 

events in complex waveforms, and perform 

networking, file systems, graphics, 

audio/video and navigation, as appropriate 

and provide integration with industry-specific 

reference hardware. Platforms also include 

the Green Hills MULTI development environment, 

and documentation, including the documentation 

and life cycle evidence required 

for industry-specific safety and security certifications 

and approvals 

www.ghs.com

obust signal analysis. 

The mixed-signal oscilloscopes (MSOs) provide 

up to 20 channels of time-correlated viewing 

and triggering with their tightly integrated four 

scope channels and 16 digital channels in the 

same acquisition system. 

The Infiniium 8000 Series also offers several 

software application suites for speeding 

mixed-signal debug in embedded designs to 

address design trends that include the integration 

of multiple circuit functions into a single 

FPGA, the proliferation of serial buses, and the 

evolution toward digital signal processing in RF 

applications. 

www.agilent.com 

MILS and ARINC 

Wind River has announced support for 

Multiple Independent Levels of Security 

(MILS), co-resident secure and non-secure 

applications on a single MMU-partitioned 

microprocessor. 

The new secure VXWorks is based on MILS 

concepts for a Secure Real Time Operating 

System (SRTOS) and is targeted for certification 

to Evaluation Assurance Level 7 (EAL7) of the 

Common Criteria for Information Technology 

Security Evaluation. 

It is bundled with an application configuration 

tool and provides multiple APIs, from a lowlevel 

Core OS Interface Library (COIL) to higherlevel 

APIs, including industry standard interfaces 

and middleware APIs. 

Wind River has also released v2.1 OF 

VxWorks 653, its enhanced ARINC 653 IMA platform 

for safety-critical systems. It is fully integrated 

into the Workbench development environment, 

allowing the use of the industry-standard 

Eclipse workspace for ARINC 653 software 

development and deployment. It has updated 

versions of all required documentation to support 

DO-178B Level A, B, C, and D certification of 

operating systems and new DO-178B qualified 

monitoring tools.. 

www.windriver.com 

ARM development kit 

for universities 

The EmbestUniversity is a teaching platform 

focused on embedded system development 

designed specially by Embest for 

universities and other educational institutes. 

It uses an ARM7TDMI based platform 

and contains evaluation board, development 

tools, laboratory exercises codes and 

teaching materials and is for embedded 

and real-time embedded systems at undergraduate 

or graduate level. 

The recommend evaluation board in 

EmbestUniversity is the Embest S3CEV40 board, 

which is based on a Samsung S3C44B0x 16/32- 

bit RISC microcontroller. The board itself is provided 

with plenty of example code and also with 

uC/OS-II and ucLinux porting. 

www.armkits.com 

 

11


12 

Boards 

PowerPC 3U CompactPCI SBC 

THE SCP/DCP-124 is a 

high performance ruggedised 

3U CompactPCI (cPCI) single 

board computer. 

Available in both conduction 

cooled and air-cooled 

versions it uses Freescale’s 7447A/7448 

PowerPC processor and is aimed at space and 

weight constrained COTS systems for military 

and aerospace applications. 

www.cwcembedded.com 

Industrial ATX 

THE FWB-880M from AAEON is an ATX form 

factor industrial motherboard with Pentium 4/ 

Celeron D supporting 1066/880/533MHz. It 

includes a GMA950 2D/3D graphics accelerator 

up to 4GB DDR2 memory, Pentium 4 CPU up to 

3.8GHz, 8 USB 2.0, 4 SATA and 1 PATA. 

www.rds-aaeon.co.uk 

E 2 Brain Interest Group 

THE E 2 BRAIN Interest Group has been founded. 

Joining Kontron are MAZeT and Ultratronik, both 

from Germany, Odyssee (France), and UniControls 

(Czech Republic). The goal of the E 2 Brain Interest 

Group is the joint development and marketing of 

RISC-based COMs designed around E 2 Brain 

(Embedded Electronic Brain) – the recently published 

COM standard from Kontron. 

www.e2brain-ig.com 

SBC with RoHS Compliance 

Evalue has announces ECM-3512, a new 3.5-inch 

ADM GX2-based single board computer that is 

fully RoSH compliant. The ECM-3512 is equipped 

with an AMD Geode GX2 GX466 processor 

clocked at 333MHz that can operate with passive 

cooling. The processor consumes only 0.9 watt. 

The board includes integrated TFT and LVDS display 

support, dual 10/100Mbps LAN, and 2-channel 

audio. It is designed for smart display, thin 

client and Internet access devices in applications 

such as medical instruments, POS/POI, test 

equipments, and industrial control systems. 

www.evalue-tech.com 

Coming in our March issue: Special 

focus on Boards and Modules with 

PC/104-Plus buyers guide. 

3U CompactPCI SBC 

Interface Concept’s IC-e6-cPCIa is a 3U 

CompactPCI SBC for use in defence, 

automation, network and 

imaging applications. 

It uses Freescale´s 

PowerPC e600 processors 

(MPC7447A-1GHz 

or MPC7448-1.4GHz) 

and has two 

Giga Ethernet 

channels, two 

high/full speed USB2 ports, two multi-purpose 

serial controllers and two high/full speed 

ports. A PMC expansion slot permits the addition 

of a 64-bit PMC card. It is available in standard, 

extended and conduction-cooled grades. 

A BSP and an enhanced BSP are provided for 

VxWorks and Linux operating systems. 

www.interfaceconcept.com 

Half-size, low 

power SBC 

The NuPRO-825 is a half sized PCI SBC from 

ADLINK. It comes with a choice of Pentium 

M processors from 1.1GHz up to 2.0GHz or 

Celeron Ms from 600MHz to 1.3GHz. 

It uses the Intel 855GME chipset with ICH5, 

350MHz integrated 24 bit RAMDAC supporting 

standard progressive scan analogue monitors 

with pixel resolution up to 1600 x 1200 at 85MHz 

and 2048 x 1536 at 75MHz. 

There is also a one channel transmitter interface 

to support LVDS panel resolutions up to UXGA. 

www.acalmicrosystems.co.uk 

Sunlight readable LCD 

RA-TEK using the sun’s own energy instead 

of extra high-powered backlights to improve 

readability of transmissive LCDs. It is a photon 

enhancement technology, implemented by 

placing reflective layers behind the glass LCD 

screen and in front of the backlights. Light 

penetrating the glass is reflected back by the 

Ra-Tek film to provide additional lighting for 

the display. The effect enhances the transmissive 

throughput of existing liquid crystal displays 

to achieve a greater level of brightness 

in all environments. In some cases, this can 

serve to double the native nit count of a standard 

TFT display. 

Ra-Tek can be used to augment any trans- 

ETX module with 

GX533 processor 

The GX2 ETX module from DSL is 

designed to provide a fully customised 

embedded solution. Software developers 

can use the development system, 

while the finished product is being manufactured. 

The ETX, 114mm x 95mm board will 

support Windows 2000, Windows XP, Windows 

XP Embedded, Windows CE.NET and Linux. 

The 400MHz AMD Geode GX 533 processor 

is supported by up to 512MB DDR RAM, full 

ISA and PCI Bus expansion, E-IDE interface, serial, 

parallel, IrDA and USB ports and 10/100 Base- 

T Ethernet. 

www.dsl-ltd.co.uk 

6U CompactPCI SBC 

SBS Technologies has announced the CE9 

6U CompactPCI CE9 SBC. 

It has a 1.8 GHz Pentium M processor, up to 2 

GBytes of 333 MHz DDR SDRAM with ECC and a 

400 MHz system bus. It can be used in a system 

or non-system slot within a 

CompactPCI 

backplane. 

It 

will integrate with 

applications designed 

using SBS Technologies' Ready 

Driver VxWorks software. 

It has a focus on reliability, and is aimed at 

rugged applications as well as those in the communications 

and automation. 

www.sbs.com 

missive LCD from any manufacturer, without 

requiring intense VHB or UHB backlights. It is 

designed for kiosk-type machines and LCD electronic 

signage, as well as portable and battery 

powered terminals required to operate outdoors. 

www.anders.co.uk

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14 

Embedded World 2006 

Embedded World is back in Nurenberg from February 14th-16th. Dick Selwood 

previews some of the announcements and will report back in the next issue. 

EVERY YEAR both European and other 

companies use embedded world to 

demonstrate new products and display 

upgrades to existing ones. It is a huge 

event and there is a tidal wave of press releases 

in the run-up to the show. Some of the interesting 

ones are discussed below. 

TenAsys 

INtime version 3.03 from TenAsys will be 

demonstrated in the Intel and Microsoft booths. 

New features designed to enhance the deployment 

of real-time Windows XP platforms 

include support for Windows XP Professional 

x64 Edition, full integration with the Visual 

Studio 2005 development environment, a virtual 

Ethernet driver to provide a sockets interface 

between Windows and INtime, a .Net component 

to allow all .NET languages to interface to 

INtime and a Windows XP Embedded SLD file 

for use with the Microsoft Target Designer. 

Digi International 

Digi International will be launching its highest 

performance core module to date: the new 

ConnectCore XP. This new module is the first 

Digi core module to utilise the latest generation 

Xscale processor from Intel and offers full Linux 

and Windows CE support. 

MAZeT 

MAZeT will have a real-time computer platform 

intended for mobile use outdoor. Based on the 

E2Brain-Modul MEB5200 and using the Fujitsu 

Coral PA graphics processor it has a range of 

video functions, as well as the MPC5200 processor. 

The incoming video stream is displayed in 

real time. It is designed for mobile use and battery 

operation. 

Also at Nürenberg will be the MTI04CS/CQ, 

the second generation of multi-channel, programmable 

transimpedance amplifiers. 

Atmel 

Atmel Corporation will unveil its AVR32 

MCU/DSP core, an ultra-low power 32-bit 

embedded MCU/DSP architecture with an integrated 

DSP and SIMD instruction set for computationally 

intensive, power-constrained systems, 

such as wireless, battery-powered applications 

that include consumer infotainment, point of 

sale terminals, biometric scanners, voice recognition 

and motion detection. 

A new family of high performance, ultra low- 

power 32-bit standard product AVR32 controllers, 

based on the new core, will be launched 

in early 2006. 

Toshiba 

Toshiba will show a range of technologies, 

including: 

● the latest generation of single-chip processors. 

● microcontroller-based speech interface IP 

solutions. 

● a new family of 8-bit and 16-bit high-density 

flash microcontrollers. 

Toshiba, as a sponsor of the World Cup will also 

be offering Embedded World visitors the chance to 

win two World Cup tickets a day with other prizes 

including MCU starter kits and footballs and football 

related products on offer during show. 

Radiometrix 

Radiometrix is introducing a 9600 baud radio 

modem module. The five-channel TDL2A effectively 

replaces a serial cable interface in applications 

where trailing cables are impractical or 

undesirable, delivering a low power, 100m data 

link. 

Combining a 433MHz-band five-channel 

transceiver with a dedicated data communication 

processor, the module deals with any 9600 

baud asynchronous data stream issues without 

user intervention or interface, and provides all 

necessary buffering, packetisation, framing, 

coding, decoding and reconstitution. 

Altera 

Altera will be showing the Nios processor in 

action in real end products built using Altera 

FPGA devices and the Nios II processor. For 

example the Nios II based Blaupunkt TravelPilot 

Rome auto navigation system will be on display, 

showing the route to the Altera Office in 

Munich. 

Silica 

Silicia is demonstrating products from a range of 

principals: 

● a ZigBee dexterity demo needs a steady 

hand to get a LED to light up within 30 seconds 

using a robot controlled by Freescale 

ZigBee. 

● Capell Valley is a reference platform for the 

new 65nm Intel Core Duo processors based 

on the Mobile Intel 945GM Express chipset. 

● An integrated power management solution 

from TI for Spartan, Virtex and Coolrunner 

FPGAs products. 

● SPEAr (Structured Processor Enhanced 

Architecture) is a new generation of 32-Bit 

ARM controllers with integrated ASIC block. 

A new Evaluation Board is based on the 

SPEAR-07-NC03 communication controller 

with ARM720T core, integrated Ethernet 

MAC and USB Full Speed Host Interface. 

Silicon Laboratories 

Silicon Laboratories are having a USB and 

Industrial Connectivity Expo based on its industry-leading 

mixed-signal microcontrollers 

(MCUs). This will showcase its 802.15.4 and 

ZigBee short-range wireless technology, 

Ethernet connectivity and an extensive line of 

USB products through live product demonstrations 

and mini-seminars. 

Sharp 

Sharp will unveil its newly-developed SoC 

roadmap for addressing the portable multimedia 

electronics market with ARM-based, 

high-end processors in its BlueStreak series. 

Altium 

Altium Designer 6.0, the latest version of 

Altium's unified electronic product development 

system, significantly strengthens support for 

FPGA-PCB co-design and allows engineers to 

make full use of FPGAs as a system platform, 

and simplify the integration of large-scale 

FPGAs with the physical PCB platform. It introduces 

the concept of dynamic net reassignment 

that allows FPGA pins to be swapped on-the-fly 

during PCB routing. 

There is support for a range of third-party 

soft and discrete processors, including the Xilinx 

MicroBlaze soft processor, Sharp BlueStreak 

LH79520 (based on the ARM720) and AMCCR 

PowerPC 405C discrete processors. 

ARTiSAN 

ARTiSAN will be demonstrating ARTiSAN Studio 

v6.0. which supports the latest UML 2.0 and 

SysML standards, It includes Ergonomic Profiling, 

providing the ability to build an environment 

based on the needs of specific domains or applications 

of UML and also providing a robust and 

consistent solution for DoDAF modellers thanks 

to the underpinning of UML 2 and SysML. 

See us at Embedded World 2006 Nuremberg, Hall 10, Stand 419 

Design to Target with 

One Graphical Environment 

Learn more about intuitive graphical programming for 

embedded design and prototyping at ni.com/labview/design 

© 2006 National Instruments Corporation. LabVIEW, National Instruments, and ni.com are trademarks of National Instruments. 

Other product and company names listed are trademarks or trade names of their respective companies. 

Design with LabVIEW 

Interactive algorithm design tools 

Native simulation capabilities 

Built-in analysis and I/O 

Prototype with LabVIEW 

Reconfigurable FPGA I/O 

COTS prototyping platform 

Deploy with LabVIEW 

32-bit processor deployment 

Same environment from algorithm design 

to implementation 

Graphical Development Platform 

for Design, Control and Test 

• Intuitive embedded programming representation 

• Rapid application development 

• Built-in I/O connectivity and ready-to-run analysis 

01635 523545 

ni.com/uk 

info.uk@ni.com


16 

MP3 players: the music database 

gets database software 

By Steven T. Graves, McObject 

Seen in one light, MP3 players are a walking database with sound attached. 

WHILE MANY consumer electronics 

devices must store and retrieve data, it 

is the digital media player (or MP3 

player) that most resembles a walking 

database. Music fans buy the devices so they can 

carry around hundreds of hours of audio, instantly 

accessing songs according to the “metadata” of 

artist, album, title, genre, and playlist. Without the 

ability to extensively index, cross-reference and 

search a music collection according to the user’s 

wishes, the devices would have little appeal. 

Less obvious is data management’s role in 

extending MP3 players’ battery life and lowering 

their manufacturing cost—but Japan’s JVC 

Company sees the connection. In late 2005, the 

company released what is probably a first: its 

new Alneo XA HD500 studio quality digital 

media player incorporates a commercial embedded 

database management system (DBMS). The 

new design reflects digital audio players’ memory 

and CPU constraints, which are extreme 

even for consumer electronics. JVC found that 

the right off-the-shelf database helps use these 

resources more efficiently. 

Reducing RAM 

In an MP3 player, RAM is precious for two reasons: 

using less memory reduces the device’s 

bill-of-materials cost, lending an important manufacturing 

cost advantage, and most RAM within 

the device is reserved for the playback buffer 

that caches the MP3 stream. Low-end CPUs are 

also deployed to minimize cost, and CPU cycles 

must be dramatically minimized, to afford a long 

playback per recharge. 

Playlist Album 

PlayListSong 

Song 

?Genre 

Figure 1: Data model of an MP3 player. 

Artist 

Early in the design process, the JVC engineers 

determined it would be difficult to obtain the 

desired efficiency, and meet a stringent development 

schedule, writing their own data management 

code. They began exploring the alternative: 

integrating a proven commercial DBMS within 

the MP3 player’s embedded software. 

The question remained, though, what kind of 

database would work. “Enterprise” DBMSs, 

designed to serve as corporations’ centralized 

data stores were an impossible fit due to cost 

and footprint; “embedded” database sounds 

closer, except that only a small subset of embedded 

databases are intended for real-time 

embedded systems (most are meant to be 

embedded in packaged software applications). 

In-memory 

For resource-constrained embedded devices, a key 

distinction within the embedded database category 

is on-disk DBMS, versus in-memory DBMS. 

Most embedded database systems manage data 

on-disk, and are designed to cache frequently 

requested data in memory – for faster access – 

but to write database updates, insertions, and 

deletes through the cache to be stored to disk. A 

newer approach is the in-memory database system 

(IMDS), which eliminates disk access and 

stores data in main memory, flushing to disk only 

when commanded to do so by the application. 

In-memory data management emerged as 

the better fit for JVC’s MP3 player. A key issue 

was on-disk databases’ indexes, which enable 

quick access to related records. To avoid disk 

access—which could potentially lead to playback 

interference in the MP3 player—the developers 

determined they would need to cache all 

of the on-disk database (data and indexes). 

Freeing memory 

A great deal of redundant data is stored in on-disk 

databases’ indexes that manifest the relationships 

between data entities. With such a database this 

is desirable because if the required data exists in 

the index, the system can avoid the disk I/O that 

would otherwise be needed to access the data 

file. Disk I/O is expensive (in performance terms), 

so on-disk databases can justify the extra storage 

space to hold redundant copies of data in indexes. 

But in-memory databases never go to disk. There 

Figure 2: Indexes to implement relationships. 

is no disk I/O to avoid, so the redundant index data 

can be eliminated, thus freeing memory. 

In making their database selection, the JVC 

engineers also noted that the software logic to 

accomplish caching and disk I/O—which are 

integral to on-disk databases but non-existent in 

in-memory architectures—posed significant 

CPU demands. By eliminating these demands, 

the in-memory database delivered better performance 

with a less powerful CPU, and allowed 

the CPU to be “clocked down” during certain 

operations to maximize battery life. 

Start-up time 

Engineers were also concerned about the startup 

time for provisioning the in-memory database. 

On-disk databases can be used immediately 

after the application opens the database, 

whereas an in-memory database is initially 

empty and must be populated (“provisioned”) 

with data. But in the final analysis, the modest 

size of the in-memory MP3 database eliminated 

this potential issue. For a database providing 

access to 5000 songs, the in-memory database 

required just 1 MB if the average song title 

string length was 20 characters; if all the song 

titles were the maximum 512 characters, the 

database was about 2 MB. With micro drive 

transfer rates up to 33 MB per second, the inmemory 

database could be provisioned in a time 

span well within usability thresholds. The competing 

on-disk database software created a 

database that was 7 MB in size. 

www.mcobject.com


18 

MOST – Intelligent network 

interface controllers 

Henry Muyshondt, SMSC 

The de-facto standard for automotive multimedia now has intelligent interfaces. 

MOST, or Media Oriented Systems 

Transport, is the de-facto standard for 

high-speed multimedia networking in 

automobiles, with 35 car models 

deploying the technology, using millions of MOST 

devices. Several carmakers are also incorporating 

the technology into their complete line-ups. 

MOST is moving into mid-range car platforms and 

may then proliferate into low-end car models. 

In the late 1970’s, many automobiles, even 

high-end cars, barely used a separate amplifier 

and radio. Over the years, audio products, such 

as cassette players and CD players, were added. 

With more devices in a car needing to interact 

with each other the number of connections rose 

exponentially, making it necessary to network 

the components. This is the need for MOST. 

All digital 

As the majority of data (music, Video CDs, DVDs, 

etc.) is stored in digital format, MOST is an alldigital 

system with analog signals only right at 

the user interface (speakers and video display). 

When a system level approach is taken to implement 

a MOST system, significant cost savings are 

achieved as duplicated components are eliminated 

and functions are integrated into single chips. 

MOST specifies not just the physical interconnection 

between devices on the network, but 

the software layers needed to build up and take 

down connections and the APIs needed to control 

standard functions, like CD-players, amplifiers, 

tuners, etc. In the first generation of MOST, 

a Network Interface Controller (NIC) provided 

the physical connection to the network, while 

NetServices - all the network management software 

ran on an External Host Controller (EHC). 

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Figure 1: NIC vs. INIC Architectures 

The EHC could be any of a variety of microcontrollers 

and DSP devices on the market. The NIC 

was programmed through a register wall and 

the integrity of the network was totally dependent 

on the EHC implementation of the 

NetServices software and APIs. Early implementations 

showed that some of the real-time 

responses needed by the low-level network 

interfaces were sometimes not met if the EHC 

was busy working on other tasks. 

MOST NICs are now Intelligent (INICs) and 

on the market. With these, the network comes 

up as a standalone entity, independent of the 

applications that reside on the EHC. INICs take 

all the lessons learned during early implementations 

and ensure that all the real-time requirements 

of network communications are taken 

care of without external intervention. 

Two Layers 

The NetServices software is divided into two 

layers. Layer 1 (the Basic Layer) includes the 

low level mechanisms needed to initialize 

MOST devices and to ensure the proper startup 

behavior of the network. This layer includes 

functions with real-time response requirements 

for the network to function properly. 

Layer 2 (Application Socket) includes 

required MOST functions and services to support 

functional addressing so applications don’t 

need to know the physical addresses of other 

devices on the MOST network. The functions 

included in layer 2 typically do not have hard 

real-time requirements. 

Figure 1 shows how INIC implements some 

of the functions of the old NIC-based approach. 

The INIC architecture includes a microcontroller 

to implement the functions in NetServices Layer 

1 and also the required MOST function block 

NetBlock that formerly resided in Layer 2. The 

NIC Engine is similar to the old external NIC and 

performs the actual formatting of data for transmission 

over the physical interconnection. 

Message based 

Another characteristic of the INIC architecture is 

that it uses a message-based interface rather 

than a register wall typical in NIC designs. This 

interface simplifies the number of commands 

that application programmers need to implement 

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Figure 2: INIC Architecture Framework 

and abstracts things like network speed and 

physical layer (e.g. various kinds of optical or 

electrical connections) from the application. This 

significantly reduces the design-in and verification 

efforts, as the network itself becomes a 

standalone entity. Specific functions on each 

device on the network register themselves as the 

device is ready and each device can take its time 

initializing itself and its operating system, if there 

is one, as well as other peripherals attached to it 

without having any effect on the network. 

The message-based architecture is implemented 

in SMSC’s line of INIC products and will 

be used in all future generations of MOST INICs. 

This architecture has the advantage that applications 

will need few, if any, changes to use 

higher speed network implementations or new 

physical layers that are introduced over time. 

Figure 2 shows a framework for INIC implementations. 

oPhy and ePhy represent optical and 

electrical physical layers, respectively. 

Current MOST systems use Plastic Optical 

Fiber (POF) driven with LEDs. Other optical transmission 

media such as Polymer Clad Silica (PCS) 

and VCSELs (Vertical Cavity Single Emission 

Lasers) are also being considered. In addition, a 

specification for an electrical physical layer has 

been developed by the MOST Cooperation. 

The INIC API removes any dependencies on 

network speed and physical layer from the applications 

that use INIC. 

The MOST Cooperation is a not-for-profit 

consortium of automakers, suppliers, and related 

companies that support the proliferation of 

the MOST protocol. 

www.smsc.com 

www.mostcooperation.com

I N T E L L I G E N T E L E C T R O N I C S S T A R T W I T H M I C R O C H I P 

Low Voltage voltage Rail-to-Rail Op 

Amp Solutions for extended 

temperature applications 

Including tiny SC-70 and SOT-23 devices 

Microchip’s Selected Extended Temperature Range Op Amps 

Part # GBWP IQ Typical Vos Max Temp. Range Supply Features 

(µA) (mV) (°C) Voltage 

MCP6275/85/95 2/5/10 MHz 170/230/445 3 -40 to +125 2.0 to 5.5V Rail-to-Rail Input/Output, 

Dual Connected with Chip Select 

Selected Standard Op Amps 

MCP6231/2/4 300 kHz 20 5 -40 to +125 1.8 to 5.5V Rail-to-Rail Input/Output 

MCP6241/2/4 650 kHz 50 5 -40 to +125 1.8 to 5.5V Rail-to-Rail Input/Output 

MCP6001/2/4 1 MHz 100 4.5 -40 to +125 1.8 to 5.5V Rail-to-Rail Input/Output 

MCP6271/2/3/4 2 MHz 170 3 -40 to +125 2.0 to 5.5V Rail-to-Rail Input/Output 

MCP601/2/3/4 2.8 MHz 230 2 -40 to +125 2.7 to 5.5V Rail-to-Rail Output 


MCP6021/2/3/4 10 MHz 1000 0.5 -40 to +125 2.5 to 5.5V Rail-to-Rail Input/Output 


Do you need low power consumption and extended 

temperature range operation? Microchip has a broad 

range of extended temperature op-amps with 

Gain-Bandwidths from 300 kHz to 10 MHz, including 

many devices in ultra-compact SOT-23 and SC-70 

packages. Microchip also offers the innovative 

MCP62X5 dual-connected op-amp family. 

www.microchip.com/opamps 

The Microchip name and logo, PIC, and dsPIC are registered trademarks of Microchip Technology Incorporated in the USA and other countries. All other trademarks and registered trademarks are the property of their 

respective owners. ©2005 Microchip Technology Inc. All rights reserved. ME145Eng/09.05


20 

Benchmarks: more 

than a marketing tool 

Markus Levy, EEMBC 

The latest of the regular columns from EEMBC explains the thinking 

behind the wider licensing of processor benchmarks 

CERTIFIED EEMBC scores for many 

processors have always been available for 

free on the EEMBC Web site, but since 

the consortium’s founding only members 

had access to the benchmark source code 

itself and the ability to run the benchmarks. 

Under a new program, OEMs, design consultants, 

and other qualified users can now license 

any or all of EEMBC’s benchmark suites. While 

the consortium will continue to allow the publication 

only of scores that have been verified by 

its certification lab, the new licensing program is 

set to make EEMBC benchmark software more 

widely available as a relevant, focused, objective 

tool for engineers choosing between 

processors for their applications. 

Typically, benchmarks are viewed as a marketing 

tool to allow vendors to compete on performance. 

However, the EEMBC benchmark software 

is also regularly used as a tool to analyze, 

tune, and validate processor architectures and 

the systems that encompass these processors. 

Although it will always be true that the best 

benchmark is the system designer’s application 

itself, the beauty of using the EEMBC software 

is that it’s easy to port to different architectures 

and platforms and user-obtained scores can be 

matched to the large database of scores on the 

EEMBC website. Furthermore, because it is such 

a widely-used code base, system designers can 

get direct support from processor vendors 

(because the majority of them are EEMBC members 

already familiar with the code). 

University 

The licensing model has quite a successful 

precedent in EEMBC U, under which faculty 

members at universities and college are entitled 

to license the benchmark source code for teaching 

and experimental purposes. EEMBC U continues 

to grow apace thanks to recent public 

exposure at several industry and academic venues, 

and its members now include faculty at 

some of the most highly regarded universities in 

the United States, Europe, and Asia. The SPEC 

consortium provides another example of how 

membership and licensing can successfully 

coexist within a single organization. 

The licensing program is also a result of 

what we’ve learned, after nearly 10 years of 

existence, about measuring EEMBC’s progress 

as a standards-setting enterprise. At various 

times, we’ve tended to gauge success according 

to the number of our member companies (which 

has averaged about 50 over the past five years), 

the number of certified processor benchmark 

scores being published, and the rate at which 

we bring new benchmark suites to completion. 

But none of these is as significant as another 

metric which is somewhat more difficult to 

know: the demand by customers of processor 

vendors for disclosure of EEMBC benchmark 

scores as a condition of considering any new 

chip for one of their system designs. The anecdotal 

evidence is that this demand has gone up 

significantly in the past few years, and more 

than one member company has told me frankly 

that its interest in joining EEMBC was the direct 

result of interest by its customers in seeing 

EEMBC benchmark scores. 

Benchmark suite 

EEMBC’s application orientation to benchmarks 

and its certification rules are two obvious 

respects in which it differs from Dhrystone mips 

and other synthetic benchmarks. Less apparent 

but just as important is the EEMBC process of 

benchmark development, in which members 

companies both large and small have an equal 

vote in the many decisions that ultimately lead to 

a completed benchmark suite. The process is not 

always fast, but it does lead to credible results. 

This is one reason why EEMBC is now being 

approached by OEMs who are not only interested 

in the consortium’s existing suites but would 

like us to develop new ones that address the par- 

Figure 1: Markus Levy, president EEMBC. 

Benchmark software is also regularly used as a tool to analyze, tune, and validate 

processor architectures and the systems that encompass these processors 

ticular needs of a given embedded application. 

This is how EEMBC came recently to form a new 

subcommittee that is working on network storage 

benchmarks and being led by Adaptec. 

Until now, most users of the EEMBC benchmarks 

have been the processor vendors that 

developed them, so part of our task in the coming 

weeks and months will be making the benchmarking 

process even more user-friendly for a 

broader audience of embedded systems designers 

and others for whom the processor is just 

part of the bigger picture. We’ll be adding to the 

information about the benchmarks on the 

EEMBC Web site, improving benchmark documentation, 

and providing more specific information 

on the workloads that EEMBC benchmarks 

address. We welcome contributions to this 

effort from everyone in the embedded systems 

community. 

www.eembc.org

ESE Magazine January 05

Some things 

have 

to go out 

on time 

As an embedded software developer, you’re always facing the next deadline. We know it’s important to get your products to market 

before your competitors, and we can help. With our Eclipse-based development tools, tightly integrated embedded software 

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and global support center practices certified by the Support Center Practices (SCP), we are dedicated to your success. 

Call +44 (0)1527 66632 

uk_info@acceleratedtechnology.com 

AcceleratedTechnology.co.uk 

©2006 Mentor Graphics Corporation. All Rights Reserved. 

For a free evaluation of EDGE Development Tools, visit our website: 

AcceleratedTechnology.com/outontime 

Embedded made easy.

ESE Magazine Jan/Feb 06

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Embedded for Leaders

Eclipse news 

Recent news from the Eclipse world. 

Eclipsecon 2006 

ECLIPSECON is the premier technical and user 

conference for Eclipse, and the third gathering 

is March 20th to 23rd at the Santa Clara 

Convention Center. There are keynotes, conference 

sessions and tutorials covering all aspects 

of the Eclipse platform. 

www.eclipsecon.org 

Workbench 

GENUITEC, has released the MyEclipse 

Enterprise Workbench 4.1. a J2EE- and Web- 

www.windriver.com 

development tool suite. It is designed for use 

on Linux, Mac OS X and Windows workstations. 

www.genuitec.com 

Eclipse 3.0 Platform 

THE QNX Momentics development suite has 

been upgraded, based on new versions of 

the Eclipse framework and the Eclipse C/C++ 

Development Tools (CDT) 

It also features better interrupt-handling 

capabilities for the QNX system profiler, and 

Supplement sponsored by 

deeper traceback and leak detection in the 

memory analysis tools for advanced debugging. 

Included are customized Eclipse plugins, 

such as a code “dietician” that reduces 

memory footprint by removing unnecessary 

functionality from shared libraries, and an 

application profiler that pinpoints problem 

algorithms and identifies functions needing 

optimization. 

www.qnx.com 

Software architecture 

management 

LATTIX has released Lattix LDM for Eclipse, 

providing Lightweight Dependency Models 

(LDM) to formalise, communicate and control 

the architecture of Eclipse projects. 

www.lattix.com/news/news.htm 

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Brief outline of the agenda: 

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No participants’ fees will apply! 

To participate, please contact: 

Tina Thalmeier Stefan Zeilner 

Microsoft® System Marketing GmbH Intel EMEA Marketing Organisation 

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34 

Measuring real-time 

performance 

John Carbone, Express Logic 

Real-time performance is one of the most important criteria for selecting 

an RTOS. But, what is “real-time performance” and how is it measured? 

REAL-TIME PERFORMANCE can be 

defined as the speed with which an 

RTOS (or any software for that matter) 

can complete its functions in 

response to an event. The “real-time” aspect 

implies that the software response to one 

event is needed before some independently 

occurring second event takes place. For example, 

in response to an automobile engine’s 

intake valve opening, the engine control software 

must calculate the correct air-fuel mixture 

and have it injected into the cylinder 

RTOS Functions Measured 

before the valve closes in preparation for the 

compression stroke. It is critical that the 

response to the first event is completed in time 

to meet the needs of the second event. This 

response may include many things, but paramount 

among them are interrupt processing 

and system services. 

Interrupt processing 

Real-time systems are generally designed to be 

reactive in nature, and the events to which they 

must react are generally made known to the 

Context Switch (CS): Time required to save current thread’s context, find highest priority ready 

thread, and restore its context. 

Interrupt Latency Range (ILR): Amount of time interrupts are disabled. 

RTOS System Services 

● tx_thread_suspend – Suspend an application theread. 

● tx_thread_resume – Resume a previously suspended thread. 

● tx_thread_relinquish – Relinquish control to other application threads. 

● tx_queue_send – Send a message to a message queue. 

● tx_queue_receive – Get a message from a message queue. 

● tx_semaphore_get – Get an instance from a counting semaphore. 

● tx_semaphore_put – Place an instance in a counting semaphore. 

● x_mutex_get – Obtain ownership of a mutex. 

● tx_mutex_put – Release ownership of a mutex. 

● tx_event_flags_set – Set or clear event flags. 

● tx_event_flags_get – Retrieve event flags. 

● tx_block_allocate – Allocate a memory block. 

● tx_block_release – Release a memory block. 

● tx_byte_allocate – Allocates bytes of memory. 

● tx_byte_release – Release a previously allocated memory area. 

For each system service, the following are measured: 

● Immediate Response (IR): Time required to process the request immediately, i.e., no thread 

suspension or thread resumption. 

● Thread Suspend (TS): Time required to process the request when the calling thread is suspended 

due to unavailability of the resource. 

● Thread Resumed (TR): Time required to process the request when a previously suspended 

thread (of the same or lower priority) is resumed as a result of the request. 

● Thread Resumed and Context Switched (TRCS): Time required to process the request 

when a previously suspended higher-priority thread is resumed as a result of the request. 

Since the resumed thread is higher-priority, a context switch to the resumed thread is also performed 

from within the request. 

system as interrupts. The processor, upon recognizing 

an interrupt, performs certain actions 

and executes instructions that were designed to 

react to this event. In most cases, the processor 

is already performing some instructions immediately 

prior to recognizing the interrupt. This 

processing must be “interrupted,” and then 

later resumed when the critical real-time 

response of the interrupt has been completed. 

Most RTOSes are designed to provide a means 

for the developer to handle interrupt processing 

and also to schedule and manage execution of 

application software threads. Interrupt processing 

generally includes the following: 

● suspending whatever thread currently is 

executing, 

● saving thread-related data that will be 

needed when the thread is resumed, 

● transferring control to an interrupt service 

routine (ISR), 

● performing some amount of processing in 

the ISR to determine exactly what action is 

needed, 

● retrieving/saving any critical (incoming) 

data associated with the interrupt, 

● setting any required device-specific (output) 

values, 

● determining which thread should now execute 

given the change in environment created 

by the interrupt and its processing, 

● clearing the interrupt hardware to allow 

the next interrupt to be recognized, 

● transferring control to the selected thread, 

including retrieval of any of its environment 

data that was saved when it was last interrupted. 

Whew! All of that (and perhaps more, depending 

on the RTOS) is included in “interrupt processing,” 

which is only one aspect of real-time 

performance. It’s no wonder that implementation 

of these operations in a particular RTOS 

can make a significant difference in real-time 

performance. 

System services 

Real-time operating systems must do more 

than simply respond to interrupts. They also 

must schedule and manage the execution of 

application software threads and handle

equests from threads to perform scheduling, 

message passing, resource allocation, and 

many other services. In most instances, services 

must be performed quickly, so the thread 

can complete its assigned processing before 

the occurrence of the next interrupt. While not 

a part of interrupt processing, the system service 

is a critical real-time response that can 

make or break a system, and includes: 

● scheduling a task or thread to run upon the 

occurrence of some future event, 

● passing a message from one thread to 

another, 

● claiming a resource from a common pool, 

Even more variable than interrupt processing, 

the implementation of system services is 

equally critical in achieving good real-time performance 

in an RTOS. Together with interrupt 

processing, system services combine to form 

the most significant processing that an RTOS 

is asked to perform. Different implementations 

will approach these functions differently, with 

different architectures to produce a wide 

range of performance. 

Why is performance so critical? 

The time required for completion of these 

functions is particularly critical in real-time 

systems, which must be deterministic, and 

also must respond rapidly or suffer loss of data 

or even fundamental malfunction of the system. 

An example might be a flight-control system 

that must respond to a pilot input in time 

to avoid a stall, or a disk-drive controller that 

must stop the drive’s read head at precisely the 

point at which data is to be read or written. 

Rapid-fire interrupts from high-speed data 

packet arrival into a DSL router also must be 

handled promptly to avoid triggering a retry 

because one was missed. 

Processor speed is critical in executing all of 

the RTOS instructions required to perform the 

desired function, but brute force alone cannot 

satisfy system demands, nor can it provide the 

most economical or efficient solution. A 2GHz 

processor might breeze through code in satisfactory 

time, but it could be too costly, draw too 

much power, or present physical packaging 

challenges. A more economical processor, running 

an efficient RTOS, might do just as well in 

performance, or even better, yet cost far less 

and not pose power/heat/packaging problems. 

Focusing on the most significant elements 

allows real-time performance to be measured 

in a rigorous fashion. Comparing how well 

multiple RTOSes on a common hardware platform 

perform specific critical functions (see 

table 1) lets developers quantify real-time performance 

and make the best decision for their 

application. 

www.expresslogic.com 

Table 1: Example timings 

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Reference platform: ARM9 processor, 40MHz. RTOS: ThreadX 

Times generally scale linearly with clock rate for most 32-bit processors 

System Service IR TS TR TRCS 

tx_thread_suspend 2.8µS 4.2µS 

tx_thread_resume 2.6µS 5.3µS 

tx_thread_relinquish 1.2µS 3.4µS 

tx_queue_send 2.1µS 5.1µS 4.3µS 6.8µS 

tx_queue_receive 1.7µS 4.9µS 4.8µS 7.6µS 

tx_semaphore_get 0.8µS 4.8µS 

tx_semaphore_put 0.9µS 3.2µS 5.8µS 

tx_mutex_get 1.1µS 5.3µS 

tx_mutex_put 2.4µS 4.4µS 7.0µS 

tx_event_flags_set 1.4µS 4.1µS 6.7µS 

tx_event_flags_get 1.2µS 5.2µS 

tx_block_allocate 1.0µS 4.9µS 

tx_block_release 1.0µS 3.4µS 6.0µS 

tx_byte_allocate 3.3µS 6.2µS 

tx_byte_release 1.9µS 6.9µS 9.5µS 

Context Switch 1.9µS 

Interrupt Latency 0µS – 1.8µS 

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35


36 

Minimizing interrupt 

response time: 4 simple rules 

David Kleidermacher, Green Hills Software, Inc. 

A failure to meet a response time requirement in a real-time system can 

be catastrophic. Sound programming coupled with proper RTOS interrupt 

architecture can ensure a minimal yet guaranteed worst case response time. 

1. Keep interrupt service 

routines (ISRs) short 

Avoid loops and other constructs which increase 

latency. When an interrupt fires, the microprocessor 

typically disables interrupts before 

executing the ISR. By keeping ISRs simple, 

developers avoid the common pitfall of leaving 

interrupts disabled for too long, increasing the 

latency of higher priority interrupts. 

2. Do not disable interrupts 

A major contributor to increased latency is the 

number and length of regions in which the operating 

system disables interrupts. By disabling 

interrupts, the kernel increases latency of high 

priority events that arrive in those disabling windows. 

Most operating systems employ what we 

call a Simple architecture, which is easy to 

implement: in order to prevent preemption, the 

kernel disables interrupts for the duration of the 

critical section 

By disabling interrupts, the Simple RTOS is 

sacrificing the latency of the highest priority 

event to avoid problems caused by handling of 

lower priority interrupts. A better solution, 

implemented in the Advanced architecture, is to 

never disable interrupts in kernel service calls. 

Not only does the Advanced RTOS guarantee 

the minimum possible latency for the highest 

priority interrupt, but also the worst case latency 

can be trivially proven. 

3. Avoid improper use of operating 

system API calls in ISRs 

ISRs commonly do not require kernel API 

access: the ISR performs basic operations 

before acknowledging the interrupt and 

returning. A more complex ISR is required to 

wake up a thread, such as by releasing a 

semaphore, for higher level processing. The 

RTOS vendor should limit ISRs to a small set 

of service calls that are necessary and deterministic. 

As an example of the peril regarding API 

usage in ISRs, consider a queue of threads 

waiting for a resource (e.g. a semaphore). 

Many Simple RTOSes use an ordinary linked 

list to hold the queue of threads. When the 

resource becomes available, the first thread, 

regardless of its importance relative to other 

waiters, is provided the resource. In contrast, 

the Advanced RTOS automatically wakes up 

the highest priority waiting thread. Some 

Simple RTOSes have a service call that pulls 

the highest priority thread out of the queue and 

jams it onto the front. One problem with this 

approach is its usability: the developer must 

remember to insert prioritisation calls and 

determine where in the code they belong. 

Worse, the RTOS must search linearly through 

the unordered list to find the highest priority 

thread; real-time behaviour is lost. 

The Advanced architecture provides a second-level 

handler, sometimes termed a callback, 

to perform higher level processing 

when the kernel has returned to a consistent 

state. If the developer must add a callback in 

the ISR and then write code in the callback to 

do the service call, this makes programming 

more difficult. Not to worry: the Advanced 

RTOS hides the details of two-level handling 

by allowing the use of a standard API call 

which places the callback on behalf of the 

programmer. 

There are some important advantages to the 

Advanced architecture’s optional two-level handler. 

By pushing work into the callback (where 

interrupts are enabled), the Advanced RTOS 

reduces the temporal footprint of the ISR, in turn 

reducing the latency for higher priority interrupts 

(Figure 1). Note that the overhead of the twolevel 

handling is negligible: a callback entails 

merely placing a function address on a list for 

the kernel to call; no heavyweight processing or 

memory is required. 

4. Properly prioritise interrupts 

relative to threads 

When a thread is awakened for higher level processing 

of the most important event, this thread 

becomes the most important thread in the system. 

The thread must complete its processing 

within a fixed period of time. 

In the Simple RTOS, the thread runs with all 

interrupts enabled. Any low priority interrupt can 

fire, delaying the most important thread and 

Figure 1: Reducing latency for higher 

priority interrupts. 

Figure 2: Minimum response time for events. 

causing missed deadlines. In fact, since interrupts 

may nest, multiple events, and all of their 

associated ISR processing, could delay this high 

priority processing by an unpredictable length of 

time. 

The Advanced RTOS allows interrupts to be 

prioritised relative to threads. When a high priority 

thread is awakened during interrupt processing, 

the kernel inhibits lower priority interrupts 

when switching to the high priority thread. 

When the high priority thread completes its 

work, the kernel reenables lower priority interrupts. 

This architecture guarantees the minimum 

thread response time for the highest priority 

real-time events (Figure 2). 

Complex embedded systems, with multiple 

concurrent tasks and interrupt sources, pose a 

challenge for RTOS interrupt handling architecture. 

Developers will achieve the best interrupt 

response time by following a few simple rules 

and employing an RTOS with an Advanced interrupt 

architecture. 

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38 

Application portability across 

RTOSs and connection media 

Terry Wright, RTI 

Middleware for embedded systems is beginning to 

make an impact on the embedded space. 

TODAY’S EMBEDDED devices are 

more connected than ever before. Indeed, 

it’s hard to conceive of a device that does 

not require connection capabilities in 

today’s world. There is a plethora of connection 

mechanisms, from the ubiquitous Ethernet and 

serial connections, to USB, Wi-Fi and fabric 

technologies. RTOS vendors deliver an essential 

service to developers by providing an efficient 

and productive environment for system design 

and integration. As well as providing an optimized 

platform for single node application 

development, the modern RTOS environment 

must integrate the huge range of device drivers 

and protocol stacks needed to meet increasingly 

complex distributed system requirements, and 

also facilitate hardware to software integration. 

What has changed in recent year’s is that 

system developers now frequently have to deal 

with applications which must span multiple connected 

nodes; they also have to run across multiple 

hardware transport mechanisms connecting 

those nodes, and even across multiple different 

OS’s, from the deeply embedded RTOS through 

RT Linux and up into the enterprise space where 

standard Unix and Windows systems are running. 

This is where middleware solutions are 

needed, providing the simplifying model of a single 

API that spans multiple OS’s and CPU types. 

Much as in the enterprise space, where middleware 

has been a key application enabler for 

many years, the embedded device space is now 

recognizing its increasing importance to cost effective 

application development and deployment. 

Open standard 

Data Distribution Services (DDS) is an embedded 

middleware solution that delivers common 

data distribution capabilities for almost any connection 

mechanism and RTOS or enterprise OS, 

but tuned to the real-time performance and 

memory requirements of what are, after all, 

highly demanding embedded devices and systems. 

Even better, the DDS mechanism is a published 

open standard developed and supported 

by the Object Management Group (OMG), which 

is already being adopted by a number of embedded 

software developers and vendors. 

Of course there is more to developing 

embedded devices than just putting the components 

together; embedded systems designers 

need to manage the available resources, be it 

the amount of work the CPU can be expected to 

do or the amount of memory available and 

required. Embedded devices are usually expected 

to operate 24/7 without failure, and some 

safety critical systems need to have built in 

redundancy and automatic failover. 

Effective Data Distribution middleware must 

also cater for real-time requirements. How is task- 

ing controlled, how is the task priority set in Data 

Distribution middleware and how is the task stack 

size determined? How is the memory required by 

the middleware for data buffering allocated? How 

is data delivered? What overheads on the transport 

bandwidth does the data distribution method 

imply? All these questions and more must be considered 

by system designers. 

The DDS standard (DDS 1.0) was released in 

2005 and details a Data Distribution API using 

the Publish-Subscribe data distribution paradigm, 

as opposed to the more widely known 

Client-Server paradigm. DDS provides for a Peer 

to Peer, loosely coupled network of connected 

devices with no single point of failure. Best 

Effort or Reliable data delivery semantics and 

automatic discovery of DDS nodes facilitates a 

“self-healing” network. Asynchronous notification 

of the data arrival and early detection of 

failing nodes are a few of the many features 

available within the DDS specification. 

Application-level security validation can also be 

achieved using DDS features. 

Vendor support 

There are already a number of software vendors 

who have decided to provide support this new 

standard, Real Time Innovations (RTI) being one 

of them. RTI have a long history in working with 

Real Time Systems and RTOS vendors. Wind 

River recently purchased the RTI tools division 

which developed some of the most widely used 

real time diagnostic tools available 

(Stethoscope, MemoryScope, ProfileScope 

,CoverageScope and TraceScope) so their experience 

in the real-time environment is widely 

acknowledged. Such experience, coupled with 

their long-standing involvement in Publish- 

Subscribe middleware and the drive for open 

standards, motivated RTI to chair the OMG standardization 

committee for the DDS specification. 

RTI designed their implementation of the 

DDS specification (NDDS4.0) to be RTOS-friend- 

Developers now frequently have to deal with 

applications which span multiple connected nodes 

ly by providing support for standard RTOS offerings 

popular in today’s heterogeneous networks; 

notably VxWorks from Wind River, Integrity from 

Greenhills and LynxOS from LynuxWorks and 

more recently QNX. 

Fine Control 

Quality of Service (QoS) settings within NDDS provide 

the fine control over system resources that 

system designers demand, such as NDDS task priorities, 

and NDDS task stack types and sizes. 

“Ahead-of-time” memory allocation for data 

buffers, no mallocs at run time, network redundancy 

and multiple concurrent transports are all standard 

supported features, in addition to the QoS 

built in to the DDS specification that handles automatic 

failover and data delivery semantics. RTI’s 

DDS implementation features a pluggable transport 

mechanism for NDDS that provides the necessary 

abstraction for application developers who 

need to move data over any transport. e.g 

Ethernet, VME backplanes, PCI Express, Shared 

Memory or indeed StarFabric transports. 

The Open DDS middleware standard, combined 

with RTI’s NDDS implementation features 

and extensive RTOS support delivers an open 

standards based solution to the most demanding 

and complex of distributed system development 

today. 

www.rti.com/resources.html 

www.omg.org/technology/

Copyright © 2006 Kontron AG. All rights reserved. Kontron and the Kontron logo and all other trademarks or registered trademarks are the property of their respective owners and are recognized. Rev. #G041eu01-WMH 

Our info hotline: 

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40 

The fourth RTOS 

Kevin Pope, Quadros Inc. 

Cores combining MCU and DSP architectures require a different kind of RTOS. 

THE EMBEDDED software market has 

historically developed two fundamentally 

different RTOS architectures, each designed 

to serve the needs of the underlying processor 

architectures; specifically MCU’s (CISC/RISC) 

and DSP's. Most commercial RTOS vendors have 

developed solutions adapted and optimized to one 

or other of these designs and their (traditionally 

somewhat different) applications. 

A third RTOS design, multiprocessor, is 

required to support multiple processor architectures, 

completing the “traditional” RTOS space. 

In recent years, however, the pressure to 

reduce both cost and power consumption in volume 

applications such as consumer hand-held 

multimedia electronics has increased dramatically. 

Consumers are driving their objects of desire 

smaller and smarter. There are many issues for 

the manufacturer, but the essential question has 

to be – how to fit more features and functions 

into an ever decreasing physical space. Inside 

the glossy exterior, there is a struggle for space 

on a PCB already overcrowded with connectors 

for USB, antenna(s), power, flash, etc. 

Convergent processors 

These market pressures have led to the emergence 

of a new type of single core hybrid, or convergent 

processor, combining both MCU and DSP 

architectures. Such ‘convergent’ processors can 

be designed as DSP's with MCU capabilities (e.g. 

Freescale’s DSP56800E) or MCU’s with DSP 

extensions (e.g. Freescale's ColdFire) or completely 

new cores designed from the ground up to 

serve both architectural needs (e.g. StarCore, or 

ADI's Blackfin). These single core designs enable 

hardware engineers to reduce chip count and 

reduce the overall size of the device, leading to a 

reduction in system cost and power consumption. 

But this creates a challenge for the design of 

the supporting RTOS architecture: should it be 

Table 1: Single stack advantages 

Multitasking Architecture 

for Control Plane Processing 

optimized for the interrupt-driven control environment 

of the MCU, or for the data-flow environment 

of DSP? In the same way that silicon 

has been forced to converge, a fourth RTOS 

type, optimized for the convergent environment 

is also needed. 

Quadros Inc have recognized this trend by 

developing a 4-way RTOS design, RTXC 

Quadros, with a version designed and optimized 

for each of the four architectural types; MCU, 

DSP, Multiprocessing, and ‘Convergent’. The 

approach taken to provide a convergent software 

solution is to use a “dual mode” RTOS 

design, with each part of the application running 

in an environment optimized either for DSP or 

MCU execution. 

Context overhead 

The main drawback of a multi-tasking MCU type 

RTOS for a DSP engineer is the necessity for 

each task to retain what is known as a context. 

This storing and restoring of data consumes 

vital processor instruction cycles and delays processing 

of the interrupt. When the interrupts are 

frequent and constant, as in streaming media, 

the context switch becomes a heavy overhead in 

the system. In the worst case, the control application 

may never get any processor time to complete 

its necessary processing or the interrupts 

may be lost because the ISRs cannot keep up 

with the demand from external events. 

With a convergent processor, these two 

roles must be balanced efficiently within a single 

resource. The obvious way to assist this situation 

is to reduce overheads and the biggest 

Multithreaded Architecture 

for Data Plane Processing 

One stack per task All threads use single stack 

Multiple priorities Multiple priority levels 

Preemption between priorities Preemption between levels 

Context saved and restored as needed No context saved or restored except on preemption 

Can wait for an event Cannot wait for an event 

Lower priority than threads Run to completion within a level 

The question is how to fit more features and 

functions into an ever decreasing physical space 

overhead in a system with many interrupts is the 

context switch. 

The dual-mode design of RTXC/dm combines 

a traditional task-based kernel architecture for 

real-time control processing with a specialized 

executive for DSP and dataflow operations. The 

control application code will execute in the 

familiar environment of a pre-emptive priority 

based scheduler, typically used for such tasks as 

user interface, communication paths and peripherals. 

Meanwhile, the signal processing application 

code will execute in a highly efficient single-stack 

environment. (See Table 1). 

Fast switching 

DSP processes, handled by lightweight code 

entities called threads, run at a priority higher 

than control tasks, ensuring they get access to 

the CPU and can meet their real-time requirements. 

Thread-to-thread switching is very fast 

because threads carry no context. Control operations 

are supported by a multitasking processing 

model with a rich set of static and dynamic 

kernel objects and inter task synchronization 

options. As a further advantage, all this takes 

place in a single development environment, so 

both DSP and MCU-based development tools 

can communicate easily between the domains 

using the object classes and related services of 

the operating system. 

Thus the use of a dual mode RTOS architecture 

ensures that the developer of such 

demanding applications can fully leverage the 

low cost, low power advantages of the new 

convergent processor designs emerging in the 

market today. 

www.quadros.com

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• High Performance Graphics using ATI, dual screen, DVI/DFP 

• Two independent video input channels; mux up to 4 inputs 

• 5V only 

Contact us 

Europe & rest of world: 

Microbus plc 

Tel: +44 (0) 1628 537333 

Fax: +44 (0) 1628 537334 

email: sales@microbus.com 

www.embedded-pc.com 

Designed and manufactured in the UK 

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Microbus 

B e t t e r b y d e s i g n


42 

XP & real-time systems 

Paul Fischer, TenAsys Corp 

A virtual machine approach combines a Windows interface with an RTOS. 

TO AUGMENT the flexibility of 

Windows as a human-machine interface 

OS with support for the deterministic 

requirements of embedded applications, 

designers usually add a dedicated real-time 

component (i.e., a second computer). 

Unfortunately, a second control computer adds 

substantial cost of goods, manufacturing complexity, 

and system-to-system coordination 

headaches. A “single-computer dual-OS” system, 

where one compute element hosts both the 

Windows system and the RTOS, significantly 

reduces the cost of goods and complexity, and 

simplifies the coordination of Windows with 

real-time processes. 

Typical real-time Windows solutions utilize a 

Windows driver inserted in the Windows kernel, 

an approach that presents many software design 

challenges. A true dual-OS solution employs virtual 

machine technology where the non-deterministic 

application elements execute on a “Windows 

virtual machine,” and deterministic software executes 

on a “real-time virtual machine” (see figure). 

A significant advantage of this virtual machine 

approach is the leverage application developers 

gain by using a single standard development tool 

for both environments. 

Interval timers 

Real-time processes and threads running on 

the RTOS virtual machine need access to highspeed 

interval timers for accurate, low-drift 

time measurements and for generating exact 

periodic intervals to insure precise control of 

real-time systems. x86 APIC uniprocessor and 

multi-processor systems, the vast majority of 

embedded and desktop Windows platforms 

built today, are excellent candidates. 

To insure efficient implementation of realtime 

threads, developers need an environment 

that supports direct access to I/O and memory, a 

fixed priority scheduling system with priorityinversion 

protection, and simplified interrupthandling 

services. They can then create and 

deploy sophisticated real-time applications 

without having to write complex and cumbersome 

device drivers for access to real-time 

hardware, simplifying development and debugging 

of control and data acquisition algorithms. 

The net gain of the virtual machine “singlecomputer 

dual-OS” approach is elimination of 

redundant computer and communication hardware 

and faster communication and coordination 

between the real-time and Windows appli- 

cation parts. The RTOS and its processes run on 

the same hardware as the standard Windows 

kernel, sharing the CPU, memory, and I/O 

resources. 

A better approach 

The virtual machine approach to adding realtime 

task processing to applications incorporating 

Windows is quite different from those 

approaches that install a real-time kernel in the 

form of a Windows device driver or subsystem. 

The device driver and subsystem models force 

real-time applications to operate as part of the 

Windows kernel. Kernel mode code has privileged 

access to the entire memory space, including 

the Windows kernel and other device drivers; 

it lacks address isolation and memory protection. 

A real-time thread running on such a system can 

easily overwrite other processes: both real-time 

and Windows processes. Because such programming 

errors are difficult to detect in kernel 

mode and result in spurious but critical failures, 

achieving reliable operation through this method 

often requires extensive testing and debugging. 

Many such errors are not detectable until the 

system has been deployed in the field. Creating 

a complex, multi-threaded, real-time application 

to run inside the Windows kernel is contrary to 

the notion of building reliable, safe, and dependable 

real-time applications. 

On the other hand, using a virtual machine to 

add real-time responsiveness to Windows, as 

TenAsys’ INtime does, enables the RTOS to 

maintain reliable operation of real-time processes 

in the event of a Windows crash. The virtual 

machine approach to real-time Windows allows 

real-time applications to run in user-mode, not 

kernel-mode. The result is improved reliability 

and robustness, as well as simplified programming 

and debugging. Each real-time process 

runs in a separate 32-bit protected memory segment. 

These segments are distinct from those 

used by Windows and provide address isolation 

and protection not just between the real-time 

processes, but also between real-time processes 

and non-real-time Windows code. 

Dual-core enhancements 

Using two virtual machines to share a single CPU 

platform that supports Windows and real-time, 

works for a large number of real-time Windows 

applications. Typically, applications with cycle 

times of one millisecond or slower are served quite 

well by this arrangement and have been deployed 

Win32 

Processes 

Win32 APIs 

Windows OS 

Windows 

Kernel 

Windows 

Virtual Machine 

Real-Time Application 

Inter-OS 

Communication 

Pentium-class processor 

Real-Time 

Processes 

INtime APIs 

Real-Time 

Kernel 

INtime 

Virtual Machine 

Figure 1: A virtual machine implementation 

on an Intel Architecture processor. 

on the current crop of desktop and industrial motherboard 

platforms (uniprocessor and hyper-threaded 

Pentium 4 class processors running at 1-3GHz). 

However, some applications demand faster 

cycle times. For these applications the solution 

is dual-core processors. Higher speed cycle 

times mean higher bandwidth controllers, a 

desirable trait because it leads to improved performance 

and throughput. 

Dual-core processors easily support two operating 

systems by dedicating one CPU to the 

RTOS. The CPU instruction cycles of the dedicated 

core are available 100% of the time to the 

RTOS. The CPU cycles of all remaining cores 

become the exclusive property of the Windows 

virtual machine. Contention for key CPU 

resources such as pipelines, cache, and the FPU 

are avoided. Coordination between the two 

processors is accomplished by using built-in 

interprocessor communication mechanisms, 

eliminating context switch. In this scenario, interrupt 

latencies are reduced by an order of magnitude, 

from 10-30 microseconds down to 1-3 

microseconds. Loop cycle times in the 50-200 

microsecond range are able to operate with high 

precision and accuracy. The advent of inexpensive 

dual-core hardware means an order of magnitude 

improvement in the quality and bandwidth 

of control algorithms can be obtained on a realtime 

Windows platform! 

An RTOS that shares the CPU with Windows, 

using virtual machine technology, allows embedded 

Windows applications to take full advantage 

of the Windows’ standard user interface, network 

capabilities, development tools, and off-the-shelf 

software and still deliver the performance required 

of critical, hard real-time tasks. 

www.tenasys.com

NO SLOWING DOWN. EVER. The market won’t care 

who gets there first. We'll work with you to architect the 

best embedded solution for your company. And you can 

start now because we are already doing it. Get your 

product out there. Fast. 

PEDAL TO THE METAL. 

www.radisys.com


44 

MILS: High-assurance security 

Joe Jacob, Objective Interface Systems 

As it becomes possible to connect systems through the 

Net, how can you preserve their integrity and security? 

NOW THAT the Internet and high-speed 

communications have made it possible 

to connect military and aerospace systems 

throughout the world through the 

U.S. Department of Defense’s Global Information 

Grid (GIG), information networks are more vulnerable 

than ever. An emerging software architecture, 

Multiple Independent Levels of Security 

(MILS), was designed to increase the level of 

security for safety- and mission-critical systems. 

It combines the best of the safety and security 

worlds to create a better solution than either 

could have devised. It draws upon FAA DO-178B 

Level A Safety technology and Common Criteria 

EAL7 Security requirements to enable highassurance 

security for mission-critical embedded 

and real-time systems, including high-assurance 

weapons, training and communications systems 

and C4I platforms. MILS dramatically reduces the 

size and complexity of security-critical code, 

thereby allowing faster and more cost-effective 

development and evaluation. 

The central idea behind MILS is to partition 

a system in such a way that (1) the failure or corruption 

of any single partition cannot affect any 

other part of the system or network, and (2) each 

partition can be security-evaluated and certified 

separately, so that no partition needs to be evaluated 

at a higher level than is required for its 

particular function. 

The MILS architecture 

To support these partitions, the MILS architecture 

is divided into three layers, the Separation 

Kernel, Middleware and Applications. 

Separation kernel: The MILS separation kernel 

divides the computer into separate address 

spaces and scheduling intervals, guarantees isolation 

of the partitions, and supports carefully 

controlled communications among them. 

Because the separation kernel performs these 

functions and only these functions, the source 

code can be small—roughly 4,000 lines of C language 

code. This makes it fast and practical to 

verify using formal analysis methods (mathematical 

verification) and to do the exhaustive 

testing and comprehensive documentation 

required for the highest level certifications. The 

separation kernel requires the highest level of 

authentication, and is the only piece of software 

that runs in privileged mode. Therefore, no other 

code, not even device drivers, has the ability to 

affect the processor’s protection mechanisms. 

Everything else, including all middleware, runs 

in user mode. The small size of the separation 

kernel is a manifestation of the most important 

MILS design objective: 

It is because of this rigorous inspection and 

evaluation that the MILS separation kernel can 

be trusted. Green Hills Software, LynuxWorks 

and Wind River each plan on delivering commercially 

available Separation Kernels. 

Middleware: In the MILS architecture, middleware 

has a broader meaning that just traditional 

middleware. Most of the traditional operating 

system functions have been moved from the 

operating system to “middleware services,” 

e.g., file systems, device drivers, trusted path, 

etc. Middleware services include a Partitioning 

Communications System (PCS) to extend the 

scope of the separation kernel to inter-system 

communication. It also includes traditional middleware 

like CORBA (Common Object Request 

Broker Architecture), DDS (Data Distribution 

Service) and Web services. Middleware resides 

in the same kind of partition as the application 

that it supports, either co-resident with the 

application or in a partition by itself. 

Middleware runs in unprivileged (user) mode, 

making these services subject to separation kernel 

policy enforcement. The services that previously 

ran in privileged mode as part of the operating 

system, such as memory allocation, device 

drivers, I/O primitives, file systems, and network 

stacks, now run in user mode in the MILS middleware 

layer. 

Applications: Applications manage, control, 

and enforce their own application-level security 

policies, such as firewalls, crypto services and 

guards. Instead of the fail-first patch-later 

approach, trusted components are mathematically 

verified so that they are “NEAT”: Nonbypassable, 

Evaluatable, Always invoked, and 

Tamperproof. 

The importance of the PCS 

When we create a distributed system configuration, 

we would like it to be as safe or secure as 

if it were just a single processor. We accomplish 

this by implementing end-to-end enforcement of 

the basic MILS separation kernel policies. The 

PCS is the enforcement mechanism. The collection 

of MILS nodes in a distributed system is 

called an enclave, and the PCS is present in each 

node in the enclave. The PCS fits between the 

applications and the partitions implementing 

U 

(SL) 

Application 

Application 

#1 

Middleware 

Application 

#1 

Middleware 

S 

(SL) 

Application 

PCSexpress 

Separation Kernel 

TS 

(SL) 

Application 

Network 

protocols & 

drivers 

Figure 2: PCSexpress within the MILS 

architecture. 

TS/S 

(MLS) 

Application 

Middleware Middleware Middleware Middleware 

Separation kernel 

Processor 

Figure 1: The basic MILS architecture. 

To open 

network 

network protocols. Objective Interface Systems 

is the developer of PCSexpress, the first product 

to conform to the secure communications architecture—the 

PCS—that Objective Interface 

invented. Designed for embedded systems, 

enterprise servers, workstations and global networks, 

PCSexpress provides off-the-shelf highassurance 

communications security that 

reduces the duration, schedule risk and cost of 

designing, evaluating, accrediting and deploying 

highly secure systems. 

Past efforts at making software truly secure 

usually added complexity and high cost. Layers 

of protection were added on top of the operating 

systems, middleware, and the applications. 

Sometimes these layers interfered with each 

other, had unintended side affects, or were not 

completely consistent with each other, giving 

both bugs and attackers the initial crack in the 

wall they needed to inflict damage. 

The MILS approach is precisely the opposite. 

Systems are made more secure by making the 

protection simpler. Because it is simpler, it can 

be trusted to work under all conditions. The 

processor, via the MILS separation kernel, is 

tightly controlled. The PCS provides the same 

assurances for distributed systems. 

www.ois.com/mils

Why use an RTOS? 

Tomoyuki Uda, Managing Director, eSOL, Inc 

An RTOS provides a great deal for the FPGA developer. 

What should you consider when choosing one? 

THE FLEXIBLE Nios II processor 

extends Altera’s FPGAs into new and 

varied application possibilities. With a 

microprocessor in the FPGA, developers 

can design more efficient and powerful 

embedded systems. With this expanded capability, 

developers for FPGA-based systems may 

be facing the decision of whether to use a Real 

Time Operating System (RTOS) for the first 

time. 

What features does 

an RTOS provide? 

An RTOS provides the foundation for building 

your embedded application. The most basic 

definition of an RTOS is that it provides multiple 

threads of execution, and a scheduler to 

switch between those threads. Multiple 

threads allow you to break up your application 

into its basic parts, separated by purpose and 

priority. 

Most RTOS kernels provide the following set 

of features: 

Multiple threads 

An RTOS allows multiple threads of execution, 

implemented as tasks or processes, depending 

on the nature of the RTOS. 

Preemptive, priority-based scheduling 

A preemptive scheduler allows interrupts and 

higher priority tasks to interrupt the currently 

running task. 

Synchronization services 

Multitasking kernel allow tasks to wait for 

other tasks to complete work, or wait for an 

event to occur. These services typically 

include mutual exclusion mechanisms (mutex 

and/or semaphores), event flags, data queues, 

etc. 

Interrupt and exception support 

The RTOS kernel provides a way to handle hardware 

interrupts and exceptions through 

installing interrupt and exception handlers. 

Predictable interrupt 

latency and task switch time 

RTOS kernels have predictable overhead for 

handling interrupts and switching tasks. 

When to use an RTOS 

An RTOS is useful in complex systems to 

streamline application development. Polling 

loops work well for dedicated, simple designs, 

but quickly get complex when the design grows. 

For example, running multiple network servers 

can work from a polling loop, however the application 

design becomes much simpler and more 

modular if each network server is run in its own 

task. 

Using an RTOS is also beneficial when an 

application needs to run on multiple CPUs – 

using an RTOS abstracts the hardwaredependence 

so porting the application to a different 

target is easier. Using an RTOS 

abstracts that dependency so the application 

concentrates only on the operations required 

to perform its functions, and the RTOS handles 

the hardware interface. Most commercial 

RTOSes support many CPUs and specific 

boards. 

An RTOS incorporates useful services that 

you would otherwise need to implement, debug, 

and maintain yourself in your own code library. 

Applications using an RTOS can dynamically 

allocate resources when they are required. 

Sharing resources reduces the overall memory 

requirements for the application. 

Choosing an RTOS 

When you consider how to design your application 

on the Nios II, you can choose to not use an 

RTOS at all, to use a free RTOS, or to use a commercial 

RTOS. If you do choose to use an RTOS, 

there are freely available solutions and commercial 

solutions. 

The following factors should be considered 

when choosing an RTOS: 

Cost 

Developers often adopt open-source solutions 

because they are free. While the licensing 

cost is free, it’s important to add up the complete 

cost for using any RTOS. Technical support 

is only offered in online forums. In a critical 

project, you may need additional technical 

support or custom services. The extra support 

and services are not free, and the associated 

fees are often more expensive than the 

license cost of a commercial RTOS. When 

considering license cost, consider the risk to 

your project vs. the cost of the license, support, 

and services. 

Licensing 

When you use an open-source operating system 

in your product, you assume the risk and liability 

for using that code. Commercial RTOS vendors 

assume the risk for their own OS implementation. 

Technical support and maintenance 

Receiving technical support from the same engineers 

who wrote and maintain the operating 

An RTOS incorporates useful services that you would otherwise 

need to implement, debug, and maintain yourself 

system shortens the support and development 

cycle. 

PrKERNELv4 

PrKERNELv4, from sCOS, is the base of a full 

RTOS suite called eParts that provides a real 

time kernel, TCP/IP connectivity with 

PrCONNECT2, an embedded file system with 

PrFILE2, integration with a graphical user interface 

library, and more. The entire eParts product 

suite is fully integrated into Altera’s development 

environment for Nios II. Support is also 

integrated with several Altera third party partners’ 

software and tools, such as Lauterbach’s 

Trace32, the MorethanIP 10/100/1000 MAC- 

NET Core and the SLS USB Core 

Conclusion 

Choosing an RTOS doesn’t need to be complex. 

When choosing an RTOS, consider the features 

you need as well as associated development 

costs for porting, support, and software 

licensing. 

www.esolglobal.com 


45


46 

Continuous time 

delta sigma ADCs 

Heribert Geib, Xignal Technologies AG 

Continuous time delta sigma analog-to-digital 

converters provide new design opportunities. 

UNTIL NOW, designers have been faced 

with a trade-off in their selection of analog-to-digital 

converters (ADCs). Pipeline 

converters offer high resolution and high 

dynamic range but at the expense of relatively high 

power consumption. Discrete time delta sigma 

converters don’t need nearly as much power but 

are severely limited in terms of speed. The continuous 

time delta sigma (CTΔΣ) technology developed 

by Xignal bridges the gap and their recently 

announced products operate at 40 MSPS (equivalent 

to 50-60 MSPS in pipeline parts), 12 or 14-bits 

of resolution, high levels of functional integration 

including an accurate on-chip clock source, and all 

this with a power consumption of just 70mW. An 

added advantage of the technology is a resistive 

input stage that’s easy to drive without resorting to 

power-hungry buffer amplifiers. Figure 1 shows 

the relative performance of these ADCs compared 

with pipeline converters based on the IEEE’s 

accepted measurement of Figure of Merit (FOM). 

FOM is a measure of the energy per conversion. It 

also shows that as process architectures scale in 

the future, continuous time delta sigma devices 

will follow the roadmap to deliver higher levels of 

performance. Figure 2 looks at a complete analog- 

Figure 1: ADC conversion power efficiency 

comparison 

Figure 2: Integrating the signal path – 

enabled by CTΔΣ ADC technology. 

to-digital conversion system. The left hand side 

shows the pipeline converter with the five external 

circuit elements that are needed for a complete 

system: a programmable gain amplifier with the 

gain controlled via a separate digital-to-analog 

converter (DAC), anti-alias filters to remove noise, 

and input driver to buffer the capacitive input of the 

ADC itself, and a high performance clock and 

phase locked loop to provide an accurate timing 

reference. By contrast, the continuous time delta 

sigma implementation removes the need for antialias 

filtering and the input driver, and Xignal’s 

implementation of the technology integrates all of 

the other functions on-chip. The generic benefits 

of CTΔΣ conversion are clear: faster and simpler 

system design, lower power consumption, and no 

compromise in dynamic range or speed. In multichannel 

applications these benefits are multiplied 

and can enable designers to adopt new and beneficial 

system architectures that were not previously 

possible. Potential applications for the technology 

are widespread in all sectors of the electronics 

industry, particularly where analog signals derived 

from various types of sensors need to be converted 

to digital signals in a power-efficient manner. 

Medical ultrasound is just one of these applications. 

Medical ultrasound applications 

In these systems a transducer is connected via a 

flexible cable to the data processing unit (PU) 

that processes the data. Each transducer element 

is connected to the PU through its own 

data-channel or multiplexing circuits are used to 

reduce the number of cables. High-end systems 

are equipped with up to 512 channels, mid-level 

performance systems with up to 256 channels 

and portable systems up to 128. 

Prior to the development of CDTS technology 

analog front-ends the pipeline ADCs consumed 

anything up to 0.5 Watt for each channel. That's 64 

Watts for a mid-range (128 channel) system with 

enough heat being generated to affect the performance 

of the transducer head and cause significant 

discomfort to both patient and doctor. By contrast, 

the CTΔΣ solution in the same system would consume 

just 8.75 Watts or even less by using a multichannel 

ADC device sharing some resources like 

the PLL across multiple channels. With an 8-chan- 

Figure 3: xxxx 

nel 12 bit ADC a power dissipation of 40mW/channel 

or 5.12 W for 128 channels can be achieved. 

Furthermore, as demand grows for portable 

systems that shrink the size of an ultrasound 

scanner from a small rack to the size of a notebook 

or even smaller, ADC power dissipation is 

an important design parameter in realizing a 

compact and low-cost system that needs minimal 

cooling, whether the conversion takes place 

in the transducer head or the PU. New systems 

may also be battery operated, so minimizing 

power consumption is even more critical. 

The simplified architecture of an ultrasound 

system with analog-to-digital conversion using 

CTΔΣ ADCs in the transducer head is shown in 

Figure 3. In addition to the ADCs, the active transducer 

houses low power variable gain amplifiers, 

serializers and a digital interface, enabling a 

greatly reduced number of cables to be used to 

interconnect with the main processor unit. 

Summary 

The advantages of CDTS ADCs are apparent wherever 

high speed, high resolution conversion is needed 

at the lowest possible power consumption. In 

sensor-related applications in automotive, medical, 

industrial and test and measurement equipment, 

the technology can be used to create new architectures 

where the conversion to a digital signal is carried 

out close to the sensor. The benefits of the 

CTΔΣ ADC conversion process itself are compelling 

and the additional system level benefits of lower 

cost cables and interconnect, and the option to use 

lower performance, lower cost receivers add to the 

attractions of this technology. 

www.xignal.com


48 

Flash storage solutions for 

microcontrollers 

Dave Hughes, HCC-Embedded 

Flash memory provides many advantages, but designers 

need to take care to extract these benefits. 

IN RECENT YEARS flash based 

microcontrollers have flooded the market 

from all the major players – they are now 

the norm rather than the exception. 

Additionally the arrival of ever larger serial flash 

devices with small erasable sectors has given 

the possibility of extending the storage capabilities 

of micros without the requirement for additional 

resources. 

Many new applications immediately suggest 

themselves, such as field customisation, field 

upgrades, dynamic configuration files, data logging, 

diagnostics and more. 

But can this flash be used as more than a 

masked ROM substitute? Can the flash be used 

reliably for these new applications? We are paying 

for the more sophisticated flash solution – 

but how do we extract the benefits? 

Flash basics 

Firstly we need to look at the issues: All flash is 

different – the specifications for each device 

used must be studied to get reliable results from 

a flash device. It is hard to find two devices from 

different product families which have identical 

flash characteristics but there are some basic 

features which are common to most: 

● Can only write down i.e. 1’s to 0’s 

● Must Erase in Blocks to set bits back to 1. 

● Write in pages or Bytes depending on flash 

type 

● Some devices write to RAM buffer and erase 

the page before writing 

● Some flash types may need refreshing to 

prevent bit flipping 

● Some devices have cumulative write time 

limits before a refresh must be done 

● All devices have a typical Erase/write Cycle 

limitation before errors develop 

● Wear-levelling is a useful process to counter 

this limitations 

● Unexpected reset problem – both in write 

and erase operations – if a write or erase is 

broken then the results in the page are 

unpredictable and it is necessary to be sure 

whether a page is valid or not. 

● Power Management – all flash is sensitive 

to unstable voltages – if the power drops 

below the specified level then erase and 

write operations will have unpredictable 

results. 

It is this collection of characteristics on flash 

devices which creates the challenge – how to 

use this flash reliably? 

Use a file system 

These problems are quite complex to address 

and there are different rules for every flash 

device type which have to be taken in to consideration 

in any design. One method to hide all 

this complexity from the developer is to use a 

file system – specifically designed for the target 

flash – which means the developer can access 

the flash thorough standard API calls and can 

forget about the details of what happens underneath. 

Using a file system has many benefits. Data 

becomes position independent, this is managed 

by the file system. There is a standard interface 

to data which makes for easy porting and testing 

across a range of platforms if necessary. And 

finally, as the the flash technology is hidden 

from the designer they are free to focus on their 

core competences. 

Connecting to a host 

The “standard route” for connecting embedded 

file systems to a host system would be to add a 

USB Mass Storage interface and a FAT file system 

but there are some disadvantages to this 

approach for embedded systems developers. As 

the FAT file system is not fail safe there needs to 

be a check disk available. While this acceptable 

when a device is connected to the PC, what happens 

when it is in the field? FAT is space hungry, 

requiring a minimum of 20K disk space before 

storing data, which can be a significant overhead 

for many flash micros. When the host accesses 

the file system the target must stop access and 

vice versa, as either system can modify the FAT 

But can flash be used as more than a masked ROM substitute? Can it be used 

reliably for new applications? We are paying for the more sophisticated flash 

solution – but how do we extract the benefits? 

Figure 1: uCDrive. 

structures, however there is no way to inform the 

host that the target has made changes or vice 

versa. There are no security options on a FAT system. 

And, what can be a major factor, USB can be 

relatively expensive to design in. 

Another possibility is to provide specialized 

host drivers which interface to the embedded 

device in much the same way as NFS works – the 

file system is managed on the target in a reliable 

way – all systems access it through API calls. A 

virtual drive can then be created on the host system 

to give the user seamless drag and drop, double 

click access to the targets file system. HCC- 

Embedded specialises in small footprint, reliable, 

file systems designed for a variety of different 

flash devices both using internal microcontroller 

flash and externally connected small sector flash. 

The uCDrive system provides this connectivity 

through a serial port, and HCC will soon be providing 

USB connectivity. Your embedded system 

then truly appears as a standard drive . 

 

www.hcc-embedded.com


A Standard individual: 

Engineering Standard, 

Marketing Release or both? 

Chris Hills 

Integrated 

Development 

Environments 

T 

Optimising 

Compilers 

Debugging & 

Performance 

Analysis 

HIS MONTH I am going back to the root of the column: 

Standards. First a quick round up of where MISRA 

is at. The MISRA-C group has started on the example 

test suite. It is progressing well and we hope to have it 

finished for the end of 06. Maybe for ESS06. We are also working 

on the Technical Corrigendum and by implication MISRA-C. 

I think we suggested we should have MISRA-C:2009. 

The MISRA-C++ team is having fun. They have assembled 

a team and are sorting out terms of reference in parallel with 

gathering source material and there is a lot of source material. 

Interestingly they tell me that most of the C++ subsets and 

coding standards they have seen have a lot in common. There 

is also the C++ coding standard from the Joint Strike Fighter 

project in the US called JSF++, which is “secret” and can only 

be seen by Security Cleared US Nationals. 

The MISRA Autocode is progressing well. The effort is 

being well supported with a good number of European OEMs 

and Tier 1s along with a smaller involvement from the USA. 

The European support is quite wide and not just the German 

automotive industry as was feared by some. I did enquire 

about first drafts for review and “mid 06” was vaguely suggested 

which means it will probably be Christmas 06. 

A less well-known MISRA standard is the Software 

Readiness for Production guide. Sources in MIRA say this 

document will be published in February 2006. 

MISRA Safety Analysis - this gives guidance on the management 

of functional safety for IEC 61508 lifecycle will be 

published mid 2006. So MISRA is doing a lot. 

New versions of C? 

Having covered the MISRA guides it is time to look at the other 

standards. Now things get vague. For some reason the C panels 

seem to have veered away from the industry. The industry, 

compiler writers and others like MISRA have stopped at C 1990 

with the amendments up to 1993/4. A part of the standards 

development process is the publication of Technical Reports. 

These are exactly what they say and are NOT part of the 

Real-Time 

Operating 

Systems 

Hardware 

Debug 

Probes 

All 

Royalty 

Free! 

Standard though often they form the basis of work that does 

get into the next version where appropriate. Two that have 

come through are the Microsoft C and C++ “Safe” Libraries and 

these may have long term consequences for the future of C. 

There is also provision for ECMA the European Computer 

Manufacturers Association to fast track completed standards 

to the final stage of ISO voting. Among those that have come 

through are a standard for C# and for C++/CLI (Common 

Language Interface). This last actually extends C++ by adding 

a couple of dozen key words and changing the way some constructs 

work, which appear to be based on Microsoft implementations 

and extensions to C++. If these get passed along 

with the two libraries in the TRs for C, then it appears to me 

as though MS C, C# & C++ will be the standard, and the 

Microsoft platform will be the only one that conforms to the 

ISO standards. I hope I am misunderstanding this. 

Ethics 

Finally I should like to bring to your attention an item from an 

IEEE newsletter. It said that: Universities no longer assume that 

the new engineer will learn ethical practices on the job and are 

now offering instruction on the subject. The IEEE is also playing 

a role in highlighting ethical practices by promoting students' 

awareness of their professional responsibilities as engineers. 

Find out more at http://boldfish.ieee.org:80/u/1353/41449924 

I wonder if they will cover Standards in their ethics classes 

or if they will run correspondence classes for busy engineers 

in other parts of the country… 

I had a quite a response from last months column! 

Thanks to all who emailed me, I intend to revisit the subject 

in a future column. I have received the first notifications of 

ESS 06. I will be there. Will you? 11 & 12th October at the 

NEC Birmingham. Stick it in the diary. 

These are not in any way an official statement or committee view, but my own 

personal views and those of my company PhaedruS SystemS. www.phaedsys.org 

which is where the full version of this column resides under the Technical Papers 

button. Any comments, praise or legal documents to chills@phaedsys.org. 

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