Newsletter_07-2024_EN
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Improved die-to-wafer assembly flow opens doors to logic/memory-on-logic stacking,<br />
and to optically interconnected systems-on-wafer<br />
Imec demonstrates die-to-wafer<br />
hybrid bonding with a Cu<br />
interconnect pad pitch of 2µm<br />
This week, at the <strong>2024</strong> IEEE Electronic Components and Technology<br />
Conference (ECTC), imec, a world-leading research and innovation<br />
hub in nanoelectronics and digital technologies, presents a<br />
Cu-to-Cu and SiCN-to-SiCN die-to-wafer bonding process resulting<br />
in a Cu bond pad pitch of only 2µm at
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