MS_DEAL_TESTJIG_BACKPLANE_REVA

5

4

3

2

1

TEST JIG BACK PLANE

D

TABLE OF CONTENTS

D

C

C

B

B

A

A

REV NO. NATURE OF CHANGE APPROVED BY DATE

5

4

Mistral Solutions Pvt. Ltd.

No.60, 'Adarsh Regent', 100 Feet Ring Road, Domlur Extension

Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B

Friday, December 01, 2023

Approved By:

Date:

Debashis

Tuesday, March 12, 2024

Title

Size TABLE OF CONTENTS

Document Number Rev

B

MS_DEAL_LTR_TESTJIG_BACK PLANE

A

Design file path:

D:\LTR\BPC_TESTJIG-02\SCHEMATIC\MOTHER\A0-15\MS_DEAL_LTR_TESTJIG_BACKPLANE_A0-15.DSN

Date: Friday, March 08, 2024

Sheet 1 o f

26

3

2

1

5

4

3

2

1

VERSION HISTORY

D

VER # DATE

DESCRIPTION OF CHANGES AUTHOR

REVIEWED BY

APPROVED BY

D

0.01 19-AUG-2023 Initial Draft

RAVI TEJA B

KARTHIKAICHELVAN

DEBASHIS PRADHAN

C

C

B

B

A

A


5

4



Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B


Approved By:

Date:

Debashis


Title

Size VERSION HISTORY

Document Number Rev

B


A

Design file path:



Sheet 2 o f

26

3

2

1

5

4

3

2

1

D

D

C

C

B

B

A

A


5

4



Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B


Approved By:

Date:

Debashis


Title

Size BLOCK DIAGRAM

Document Number Rev

B


A

Design file path:



Sheet 3 o f

26

3

2

1

5

4

3

TEST JIG - CIRCULAR VPX_CONNECTOR_J0

2

1

D

VS3_5V0

TP47

TP20_SMD

VS3_5V0

VPX_JTAG_TRSTn

A1

A2

A3

A4

A5

A6

A7

A8

C1

C2

C3

C4

C5

C6

C7

C8

J18A

B1

B2

B3

B4

B5

B6

B7

B8

D1

D2

D3

D4

D5

D6

D7

D8

VS3_5V0

VPX_JTAG_TMS {10}

VS3_5V0

VS3_5V0

J18B

VS1_12V0

E1

F1

E2

F2

E3

F3

E4

F4

VS3_5V0

E5

F5

E6

F6

{10} VPX_JTAG_TDI

E7

F7

E8

F8

VPX_JTAG_TDO {10}

VS1_12V0

VS1_12V0

G1

G2

G3

G4

G5

G6

G7

G8

H1

H2

H3

H4

H5

H6

H7

H8

VS3_5V0

VS3_5V0

{10} VPX_JTAG_TCK

VS1_12V0

I1

I2

I3

I4

I5

I6

I7

I8

J18C

CON_VPX_8X9_1410186-1

D

CON_VPX_8X9_1410186-1

CON_VPX_8X9_1410186-1

C

C

B

MH4

MHOLE_PAN HEAD_M3_PTH

M3 PLATED PAN HEAD MOUNTING HOLE

MH2

MH6

MH5




ACC5

1

2

3

4

5

6

ACCESSORIES

ACC3

1

2

3

4

5

6

ACC2

1

2

3

4

5

6

B

GUIDEPIN

GUIDEPIN

GUIDEPIN

MH8


MH9


MH7


MH1


ACC4

1

2

3

4

5

6

ACC6

1

2

3

4

5

6

ACC1

1

2

3

4

5

6

MH10

MH3

GUIDEPIN

GUIDEPIN

GUIDEPIN



A

A


5

4



Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B


Approved By:

Date:

Debashis


Title

Size CIRCULAR_VPX_CONNECTOR_J0

Document Number Rev

B


A

Design file path:



Sheet 4 o f

26

3

2

1

5

4

3

2

1


J13A

J13B

D

C

{14,19} RS232_CIRC_TX0

A1

B1

A2

B2

RS232_CIRC_RX0 {14,19}

{15} LVDS_RX_P0

A3

B3

A4

B4

LVDS_RX_N0 {15}

A5

B5

A6

B6

{13} VPX_OLED_/BS0

A7

B7

A8

B8

VPX_OLED_SCK {13}

{13} C1

{13} R6

{11} RS232_TX2

LVDS_RX_P1

{13} VPX_OLED_/RES

{13} R3

{11} OPAMP_SPEAKER

A9

A10

A11

A12

A13

A14

A15

A16

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

B9

B10

B11

B12

B13

B14

B15

B16

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

C2 {13}

RS232_RX2 {11}

LVDS_RX_N1

VPX_OLED_D/C {13}

R2 {13}

OPAMP_MIC {11}

{14,19} RS232_CIRC_TX1

{15} LVDS_TX_P0

{13} VPX_OLED_MOSI

{13} C3

{11} RS232_TX3

LVDS_TX_P1

{13} VPX_OLED_/CS

{13} R4

E1

E2

E3

E4

E5

E6

E7

E8

E9

E10

E11

E12

E13

E14

E15

E16

G1

G2

G3

G4

G5

G6

G7

G8

G9

G10

G11

G12

G13

G14

G15

G16

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

F11

F12

F13

F14

F15

F16

H1

H2

H3

H4

H5

H6

H7

H8

H9

H10

H11

H12

H13

H14

H15

H16

RS232_CIRC_RX1 {14,19}

LVDS_TX_N0 {15}

VPX_OLED_MISO {13}

R1 {13}

RS232_RX3 {11}

LVDS_TX_N1

VPX_OLED_/BS1 {13}

R5 {13}

FPGA_GPIO11

{12} 1PPS_SIGNAL

{12} FPGA_GPIO2

{12} FPGA_GPIO6

TP27

TP20_SMD

FPGA_GPIO11

I1

I2

I3

I4

I5

I6

I7

I8

I9

I10

I11

I12

I13

I14

I15

I16

J13C

CON_VPX_16X9_1410140-1

D

C

CON_VPX_16X9_1410140-1

CON_VPX_16X9_1410140-1

Testing purpose Test Points

B

TP41

LVDS_TX_P1

C29

0.1uF

LVDS_RX_P1

TP39

B

TP20_SMD

DNI

TP20_SMD

TP35

LVDS_TX_N1

C26

0.1uF

LVDS_RX_N1

TP37

TP20_SMD

DNI

TP20_SMD

A

A


5

4



Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B


Approved By:

Date:

Debashis


Title


Document Number Rev

B


A

Design file path:



Sheet 5 o f

26

3

2

1

5

4

3

2

1


D

C

{14,19} RS422_CIRC_TX_P2

{11} RS422_TX_P4

{13} LED_DRIVER_PWM

{19} FPGA_ETH_PORT1_CIRC_TRX_P0

{14,19} RS422_CIRC_TX_P1

{14,19} RS422_CIRC_TX_P3

{9} HPS_UART_RX

{19} FPGA_ETH_PORT0_CIRC_TRX_N3

{19} HPS_ETH_PORT0_CIRC_TRX_N1


A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

J6A

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

RS422_CIRC_TX_N2 {14,19}

RS422_TX_N4 {11}

FPGA_GPIO10

FPGA_ETH_PORT1_CIRC_TRX_N0 {19}

RS422_CIRC_TX_N1 {14,19}

RS422_CIRC_TX_N3 {14,19}

HPS_UART_TX {9}

FPGA_ETH_PORT0_CIRC_TRX_P3 {19}

HPS_ETH_PORT0_CIRC_TRX_P1 {19}


{14,19} RS422_CIRC_RX_P2

{11} RS422_RX_P4

{12} FPGA_GPIO7




{14,19} RS422_CIRC_RX_P1

{14,19} RS422_CIRC_RX_P3

{12} FPGA_GPIO5




{19} HPS_ETH_PORT0_CIRC_TRX_P0


E1

E2

E3

E4

E5

E6

E7

E8

E9

E10

E11

E12

E13

E14

E15

E16

G1

G2

G3

G4

G5

G6

G7

G8

G9

G10

G11

G12

G13

G14

G15

G16

J6B

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

F11

F12

F13

F14

F15

F16

H1

H2

H3

H4

H5

H6

H7

H8

H9

H10

H11

H12

H13

H14

H15

H16

RS422_CIRC_RX_N2 {14,19}

RS422_RX_N4 {11}

FPGA_GPIO0 {12}




RS422_CIRC_RX_N1 {14,19}

RS422_CIRC_RX_N3 {14,19}

FPGA_GPIO9 {12}




HPS_ETH_PORT0_CIRC_TRX_N0 {19}


D

C

CON_VPX_16X9_1410142-1

CON_VPX_16X9_1410142-1

J6C

B

TP6

TP20_SMD

FPGA_GPIO10

{12} FPGA_GPIO4

{12} FPGA_GPIO8

{12} FPGA_GPIO1

{12} FPGA_GPIO3

I1

I2

I3

I4

I5

I6

I7

I8

I9

I10

I11

I12

I13

I14

I15

I16

B

CON_VPX_16X9_1410142-1

A

A


5

4



Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B


Approved By:

Date:

Debashis


Title


Document Number Rev

B


A

Design file path:



Sheet 6 o f

26

3

2

1

5

4

3

2

1

POWER_REGULATOR_12V_&_5V

VCC_28V0_VOUT

VCC_12V0_VOUT

D

VCC_28V0_VOUT

C41

+

100uF_50V

C70

10uF

R134

0E

MOD1

1

VIN+

VOUT+

8

2

ON/OFF

SENSE +

7

3

VIN-/GND

TRIM 6

VOUT-/GND 4

I6A24014A033V-001-R

R133

1.4K_1%

C72

10uF

C66

10uF

C71

0.1uF

C65

22uF

Power Decaps & Filtering

FL6

1 2

D

VCC_12V0_VOUT

FL7

50E

VS1_12V0

1 2

C

B

VCC_12V0_VOUT

R103

68.1K_1%

R104

9.31K_1%

VCC_12V0_VOUT

INH/UVLO

C32

+

68uF_25V

C33

UVLO is set at 10V input

22uF

R95 0E

C34

0.1uF

R98 267E_1%

5V_PWR_GD

R88 105K_1%

C39 4700pF

R102 0E

INH/UVLO

VCC_5V0_VOUT

R81

1K

U13

39

40 PVIN1

41

PVIN2

PVIN3

42

VIN

43

VADJ

33

35 PWRGD

6 RT/CLK

7 SS/TR

STSEL

8

9 INH/UVLO_1

INH/UVLO_2

3

4

DNC1

5 DNC2

15 DNC3

16 DNC4

18 DNC5

19

DNC6

20 DNC7

22 DNC8

DNC9

PGND

PGND

PGND

AGND

AGND

AGND

AGND

36

37

38

1

2

34

45

21

VO1 24

VO2

25

VO3 26

VO4 27

VO5 28

VO6 29

VO7

47

VO8

44

SENSE+

10

PH1 11

PH2 12

PH3 13

PH4 14

PH5

17

PH6 46

PH7

23

DNC10

30

DNC11 31

DNC12 32

DNC13

LMZ31503RUQR

C30

47uF

C31

VCC_5V0_VOUT

Sense must be taped from load end

Make Plane for PH pins as

recommended in the layout

guideline

VCC_3V3

47uF

C53

+

100uF_16V

100uF_25V

E7260

25V

C60

+ C74

VCC_5V0_VOUT

C58

+

100uF_25V

E7260

25V

22uF

2220

63V

C59

10uF

1210

50V

C73

10uF

1210

50V

C37

0.1uF

0402

16V

C36

0.1uF

0201

35V

C61

0.1uF

MP2

FL5

50E

1 2

1

50E

C75

+

100uF_25V

E7260

25V

C76

22uF

2220

63V

VS3_5V0

C63

0.1uF

0402

16V

VCC_28V0_VIN

0.1uF

VCC_28V0_VIN

C38

C69

0.1uF

0201

35V

FL4

1 2

VCC_28V0_VOUT

C40

50E +

100uF_40V

HCASE

40V

C35

22uF

2220

63V

C

B

3

1 2

LD4

APPA3010CGCK

5V_PWR_GD

R89

10K

STUD_KFH-M3-10ET

MP1

1

STUD_KFH-M3-10ET

A

A


5

4



Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B


Approved By:

Date:

Debashis


Title

Size POWER REGULATOR-1

Document Number Rev

B


A

Design file path:



Sheet 7 o f

26

3

2

1

5

4

3

2

POWER_REGULATOR_5V_&_3V3 & 1V8

1

D

C

VCC_5V0

INT_VCC_3V3

C7

0402

+ C8

22uF_16V

0.1uF

INT_VCC_3V3

R2

180K_0.1%

0402

DNI

C9

10uF

C2

0.1uF

0402

C1

10uF

DNI

5V TO 3.3V, 1V8 GENERATION

R6

324K_1%

0402

U1

D3

E2 VIN1_1

VIN1_2

A2

B3 VIN2_1

VIN2_2

D2

B2 RUN1

RUN2

C3

C5

INTVCC

SYNC/MODE

E3

A3 TRACK/SS1

TRACK/SS2

C4

FREQ

LTM4622EV

LGA25

2.5A EACH

GND

GND

GND

GND

B5

C1

C2

D5

D1

VOUT1_1 E1

VOUT1_2

A1

VOUT2_1 B1

VOUT2_2

E5

COMP1 A5

COMP2

E4

FB1 A4

FB2

D4

PGOOD1

B4

PGOOD2

FB1

FB2

PG_3V3

PG_1V8

PG_3V3

PG_1V8

R8

R4

C5

22uF

C4

22uF

040210K

040210K

0402

+ C6

47uF_10V

R1

R3

30.1K_1%

INT_VCC_3V3

R16

+ C3

47uF_10V

0E

0402

0E

VCC_3V3

TP4

VCC_1V8_PWR

TP1

R10

13.3K_0.1%

SMD

SMD

TP30_SMD

TP30_SMD

VDD_2V5

2

1

0402

R55

330E

0402

LD2

VLMS1500-GS08

VCC_3V3

2

1

0402

R30

330E

0402

LD1

VLMS1500-GS08

D

C

VCC_5V0_VOUT

FL2

VCC_5V0

B

1 2

50E

VCC_3V3

C10

0.1uF

0402

C11

4.7uF

0402

3V3 TO 2V5 LDO FOR ADC

R34

0E_1%

0402

U3

7

8 VIN1

VIN2

5

EN

4

SS

ADM7172ACPZ-2.5

C13

1000pF

6

GND

1

VOUT1 2

VOUT2

3

SENSE

9

EP

R46

0E

VDD_2V5

C14

4.7uF

0402

B

A

A


5

4



Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B


Approved By:

Date:

Debashis


Title

Size POWER REGULATOR-2

Document Number Rev

B


A

Design file path:



Sheet 8 o f

26

3

2

1

5

4

3

2

1

D

USB-TO-UART

D

USB_BUS_PWR_5V0

FB7

VCC_FT232_CIR

VCC_3V3 VCC_FT232_CIR VCC_1V8_PWR

FB8

1 2

120E

DNI

VCC_FT232_CIR

1 2

120E

C27 C28

0.1uF 4.7uF

C22

0.1uF

USB_3V3_OUT

C25

TP38

R84

0.1uF

C

HPS_UART_TX

R70

4.7K_1%

4.7K_1%

VCC_1V8_PWR

{10} USB_DM

{10} USB_DP

TP26

TP30_SMD

TP25

TP30_SMD

TP34

TP30_SMD

TP33

TP30_SMD

U11

15

USBDM

14

USBDP

18

RESET#

6

DSR#

7

DCD#

8

CTS#

3

RI#

26

TEST

27

OSCI

28

OSCO

FT232RNQ

VCC 19

VCCIO 1

GND

GND

GND

AGND

EP

4

17

20

24

33

16

3V3OUT

TXD 30

RXD 2

32

RTS#

31

DTR#

22

CBUS0 21

CBUS1 10

CBUS2

11

CBUS3 9

CBUS4

5

NC1 12

NC2

13

NC3 23

NC4 25

NC5 29

NC6

R74

R72

0E

0E

TP31

TP30_SMD

TP42 TP30_SMD

TP40 TP30_SMD

TP20 TP30_SMD

TP24 TP30_SMD

TP17 TP30_SMD

HPS_UART_RX {6}

HPS_UART_TX {6}

C

HPS_UART_RX

R78

4.7K_1%

B

B

A

A


5

4



Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B


Approved By:

Date:

Debashis


Title

Size USB TO UART

Document Number Rev

B


A

Design file path:



Sheet 9 o f

26

3

2

1

5

4

3

2

1

USB, 1-PPS AND JTAG PROTECTION

USB PROTECTION

D

JTAG AND 1PPS SIGNALS PROTECTION

D

VCC_5V0_VOUT

FB3

USB_BUS_PWR_5V0 FB6 USB_BUS_PWR_5V0_FIL USB_BUS_PWR_5V0_CIRC

1 2

90E

1 2

90E

F1

1 2

0.5A

{19} VPX_JTAG_TCK_CIRC

D8

8

1

R75

0E

VPX_JTAG_TCK {4}

7

2

{9} USB_DP

{9} USB_DM

6

7

U12

3

D1+ 2

D1-

ID 4

ECMF02-4CMX8

D2+

D2-

GND

1

VBUS

GND

8

5

USB_DP_CIRC {19}

USB_DM_CIRC {19}

6

3

5

4

LCDA05.TBT

{19} VPX_JTAG_TMS_CIRC

R83

0E

VPX_JTAG_TMS {4}

C

C

R69

{19} VPX_JTAG_TDI_CIRC

D7

8

1

0E

VPX_JTAG_TDI {4}

7

2

ADC PROTECTION CIRCULAR

R12

6

5

3

4

LCDA05.TBT

R73

{19} VPX_JTAG_TDO_CIRC

VPX_JTAG_TDO {4}

B

0E

R7

VCC_5V0_VOUT

0E

B

VDD_2V5

R11

U2

4

-

3

+

5

2

OUT

1

0E

R5

R9

0E

AIN_P1 {19}

AIN_N1 {19}

0E

OPA320AIDBVR

0E

A

A


5

4



Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B


Approved By:

Date:

Debashis


Title

Size USB.1-PPS AND JTAG PROTECTION CKT

Document Number Rev

B


A

Design file path:



Sheet 10 o f

26

3

2

1

5

4

3

2

1

CONNECTORS RS232 & RS422

D

RS232 X2 RS422 X1 RJ11 X1

D

J1

{5} RS232_TX3

{5} RS232_RX3

1

3

5

7

9

J12

2

4

6

8

10

{5} RS232_TX2

{5} RS232_RX2

1

3

5

7

9

J10

2

4

6

8

10

{6} RS422_TX_P4

{6} RS422_TX_N4

{6} RS422_RX_P4

{6} RS422_RX_N4

1

3

5

7

9

J4

2

4

6

8

10

4

3

2

1

OPAMP_SPEAKER {5}

OPAMP_MIC {5}

CON_BOX_2X5_M

CON_BOX_2X5_M

CON_BOX_2X5_M

CON_RJ45-4_42410-6314

C

C

D6

10

RS422_TX_P4

FAN CONNECTOR

VCC_12V0_FAN

B

8

7

11

4

14

9

6

5

13

12

RS422_TX_N4

RS422_RX_P4

RS422_RX_N4

RS232_TX2

RS232_RX2

VCC_12V0_VOUT

FL1

VCC_12V0_FAN

2

60E

FB9

1

J22

1

3

2

CON_PWRJACK3_PJ-102A

B

1

3

RS232_TX3

1 2

2

RS232_RX3

50E

SMDA12C-8.TBT

VCC_12V0_FAN

2

60E

FB1

1

J3

1

3

2

A

CON_PWRJACK3_PJ-102A

A


5

4



Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B


Approved By:

Date:

Debashis


Title

Size CONNECTORS RS232,RS422 & RJ11

Document Number Rev

B


A

Design file path:



Sheet 11 o f

26

3

2

1

5

4

3

GPIO PROTECTION

2

1

VCC_1V8_PWR VCC_5V0_VOUT VCC_1V8_PWR

VCC_5V0_VOUT

D

C42

0.1uF

U14

1

14

C43

0.1uF

C48

0.1uF

U16

1

14

C49

0.1uF

FPGA_CIRC_GPIO0

D1

1

8

FPGA_CIRC_GPIO4

D3

1

8

D

{6} FPGA_GPIO0

{6} FPGA_GPIO1

{5} FPGA_GPIO2

{6} FPGA_GPIO3

VCC_1V8_PWR R109

10K

2

3

4

5

8

A1

A2

A3

A4

OE

VCCA

7

GND

VCCB

13

B1 12

B2 11

B3

10

B4

6

NC1 9

NC2

TXB0104QPWRQ1

FPGA_FIL_GPIO0

FPGA_FIL_GPIO1

FPGA_FIL_GPIO2

FPGA_FIL_GPIO3

VCC_1V8_PWR

VCC_1V8_PWR

{6} FPGA_GPIO4

{6} FPGA_GPIO5

{5} FPGA_GPIO6

{6} FPGA_GPIO7

R117 10K

VCC_5V0_VOUT

2

3

4

5

8

A1

A2

A3

A4

OE

VCCA

7

GND

VCCB

13

B1 12

B2 11

B3

10

B4

6

NC1 9

NC2

TXB0104QPWRQ1

FPGA_FIL_GPIO4

FPGA_FIL_GPIO5

FPGA_FIL_GPIO6

FPGA_FIL_GPIO7

FPGA_CIRC_GPIO1

FPGA_CIRC_GPIO2

FPGA_CIRC_GPIO3

2

7

3

6

4 5

SMDA12C

FPGA_CIRC_GPIO5

FPGA_CIRC_GPIO6

FPGA_CIRC_GPIO7

2

7

3

6

4 5

SMDA12C

C44

C45

0.1uF

U15

1

14

0.1uF

D2

C

{6} FPGA_GPIO8

{6} FPGA_GPIO9

{5} 1PPS_SIGNAL

VCC_1V8_PWR R114

10K

2

3

4

5

8

A1

A2

A3

A4

OE

VCCA

GND

VCCB

B1

B2

B3

B4

NC1

NC2

13

12

11

10

6

9

FPGA_FIL_GPIO8

FPGA_FIL_GPIO9

1PPS_SIGNAL_FIL

FPGA_CIRC_GPIO8

FPGA_CIRC_GPIO9

1PPS_SIGNAL_CIRC

1

2

3

8

7

6

C

7

TXB0104QPWRQ1

4 5

FPGA_FIL_GPIO0

R14

FPGA_CIRC_GPIO0 {19}

FPGA_FIL_GPIO4

R38


SMDA12C

0E

0E

FPGA_FIL_GPIO1

R17


FPGA_FIL_GPIO5

R40


FPGA_FIL_GPIO8

R28


0E

0E

0E

B

B

FPGA_FIL_GPIO2

R20


FPGA_FIL_GPIO6

R41


FPGA_FIL_GPIO9

R31


0E

0E

0E

FPGA_FIL_GPIO3

R24


FPGA_FIL_GPIO7

R45


1PPS_SIGNAL_FIL

R33

1PPS_SIGNAL_CIRC {19}

0E

0E

0E

A

A


5

4



Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B


Approved By:

Date:

Debashis


Title

Size GPIO PROTECTION CIRCUIT

Document Number Rev

B


A

Design file path:



Sheet 12 o f

26

3

2

1

5

4

3

2

1

OLED & KEYPAD CONNECTOR

D

OLED CONNECTOR

VCC_5V0

D

{5} VPX_OLED_/RES

{5} VPX_OLED_D/C

{5} VPX_OLED_/CS

{5} VPX_OLED_/BS1

{5} VPX_OLED_/BS0

{5} VPX_OLED_SCK

{5} VPX_OLED_MOSI

{5} VPX_OLED_MISO

LED_Backlight_+VE

LED_Backlight_-VE

2

4

6

8

10

12

14

16

18

20

J11

1

3

5

7

9

11

13

15

17

19

OLED_VCC

OLED_VCOMH

C23

C52

4.7uF

4.7uF

C17

2.2uF

C15

2.2uF

R49

DNI 0E_1%

R47

0E_1%

C12

0.1uF

VCC_3V3

HDR_2X10

C

C

LED DRIVER POWER SECTION

KEYPAD CONNECTOR

B

{6} LED_DRIVER_PWM

VCC_5V0

C50

1uF

L1

U17

5

VIN

4

SHDN

LT1937ES5#TRMPBF

2

GND

22uH

SW 1

3

FB

R124

1E

D10

2 1

CMDSH05-4

LED_Backlight_-VE

TP32

LED_Backlight_+VE

C51

1uF

TP36

{5} R1

{5} R2

{5} R3

{5} R4

{5} R5

1

3

5

7

9

J9

HDR_2X5

2

4

6

8

10

R6 {5}

C1 {5}

C2 {5}

C3 {5}

VCC_3V3

B

R950 = 95mV/ILED

ILED = 95mA

LED_Backlight_+VE

R122

DNI 0E_1%

OLED_VCC

LED_Backlight_-VE

R123

0E_1%

DNI

A

A


5

4



Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B


Approved By:

Date:

Debashis


Title

Size OLED & KEYPAD CONNECTOR

Document Number Rev

B


A

Design file path:



Sheet 13 o f

26

3

2

1

5

4

3

2

1

D

D

D4

8

7

11

4

14

1

10

9

6

5

13

12

3

2

RS422_CIRC_TX_P1

RS422_CIRC_TX_N1

RS422_CIRC_RX_P1

RS422_CIRC_RX_N1

RS422_CIRC_TX_P2

RS422_CIRC_TX_N2

RS422_CIRC_RX_P2

RS422_CIRC_RX_N2

RS422_CIRC_TX_P1 {6,19}

RS422_CIRC_TX_N1 {6,19}

RS422_CIRC_RX_P1 {6,19}

RS422_CIRC_RX_N1 {6,19}

RS422_CIRC_TX_P2 {6,19}

RS422_CIRC_TX_N2 {6,19}

RS422_CIRC_RX_P2 {6,19}

RS422_CIRC_RX_N2 {6,19}

C

SMDA12C-8.TBT

C

D5

8

7

11

4

14

1

10

9

6

5

13

12

3

2

RS422_CIRC_TX_P3

RS422_CIRC_TX_N3

RS422_CIRC_RX_P3

RS422_CIRC_RX_N3

RS232_CIRC_TX0

RS232_CIRC_RX0

RS232_CIRC_TX1

RS232_CIRC_RX1

RS422_CIRC_TX_P3 {6,19}

RS422_CIRC_TX_N3 {6,19}

RS422_CIRC_RX_P3 {6,19}

RS422_CIRC_RX_N3 {6,19}

RS232_CIRC_TX0 {5,19}

RS232_CIRC_RX0 {5,19}

RS232_CIRC_TX1 {5,19}

RS232_CIRC_RX1 {5,19}

SMDA12C-8.TBT

B

B

A

A


5

4



Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B


Approved By:

Date:

Debashis


Title

Size RS232 & RS422 PROTECTION CIRCUIT

Document Number Rev

B


A

Design file path:



Sheet 14 o f

26

3

2

1

5

4

3

2

1

5V POWER AND LVDS PROTECTION

LVDS_TX_P0

LVDS PROTECTION

D

R66

Place it near U4

100E_1%

LVDS_TX_N0

{5} LVDS_TX_P0

{5} LVDS_TX_N0

U8

6

OUT_1+

5

OUT_1-

U9

3

2 IN+

IN-

VCC_3V3_PWR

VCC 5

C19

0.1uF

6

OUT+ 7

OUT-

LVDS_TX_P0_FIL

LVDS_TX_N0_FIL

IN_1-

IN_1+

1

2

LVDS_TX_P0_CIRC {19}

LVDS_TX_N0_CIRC {19}

D

VCC_3V3_PWR

R63

10K

8

EN

1

GND

NC 4

DS90LV001TM

4

VN

3 VN

EMI8141MUTAG

VCC_3V3_PWR

C16

0.1uF

C

VCC_3V3

R120

0E

VCC_3V3_PWR

{5} LVDS_RX_P0

{5} LVDS_RX_N0

IN+

IN-

U5

6

7 OUT+

OUT-

VCC 5

OUT_1-

3

2

LVDS_RX_P0_FIL

LVDS_RX_N0_FIL

U6

6

OUT_1+

5

IN_1+

IN_1-

1

2

LVDS_RX_P0_CIRC {19}

LVDS_RX_N0_CIRC {19}

C

4

NC

1

GND

10K

EN 8

DS90LV001TM

R52

VCC_3V3_PWR

LVDS_RX_P0_FIL

R56

4

VN

3 VN

EMI8141MUTAG

Place it near U6

100E_1%

LVDS_RX_N0_FIL

VCC_3V3_JTAG PROTECTION

B

B

VCC_3V3_PWR VCC_3V3_PWR_FIL VCC_3V3_JTAG

FB12

1 2

90E

SD05C.TCT

2 1

D9

F2

1 2

0.5A

A

A


5

4



Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B


Approved By:

Date:

Debashis


Title

Size 5V POWER & LVDS PROTECTION CIRCUIT

Document Number Rev

B


A

Design file path:



Sheet 15 o f

26

3

2

1

5

4

3

2

1

BPC VPX_CONNECTOR_J0

D

D

J19A

VS1_12V0

C

VS3_5V0

TP48

TP20_SMD

VS3_5V0

BPC_VPX_JTAG_TRSTn

A1

A2

A3

A4

A5

A6

A7

A8

C1

C2

C3

C4

C5

C6

C7

C8

B1

B2

B3

B4

B5

B6

B7

B8

D1

D2

D3

D4

D5

D6

D7

D8

CON_VPX_8X9_1410186-1

1410186-1

VS3_5V0

BPC_VPX_JTAG_TMS

BPC_VPX_JTAG_TDI

VS1_12V0

VS3_5V0

VS3_5V0

E1

E2

E3

E4

E5

E6

E7

E8

G1

G2

G3

G4

G5

G6

G7

G8

J19B

F1

F2

F3

F4

F5

F6

F7

F8

H1

H2

H3

H4

H5

H6

H7

H8

CON_VPX_8X9_1410186-1

1410186-1

VS3_5V0

BPC_VPX_JTAG_TDO

VS1_12V0

VS3_5V0

VS1_12V0

VS3_5V0

BPC_VPX_JTAG_TCK

I1

I2

I3

I4

I5

I6

I7

I8

J19C

CON_VPX_8X9_1410186-1

1410186-1

C

JTAG Configuration

VCC_3V3_BPC_JTAG

B

VCC_3V3

R125

VCC_3V3_BPC_JTAG

0E

6

1

5

2

D11

BAT54TW-7

VCC_3V3_BPC_JTAG

C55

0.1uF

B

BPC_VPX_JTAG_TCK

BPC_VPX_JTAG_TDO

BPC_VPX_JTAG_TMS

BPC_VPX_JTAG_TDI

R93

R90

R85

22E_1%

22E_1%

22E_1%

JTAG_TCK_H2

JTAG_TDO_H2

JTAG_TDI_H2

10pF

10pF

10pF

3 4

J17

1

3

5

7

9

2

4

6

8

10

C54

C56

C57

HDR_2X5

A

A


5

4



Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B


Approved By:

Date:

Debashis


Title

Size <Title>

Document Number Rev

B


A

Design file path:


Date: Tuesday, March 12, 2024

Sheet 16 o f

26

3

2

1

5

4

3

2

1

BPC VPX_CONNECTOR_J1

D

C

J14A

A1

B1

{24} BPC_RS232_TX0

A2

B2

BPC_RS232_RX0 {24}

A3

B3

{24} BPC_LVDS_TX_P0

BPC_LVDS_TX_N0 {24}

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

C1

D1

{24} BPC_RS232_TX2

C2

D2

C3

D3

BPC_RS232_RX2 {24}

{24} BPC_LVDS_TX_P1

C4

D4

C5

D5

BPC_LVDS_TX_N1 {24}

C6

D6

C7

D7

C8

D8

C9

C10

C11

C12

C13

C14

C15

C16

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

D9

D10

D11

D12

D13

D14

D15

D16

CON_VPX_16X9_1410140-1

1410140-1

{26} BPC_AIN_P2

J14B

E1

F1

{24} BPC_RS232_TX1

E2

F2

BPC_RS232_RX1 {24}

E3

F3

{24} BPC_LVDS_RX_P1

BPC_LVDS_RX_N1 {24}

E4

E5

E6

E7

E8

E9

E10

E11

E12

E13

E14

E15

E16

G1

H1

{24} BPC_LVDS_RX_P0

G2

H2

G3

H3

BPC_LVDS_RX_N0 {24}

G4

H4

G5

H5

G6

H6

G7

H7

G8

H8

G9

G10

G11

G12

G13

G14

G15

G16

F4

F5

F6

F7

F8

F9

F10

F11

F12

F13

F14

F15

F16

H9

H10

H11

H12

H13

H14

H15

H16

CON_VPX_16X9_1410140-1

1410140-1

BPC_AIN_N2 {26}

J14C

I1

I2

I3

I4

I5

I6

I7

I8

I9

I10

I11

I12

I13

I14

I15

I16

CON_VPX_16X9_1410140-1

1410140-1

BPC_FPGA_GPIO12 {26}




D

C

B

B

A

A


5

4



Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B


Approved By:

Date:

Debashis


Title

Size <Title>

Document Number Rev

B


A

Design file path:



Sheet 17 o f

26

3

2

1

5

4

3

2

1

BPC VPX_Connector_J2

D

{24} BPC_FPGA_GPIO11

{23} BPC_FPGA_ETH_PORT0_TRX_P1


J7A

A1

B1

A2

B2

{24} BPC_RS422_TX_P2

A3

B3

A4

B4

BPC_RS422_TX_N2 {24}

{26} BPC_FPGA_XCVR_SERDOUT_P0

A5

B5

BPC_FPGA_XCVR_SERDOUT_N0 {26}

A6

A7

A8


{23} BPC_HPS_ETH_PORT0_TRX_P3

A9

B9

BPC_HPS_ETH_PORT0_TRX_N3 {23}

A10

B10


A11

B11


A12

A13

A14

A15

A16

B6

B7

B8

B12

B13

B14

B15

B16

BPC_FPGA_ETH_PORT0_TRX_N1 {23}


J7B

{26} BPC_AIN_P1

E1

F1

E2

F2

BPC_AIN_N1 {26}

{24} BPC_RS422_RX_P2

E3

F3

E4

F4

BPC_RS422_RX_N2 {24}

{26} BPC_FPGA_XCVR_SERDIN_P0

E5

F5

E6

F6

BPC_FPGA_XCVR_SERDIN_N0 {26}

{24} BPC_FPGA_GPIO7

E7

F7

E8

F8

BPC_FPGA_GPIO0 {24}


E9

F9

E10

F10



E11

F11

E12

F12



E13

F13

E14

F14



E15

F15

E16

F16


D

C

C1

D1


C2

D2

C3

D3



C4

D4

C5

D5


C6

D6

C7

D7

BPC_1PPS_SIGNAL {24}

C8

D8

{24} BPC_FPGA_GPIO6

BPC_FPGA_GPIO2 {24}

C9

D9


C10

D10

C11

D11



C12

D12

C13

D13



C14

D14

C15

D15



C16

D16


G1

H1


G2

H2

G3

H3



G4

H4

G5

H5


{24} BPC_FPGA_GPIO5

G6

H6

G7

H7

BPC_FPGA_GPIO9 {24}

G8

H8

{25} BPC_USB_DP



BPC_USB_DM {25}

G9

H9


G10

H10


G11

H11


G12

H12


G13

G14

G15

G16

H13

H14

H15

H16



C

CON_VPX_16X9_1410142-1

1410142-1

CON_VPX_16X9_1410142-1

1410142-1

R135

1M

B

USB_BUS_PWR_5V0

FB10

1 2

120E

VCC_5V0_USB_CONN_BPC DNI

FB11

1 2

DNI 90E

{24} BPC_FPGA_GPIO4

{24} BPC_FPGA_GPIO8

{24} BPC_FPGA_GPIO1

{24} BPC_FPGA_GPIO3

I1

I2

I3

I4

I5

I6

I7

I8

I9

I10

I11

I12

I13

I14

I15

I16

J7C


{18} BPC_HPS_ETH_PORT1_TRX_N0







8

7

6

5

4

3

2

1

SH1 SH2

SHLD2

SHLD1

J2

CON_JACK-8_6116202-1

B

CON_VPX_16X9_1410142-1

1410142-1

A

A


5

4



Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B


Approved By:

Date:

Debashis


Title

Size <Title>

Document Number Rev

B


A

Design file path:


Date: Tuesday, March 12, 2024

Sheet 18 o f

26

3

2

1

5

4

3

2

1

37 Pin Circular Connector 55 Pin Circular Connector

D

C

B

VCC_28V0_VIN

VCC_5V0_FP

R71

1K

TP44

TP22

TP2

TP3

FL3

1 2

USB_BUS_PWR_5V0_CIRC

VCC_3V3_JTAG

VCC_5V0_FP

50E

VCC_28V0_CIRC

{8} FPGA_CIRC_GPIO0

{8} FPGA_CIRC_GPIO1

{7} RS422_CIRC_RX_P1

{7} RS422_CIRC_RX_N1

{7} RS422_CIRC_TX_P1

{7} RS422_CIRC_TX_N1

{10} USB_DP_CIRC

{10} USB_DM_CIRC

{10} VPX_JTAG_TDI_CIRC

{10} VPX_JTAG_TMS_CIRC

{10} VPX_JTAG_TCK_CIRC

{10} VPX_JTAG_TDO_CIRC

{7} RS232_CIRC_TX0

{7} RS232_CIRC_RX0



GND_5V0_FIL







DN2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

CON_D38999_CIRDIN37

DN1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

CON_D38999_CIRDIN55

















1PPS_SIGNAL_CIRC {8,10}

LVDS_TX_P0_CIRC {9}

LVDS_TX_N0_CIRC {9}

LVDS_RX_P0_CIRC {9}

LVDS_RX_N0_CIRC {9}

FPGA_CIRC_GPIO2 {8}

FPGA_CIRC_GPIO3 {8}

FPGA_CIRC_GPIO4 {8}

FPGA_CIRC_GPIO5 {8}

FPGA_CIRC_GPIO6 {8}

FPGA_CIRC_GPIO7 {8}

FPGA_CIRC_GPIO8 {8}

FPGA_CIRC_GPIO9 {8}

AIN_P1 {4}

RS422_CIRC_RX_P3 {7}

RS422_CIRC_RX_P2 {7}

RS422_CIRC_RX_N2 {7}

RS422_CIRC_TX_P2 {7}

RS422_CIRC_TX_N2 {7}

AIN_N1 {10}

RS422_CIRC_RX_N3 {7}

RS422_CIRC_TX_N3 {7}

RS422_CIRC_TX_P3 {7}

RS232_CIRC_TX1 {7}

RS232_CIRC_RX1 {7}

GND_5V0_FIL

VCC_5V0_FP

LVDS_TX_P0_CIRC

Place it near DN2

LVDS_TX_N0_CIRC

R36

100E_1%

D

C

B

3

1 2

LD3

APPA3010CGCK

GND_5V0_FIL

A

A


5

4



Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B


Approved By:

Date:

Debashis


Title

Size <Title>

Document Number Rev

B


A

Design file path:



Sheet 19 o f

26

3

2

1

5

4

3

2

1

TEST JIG2 - BPC_ VPX_CONNECTOR_J0

D

VS3_5V0

TP46

TP20_SMD

VS3_5V0

TJ_VPX_JTAG_TRSTn

A1

A2

A3

A4

A5

A6

A7

A8

C1

C2

C3

C4

C5

C6

C7

C8

J20A

B1

B2

B3

B4

B5

B6

B7

B8

D1

D2

D3

D4

D5

D6

D7

D8

VS3_5V0

VS3_5V0

TJ_VPX_JTAG_TMS

TJ_VPX_JTAG_TDI

VS3_5V0

VS1_12V0

E1

E2

E3

E4

E5

E6

E7

E8

G1

G2

G3

G4

G5

G6

G7

G8

J20B

F1

F2

F3

F4

F5

F6

F7

F8

H1

H2

H3

H4

H5

H6

H7

H8

VS1_12V0

VS3_5V0

TJ_VPX_JTAG_TDO

VS3_5V0

VS1_12V0

VS3_5V0 TJ_VPX_JTAG_TCK

VS1_12V0

I1

I2

I3

I4

I5

I6

I7

I8

J20C

CON_VPX_8X9_1410186-1

D

C

CON_VPX_8X9_1410186-1

CON_VPX_8X9_1410186-1

C

JTAG Configuration

VCC_3V3_TJ_JTAG

B

VCC_3V3

R131

VCC_3V3_TJ_JTAG

0E

6

1

5

2

3 4

D12

BAT54TW-7

J21

VCC_3V3_TJ_JTAG

C64

0.1uF

B

TJ_VPX_JTAG_TCK

TJ_VPX_JTAG_TDO

TJ_VPX_JTAG_TMS

TJ_VPX_JTAG_TDI

R105

R101

R94

22E_1%

22E_1%

22E_1%

JTAG_TCK_H1

JTAG_TDO_H1

JTAG_TDI_H1

1

3

5

7

9

2

4

6

8

10

C62

C67

C68

HDR_2X5

10pF

10pF

10pF

A

A


5

4



Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B


Approved By:

Date:

Debashis


Title

Size <Title>

Document Number Rev

B


A

Design file path:



Sheet 21 o f

26

3

2

1

5

4

3

2

1

TEST JIG2 - BPC VPX_CONNECTOR_J1

D

C

J15A

{24} TJ_RS232_TX0

A1

B1

A2

B2

TJ_RS232_RX0 {24}

{24} TJ_LVDS_RX_P0

A3

B3

A4

B4

TJ_LVDS_RX_N0 {24}

A5

B5

A6

B6

A7

B7

A8

B8

A9

A10

A11

A12

A13

A14

A15

A16

C1

D1

{24} TJ_RS232_TX2

C2

D2

C3

D3

TJ_RS232_RX2 {24}

{24} TJ_LVDS_RX_P1

C4

D4

C5

D5

TJ_LVDS_RX_N1 {24}

C6

D6

C7

D7

C8

D8

C9

C10

C11

C12

C13

C14

C15

C16

B9

B10

B11

B12

B13

B14

B15

B16

D9

D10

D11

D12

D13

D14

D15

D16

J15B

E1

F1

{24} TJ_RS232_TX1

E2

F2

TJ_RS232_RX1 {24}

{24} TJ_LVDS_TX_P0

E3

F3

TJ_LVDS_TX_N0 {24}

E4

E5

E6

E7

E8

E9

E10

E11

E12

E13

E14

E15

E16

F4

F5

F6

F7

F8

G1

H1

G2

H2

{24} TJ_RS232_TX3

G3

H3

TJ_RS232_RX3 {24}

{24} TJ_LVDS_TX_P1

G4

H4

TJ_LVDS_TX_N1 {24}

G5

G6

G7

G8

G9

G10

G11

G12

G13

G14

G15

G16

F9

F10

F11

F12

F13

F14

F15

F16

H5

H6

H7

H8

H9

H10

H11

H12

H13

H14

H15

H16

{24} TJ_FPGA_GPIO11

{24} TJ_1PPS_SIGNAL

{24} TJ_FPGA_GPIO2

{24} TJ_FPGA_GPIO6

I1

I2

I3

I4

I5

I6

I7

I8

I9

I10

I11

I12

I13

I14

I15

I16

J15C

CON_VPX_16X9_1410140-1

D

C

CON_VPX_16X9_1410140-1

CON_VPX_16X9_1410140-1

B

B

A

A


5

4



Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B


Approved By:

Date:

Debashis


Title

Size <Title>

Document Number Rev

B


A

Design file path:



Sheet 22 o f

26

3

2

1

5

4

3

2

1

TEST JIG2 - BPC VPX_CONNECTOR_J2

D

C

{24} TJ_RS422_TX_P2

{24} TJ_RS422_TX_P4

{18} TJ_FPGA_ETH_PORT1_TRX_P0

{25} TJ_HPS_UART_RX

{18} TJ_FPGA_ETH_PORT0_TRX_N3

{18} TJ_HPS_ETH_PORT0_TRX_N1


A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

J8A

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

TJ_RS422_TX_N2 {24}

TJ_RS422_TX_N4 {24}

TJ_FPGA_GPIO10 {24}

TJ_FPGA_ETH_PORT1_TRX_N0 {18}

C1

D1

{24} TJ_RS422_TX_P1

C2

D2

C3

D3

TJ_RS422_TX_N1 {24}

{24} TJ_RS422_TX_P3

C4

D4

C5

D5

TJ_RS422_TX_N3 {24}

C6

D6

C7

D7

C8

D8

C9

C10

C11

C12

C13

C14

C15

C16

D9

D10

D11

D12

D13

D14

D15

D16

TJ_HPS_UART_TX {25}

TJ_FPGA_ETH_PORT0_TRX_P3 {18}

TJ_HPS_ETH_PORT0_TRX_P1 {18}


{24} TJ_FPGA_GPIO7







{18} TJ_HPS_ETH_PORT0_TRX_P0


J8B

E1

F1

E2

F2

{24} TJ_RS422_RX_P2

E3

F3

E4

F4

TJ_RS422_RX_N2 {24}

{24} TJ_RS422_RX_P4

E5

F5

TJ_RS422_RX_N4 {24}

E6

E7

E8

E9

E10

E11

E12

E13

E14

E15

E16

F6

F7

F8

TJ_FPGA_GPIO0 {24}




G1

H1

{24} TJ_RS422_RX_P1

G2

H2

G3

H3

TJ_RS422_RX_N1 {24}

{24} TJ_RS422_RX_P3

G4

H4

G5

H5

TJ_RS422_RX_N3 {24}

{24} TJ_FPGA_GPIO5

G6

H6

G7

H7

TJ_FPGA_GPIO9 {24}

G8

H8

G9

G10

G11

G12

G13

G14

G15

G16

F9

F10

F11

F12

F13

F14

F15

F16

H9

H10

H11

H12

H13

H14

H15

H16




TJ_HPS_ETH_PORT0_TRX_N0 {18}


D

C

CON_VPX_16X9_1410142-1

CON_VPX_16X9_1410142-1

J8C

B

{24} TJ_FPGA_GPIO4

{24} TJ_FPGA_GPIO8

{24} TJ_FPGA_GPIO1

{24} TJ_FPGA_GPIO3

I1

I2

I3

I4

I5

I6

I7

I8

I9

I10

I11

I12

I13

I14

I15

I16

B

CON_VPX_16X9_1410142-1

A

A


5

4



Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B


Approved By:

Date:

Debashis


Title

Size <Title>

Document Number Rev

B


A

Design file path:



Sheet 23 o f

26

3

2

1

5

4

3

2

1

TESTJIG & BPC INTERFACING - 1

D

LVDS

GPIO

D

{22} TJ_LVDS_TX_P0

{22} TJ_LVDS_TX_N0

{22} TJ_LVDS_RX_P0

{22} TJ_LVDS_RX_N0

{22} TJ_LVDS_TX_P1

{22} TJ_LVDS_TX_N1

R128

R129

R126

R127

R91

R92

0E

0E

0E

0E

0E

0E

BPC_LVDS_RX_P0 {17}

BPC_LVDS_RX_N0 {17}

BPC_LVDS_TX_P0 {17}

BPC_LVDS_TX_N0 {17}

BPC_LVDS_RX_P1 {17}

BPC_LVDS_RX_N1 {17}

{23} TJ_FPGA_GPIO0

{23} TJ_FPGA_GPIO1

{22} TJ_FPGA_GPIO2

{23} TJ_FPGA_GPIO3

{23} TJ_FPGA_GPIO4

{23} TJ_FPGA_GPIO5

{22} TJ_FPGA_GPIO6

{23} TJ_FPGA_GPIO7

{23} TJ_FPGA_GPIO8

{23} TJ_FPGA_GPIO9

{23} TJ_FPGA_GPIO10

{22} TJ_FPGA_GPIO11

{22} TJ_1PPS_SIGNAL

R18

R13

R21

R106

R15

R112

R108

R110

R107

R27

R111

R29

R113

0E

0E

0E

0E

0E

0E

0E

0E

0E

0E

0E

0E

0E

BPC_FPGA_GPIO0 {18}

BPC_FPGA_GPIO1 {18}

BPC_FPGA_GPIO2 {18}

BPC_FPGA_GPIO3 {18}

BPC_FPGA_GPIO4 {18}

BPC_FPGA_GPIO5 {18}

BPC_FPGA_GPIO6 {18}

BPC_FPGA_GPIO7 {18}

BPC_FPGA_GPIO8 {18}

BPC_FPGA_GPIO9 {18}



BPC_1PPS_SIGNAL {18}

C

{22} TJ_LVDS_RX_P1

{22} TJ_LVDS_RX_N1

R86

R87

0E

0E

BPC_LVDS_TX_P1 {17}

BPC_LVDS_TX_N1 {17}

C

RS422

RS232

UART_TX

UART_RX

{23} TJ_RS422_TX_P1

{23} TJ_RS422_TX_N1

{23} TJ_RS422_RX_P1

{23} TJ_RS422_RX_N1

R42

R48

R57

R53

0E

0E

0E

0E

BPC_RS422_RX_P1 {18}


BPC_RS422_TX_P1 {18}


UART_RX

UART_TX

B

UART_RX

UART_TX

UART_RX

UART_TX

{22} TJ_RS232_TX0

{22} TJ_RS232_RX0

{22} TJ_RS232_TX1

{22} TJ_RS232_RX1

R132

R130

R100

R99

0E

0E

0E

0E

BPC_RS232_RX0 {17}

BPC_RS232_TX0 {17}

BPC_RS232_RX1 {17}

BPC_RS232_TX1 {17}

UART_TX

UART_RX

UART_TX

UART_RX

UART_TX

UART_RX

{23} TJ_RS422_TX_P2

{23} TJ_RS422_TX_N2

{23} TJ_RS422_RX_P2

{23} TJ_RS422_RX_N2

R39

R37

R118

R119

0E

0E

0E

0E





UART_RX

UART_TX

B

UART_RX

UART_TX

UART_RX

UART_TX

{22} TJ_RS232_TX2

{22} TJ_RS232_RX2

{22} TJ_RS232_TX3

{22} TJ_RS232_RX3

R97 0E

R96 0E

TP43

TP45

BPC_RS232_RX2 {17}

BPC_RS232_TX2 {17}

UART_TX

UART_RX

UART_TX

UART_RX

{23} TJ_RS422_TX_P3

{23} TJ_RS422_TX_N3

{23} TJ_RS422_RX_P3

{23} TJ_RS422_RX_N3

R32

R35

R115

R116

0E

0E

0E

0E





UART_RX

UART_TX

UART_TX

{23} TJ_RS422_TX_P4

{23} TJ_RS422_TX_N4

TP5

TP9

UART_RX

{23} TJ_RS422_RX_P4

{23} TJ_RS422_RX_N4

TP7

TP8

A

A


5

4



Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B


Approved By:

Date:

Debashis


Title

Size <Title>

Document Number Rev

B


A

Design file path:



Sheet 24 o f

26

3

2

1

5

4

3

2

1

FPGA ETH PORT0


D

{18,23} TJ_FPGA_ETH_PORT0_TRX_P0

{18,23} TJ_FPGA_ETH_PORT0_TRX_N0



BPC_FPGA_ETH_PORT0_TRX_P0 {18,23}

BPC_FPGA_ETH_PORT0_TRX_N0 {18,23}



USB-TO-UART

D

C













{18,23} TJ_HPS_ETH_PORT0_TRX_P0

{18,23} TJ_HPS_ETH_PORT0_TRX_N0



FPGA ETH PORT1

HPS ETH PORT0













BPC_HPS_ETH_PORT0_TRX_P0 {18,23}

BPC_HPS_ETH_PORT0_TRX_N0 {18,23}



USB_BUS_PWR_5V0

FB5

1 2

120E

VCC_5V0_USB_CONN_TJ DNI

FB4

1 2

DNI 90E

TJ_HPS_UART_TX R67

TJ_HPS_UART_RX R60

4.7K_1%

4.7K_1%

VCC_FT232

VCC_FT232

R121

4.7K_1%

VCC_1V8_PWR

VCC_3V3 VCC_FT232 VCC_1V8_PWR

FB2

TP21

TP30_SMD

TP18

TP30_SMD

TP10

TP30_SMD

TP11

TP30_SMD

1 2

120E

TJ_USB_DM

TJ_USB_DP

15

14

18

6

7

8

3

26

27

28

C21

C20

0.1uF 4.7uF

U10

USBDM

USBDP

RESET#

DSR#

DCD#

CTS#

RI#

TEST

OSCI

OSCO

FT232RNQ

4

VCC 19

GND

GND

GND

17

20

VCCIO 1

24

AGND

C18

0.1uF

33

EP

3V3OUT

RXD 2

16

TXD 30

RTS#

32

31

DTR#

22

CBUS0 21

CBUS1 10

CBUS2

11

CBUS3 9

CBUS4

5

NC1 12

NC2

13

NC3 23

NC4 25

NC5 29

NC6

USB_3V3_OUT1

R65

R68

C24

0.1uF

0E

0E

TP12

TP30_SMD

TP14 TP30_SMD

TP15 TP30_SMD

TP29 TP30_SMD

TP30 TP30_SMD

TP28 TP30_SMD

TJ_HPS_UART_RX {23}

TJ_HPS_UART_TX {23}

C

B





B





VCC_5V0_USB_CONN_BPC

VCC_5V0_USB_CONN_TJ

{18} BPC_USB_DM

{18} BPC_USB_DP

TRI- PAD the Resistors


R26 DNI 0E

R76 DNI 0E

R23 0E BPC_USB_CONN_DM

TJ_USB_CONN_DM R79 0E TJ_USB_DM

R25 DNI 0E

R77 DNI 0E

R22 0E BPC_USB_CONN_DP

TJ_USB_CONN_DP R80 0E TJ_USB_DP

BPC_USB_CONN_DM

BPC_USB_CONN_DP

R19 DNI 0E

J5

1

2 VBUS

3

D-

4 D+

5 ID

GND

6

7

SH1

SH2

8

SH3

CON_MUSB-B_5_F

TJ_USB_CONN_DM

TJ_USB_CONN_DP

R82 DNI 0E

J16

1

2 VBUS

3

D-

4 D+

5 ID

GND

6

7

SH1

SH2

8

SH3

CON_MUSB-B_5_F



A

A


5

4



Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B


Approved By:

Date:

Debashis


Title

Size <Title>

Document Number Rev

B


A

Design file path:



Sheet 25 o f

26

3

2

1

5

4

3

2

1


D

D

BPC SERDES

BPC GPIO

TP23


{18} BPC_FPGA_XCVR_SERDOUT_P0

{18} BPC_FPGA_XCVR_SERDOUT_N0

C46

C47

0.1uF

0.1uF

BPC_FPGA_XCVR_SERDIN_P0 {18}

BPC_FPGA_XCVR_SERDIN_N0 {18}

TP19

TP16

TP13




C

C

BPC LOW SPEED ADC INPUT

R43

0E

R58

0E

VCC_5V0_VOUT

VCC_5V0_VOUT

R50

0E

R61

0E

U4

5

U7

5

B

VDD_2V5

R44

0E

4

3

-

+

2

OUT

1

OPA320AIDBVR

4

-

R51 0E

VDD_2V5

1

R62 0E

OUT

BPC_AIN_P1 {18}

3

+

OPA320AIDBVR

BPC_AIN_P2 {17}

R54 0E

BPC_AIN_N1 {18}

R59 0E

R64 0E

BPC_AIN_N2 {17}

2

B

A

A


5

4



Bangalore 560 071,Ph : +91-80-45621100, Fax :+91-80-25356444

Drawn by:

Date:

Ravi Teja B


Approved By:

Date:

Debashis


Title

Size <Title>

Document Number Rev

B


A

Design file path:



Sheet 26 o f

26

3

2

1

MS_DEAL_TESTJIG_BACKPLANE_REVA

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