CompTIA A+ Certification All-in-One Exam Guide

Figure 3-28 CPU-Z displaying the cache information for a Ryzen 7 processor
The L2 cache on the early CPUs that had L2 cache included on the CPU
package ran at a slower clock speed than the L1 cache. The L1 cache was in
the CPU and thus ran at the speed of the CPU. The L2 cache connected to the
CPU via a tiny set of wires on the CPU package. The first L2 caches ran at
half the speed of the CPU.
The inclusion of the L2 cache on the chip gave rise to some new terms to
describe the connections between the CPU, MCC, RAM, and L2 cache. The
address bus and external data bus (connecting the CPU, MCC, and RAM)
were lumped into a single term called the frontside bus, and the connection
between the CPU and the L2 cache became known as the backside bus (see
Figure 3-29). (These terms don’t apply well to current computers, so they
have fallen out of use. See the “Integrated Memory Controller” section later
in this chapter.)
Figure 3-29 Frontside and backside buses
NOTE To keep up with faster processors, motherboard manufacturers
began to double and even quadruple the throughput of the frontside bus.
Techs sometimes refer to these as double-pumped and quad-pumped frontside
buses.