CompTIA A+ Certification All-in-One Exam Guide

Figure 3-24 Simple pipeline
Pipelines keep every stage of the processor busy on every click of the
clock, making a CPU run more efficiently without increasing the clock speed.
Note that at this point, the CPU has four stages: fetch, decode, execute, and
write—a four-stage pipeline. No CPU ever made has fewer than four stages,
but advancements in caching (see “Cache,” next) have increased the number
of stages over the years. Current CPU pipelines contain many more stages, up
to 20 in some cases.
Pipelining isn’t perfect. Sometimes a stage hits a complex command that
requires more than one clock cycle, forcing the pipeline to stop. Your CPU
tries to avoid these stops, or pipeline stalls. The decode stage tends to cause
the most pipeline stalls; certain commands are complex and therefore harder
to decode than other commands. Current processors use multiple decode
stages to reduce the chance of pipeline stalls due to complex decoding.
The inside of the CPU is composed of multiple chunks of circuitry to
handle the many types of calculations your PC needs to do. For example, one