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z/VM: CP Commands and Utilities Reference - z/VM - IBM

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EXTERNAL<br />

►►<br />

EXTernal<br />

Authorization<br />

Purpose<br />

Oper<strong>and</strong>s<br />

KEY<br />

INTerval<br />

CALL<br />

EMERGency<br />

MALFunction<br />

code<br />

cpuaddr<br />

CR0 bitno CMD<br />

Privilege Class: G<br />

comm<strong>and</strong><br />

Use EXTERNAL to simulate external-interrupt-pending to your virtual machine.<br />

Note: The virtual machine takes immediate control.<br />

KEY<br />

identifies the operator external interrupt key. KEY is the default.<br />

INTerval<br />

identifies the interval timer at location 80. You can specify INTERVAL only if the<br />

370 Accommodation facility is active. Use the <strong>CP</strong> SET 370ACCOM ON<br />

comm<strong>and</strong> to activate the 370 Accommodation facility. When you specify<br />

INTERVAL, an interval timer interrupt is made pending.<br />

CALL<br />

identifies an external call SIGP signal from the specified virtual processor<br />

address <strong>and</strong> is accepted only when no external call is already pending.<br />

EMERGency<br />

identifies an emergency signal from the specified virtual processor address.<br />

MALFunction<br />

identifies a malfunction alert signal from the specified virtual processor address.<br />

cpuaddr<br />

identifies a virtual processor address from 0 to 3F (hexadecimal).<br />

code<br />

identifies an external interrupt code.<br />

EXTERNAL<br />

CR0 bitno<br />

indicates that a mask bit in CR0 (control register 0) is to be applied to this<br />

interrupt. The oper<strong>and</strong> bitno is the bit number in CR0 that masks this interrupt;<br />

it is a decimal number from 16 to 31. For an ESA/390 virtual machine,<br />

specifying 16-31 refers to the masks in bits 16-31 of control register 0. For a<br />

z/Architecture mode virtual machine, specifying 16-31 refers to the<br />

corresponding masks that are in bits 48-63 of control register 0.<br />

CMD comm<strong>and</strong><br />

indicates that a <strong>CP</strong> comm<strong>and</strong> is to be issued when the interrupt is reflected.<br />

►◄<br />

Chapter 2. <strong>CP</strong> <strong>Comm<strong>and</strong>s</strong> 433

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