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z/VM: CP Commands and Utilities Reference - z/VM - IBM

z/VM: CP Commands and Utilities Reference - z/VM - IBM

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STORE Guest Storage (ESA/390)<br />

Usage Notes<br />

1540 z/<strong>VM</strong>: <strong>CP</strong> <strong>Comm<strong>and</strong>s</strong> <strong>and</strong> <strong>Utilities</strong> <strong>Reference</strong><br />

specified address are used instead of the address itself. In this case, the 64 bits<br />

at the specified address are used as the new address for the Store comm<strong>and</strong>.<br />

The indirect address specified here (following INDEX <strong>and</strong> BASE) is determined<br />

after BASE <strong>and</strong> INDEX are applied.<br />

A maximum of 16 indirection characters can be specified.<br />

data<br />

is the data you want to place in storage. It takes on different meanings,<br />

depending on the type of STORE you are performing (N, S, K, or U). See the<br />

descriptions of each of these oper<strong>and</strong>s for the meaning of data.<br />

1. An attempt to store at an address in a protected page, or to change the key at<br />

an address in a protected page, results in an error message. A protected page<br />

is a page of read-only storage.<br />

2. The oper<strong>and</strong>s HOME, AREGareg., ALEThexword., <strong>and</strong> ALEThexword.ALraddr.<br />

are valid only if the the virtual machine is an ESA virtual machine.<br />

3. When you use the oper<strong>and</strong> ALEThexword.ALraddr., the primary list bit in the<br />

ALET is ignored.<br />

4. The oper<strong>and</strong>s L, PRI, SECO, HOME, ASTEraddr., STDhexword., ASNasn.,<br />

AREGareg., ALEThexword., <strong>and</strong> ALEThexword.ALraddr. use the access<br />

register translation (ART), the ASN translation or the dynamic address<br />

translation (DAT) processes. These contain special case translation processes<br />

including the following:<br />

v ALET 0 always indicates the current primary address space designated by<br />

the STD in guest control register 1, regardless of the current contents of the<br />

dispatchable-unit access list.<br />

v ALET 1 always indicates the current secondary address space designated<br />

by the STD in guest control register 7, regardless of the current contents of<br />

the dispatchable-unit access list.<br />

v Access register 0 is always treated as containing the ALET 0. The contents<br />

of access register 0 are not used during ART processing.<br />

v General register 0 is always treated as containing the value 0 when used as<br />

the base or index register. The contents of GR 0 are never used.<br />

5. The BASE oper<strong>and</strong> is primarily intended for use in conjunction with the L<br />

oper<strong>and</strong>. It allows a user to modify the storage his virtual machine uses in one<br />

less step than would otherwise be possible. Without the BASE oper<strong>and</strong>, a user<br />

may need to display the contents of a general register, then add the<br />

displacement, <strong>and</strong> then enter the STORE comm<strong>and</strong> to modify storage his<br />

program is using. With the use of access registers, the BASE option allows the<br />

user to modify storage without needing to know whether his program is<br />

currently in access register mode. This is done automatically for him by <strong>CP</strong>.<br />

6. If you use the BASEnn <strong>and</strong> INDEXnn oper<strong>and</strong>s together, the specified hexloc<br />

is used as a displacement from the address formed by the sum of the contents<br />

of the two specified registers.<br />

The values in the registers specified by the BASEnn <strong>and</strong> INDEXnn oper<strong>and</strong>s<br />

are treated as 24-bit or 31-bit real addresses according to the addressing<br />

mode (A) bit in the virtual machine’s PSW. That is, if the A bit is 1, the value is<br />

a 31-bit address. If the A bit is 0, the value is a 24-bit address. Address<br />

wrap-around is applied to the sum of the specified starting address <strong>and</strong> the<br />

contents of the two specified registers.

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