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Chapter 16
Figure 2: TPU v1 design schema (source [3])
TPU v1 is manufactured on a 28 nm process with a die size ≤ 331 mm2, clock
speed of 700 MHz, 28 MB of on-chip memory, 4 MB of 32-bit accumulators,
and a 256×256 systolic array of 8-bit multipliers. For this reason, we can get
700Mhz*65536 (multipliers) → 92 Tera operations/sec. This is an amazing
performance for matrix multiplications: Figure 3 shows the TPU circuit board
and flow of data for the systolic matrix multiplication performed by the MMU.
In addition, TPU v1 has an 8 GB dual-channel 2133 MHz DDR3 SDRAM offering
34 GB/s of bandwidth. The external memory is standard, and it is used to store and
fetch the weights used during the inference. Notice also that TPU v1 has a thermal
design power of 28-40 Watts, which is certainly low consumption compared to
GPUs and CPUs. Moreover, TPU v1 are normally mounted in a PCI slot used for
SATA disks so they do not require any modification in the host server [3]. Up to 4
cards can be mounted in each server. Figure 3 shows TPU v1 card and the process of
systolic computation:
Figure 3: On the left you can see a TPU v1 board, and on the right an example of how the data is processed
during the systolic computation
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