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8<br />
7<br />
6 5 4 3<br />
2 1<br />
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.<br />
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.<br />
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.<br />
"LOHWILL" MLB SCHEMATIC<br />
LAST_MODIFICATION = 2016-10-23 12:22:45 PROTO1A : PRELIMINARY TEST<br />
REV ECN DESCRIPTION OF REVISION<br />
9 0006941568 ENGINEERING RELEASED<br />
CK<br />
APPD<br />
DATE<br />
2016-10-23<br />
D<br />
C<br />
B<br />
A<br />
Schematic / PCB #'s<br />
PAGE<br />
1<br />
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58<br />
59<br />
60<br />
051-00777 1 SCHEM,MLB,Lohwill<br />
SCH<br />
<strong>820</strong>-<strong>00923</strong> 1 PCBF,MLB,Lohwill<br />
PCB<br />
CSA CONTENTS<br />
SYNC<br />
DATE<br />
PAGE CSA CONTENTS<br />
SYNC<br />
DATE<br />
1 Table of Contents<br />
61 63 AUDIO JACK CODEC<br />
J79_JCURCIO 05/13/2016<br />
2 BOM Configuration<br />
SHART_J44 11/27/2012<br />
62 64 Left Speaker Amps & Conn<br />
J79_JCURCIO 11/18/2015<br />
3 BOM Configuration<br />
J79_JACK<br />
04/07/2016<br />
63 65 Right Speaker Amps & Conn<br />
J79_JCURCIO 12/03/2015<br />
4 PD Parts<br />
LDUNN_J44 01/13/2013<br />
64 66 AUDIO JACK CONNECTOR<br />
J79_JCURCIO 12/18/2015<br />
5 CPU GFX<br />
J130_DEV_MLB_U 04/29/2015<br />
65 69 DC-In & Battery Connectors<br />
J79_JSHAO 12/03/2015<br />
6 CPU MISC/JTAG/CFG/RSVD<br />
J130_DEV_MLB_U 04/28/2015<br />
66 70 PBUS Supply & Battery Charger<br />
J79_JSHAO 12/03/2015<br />
7 CPU LPDDR3 Interface<br />
J52_MLB<br />
05/12/2015<br />
67 71 CORE & SA IMVP IC<br />
J79_JSHAO 03/02/2016<br />
8 CPU & PCH Power<br />
J79_JSHAO 03/14/2016<br />
68 72 CORE & SA IMVP POWER BLOCK<br />
J79_JSHAO 12/03/2015<br />
9 CPU & PCH Grounds<br />
J79_ALFRED 05/12/2015<br />
69 73 Empty<br />
J79_SILUCHEN 04/02/2015<br />
10 CPU Core Decoupling<br />
J79_JSHAO 08/28/2015<br />
70 74 GT & GTX IMVP POWER BLOCK<br />
J79_JSHAO 09/25/2015<br />
11 CPU GT Decoupling<br />
J79_JSHAO 08/28/2015<br />
71 75 Empty<br />
J79_SILUCHEN 03/27/2015<br />
12 PCH Decoupling<br />
J79_JSHAO 03/14/2016<br />
72 76 Power - 5V 3.3V Supply<br />
J79_JSHAO 03/23/2016<br />
13 PCH Audio/LPC/SPI/SMBus<br />
J130_MLB<br />
02/22/2016<br />
73 77 Power - EOPIO EDRAM Supply<br />
J79_JSHAO 04/12/2016<br />
14 PCH Power Management<br />
J130_MLB<br />
05/04/2016<br />
74 78 PMIC-1 & Power Control<br />
J79_JSHAO 09/09/2015<br />
15 PCH PCIE/USB/CLKS<br />
J130_MLB<br />
06/23/2015<br />
75 79 PMIC-1 1.2V 0.6V VCCIO<br />
J79_JSHAO 12/03/2015<br />
16 PCH SPI/UART/GPIO<br />
J130_MLB<br />
12/08/2015<br />
76 80 PMIC-1 1V 1.8V VCCPCH<br />
J79_JSHAO 12/03/2015<br />
18 CPU/PCH Merged XDP<br />
J130_MLB<br />
12/08/2015<br />
77 81 PMIC-1 Aliases & TPs<br />
J79_SILUCHEN 07/17/2015<br />
19 Chipset Support 1<br />
J79_GREG<br />
09/09/2015<br />
78 82 Power FETs<br />
J79_JSHAO 03/14/2016<br />
20 Chipset Support 2<br />
J79_GREG<br />
07/05/2016<br />
79 84 LCD Backlight Driver<br />
J79_RUENJOU 09/09/2015<br />
22 LPDDR3 VREF Margining<br />
J52_MLB<br />
05/12/2015<br />
80 85 eDP Display Connector<br />
J79_RUENJOU 09/12/2015<br />
23 LPDDR3 DRAM Channel A (00-31)<br />
J52_MLB<br />
05/12/2015<br />
81 86 S3X CORE PCIE<br />
J79_RUENJOU 08/20/2015<br />
24 LPDDR3 DRAM Channel A (32-63)<br />
J52_MLB<br />
05/12/2015<br />
82 87 S3X POWER<br />
J79_RIO<br />
06/18/2015<br />
25 LPDDR3 DRAM Channel B (00-31)<br />
J52_MLB<br />
05/12/2015<br />
83 88 S3X GND<br />
J79_RIO<br />
06/18/2015<br />
26 LPDDR3 DRAM Channel B (32-63)<br />
J52_MLB<br />
05/12/2015<br />
84 89 Connector<br />
J79_RUENJOU 09/09/2015<br />
27 LPDDR3 DRAM Termination<br />
J52_MLB<br />
05/12/2015<br />
85 90 NAND VR, I2C ROM, TEMP SENSORS<br />
J79_RUENJOU 09/12/2015<br />
28 USB-C HIGH SPEED 1<br />
J79_GREG<br />
07/27/2015<br />
86 91 ANI[3:0]<br />
J79_RUENJOU 09/25/2015<br />
29 USB-C HIGH SPEED 2<br />
J79_GREG<br />
09/09/2015<br />
87 92 ANI[7:4]<br />
J79_RUENJOU 09/25/2015<br />
30 USB-C Support<br />
J79_GREG<br />
08/08/2016<br />
88 93 PICCOLO PMIC<br />
J79_RUENJOU 09/24/2015<br />
31 USB-C PORT CONTROLLER A<br />
J79_GREG<br />
08/08/2016<br />
89 94 SSD NAND VR<br />
J79_JSHAO 12/18/2015<br />
32 USB-C PORT CONTROLLER B<br />
J79_GREG<br />
02/28/2016<br />
90 95 Empty<br />
J14<br />
10/23/2012<br />
33 USB-C CONNECTOR A<br />
J79_GREG<br />
07/05/2016<br />
91 96 LIFEBOAT<br />
J79_RUENJOU 09/09/2015<br />
34 USB-C CONNECTOR B<br />
J79_GREG<br />
03/24/2016<br />
92 110 USB-C HIGH SPEED 1<br />
J79_GREG<br />
07/28/2015<br />
35 TBT 5V REGULATOR<br />
J79_JSHAO 12/18/2015<br />
93 111 USB-C HIGH SPEED 2<br />
J79_GREG<br />
08/28/2015<br />
36 Display Mux<br />
J79_GREG<br />
02/28/2016<br />
94 112 USB-C Support<br />
J79_GREG<br />
07/05/2016<br />
37<br />
38<br />
WIFI/BT: MODULE 1<br />
WIFI/BT: MODULE 2<br />
J79_METE<br />
J79_METE<br />
05/17/2016<br />
03/02/2016<br />
95<br />
96<br />
113<br />
114<br />
USB-C PORT CONTROLLER A<br />
USB-C PORT CONTROLLER B<br />
J79_GREG<br />
J79_GREG<br />
02/28/2016<br />
02/28/2016<br />
39 Camera/DFR 1<br />
J80_MLB_BAFFIN 07/22/2016<br />
97 115 USB-C CONNECTOR A<br />
J79_GREG<br />
07/05/2016<br />
40 Camera/DFR 2<br />
J79_ANDREW 03/22/2016<br />
98 116 USB-C CONNECTOR B<br />
J79_GREG<br />
03/24/2016<br />
41 Camera/DFR 3<br />
J79_ANDREW 04/25/2016<br />
99 117 TBT 5V REGULATOR<br />
J79_JSHAO 12/18/2015<br />
42 Berkelium - 1<br />
J79_ANDREW 03/14/2016<br />
100 120 Power Aliases - 1<br />
J79_ALFRED 06/17/2015<br />
43 Berkelium - 2<br />
J79_ANDREW 02/01/2016<br />
101 121 Power Aliases - 2<br />
J79_ALFRED 06/18/2015<br />
44 T208 Support<br />
J79_ANDREW 07/01/2016<br />
102 122 Signal Aliases<br />
SHART_J44 11/19/2012<br />
45 Connectors&ESD<br />
J79_GAREN 11/21/2015<br />
103 123 LPDDR3 Bit & Byte Swizzle<br />
AHARTMAN_J52 10/29/2013<br />
46 Empty<br />
J79_DAYU<br />
05/26/2015<br />
104 124 ICT FCT 1<br />
YHARTANTO_J44 12/18/2012<br />
47 Empty<br />
J79_DAYU<br />
05/26/2015<br />
105 125 ICT FCT 2<br />
YHARTANTO_J44 12/18/2012<br />
48 Empty<br />
J79_DAYU<br />
05/12/2015<br />
106 127 Desense Capacitors<br />
YHARTANTO_J44 01/09/2013<br />
49 MESA<br />
J79_ANDREW 01/06/2016<br />
107 129 Empty<br />
J79_RIO<br />
06/18/2015<br />
50 SMC<br />
J79_JACK<br />
04/11/2016<br />
108 130 PCB Rule Definitions<br />
YHARTANTO_J44 12/14/2012<br />
51 SMC Shared Support<br />
J79_JACK<br />
04/14/2016<br />
109 131 CPU Constraints<br />
YHARTANTO_J44 01/13/2013<br />
52 SMC Project Support<br />
J79_JACK<br />
04/11/2016<br />
110 132 PCH Constraints<br />
YHARTANTO_J44 01/08/2013<br />
53 SMBus Connections<br />
J79_JACK<br />
03/31/2016<br />
111 133 Memory Constraints<br />
YHARTANTO_J44 01/02/2013<br />
54 Power Sensors: High Side<br />
J79_JACK<br />
12/07/2015<br />
112 134 TBT DP HDMI Constraints<br />
J79_JACK<br />
05/19/2015<br />
55 Power Sensors: Load Side<br />
J79_JACK<br />
04/03/2016<br />
113 135 PCIe Constraints<br />
J79_JACK<br />
05/19/2015<br />
56 Power Sensors: Extended<br />
J79_JACK<br />
01/08/2016<br />
114 136 USB Constraints<br />
J79_JACK<br />
05/21/2015<br />
57 Power Sensors: Extended 2<br />
J79_JACK<br />
05/10/2016<br />
115 137 SMC Constraints<br />
YHARTANTO_J44 01/02/2013<br />
58 Thermal Sensors<br />
J79_JACK<br />
09/24/2015<br />
116 138 Camera Constraints<br />
YHARTANTO_J44 01/09/2013<br />
59 Power Sensors:Extended 3<br />
J79_JACK<br />
04/14/2016<br />
117 139 Sensors & Audio Constraints<br />
YHARTANTO_J44 01/04/2013<br />
60 Fans<br />
J79_JACK<br />
08/21/2015<br />
118 140 References<br />
J79_RUENJOU_CONSTRAINTS 06/11/2015<br />
61 SPI Debug Connector<br />
J52_MLB<br />
05/12/2015<br />
119 145 Alternates BOM Table<br />
J80_MLB<br />
12/12/2015<br />
62 HDA Bridge<br />
J79_JCURCIO 03/24/2016<br />
PART NUMBER QTY DESCRIPTION<br />
REFERENCE DES CRITICAL BOM OPTION<br />
CRITICAL<br />
CRITICAL<br />
xTN20JE19<br />
DRAWING TITLE<br />
R<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
IV ALL RIGHTS RESERVED<br />
SCHEM,MLB,Lohwill<br />
Apple Inc.<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
DRAWING NUMBER<br />
051-00777<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
9.0.0<br />
dvt-fab09-0<br />
1 OF 145<br />
1 OF 119<br />
SIZE<br />
D<br />
D<br />
C<br />
B<br />
A<br />
8<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2<br />
1
TABLE_BOMGROUP_HEAD<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_STRATEGIC_HEAD<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC_HEAD<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_STRATEGIC__ITEM<br />
TABLE_BOMGROUP_HEAD<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_HEAD<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
8<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2 1<br />
BOM Groups<br />
BOM GROUP<br />
Lohwill_COMMON<br />
BOM OPTIONS<br />
ALTERNATE,COMMON,Lohwill_COMMON1,Lohwill_COMMON2,Lohwill_COMMON3,Lohwill_PROGPARTS<br />
Variable BOM Groups<br />
Development/Base BOMs<br />
Lohwill_COMMON1<br />
SE:PROD,BOARD_ID:8,T208_PROG:REV5,TBTTHRM_SNS,S3XCLK:INT<br />
PART NUMBER QTY DESCRIPTION<br />
REFERENCE DES CRITICAL BOM OPTION<br />
D<br />
Lohwill_COMMON2<br />
Lohwill_COMMON3<br />
Lohwill_PROGPARTS<br />
Lohwill_DEVEL:ENG<br />
Lohwill_DEVEL:DVT<br />
Lohwill_DEVEL:PVT<br />
Module Parts<br />
337S00717 1<br />
CPU,KBLU,SR362,PRQ,3.1,28W,B1356<br />
U0500 CRITICAL<br />
337S00718 1 CPU,KBLU,SR360,PRQ,3.3,28W,B1356<br />
U0500<br />
CRITICAL CPU_KBL24:3.3G<br />
337S00719 1<br />
998-04195<br />
338S00254<br />
1<br />
EDP_ENABLE,XDP:YES,PCH_CLK:GRNCLK,TBT_DBG,SAMCONN,SKIP_5V3V3:AUDIBLE,SOC_BOOT:SPI<br />
CPUTHRM:ALRT,TBTTHRM:ALRT,LOADRC:NO,CUMULUS_IPD,S3_STATE:YES,VCCPLLOC:S3<br />
BOOTROM_PROG,SMC_PROG,AR_LT_PROG,AR_RT_PROG,WIFI_PROG,BTROM_PROG<br />
ALTERNATE,DBGLED,USBC_DBG,XDP_CONN:YES,WIFI_DBG,S3X_DBG,DEBUG_BUTTON,LOADISNS<br />
ALTERNATE,USBC_DBG,XDP_CONN:YES,WIFI_DBG<br />
ALTERNATE<br />
PART NUMBER QTY DESCRIPTION<br />
REFERENCE DES CRITICAL BOM OPTION<br />
CPU,KBLU,SR367,PRQ,3.5,28W,B1356 U0500<br />
CRITICAL CPU_KBL24:3.5G<br />
INTERPOSER,VTT ADAPTER,KBL-U,BGA1356<br />
2 IC,TBT,ALPINE RIDGE,QSTY,PRQ,C1,CSP337<br />
U0500<br />
U2800,UB000<br />
CRITICAL<br />
CRITICAL<br />
CPU_KBL24:3.1G<br />
CPU_SOCKET<br />
685-00055<br />
985-00070<br />
Main DRAM Parts<br />
IC,SDRAM,LPDDR3-2133,16GBIT,20NM,BGA178<br />
U2300,U2400,U2500,U2600<br />
333S00070 4 IC,SDRAM,LPDDR3-2133,32GBIT,20NM,BGA178<br />
U2300,U2400,U2500,U2600 CRITICAL 16G_MICRON_2133<br />
Main DRAM SPD Straps<br />
1 DEV,MLB,X362 DEVEL<br />
CRITICAL<br />
DEVEL_BOM<br />
PART NUMBER QTY DESCRIPTION<br />
REFERENCE DES CRITICAL BOM OPTION<br />
333S00069 4 CRITICAL 8G_MICRON_2133<br />
333S00068<br />
333S00050<br />
1<br />
COMMON PARTS,MLB,X362<br />
BASE<br />
CRITICAL<br />
4<br />
4 IC,SDRAM,LPDDR3-2133,32GBIT,20NM,BGA178<br />
U2300,U2400,U2500,U2600 CRITICAL<br />
BASE_BOM<br />
IC,SDRAM,LPDDR3-2133,16GBIT,20NM,BGA178 U2300,U2400,U2500,U2600 CRITICAL 8G_SAMSUNG_2133<br />
16G_SAMSUNG_2133<br />
CPU DRAM CFG Chart<br />
DIE REV<br />
CFG 4<br />
A 0<br />
B<br />
1<br />
SPEED<br />
CFG 3<br />
2133<br />
0<br />
1866<br />
1<br />
CAPACITY<br />
CFG 2<br />
8GB<br />
0<br />
16GB<br />
1<br />
D<br />
353S00961<br />
338S00276<br />
333S00055<br />
333S00056<br />
4<br />
1<br />
IC,CD3215,ACE,C00,USB PWR SW,BLNK,BGA96<br />
IC,CNTLR,S3X,B1,FCBGA900<br />
U3100,U3200,UB300,UB400<br />
U8600<br />
CRITICAL<br />
1 IC,LPDDR3-2133,4GBIT,25NM,A,276B<br />
POP8600<br />
POP_4GBIT<br />
1<br />
IC,LPDDR3-2133,8GBIT,25NM,A,276B<br />
POP8600<br />
CRITICAL<br />
CRITICAL<br />
CRITICAL<br />
343S00147 1<br />
IC,SLG4AP41172,PAK3,STQFN20<br />
U3620 CRITICAL<br />
POP_8GBIT<br />
BOM GROUP<br />
RAM_8G_MICRON_2133<br />
RAM_16G_MICRON_2133<br />
RAM_8G_SAMSUNG_2133<br />
RAM_16G_SAMSUNG_2133<br />
BOM OPTIONS<br />
8G_MICRON_2133,RAMCFG4_L,RAMCFG3_L,RAMCFG2_L,RAMCFG1_L<br />
16G_MICRON_2133,RAMCFG4_L,RAMCFG3_L,RAMCFG1_L<br />
8G_SAMSUNG_2133,RAMCFG4_L,RAMCFG3_L,RAMCFG2_L,RAMCFG0_L<br />
16G_SAMSUNG_2133,RAMCFG4_L,RAMCFG3_L,RAMCFG0_L<br />
VENDOR<br />
HYNIX<br />
MICRON<br />
SAMSUNG<br />
N/A<br />
CFG 1<br />
0<br />
0<br />
1<br />
1<br />
CFG 0<br />
0<br />
1<br />
0<br />
1<br />
C<br />
338S00221<br />
353S01016<br />
338S00227<br />
Programmables (All Builds)<br />
EFI ROM<br />
341S00698<br />
SMC ROM<br />
341S00700<br />
TBT ROMs<br />
341S00717<br />
341S00718<br />
WIFI/BT ROM<br />
1 IC,PMU,SN650839,7X7MM,BGA168<br />
U7800<br />
CRITICAL<br />
1 IC,ISL9239HIZ,PMU,TUBA,WCSP40,2.1X3.3MM<br />
U7000<br />
1 IC,PMU,PICCOLO,D2231A0,OTP-AK,WLCSP96<br />
U9300<br />
1 IC,EFI ROM (V0193) DVT,X362 U6100<br />
1<br />
1<br />
1<br />
IC,SMC-B1,EXT (V2.37F6) PVT,X362<br />
T29,AR1 (VTBD) PVT,X362<br />
T29,AR2 (VTBD) PVT,X362<br />
U5000<br />
U2890<br />
UB090<br />
CRITICAL<br />
CRITICAL<br />
CRITICAL<br />
CRITICAL<br />
CRITICAL<br />
CRITICAL<br />
BOOTROM_PROG<br />
SMC_PROG<br />
PART NUMBER QTY DESCRIPTION<br />
REFERENCE DES CRITICAL BOM OPTION<br />
AR_LT_PROG<br />
AR_RT_PROG<br />
NAND Parts<br />
PART NUMBER QTY DESCRIPTION<br />
REFERENCE DES CRITICAL BOM OPTION<br />
335S00124 4 NAND,1ZNM,64GB,TOGG,HPN,128G,LGA60<br />
U9100,U9120,U9200,U9220 CRITICAL NAND_SDISK_256GB<br />
335S00125 4 NAND,1ZNM,128GB,TOGG,HPN,128G,LGA60<br />
U9100,U9120,U9200,U9220 CRITICAL NAND_SDISK_512GB<br />
335S00126 4<br />
NAND,1ZNM,256GB,TOGG,HPN,128G,LGA60<br />
U9100,U9120,U9200,U9220 CRITICAL<br />
NAND_SDISK_1TB<br />
335S00261 4 NAND,TGDDR2,128GX4,15NM,HP,USHD,T2,LGA60<br />
U9100,U9120,U9200,U9220 CRITICAL NAND_TSHBA_256GB<br />
335S00262 4<br />
NAND,TGDDR2,128GX8,15NM,HP,USHD,T2,LGA60<br />
U9100,U9120,U9200,U9220 CRITICAL NAND_TSHBA_512GB<br />
335S00263 4 NAND,TGDDR2,128GX16,15NM,HP,UHD,T2,LGA60<br />
U9100,U9120,U9200,U9220 CRITICAL<br />
NAND_TSHBA_1TB<br />
NAND Straps<br />
BOM GROUP<br />
SAND_256G<br />
SAND_512G<br />
SAND_1T<br />
TOSH_256G<br />
TOSH_512G<br />
TOSH_1T<br />
BOM OPTIONS<br />
ALTERNATE,NAND_SDISK_256GB,POP_4GBIT,CAPACITY1,CAPACITY0<br />
ALTERNATE,NAND_SDISK_512GB,POP_4GBIT,CAPACITY2<br />
ALTERNATE,NAND_SDISK_1TB,POP_8GBIT,CAPACITY2,CAPACITY0<br />
ALTERNATE,NAND_TSHBA_256GB,POP_4GBIT,CAPACITY1,CAPACITY0<br />
ALTERNATE,NAND_TSHBA_512GB,POP_4GBIT,CAPACITY2<br />
ALTERNATE,NAND_TSHBA_1TB,POP_8GBIT,CAPACITY2,CAPACITY0<br />
C<br />
B<br />
PART NUMBER QTY DESCRIPTION<br />
REFERENCE DES CRITICAL BOM OPTION<br />
341S00715 1 IC,BT ROM (V32) PVT,X362/X363<br />
U3750<br />
CRITICAL<br />
BTROM_PROG<br />
341S00716<br />
1<br />
WIFI ROM (P108) PVT,WW1,X362/X363<br />
U3710<br />
CRITICAL<br />
WIFI_PROG<br />
B<br />
Strategic Silicon<br />
PART#<br />
STRATEGIC VALUE<br />
COMMENT<br />
PART#<br />
STRATEGIC VALUE<br />
COMMENT<br />
337S00266<br />
08<br />
CPU<br />
338S00227<br />
02 PICCOLO<br />
337S00267 08 CPU<br />
343S00135<br />
10 T208<br />
337S00268<br />
08 CPU<br />
343S00136<br />
10 T208<br />
333S00050<br />
07<br />
MEMORY<br />
343S00137<br />
10<br />
T208<br />
333S00068 07 MEMORY<br />
343S00138<br />
10 T208<br />
333S00069<br />
07 MEMORY<br />
338S00193<br />
09<br />
BERKELIUM<br />
333S00070<br />
07<br />
MEMORY<br />
353S3978<br />
02<br />
MOJAVE<br />
335S00124<br />
02 NAND<br />
338S00147<br />
02<br />
SECURE ELEMENT<br />
335S00125<br />
02 NAND<br />
338S00254 08 ALPINE RIDGE<br />
335S00126<br />
02 NAND<br />
353S00961<br />
09<br />
ACE<br />
335S00261<br />
02 NAND<br />
338S00142<br />
09<br />
CLIFDEN<br />
335S00262<br />
02 NAND<br />
353S00685<br />
07<br />
AUDIO AMP<br />
A<br />
335S00263<br />
333S00025<br />
333S00108<br />
02 NAND<br />
02<br />
S3X DRAM<br />
333S00026 02 S3X DRAM<br />
333S00055<br />
333S00056<br />
333S00107<br />
998-06736<br />
02<br />
02<br />
02<br />
S3X DRAM<br />
S3X DRAM<br />
S3X DRAM<br />
02 S3X DRAM<br />
02<br />
S3X CONTROLLER<br />
353S4316<br />
338S00221<br />
353S01016<br />
339S00056<br />
343S00147<br />
359S00006<br />
353S00795<br />
08<br />
08<br />
09<br />
05<br />
08<br />
08<br />
09<br />
BAYSIDE<br />
BANJO<br />
TUBA<br />
ICEBOCK<br />
PAK<br />
GREEN CLOCK<br />
DEBUG MUX<br />
SYNC_MASTER=SHART_J44<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
BOM Configuration<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
BRANCH<br />
051-00777<br />
REVISION<br />
PAGE<br />
SHEET<br />
SYNC_DATE=11/27/2012<br />
9.0.0<br />
dvt-fab09-0<br />
2 OF 145<br />
2 OF 119<br />
SIZE<br />
D<br />
A
TABLE_ALT_HEAD<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_BOMGROUP_HEAD<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_BOMGROUP_HEAD<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
BOM Variants<br />
BOM NUMBER BOM NAME BOM OPTIONS<br />
BOM NUMBER BOM NAME BOM OPTIONS<br />
685-00055 COMMON PARTS,MLB,X362 X362_COMMON<br />
639-01988 MLB,NO CPU,X362<br />
BASE_BOM,DEVEL_BOM,RAM_16G_SAMSUNG_2133,SAND_512G<br />
985-00070 DEV,MLB,X362 X362_DEVEL:DVT<br />
639-01989<br />
MLB,CPU SOCKET,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SOCKET,RAM_16G_SAMSUNG_2133,SAND_512G<br />
639-01870 MLB,2.9G,SAM-8G,SAND-256G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_SAMSUNG_2133,SAND_256G<br />
639-02521 MLB,2.9G,SAM-8G,TOSH-256G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_SAMSUNG_2133,TOSH_256G<br />
639-01871 MLB,2.9G,SAM-16G,SAND-256G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_SAMSUNG_2133,SAND_256G<br />
639-02522 MLB,2.9G,SAM-16G,TOSH-256G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_SAMSUNG_2133,TOSH_256G<br />
D<br />
639-01872 MLB,2.9G,MIC-8G,SAND-256G,X362<br />
639-01873 MLB,2.9G,MIC-16G,SAND-256G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_MICRON_2133,SAND_256G<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_MICRON_2133,SAND_256G<br />
639-01984 MLB,2.9G,SAM-8G,SAND-512G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_SAMSUNG_2133,SAND_512G<br />
639-02523 MLB,2.9G,MIC-8G,TOSH-256G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_MICRON_2133,TOSH_256G<br />
639-02524 MLB,2.9G,MIC-16G,TOSH-256G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_MICRON_2133,TOSH_256G<br />
639-02525 MLB,2.9G,SAM-8G,TOSH-512G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_SAMSUNG_2133,TOSH_512G<br />
D<br />
639-01985 MLB,2.9G,SAM-16G,SAND-512G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_SAMSUNG_2133,SAND_512G<br />
639-02526 MLB,2.9G,SAM-16G,TOSH-512G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_SAMSUNG_2133,TOSH_512G<br />
639-01986 MLB,2.9G,MIC-8G,SAND-512G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_MICRON_2133,SAND_512G<br />
639-02527 MLB,2.9G,MIC-8G,TOSH-512G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_MICRON_2133,TOSH_512G<br />
639-01987 MLB,2.9G,MIC-16G,SAND-512G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_MICRON_2133,SAND_512G<br />
639-02528 MLB,2.9G,MIC-16G,TOSH-512G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_MICRON_2133,TOSH_512G<br />
639-02517 MLB,2.9G,SAM-8G,SAND-1T,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_SAMSUNG_2133,SAND_1T<br />
639-02529 MLB,2.9G,SAM-8G,TOSH-1T,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_SAMSUNG_2133,TOSH_1T<br />
639-02518 MLB,2.9G,SAM-16G,SAND-1T,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_SAMSUNG_2133,SAND_1T<br />
639-02530 MLB,2.9G,SAM-16G,TOSH-1T,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_SAMSUNG_2133,TOSH_1T<br />
639-02519 MLB,2.9G,MIC-8G,SAND-1T,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_MICRON_2133,SAND_1T<br />
639-02531 MLB,2.9G,MIC-8G,TOSH-1T,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_MICRON_2133,TOSH_1T<br />
639-02520 MLB,2.9G,MIC-16G,SAND-1T,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_MICRON_2133,SAND_1T<br />
639-02532 MLB,2.9G,MIC-16G,TOSH-1T,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_MICRON_2133,TOSH_1T<br />
639-01874 MLB,3.1G,SAM-8G,SAND-256G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_SAMSUNG_2133,SAND_256G<br />
639-02533 MLB,3.1G,SAM-8G,TOSH-256G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_SAMSUNG_2133,TOSH_256G<br />
639-01875 MLB,3.1G,SAM-16G,SAND-256G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_SAMSUNG_2133,SAND_256G<br />
639-02534 MLB,3.1G,SAM-16G,TOSH-256G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_SAMSUNG_2133,TOSH_256G<br />
639-01876 MLB,3.1G,MIC-8G,SAND-256G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_MICRON_2133,SAND_256G<br />
639-02535 MLB,3.1G,MIC-8G,TOSH-256G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_MICRON_2133,TOSH_256G<br />
639-01877 MLB,3.1G,MIC-16G,SAND-256G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_MICRON_2133,SAND_256G<br />
639-02536 MLB,3.1G,MIC-16G,TOSH-256G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_MICRON_2133,TOSH_256G<br />
639-01883 MLB,3.1G,SAM-8G,SAND-512G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_SAMSUNG_2133,SAND_512G<br />
639-02537 MLB,3.1G,SAM-8G,TOSH-512G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_SAMSUNG_2133,TOSH_512G<br />
639-01884 MLB,3.1G,SAM-16G,SAND-512G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_SAMSUNG_2133,SAND_512G<br />
639-02538 MLB,3.1G,SAM-16G,TOSH-512G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_SAMSUNG_2133,TOSH_512G<br />
639-01885 MLB,3.1G,MIC-8G,SAND-512G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_MICRON_2133,SAND_512G<br />
639-02539 MLB,3.1G,MIC-8G,TOSH-512G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_MICRON_2133,TOSH_512G<br />
639-01886 MLB,3.1G,MIC-16G,SAND-512G,X362 BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_MICRON_2133,SAND_512G<br />
639-02540 MLB,3.1G,MIC-16G,TOSH-512G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_MICRON_2133,TOSH_512G<br />
C<br />
639-01887 MLB,3.1G,SAM-8G,SAND-1T,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_SAMSUNG_2133,SAND_1T<br />
639-01888 MLB,3.1G,SAM-16G,SAND-1T,X362<br />
639-01889 MLB,3.1G,MIC-8G,SAND-1T,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_SAMSUNG_2133,SAND_1T<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_MICRON_2133,SAND_1T<br />
639-02541 MLB,3.1G,SAM-8G,TOSH-1T,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_SAMSUNG_2133,TOSH_1T<br />
639-02542 MLB,3.1G,SAM-16G,TOSH-1T,X362<br />
639-02543 MLB,3.1G,MIC-8G,TOSH-1T,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_SAMSUNG_2133,TOSH_1T<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_MICRON_2133,TOSH_1T<br />
C<br />
639-01890 MLB,3.1G,MIC-16G,SAND-1T,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_MICRON_2133,SAND_1T<br />
639-02544 MLB,3.1G,MIC-16G,TOSH-1T,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_MICRON_2133,TOSH_1T<br />
639-02221 MLB,3.3G,SAM-8G,SAND-256G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_SAMSUNG_2133,SAND_256G<br />
639-02545 MLB,3.3G,SAM-8G,TOSH-256G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_SAMSUNG_2133,TOSH_256G<br />
639-02222 MLB,3.3G,SAM-16G,SAND-256G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_SAMSUNG_2133,SAND_256G<br />
639-02546 MLB,3.3G,SAM-16G,TOSH-256G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_SAMSUNG_2133,TOSH_256G<br />
639-02223 MLB,3.3G,MIC-8G,SAND-256G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_MICRON_2133,SAND_256G<br />
639-02547 MLB,3.3G,MIC-8G,TOSH-256G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_MICRON_2133,TOSH_256G<br />
639-02224 MLB,3.3G,MIC-16G,SAND-256G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_MICRON_2133,SAND_256G<br />
639-02548 MLB,3.3G,MIC-16G,TOSH-256G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_MICRON_2133,TOSH_256G<br />
639-01891 MLB,3.3G,SAM-8G,SAND-512G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_SAMSUNG_2133,SAND_512G<br />
639-02549 MLB,3.3G,SAM-8G,TOSH-512G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_SAMSUNG_2133,TOSH_512G<br />
639-01892 MLB,3.3G,SAM-16G,SAND-512G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_SAMSUNG_2133,SAND_512G<br />
639-02550 MLB,3.3G,SAM-16G,TOSH-512G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_SAMSUNG_2133,TOSH_512G<br />
639-01893 MLB,3.3G,MIC-8G,SAND-512G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_MICRON_2133,SAND_512G<br />
639-02551 MLB,3.3G,MIC-8G,TOSH-512G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_MICRON_2133,TOSH_512G<br />
639-01894 MLB,3.3G,MIC-16G,SAND-512G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_MICRON_2133,SAND_512G<br />
639-02552 MLB,3.3G,MIC-16G,TOSH-512G,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_MICRON_2133,TOSH_512G<br />
639-01895 MLB,3.3G,SAM-8G,SAND-1T,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_SAMSUNG_2133,SAND_1T<br />
639-02553 MLB,3.3G,SAM-8G,TOSH-1T,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_SAMSUNG_2133,TOSH_1T<br />
639-01896 MLB,3.3G,SAM-16G,SAND-1T,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_SAMSUNG_2133,SAND_1T<br />
639-02554 MLB,3.3G,SAM-16G,TOSH-1T,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_SAMSUNG_2133,TOSH_1T<br />
639-01897 MLB,3.3G,MIC-8G,SAND-1T,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_MICRON_2133,SAND_1T<br />
639-02555 MLB,3.3G,MIC-8G,TOSH-1T,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_MICRON_2133,TOSH_1T<br />
639-01898 MLB,3.3G,MIC-16G,SAND-1T,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_MICRON_2133,SAND_1T<br />
639-02556 MLB,3.3G,MIC-16G,TOSH-1T,X362<br />
BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_MICRON_2133,TOSH_1T<br />
Alternate Parts<br />
B<br />
PART NUMBER<br />
152S00367<br />
ALTERNATE FOR<br />
PART NUMBER<br />
152S00266<br />
BOM OPTION<br />
REF DES<br />
ALL<br />
COMMENTS:<br />
Text note to be updated<br />
138S0701 138S0689<br />
ALL Text note to be updated<br />
138S00012 138S0771<br />
ALL<br />
Text note to be updated<br />
B<br />
152S00368<br />
152S00269<br />
ALL<br />
Text note to be updated<br />
138S0772<br />
138S00013<br />
ALL<br />
Text note to be updated<br />
152S00370 152S00270 ALL Text note to be updated<br />
152S00401 152S0529<br />
ALL Text note to be updated<br />
353S4068<br />
353S4070<br />
ALL<br />
Text note to be updated<br />
152S00344<br />
152S1683<br />
ALL<br />
Text note to be updated<br />
353S00772<br />
353S4070<br />
ALL<br />
Text note to be updated<br />
152S00331 152S00283<br />
ALL Text note to be updated<br />
138S00086<br />
138S0884<br />
ALL<br />
Text note to be updated<br />
152S2034<br />
152S00190<br />
ALL<br />
Text note to be updated<br />
107S0248<br />
107S0250<br />
ALL<br />
TFT alt to Cyntec<br />
197S0613 197S0612 ALL Text note to be updated<br />
152S00434<br />
152S1829<br />
ALL<br />
Text note to be updated<br />
311S00121<br />
311S0398<br />
ALL<br />
Text note to be updated<br />
371S00019<br />
371S0463<br />
ALL<br />
Rohm alt to Rohm<br />
371S0713<br />
371S0558<br />
ALL<br />
Text note to be updated<br />
353S00107<br />
353S3239<br />
ANY<br />
ALL<br />
Onsemi alt to Intersil<br />
371S00074<br />
371S0602<br />
ALL<br />
Text note to be updated<br />
353S00231<br />
353S3987<br />
ALL<br />
NXP alt to TI<br />
333S00025<br />
333S00055<br />
POP_4GBIT ALL MICRON SSD POP ALT for HYNIX<br />
333S00026<br />
333S00056<br />
POP_8GBIT ALL MICRON SSD POP ALT for HYNIX<br />
333S00107<br />
333S00055<br />
POP_4GBIT<br />
ALL<br />
HYNIX SSD POP REPLACEMENT for HYNIX<br />
333S00108<br />
333S00056<br />
POP_8GBIT<br />
ALL<br />
HYNIX SSD POP REPLACEMENT for HYNIX<br />
A<br />
SYNC_MASTER=J79_JACK<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
BOM Configuration<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
BRANCH<br />
051-00777<br />
REVISION<br />
PAGE<br />
SHEET<br />
9.0.0<br />
dvt-fab09-0<br />
3 OF 145<br />
3 OF 119<br />
SYNC_DATE=04/07/2016<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
BOARD MECHANICALS<br />
Shield Cans - BOTTOM SIDE<br />
Shield Cans - TOP SIDE<br />
POGO PINS<br />
Cowling Bosses - BOTTOM SIDE<br />
ALPINE RIDGE - LIO (U2800) - 806-06077<br />
T208 (U3900) - 806-06264<br />
LIO and RIO -2X (870-5071)<br />
DFR TOUCH CONN (J4402) - 860-00414<br />
D<br />
1<br />
SH0418<br />
SM<br />
SHLD-FENCE-ALPINE-X379<br />
1<br />
SH0412<br />
SM<br />
SHLD-FENCE-M8-X379<br />
SH0471<br />
POGO-2.0OD-2.95H-SM<br />
SM<br />
1<br />
SH0472<br />
POGO-2.0OD-2.95H-SM<br />
SM<br />
1<br />
SH0425<br />
6.25X3.85R-1.75ID-1.938H-SM<br />
1<br />
D<br />
LPDDR3 (U2300 ~ U2600) - 806-06167<br />
1<br />
SHLD-FENCE-X379<br />
NAND - BOTTOM SOUTH (U9120) - 806-05945<br />
1<br />
SH0415<br />
SM<br />
SH0417<br />
SM<br />
DIPLEXERS - 806-06266<br />
1<br />
NAND - TOP SOUTH (U9100) - 806-06262<br />
1<br />
SH0411<br />
SM<br />
SHLD-MLB-DIPLEXER-X379<br />
SH0416<br />
SM<br />
AROUND THE FAN AND CENTER - 8X (870-01518)<br />
SH0463<br />
POGO-2.3OD-4.0H-SM<br />
SM<br />
1<br />
SH0467<br />
POGO-2.3OD-4.0H-SM<br />
SM<br />
SH0464<br />
POGO-2.3OD-4.0H-SM<br />
SM<br />
1<br />
SH0468<br />
POGO-2.3OD-4.0H-SM<br />
SM<br />
SH0465<br />
POGO-2.3OD-4.0H-SM<br />
SM<br />
1<br />
SH0469<br />
POGO-2.3OD-4.0H-SM<br />
SM<br />
SH0466<br />
POGO-2.3OD-4.0H-SM<br />
SM<br />
1<br />
SH0470<br />
POGO-2.3OD-4.0H-SM<br />
SM<br />
USB-C CONN - LIO (J3300) - 860-00392<br />
SH0445<br />
SH0446<br />
3.4OD1.75ID-1.12H-SM<br />
1<br />
DFR DISPLAY CONN (J4401) - 860-00412<br />
SH0426<br />
3.4OD1.75ID-1.7H-SM<br />
1<br />
3.4OD1.75ID-1.12H-SM<br />
1<br />
SH0427<br />
3.4OD1.75ID-1.7H-SM<br />
1<br />
SHLD-FENCE-NAND-BOT-SOUTH-X379<br />
S3X (U8600) - 806-06023<br />
SHLD-FENCE-MLB-NAND-TOP-SOUTH-X379<br />
NAND - TOP NORTH (9220) - 806-06258<br />
1<br />
1<br />
1<br />
1<br />
IPD CONN (J4501) - 860-00412<br />
1<br />
SH0414<br />
SM<br />
1<br />
SH0413<br />
SM<br />
SH0428<br />
3.4OD1.75ID-1.7H-SM<br />
1<br />
SH0429<br />
3.4OD1.75ID-1.7H-SM<br />
1<br />
C<br />
SHLD-FENCE-S3X-X379<br />
NAND - BOTTOM NORTH (U9200) - 806-06265<br />
1<br />
SH0419<br />
SM<br />
SHLD-FENCE-MLB-NAND-NORTH-X379<br />
KBD CONN (J4500) - 860-00412<br />
SH0430<br />
3.4OD1.75ID-1.7H-SM<br />
SH0431<br />
3.4OD1.75ID-1.7H-SM<br />
C<br />
SHLD-FENCE-MLB-NAND-BTM-NORTH-X379<br />
1<br />
1<br />
ALPINE RIDGE - RIO (UB000) - 806-06077<br />
1<br />
SH0420<br />
SM<br />
SHLD-FENCE-ALPINE-X379<br />
USB-C CONN - RIO (JB500) - 860-00392<br />
SH0447<br />
3.4OD1.75ID-1.12H-SM<br />
1<br />
SH0448<br />
3.4OD1.75ID-1.12H-SM<br />
1<br />
Shield CAN Alignment Slots 14X - 998-04440 (1.2mm X 0.4mm)<br />
SH0449<br />
1<br />
TH-NSP<br />
SH0450<br />
TH-NSP<br />
1<br />
SH0451<br />
1<br />
TH-NSP<br />
SH0452<br />
TH-NSP<br />
1<br />
SH0453<br />
TH-NSP<br />
1<br />
Thermal Stage Mounting Holes<br />
Plated Through Hole - 3.15mm - APN 998-0845<br />
SH0490<br />
3P9R3P15<br />
1<br />
AUDIO JACK CONN (J6600) - 860-00399<br />
SH0432<br />
3.3X1.8R-1.4ID-1.64H-SM<br />
1<br />
B<br />
SL-1.2X0.4-1.5X0.7<br />
SH0454<br />
1<br />
SH0459<br />
1<br />
TH-NSP<br />
SL-1.2X0.4-1.5X0.7<br />
TH-NSP<br />
SL-1.2X0.4-1.5X0.7<br />
SH0455<br />
TH-NSP<br />
1<br />
SL-1.2X0.4-1.5X0.7<br />
SH0460<br />
TH-NSP<br />
1<br />
SL-1.2X0.4-1.5X0.7<br />
SH0461<br />
TH-NSP<br />
1<br />
SL-1.2X0.4-1.5X0.7<br />
SH0457<br />
TH-NSP<br />
1<br />
SL-1.2X0.4-1.5X0.7<br />
SL-1.2X0.4-1.5X0.7<br />
SH0458<br />
TH-NSP<br />
1<br />
SL-1.2X0.4-1.5X0.7<br />
Plated Through Hole - 3.6mm - APN 998-03850<br />
SH0491<br />
4.0R3.6-NSP<br />
1<br />
SH0492<br />
4.0R3.6-NSP<br />
1<br />
SH0493<br />
4.0R3.6-NSP<br />
1<br />
MESA CONN (J4900) - 860-00399<br />
SH0433<br />
3.3X1.8R-1.4ID-1.64H-SM<br />
1<br />
B<br />
SL-1.2X0.4-1.5X0.7<br />
SL-1.2X0.4-1.5X0.7<br />
SL-1.2X0.4-1.5X0.7<br />
LIFEBOAT CONN (J9600) - 860-00413<br />
SH0473<br />
SH0474<br />
3.4OD1.75ID-1.57H-SM<br />
3.4OD1.75ID-1.57H-SM<br />
1<br />
1<br />
TOP Rubber Mount Standoffs - 12X - (860-00430)<br />
SH0400<br />
2.8OD1.2ID-1.435H-SM<br />
1<br />
2<br />
SH0401<br />
2.8OD1.2ID-1.435H-SM<br />
1<br />
2<br />
SH0402<br />
2.8OD1.2ID-1.435H-SM<br />
1<br />
2<br />
SH0403<br />
2.8OD1.2ID-1.435H-SM<br />
1<br />
2<br />
Bottom Rubber Mount Standoffs - 1X - (860-00476)<br />
Cowling Bosses - TOP SIDE<br />
eDP CONN (J8500) - 860-00415<br />
SH0421<br />
3.4OD1.75ID-0.844H-SM<br />
SH0422<br />
3.4OD1.75ID-0.844H-SM<br />
1<br />
1<br />
A<br />
SH0404<br />
2.8OD1.2ID-1.435H-SM<br />
1<br />
2<br />
SH0408<br />
2.8OD1.2ID-1.435H-SM<br />
1<br />
2<br />
SH0405<br />
2.8OD1.2ID-1.435H-SM<br />
1<br />
2<br />
SH0409<br />
2.8OD1.2ID-1.435H-SM<br />
1<br />
2<br />
SH0406<br />
2.8OD1.2ID-1.435H-SM<br />
1<br />
2<br />
SH0410<br />
2.8OD1.2ID-1.435H-SM<br />
1<br />
2<br />
SH0407<br />
2.8OD1.2ID-1.435H-SM<br />
1<br />
2<br />
SH0436<br />
2.8OD1.2ID-1.435H-SM<br />
1<br />
2<br />
SH0437<br />
2.8OD1.2ID-3.25H-SM<br />
1<br />
2<br />
BOM_COST_GROUP=MECHANICALS<br />
SYNC_MASTER=LDUNN_J44<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
PD Parts<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
SYNC_DATE=01/13/2013<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
4 OF 145<br />
4 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
105 34<br />
105 34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
105 34<br />
105 34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
DP_DDI1_ML_C_N<br />
DP_DDI1_ML_C_P<br />
DP_DDI1_ML_C_N<br />
DP_DDI1_ML_C_P<br />
DP_DDI1_ML_C_N<br />
DP_DDI1_ML_C_P<br />
DP_DDI1_ML_C_N<br />
DP_DDI1_ML_C_P<br />
DP_DDI2_ML_C_N<br />
DP_DDI2_ML_C_P<br />
DP_DDI2_ML_C_N<br />
DP_DDI2_ML_C_P<br />
DP_DDI2_ML_C_N<br />
DP_DDI2_ML_C_P<br />
DP_DDI2_ML_C_N<br />
DP_DDI2_ML_C_P<br />
E55<br />
F55<br />
E58<br />
F58<br />
F53<br />
G53<br />
F56<br />
G56<br />
C50<br />
D50<br />
C52<br />
D52<br />
A50<br />
B50<br />
D51<br />
C51<br />
DDI1_TXN[0]<br />
DDI1_TXP[0]<br />
DDI1_TXN[1]<br />
DDI1_TXP[1]<br />
DDI1_TXN[2]<br />
DDI1_TXP[2]<br />
DDI1_TXN[3]<br />
DDI1_TXP[3]<br />
DDI2_TXN[0]<br />
DDI2_TXP[0]<br />
DDI2_TXN[1]<br />
DDI2_TXP[1]<br />
DDI2_TXN[2]<br />
DDI2_TXP[2]<br />
DDI2_TXN[3]<br />
DDI2_TXP[3]<br />
OMIT_TABLE<br />
U0500<br />
SKL-ULT-2+3E<br />
TBD<br />
BGA<br />
SYM 1 OF 20<br />
DDI<br />
EDP<br />
EDP_TXN[0]<br />
EDP_TXP[0]<br />
EDP_TXN[1]<br />
EDP_TXP[1]<br />
EDP_TXN[2]<br />
EDP_TXP[2]<br />
EDP_TXN[3]<br />
EDP_TXP[3]<br />
EDP_AUXN<br />
EDP_AUXP<br />
EDP_DISP_UTIL<br />
DDI1_AUXN<br />
DDI1_AUXP<br />
DDI2_AUXN<br />
DDI2_AUXP<br />
C47<br />
C46<br />
D46<br />
C45<br />
A45<br />
B45<br />
A47<br />
B47<br />
E45<br />
F45<br />
B52<br />
G50<br />
F50<br />
E48<br />
F48<br />
EDP_INT_ML_N<br />
EDP_INT_ML_P<br />
EDP_INT_ML_N<br />
EDP_INT_ML_P<br />
EDP_INT_ML_N<br />
EDP_INT_ML_P<br />
EDP_INT_ML_N<br />
EDP_INT_ML_P<br />
EDP_INT_AUX_N<br />
EDP_INT_AUX_P<br />
NC<br />
DP_DDI1_AUXCH_C_N<br />
DP_DDI1_AUXCH_C_P<br />
DP_DDI2_AUXCH_C_N<br />
DP_DDI2_AUXCH_C_P<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
80<br />
80<br />
80<br />
80<br />
80<br />
80<br />
80<br />
80<br />
80<br />
80<br />
34<br />
34<br />
34<br />
34<br />
D<br />
C<br />
100<br />
8<br />
PPVCCIO_S0_CPU<br />
PLACE_NEAR=U0500.E52:15.24MM<br />
1<br />
R0530<br />
24.9<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
94 17 5<br />
34<br />
34<br />
94 28 5<br />
104 80<br />
IN<br />
IN<br />
IN<br />
19<br />
OUT<br />
IN<br />
XDP_USB_EXTD_OC_L<br />
DP_DDPB_HPD<br />
DP_DDPC_HPD<br />
NC_PCH_GPP_E15<br />
JTAG_ISP_TDO<br />
DP_INT_HPD<br />
EDP_COMP<br />
B9<br />
L9<br />
L7<br />
L6<br />
N9<br />
L10<br />
E52<br />
DISPLAY SIDEBANDS<br />
GPP_E12/USB2_OC3*<br />
GPP_E13/DDPB_HPD0<br />
GPP_E14/DDPC_HPD1<br />
GPP_E15/DDPD_HPD2<br />
GPP_E16/DDPE_HPD3<br />
GPP_E17/EDP_HPD<br />
EDP_RCOMP<br />
GPP_E7/CPU_GP1<br />
GPP_E8/SATALED*<br />
GPP_E9/USB2_OC0*<br />
GPP_E10/USB2_OC1*<br />
GPP_E11/USB2_OC2*<br />
EDP_BKLTEN<br />
EDP_BKLTCTL<br />
EDP_VDDEN<br />
A7<br />
H1<br />
A9<br />
C9<br />
D9<br />
R12<br />
R11<br />
U13<br />
XDP_PCH_OBSDATA_A3<br />
XDP_PCH_OBSDATA_B0<br />
XDP_USB_EXTA_OC_L<br />
XDP_USB_EXTB_OC_L<br />
XDP_USB_EXTC_OC_L<br />
EDP_BKLT_EN<br />
BKLT_PWM_MLB2TCON<br />
EDP_PANEL_PWR_EN<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
17<br />
17<br />
5 17 28<br />
5 17 28<br />
5 17 94<br />
79<br />
80 104<br />
80<br />
C<br />
OMIT_TABLE<br />
B<br />
12<br />
12<br />
FOR FUTURE PRODUCT PER PDG<br />
PP1V8_SUS_PCH_VCC1P8<br />
PP1V8_SUS_PCH_VCC1P8<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
AW69<br />
AW68<br />
AU56<br />
AW48<br />
C7<br />
U12<br />
U11<br />
H11<br />
G46<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
U0500<br />
SKL-ULT-2+3E<br />
TBD<br />
BGA<br />
SYM 20 OF 20<br />
SPARE<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
F6<br />
E3<br />
C11<br />
B11<br />
A11<br />
D12<br />
C12<br />
F52<br />
F46<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
B<br />
A<br />
PP3V3_SUS 8 12 101<br />
R0550 1 2<br />
100K<br />
R0551 100K 1 2<br />
R0552 100K 1 2<br />
R0553 100K 1 2<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
PP3V3_S0 13 14 16 19 94 101<br />
R0554 10K 1 2<br />
5% 1/20W MF 201<br />
XDP_USB_EXTA_OC_L<br />
XDP_USB_EXTB_OC_L<br />
XDP_USB_EXTC_OC_L<br />
XDP_USB_EXTD_OC_L<br />
JTAG_ISP_TDO<br />
5<br />
5<br />
5<br />
5<br />
5<br />
17<br />
17<br />
17<br />
17<br />
28<br />
28<br />
28<br />
94<br />
94<br />
94<br />
BOM_COST_GROUP=CPU & CHIPSET<br />
DESIGN: X502/DEV_MLB_U<br />
LAST CHANGE: Tue Apr 28 20:32:21 2015<br />
SYNC_MASTER=J130_DEV_MLB_U<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
CPU GFX<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
5 OF 145<br />
5 OF 119<br />
SYNC_DATE=04/29/2015<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
101<br />
19<br />
14<br />
10<br />
8<br />
PP1V0_S3<br />
D<br />
101<br />
17<br />
10<br />
8<br />
PP1V0_S0SW<br />
67 49 48<br />
PLACE_NEAR=R0611:1MM<br />
R0610<br />
1<br />
BI<br />
CPU_PROCHOT_L<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
201 2<br />
R0611<br />
499<br />
1%<br />
1/20W<br />
MF<br />
201<br />
PLACE_NEAR=U0500.C65:25.4MM<br />
2<br />
1<br />
49 48<br />
OUT<br />
PLACE_NEAR=U0500.C63:254MM<br />
1<br />
R0612<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
48 19<br />
49<br />
OUT<br />
BI<br />
105 BI<br />
102 BI<br />
102 BI<br />
102 BI<br />
13 IN<br />
17 OUT<br />
105 13 OUT<br />
35 13 OUT<br />
CPU_CATERR_L<br />
CPU_PECI<br />
CPU_PROCHOT_R_L<br />
PM_THRMTRIP_L<br />
XDP_BPM_L<br />
NC_XDP_BPM_L<br />
NC_XDP_BPM_L<br />
NC_XDP_BPM_L<br />
MLB_RAMCFG4<br />
XDP_PCH_OBSDATA_D2<br />
BT_PWRRST_L<br />
BT_TIMESTAMP<br />
PROC_POPIRCOMP<br />
PCH_OPIRCOMP<br />
OPCE_RCOMP<br />
OPC_RCOMP<br />
NC<br />
D63<br />
A54<br />
C65<br />
C63<br />
A65<br />
C55<br />
D55<br />
B54<br />
C56<br />
V1<br />
H3<br />
BA5<br />
AY5<br />
AT16<br />
AU16<br />
H66<br />
H65<br />
CATERR*<br />
PECI<br />
PROCHOT*<br />
THERMTRIP*<br />
SKTOCC*<br />
BPM[0]*<br />
BPM[1]*<br />
BPM[2]*<br />
BPM[3]*<br />
OMIT_TABLE<br />
U0500<br />
SKL-ULT-2+3E<br />
TBD<br />
BGA<br />
SYM 4 OF 20<br />
CPU MISC<br />
GPP_D21/SPI1_IO2<br />
GPP_E1/SATAXPCIE1/SATAGP1<br />
GPP_B3/CPU_GP2<br />
GPP_B4/CPU_GP3<br />
PROC_POPIRCOMP<br />
PCH_OPIRCOMP<br />
OPCE_RCOMP<br />
OPC_RCOMP<br />
JTAG<br />
PROC_TCK<br />
PROC_TDI<br />
PROC_TDO<br />
PROC_TMS<br />
PROC_TRST*<br />
PCH_JTAG_TCK<br />
PCH_JTAG_TDI<br />
PCH_JTAG_TDO<br />
PCH_JTAG_TMS<br />
PCH_TRST*<br />
JTAGX<br />
B61<br />
D60<br />
A61<br />
C60<br />
B59<br />
B56<br />
D59<br />
A56<br />
C59<br />
C61<br />
A59<br />
XDP_CPU_TCK<br />
XDP_CPU_TDI<br />
XDP_CPU_TDO<br />
XDP_CPU_TMS<br />
XDP_CPU_TRST_L<br />
XDP_PCH_TCK<br />
XDP_PCH_TDI<br />
XDP_PCH_TDO<br />
XDP_PCH_TMS<br />
XDP_PCH_TRST_L<br />
PCH_JTAGX<br />
IN<br />
IN<br />
OUT<br />
IN<br />
IN<br />
IN<br />
IN<br />
OUT<br />
IN<br />
IN<br />
BI<br />
17<br />
17<br />
17<br />
17<br />
17<br />
17<br />
17<br />
17<br />
17<br />
17<br />
17<br />
D<br />
R0681 1<br />
49.9 1%<br />
1/20W<br />
MF<br />
201 2<br />
R0682 1<br />
49.9<br />
1%<br />
1/20W<br />
MF<br />
201 2<br />
R0683 1<br />
49.9<br />
1%<br />
1/20W<br />
MF<br />
201 2<br />
R0684 1<br />
49.9 1%<br />
1/20W<br />
MF<br />
201 2<br />
C<br />
B<br />
A<br />
CFG :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED<br />
CPU_CFG<br />
EDP_ENABLE<br />
1<br />
R0634<br />
1K 5%<br />
1/20W<br />
MF<br />
2 201<br />
6<br />
17<br />
PLACE_NEAR=U0500.AT16:12.7MM<br />
PLACE_NEAR=U0500.H65:12.7MM<br />
PLACE_NEAR=U0500.AU16:12.7MM<br />
PLACE_NEAR=U0500.H66:12.7MM<br />
R0680 1<br />
49.9<br />
1%<br />
1/20W<br />
MF<br />
201 2<br />
17<br />
17<br />
17<br />
17<br />
17 6<br />
17<br />
17<br />
17<br />
17<br />
17<br />
17<br />
17<br />
17<br />
17<br />
17<br />
17<br />
17<br />
17<br />
17<br />
17<br />
17<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
OUT<br />
NC_CPU_RSVD_BA70<br />
102<br />
NC_CPU_RSVD_BA68<br />
102<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG_RCOMP<br />
ITP_PMODE<br />
E68<br />
B67<br />
D65<br />
D67<br />
E70<br />
C68<br />
D68<br />
C67<br />
F71<br />
G69<br />
F70<br />
G68<br />
H70<br />
G71<br />
H69<br />
G70<br />
E63<br />
F63<br />
E66<br />
F66<br />
E60<br />
E8<br />
AY2<br />
AY1<br />
D1<br />
D3<br />
K46<br />
K45<br />
AL25<br />
AL27<br />
C71<br />
B70<br />
F60<br />
A52<br />
BA70<br />
BA68<br />
J71<br />
J68<br />
F65<br />
G65<br />
F61<br />
E61<br />
(IPU)<br />
(IPU)<br />
(IPU)<br />
(IPU)<br />
(IPU)<br />
(IPU)<br />
(IPU)<br />
(IPU)<br />
(IPU)<br />
(IPU)<br />
(IPU)<br />
(IPU)<br />
(IPU)<br />
(IPU)<br />
(IPU)<br />
(IPU)<br />
(IPU)<br />
(IPU)<br />
(IPU)<br />
(IPU)<br />
OMIT_TABLE<br />
U0500<br />
SKL-ULT-2+3E<br />
TBD<br />
BGA<br />
SYM 19 OF 20<br />
BB68<br />
BB69<br />
AK13<br />
AK12<br />
BB2<br />
BA3<br />
AU5<br />
AT5<br />
D5<br />
D4<br />
B2<br />
C2<br />
B3<br />
A3<br />
AW1<br />
E1<br />
E2<br />
BA4<br />
BB4<br />
A4<br />
C4<br />
BB5<br />
A69<br />
B69<br />
AY3<br />
D71<br />
C70<br />
C54<br />
D54<br />
AY4<br />
BB3<br />
AY71<br />
AR56<br />
AW71<br />
AW70<br />
AP56<br />
C64<br />
NC_CPU_RSVD_BB68 102<br />
NC_CPU_RSVD_BB69 102<br />
NC_CPU_RSVD_AK13 102<br />
NC_CPU_RSVD_AK12 102<br />
NC_CPU_AU5 102<br />
NC_CPU_AT5 102<br />
NC_CPU_BB5 102<br />
NC_CPU_AY4 102<br />
NC_CPU_BB3 102<br />
CPU_ZVM_L<br />
NC_CPU_RSVD_AW71 102<br />
NC_CPU_RSVD_AW70 102<br />
NC_CPU_MSM_L<br />
73<br />
73<br />
CONNECT TO OPC VRS<br />
CONNECT TO OPC VRS<br />
BOM_COST_GROUP=CPU & CHIPSET<br />
DESIGN: X502/DEV_MLB_U<br />
LAST CHANGE: Mon Apr 27 22:56:39 2015<br />
SYNC_MASTER=J130_DEV_MLB_U<br />
CPU MISC/JTAG/CFG/RSVD<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
CFG[0]<br />
CFG[1]<br />
CFG[2]<br />
CFG[3]<br />
CFG[4]<br />
CFG[5]<br />
CFG[6]<br />
CFG[7]<br />
CFG[8]<br />
CFG[9]<br />
CFG[10]<br />
CFG[11]<br />
CFG[12]<br />
CFG[13]<br />
CFG[14]<br />
CFG[15]<br />
CFG[16]<br />
CFG[17]<br />
CFG[18]<br />
CFG[19]<br />
CFG_RCOMP<br />
ITP_PMODE<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD_TP<br />
RSVD_TP<br />
RSVD<br />
RSVD<br />
VSS<br />
VSS<br />
RSVD<br />
RSVD<br />
RESERVED<br />
RSVD_TP<br />
RSVD_TP<br />
RSVD_TP<br />
RSVD_TP<br />
RSVD<br />
RSVD<br />
TP5<br />
TP6<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
TP4<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
RSVD<br />
TP1<br />
TP2<br />
VSS<br />
ZVM*<br />
RSVD_TP<br />
RSVD_TP<br />
MSM*<br />
PROC_SELECT*<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
OUT<br />
OUT<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
6 OF 145<br />
6 OF 119<br />
SYNC_DATE=04/28/2015<br />
SIZE<br />
D<br />
C<br />
B<br />
A
9.0.0<br />
7 OF 119<br />
7 OF 145<br />
dvt-fab09-0<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_A_DQ<br />
MEM_A_DQS_P<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQS_P<br />
MEM_B_DQS_P<br />
CPU_DIMMB_VREFDQ<br />
CPU_DIMMA_VREFDQ<br />
CPU_DIMM_VREFCA<br />
MEM_A_DQS_P<br />
MEM_A_DQS_P<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_CKE<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_CAB<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQS_N<br />
MEM_A_CAB<br />
MEM_A_CAB<br />
MEM_A_CAA<br />
MEM_A_CAB<br />
MEM_A_CAB<br />
MEM_A_CAB<br />
MEM_A_CAA<br />
MEM_A_CAA<br />
MEM_A_CAB<br />
MEM_A_CAB<br />
MEM_A_CS_L<br />
MEM_A_CS_L<br />
MEM_A_ODT<br />
MEM_A_CLK_P<br />
MEM_A_DQS_P<br />
MEM_A_DQS_N<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P<br />
MEM_A_DQS_N<br />
MEM_A_DQS_N<br />
MEM_A_DQS_N<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P<br />
MEM_A_DQS_P<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQS_P<br />
MEM_B_DQS_P<br />
MEM_B_DQS_P<br />
MEM_B_DQS_P<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MEM_B_DQS_N<br />
MEM_B_DQS_N<br />
MEM_B_DQS_N<br />
MEM_B_DQS_N<br />
MEM_B_DQS_N<br />
MEM_B_DQS_N<br />
MEM_B_DQS_N<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_ODT<br />
MEM_B_DQ<br />
MEM_B_CS_L<br />
MEM_B_CS_L<br />
MEM_B_CKE<br />
MEM_B_CKE<br />
MEM_B_CKE<br />
MEM_B_CKE<br />
MEM_B_CLK_P<br />
MEM_B_CLK_P<br />
MEM_B_CLK_N<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_A_CAA<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_A_CAB<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_B_DQ<br />
MEM_A_CAB<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_A_CLK_N<br />
MEM_B_CLK_N<br />
PM_MEMVTT_EN<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
CPU_DDR_RCOMP<br />
CPU_DDR_RCOMP<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_A_CAA<br />
MEM_B_DQ<br />
MEM_B_DQS_P<br />
MEM_A_CAA<br />
MEM_A_CAA<br />
MEM_A_CAA<br />
MEM_A_CAA<br />
MEM_A_CAA<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_A_CKE<br />
MEM_A_CKE<br />
MEM_A_CLK_P<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
CPU_DDR_RCOMP<br />
MEM_B_CAA<br />
MEM_A_CKE<br />
MEM_A_CLK_N<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
BOM_COST_GROUP=CPU & CHIPSET<br />
CPU LPDDR3 Interface<br />
SYNC_MASTER=J52_MLB<br />
SYNC_DATE=05/12/2015<br />
201<br />
200<br />
MF<br />
1%<br />
1/20W<br />
PLACE_NEAR=U0500.AR18:6MM<br />
1 R0702<br />
2<br />
201<br />
80.6<br />
MF<br />
1/20W<br />
1%<br />
PLACE_NEAR=U0500.AT18:6MM<br />
1 R0701<br />
2<br />
1%<br />
201<br />
162<br />
MF<br />
1/20W<br />
PLACE_NEAR=U0500.AU18:6MM<br />
1 R0700<br />
2<br />
75<br />
25<br />
23<br />
25<br />
23<br />
25<br />
24<br />
25<br />
24<br />
25<br />
21<br />
25<br />
21<br />
25<br />
22<br />
25<br />
22<br />
25<br />
22<br />
21<br />
25<br />
22<br />
21<br />
25<br />
21<br />
25<br />
21<br />
25<br />
22<br />
25<br />
22<br />
25<br />
22<br />
21<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
OMIT_TABLE<br />
TBD<br />
BGA<br />
SKL-ULT-2+3E<br />
U0500<br />
AN43<br />
AY48<br />
AP50<br />
BA48<br />
BB48<br />
AP48<br />
AP52<br />
AN50<br />
AN48<br />
AN53<br />
AN52<br />
BA43<br />
AY43<br />
AY44<br />
AW44<br />
BB44<br />
AY47<br />
BA44<br />
AW46<br />
AY46<br />
BA46<br />
AN56<br />
AP55<br />
AN55<br />
AP53<br />
AN45<br />
AN46<br />
AP45<br />
AP46<br />
BB42<br />
AY42<br />
AY39<br />
AW39<br />
AY37<br />
AW37<br />
BB39<br />
BA39<br />
BA37<br />
BB37<br />
AY35<br />
AW35<br />
AY33<br />
AW33<br />
BB35<br />
BA35<br />
BA33<br />
BB33<br />
AU40<br />
AT40<br />
AT37<br />
AU37<br />
AR40<br />
AP40<br />
AP37<br />
AR37<br />
AT33<br />
AU33<br />
AU30<br />
AT30<br />
AR33<br />
AP33<br />
AR30<br />
AP30<br />
AY31<br />
AW31<br />
AY29<br />
AW29<br />
BB31<br />
BA31<br />
BA29<br />
BB29<br />
AY27<br />
AW27<br />
AY25<br />
AW25<br />
BB27<br />
BA27<br />
BA25<br />
BB25<br />
AU27<br />
AT27<br />
AT25<br />
AU25<br />
AP27<br />
AN27<br />
AN25<br />
AP25<br />
AT22<br />
AU22<br />
AU21<br />
AT21<br />
AN22<br />
AP22<br />
AP21<br />
AN21<br />
BA38<br />
AY34<br />
AT38<br />
AT32<br />
BA30<br />
AY26<br />
AR25<br />
AR22<br />
AY38<br />
BA34<br />
AR38<br />
AR32<br />
AY30<br />
BA26<br />
AR27<br />
AR21<br />
BB46<br />
BA47<br />
BA42<br />
AW42<br />
AP43<br />
AR18<br />
AT18<br />
AU18<br />
AT13<br />
OMIT_TABLE<br />
SKL-ULT-2+3E<br />
TBD<br />
BGA<br />
U0500<br />
AW50<br />
BA51<br />
BB54<br />
BA52<br />
AY52<br />
AW52<br />
AY55<br />
AW54<br />
BA54<br />
BA55<br />
AY54<br />
AU46<br />
AU48<br />
AT46<br />
AU50<br />
AU52<br />
AY51<br />
AT48<br />
AT50<br />
BB50<br />
AY50<br />
BA56<br />
BB56<br />
AW56<br />
AY56<br />
AU53<br />
AU55<br />
AT53<br />
AT55<br />
AU45<br />
AU43<br />
AL71<br />
AL68<br />
AN68<br />
AN69<br />
AL70<br />
AL69<br />
AN70<br />
AN71<br />
AR70<br />
AR68<br />
AU71<br />
AU68<br />
AR71<br />
AR69<br />
AU70<br />
AU69<br />
AF65<br />
AF64<br />
AK65<br />
AK64<br />
AF66<br />
AF67<br />
AK67<br />
AK66<br />
AF70<br />
AF68<br />
AH71<br />
AH68<br />
AF71<br />
AF69<br />
AH70<br />
AH69<br />
BB65<br />
AW65<br />
AW63<br />
AY63<br />
BA65<br />
AY65<br />
BA63<br />
BB63<br />
BA61<br />
AW61<br />
BB59<br />
AW59<br />
BB61<br />
AY61<br />
BA59<br />
AY59<br />
AT66<br />
AU66<br />
AP65<br />
AN65<br />
AN66<br />
AP66<br />
AT65<br />
AU65<br />
AT61<br />
AU61<br />
AP60<br />
AN60<br />
AN61<br />
AP61<br />
AT60<br />
AU60<br />
AM70<br />
AT69<br />
AH66<br />
AG69<br />
BA64<br />
AY60<br />
AR66<br />
AR61<br />
AM69<br />
AT70<br />
AH65<br />
AG70<br />
AY64<br />
BA60<br />
AR65<br />
AR60<br />
BA50<br />
BB52<br />
AT45<br />
AT43<br />
AT52<br />
AY68<br />
BA67<br />
AY67<br />
AW67<br />
25<br />
24<br />
25<br />
24<br />
25<br />
24<br />
25<br />
24<br />
25<br />
24<br />
25<br />
24<br />
25<br />
24<br />
25<br />
24<br />
25<br />
24<br />
25<br />
23<br />
25<br />
24<br />
25<br />
23<br />
25<br />
23<br />
25<br />
23<br />
25<br />
23<br />
25<br />
23<br />
25<br />
23<br />
25<br />
23<br />
25<br />
23<br />
25<br />
23<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
25<br />
22<br />
25<br />
22<br />
25<br />
22<br />
25<br />
22<br />
25<br />
22<br />
25<br />
22<br />
25<br />
22<br />
25<br />
22<br />
25<br />
22<br />
25<br />
22<br />
25<br />
21<br />
25<br />
21<br />
25<br />
21<br />
25<br />
21<br />
25<br />
21<br />
25<br />
21<br />
25<br />
21<br />
25<br />
21<br />
25<br />
21<br />
25<br />
21<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
25<br />
24<br />
23<br />
25<br />
24<br />
23<br />
25<br />
24<br />
23<br />
25<br />
24<br />
25<br />
24<br />
25<br />
23<br />
25<br />
23<br />
20<br />
20<br />
20<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
3<br />
6<br />
BRANCH<br />
REVISION<br />
DRAWING NUMBER<br />
SIZE<br />
D<br />
R<br />
IV ALL RIGHTS RESERVED<br />
SHEET<br />
PAGE TITLE<br />
C<br />
A<br />
D<br />
2 1<br />
PAGE<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
A<br />
B<br />
C<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
D<br />
B<br />
8 7 5 4 2 1<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
Apple Inc.<br />
OUT<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
NC<br />
NC<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
LPDDR3 NON-INTERLEAVED<br />
SYM 3 OF 20<br />
DDR1_DQ[0]<br />
DDR1_DQ[1]<br />
DDR1_DQ[2]<br />
DDR1_DQ[3]<br />
DDR1_MA[3]<br />
DDR1_MA[4]<br />
DRAM_RESET*<br />
DDR_RCOMP[2]<br />
DDR_RCOMP[0]<br />
DDR_RCOMP[1]<br />
DDR1_PAR<br />
DDR1_ALERT*<br />
DDR1_DQSP[6]<br />
DDR1_DQSP[7]<br />
DDR1_DQSP[5]<br />
DDR1_DQSP[4]<br />
DDR1_DQSP[3]<br />
DDR1_DQSP[2]<br />
DDR1_DQSP[1]<br />
DDR1_DQSP[0]<br />
DDR1_DQSN[7]<br />
DDR1_DQSN[6]<br />
DDR1_DQSN[5]<br />
DDR1_DQSN[4]<br />
DDR1_DQSN[3]<br />
DDR1_DQSN[2]<br />
DDR1_DQSN[1]<br />
DDR1_DQSN[0]<br />
DDR1_CAB[9]<br />
DDR1_CAB[8]<br />
DDR1_CAB[7]<br />
DDR1_CAB[6]<br />
DDR1_CAB[5]<br />
DDR1_CAB[4]<br />
DDR1_CAB[3]<br />
DDR1_CAB[2]<br />
DDR1_CAB[1]<br />
DDR1_CAB[0]<br />
DDR1_CAA[9]<br />
DDR1_CAA[8]<br />
DDR1_CAA[7]<br />
DDR1_CAA[6]<br />
DDR1_CAA[5]<br />
DDR1_CAA[4]<br />
DDR1_CAA[3]<br />
DDR1_CAA[2]<br />
DDR1_CAA[1]<br />
DDR1_CAA[0]<br />
DDR1_ODT[1]<br />
DDR1_ODT[0]<br />
DDR1_DQ[33]<br />
DDR1_DQ[29]<br />
DDR1_CS[1]*<br />
DDR1_CS[0]*<br />
DDR1_CKE[3]<br />
DDR1_CKE[2]<br />
DDR1_CKE[1]<br />
DDR1_CKE[0]<br />
DDR1_CKN[0]<br />
DDR1_CKP[0]<br />
DDR1_CKP[1]<br />
DDR1_CKN[1]<br />
DDR1_DQ[8]<br />
DDR1_DQ[6]<br />
DDR1_DQ[5]<br />
DDR1_DQ[4]<br />
DDR1_DQ[7]<br />
DDR1_DQ[9]<br />
DDR1_DQ[19]<br />
DDR1_DQ[18]<br />
DDR1_DQ[17]<br />
DDR1_DQ[16]<br />
DDR1_DQ[15]<br />
DDR1_DQ[14]<br />
DDR1_DQ[10]<br />
DDR1_DQ[13]<br />
DDR1_DQ[12]<br />
DDR1_DQ[11]<br />
DDR1_DQ[23]<br />
DDR1_DQ[20]<br />
DDR1_DQ[21]<br />
DDR1_DQ[22]<br />
DDR1_DQ[24]<br />
DDR1_DQ[25]<br />
DDR1_DQ[26]<br />
DDR1_DQ[27]<br />
DDR1_DQ[28]<br />
DDR1_DQ[30]<br />
DDR1_DQ[31]<br />
DDR1_DQ[32]<br />
DDR1_DQ[34]<br />
DDR1_DQ[35]<br />
DDR1_DQ[36]<br />
DDR1_DQ[37]<br />
DDR1_DQ[38]<br />
DDR1_DQ[39]<br />
DDR1_DQ[40]<br />
DDR1_DQ[46]<br />
DDR1_DQ[47]<br />
DDR1_DQ[48]<br />
DDR1_DQ[49]<br />
DDR1_DQ[50]<br />
DDR1_DQ[42]<br />
DDR1_DQ[41]<br />
DDR1_DQ[45]<br />
DDR1_DQ[44]<br />
DDR1_DQ[43]<br />
DDR1_DQ[60]<br />
DDR1_DQ[51]<br />
DDR1_DQ[52]<br />
DDR1_DQ[53]<br />
DDR1_DQ[54]<br />
DDR1_DQ[55]<br />
DDR1_DQ[56]<br />
DDR1_DQ[57]<br />
DDR1_DQ[58]<br />
DDR1_DQ[59]<br />
DDR1_DQ[61]<br />
DDR1_DQ[62]<br />
DDR1_DQ[63]<br />
SYM 2 OF 20<br />
LPDDR3 NON-INTERLEAVED0<br />
DDR0_PAR<br />
DDR0_ALERT*<br />
DDR0_DQSP[7]<br />
DDR0_DQSP[4]<br />
DDR0_DQSP[1]<br />
DDR0_DQSP[0]<br />
DDR0_DQSN[7]<br />
DDR0_DQSN[6]<br />
DDR0_DQSN[5]<br />
DDR0_DQSN[4]<br />
DDR0_DQSN[3]<br />
DDR0_DQSN[2]<br />
DDR0_DQSN[1]<br />
DDR0_DQSN[0]<br />
DDR0_MA[3]<br />
DDR0_DQ[49]<br />
DDR_VTT_CNTL<br />
DDR1_VREF_DQ<br />
DDR0_VREF_DQ<br />
DDR_VREF_CA<br />
DDR0_MA[4]<br />
DDR0_DQSP[6]<br />
DDR0_DQSP[5]<br />
DDR0_DQSP[3]<br />
DDR0_DQSP[2]<br />
DDR0_CAB[9]<br />
DDR0_CAB[8]<br />
DDR0_CAB[7]<br />
DDR0_CAB[6]<br />
DDR0_CAB[4]<br />
DDR0_CAB[5]<br />
DDR0_CAB[3]<br />
DDR0_CAB[2]<br />
DDR0_CAB[1]<br />
DDR0_CAB[0]<br />
DDR0_DQ[24]<br />
DDR0_CAA[9]<br />
DDR0_CAA[8]<br />
DDR0_CAA[7]<br />
DDR0_CAA[6]<br />
DDR0_CAA[5]<br />
DDR0_CAA[4]<br />
DDR0_CAA[3]<br />
DDR0_CAA[2]<br />
DDR0_CAA[1]<br />
DDR0_CAA[0]<br />
DDR0_ODT[1]<br />
DDR0_ODT[0]<br />
DDR0_CKN[1]<br />
DDR0_CKP[0]<br />
DDR0_CKE[3]<br />
DDR0_DQ[4]<br />
DDR0_DQ[5]<br />
DDR0_CS[0]*<br />
DDR0_CKE[1]<br />
DDR0_CKE[2]<br />
DDR0_CKN[0]<br />
DDR0_DQ[3]<br />
DDR0_DQ[61]<br />
DDR0_DQ[62]<br />
DDR0_DQ[60]<br />
DDR0_DQ[59]<br />
DDR0_DQ[58]<br />
DDR0_DQ[57]<br />
DDR0_DQ[56]<br />
DDR0_DQ[53]<br />
DDR0_DQ[54]<br />
DDR0_DQ[55]<br />
DDR0_DQ[51]<br />
DDR0_DQ[52]<br />
DDR0_DQ[48]<br />
DDR0_DQ[50]<br />
DDR0_DQ[47]<br />
DDR0_DQ[46]<br />
DDR0_DQ[45]<br />
DDR0_DQ[43]<br />
DDR0_DQ[44]<br />
DDR0_DQ[41]<br />
DDR0_DQ[42]<br />
DDR0_DQ[40]<br />
DDR0_DQ[39]<br />
DDR0_DQ[38]<br />
DDR0_DQ[36]<br />
DDR0_DQ[37]<br />
DDR0_DQ[35]<br />
DDR0_DQ[34]<br />
DDR0_DQ[33]<br />
DDR0_DQ[32]<br />
DDR0_DQ[31]<br />
DDR0_DQ[30]<br />
DDR0_DQ[28]<br />
DDR0_DQ[29]<br />
DDR0_DQ[25]<br />
DDR0_DQ[26]<br />
DDR0_DQ[27]<br />
DDR0_DQ[21]<br />
DDR0_DQ[20]<br />
DDR0_DQ[19]<br />
DDR0_DQ[18]<br />
DDR0_DQ[17]<br />
DDR0_DQ[16]<br />
DDR0_DQ[15]<br />
DDR0_DQ[14]<br />
DDR0_DQ[13]<br />
DDR0_DQ[12]<br />
DDR0_DQ[11]<br />
DDR0_DQ[10]<br />
DDR0_DQ[9]<br />
DDR0_DQ[8]<br />
DDR0_DQ[7]<br />
DDR0_DQ[6]<br />
DDR0_DQ[2]<br />
DDR0_DQ[1]<br />
DDR0_DQ[0]<br />
DDR0_CS[1]*<br />
DDR0_CKE[0]<br />
DDR0_CKP[1]<br />
DDR0_DQ[63]<br />
DDR0_DQ[23]<br />
DDR0_DQ[22]<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
<br />
<br />
051-00777
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
C<br />
B<br />
A<br />
101<br />
19<br />
101<br />
14<br />
17<br />
101<br />
100<br />
101<br />
101<br />
10<br />
10<br />
100<br />
101<br />
55<br />
101<br />
101<br />
101<br />
101<br />
101<br />
12<br />
101<br />
100<br />
100<br />
8<br />
8<br />
12<br />
12<br />
8<br />
6<br />
6<br />
10<br />
10<br />
8<br />
12<br />
19 12<br />
12<br />
12<br />
12<br />
12<br />
8<br />
14<br />
12<br />
13<br />
12<br />
5<br />
78 12<br />
12<br />
PP1V2_S3_CPUDDR<br />
PP1V2_S3_CPUDDR<br />
PP1V0_S3<br />
PP1V0_S0SW<br />
PP1V2_S0SW<br />
PP1V0_S3<br />
PP1V0_SUS<br />
PPVCCPRIMCORE_SUS_PCH<br />
PP1V_S5_PCH_DCPDSW<br />
PP1V0_SUS<br />
PP1V0_SUSSW<br />
PP1V_SUSSW_PCH_VCCAMPHYPLL_F<br />
PP1V_SUS_PCH_VCCAPLL_F<br />
PP1V0_SUS<br />
PP3V3_S5<br />
PP1V8_S0_PCH_VCCHDA_F<br />
PP3V3_SUS<br />
PP1V0_SUSSW<br />
PP3V3_SUS<br />
PP1V0_SUSFUSE<br />
PP1V0_SUSSW<br />
AU23<br />
AU28<br />
AU35<br />
AU42<br />
BB23<br />
BB32<br />
BB41<br />
BB47<br />
BB51<br />
AM40<br />
A18<br />
A22<br />
AL23<br />
K20<br />
K21<br />
AB19<br />
AB20<br />
P18<br />
AF18<br />
AF19<br />
V20<br />
V21<br />
AL1<br />
K17<br />
L1<br />
N15<br />
N16<br />
N17<br />
P15<br />
P16<br />
K15<br />
L15<br />
V15<br />
AB17<br />
Y18<br />
AD17<br />
AD18<br />
AJ17<br />
AJ19<br />
AJ16<br />
AF20<br />
AF21<br />
T19<br />
T20<br />
AJ21<br />
AK20<br />
N18<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQ<br />
VDDQC<br />
VCCST<br />
VCCSTG<br />
VCCPLL_OC<br />
VCCPLL<br />
VCCPLL<br />
VCCPRIM_1P0<br />
VCCPRIM_1P0<br />
VCCPRIM_1P0<br />
VCCPRIM_CORE<br />
VCCPRIM_CORE<br />
VCCPRIM_CORE<br />
VCCPRIM_CORE<br />
DCPDSW_1P0<br />
VCCMPHYAON_1P0<br />
VCCMPHYAON_1P0<br />
VCCMPHYGT_1P0<br />
VCCMPHYGT_1P0<br />
VCCMPHYGT_1P0<br />
VCCMPHYGT_1P0<br />
VCCMPHYGT_1P0<br />
VCCAMPHYPLL_1P0<br />
VCCAMPHYPLL_1P0<br />
VCCAPLL_1P0<br />
VCCPRIM_1P0<br />
VCCPRIM_1P0<br />
VCCDSW_3P3<br />
VCCDSW_3P3<br />
VCCDSW_3P3<br />
VCCHDA<br />
VCCSPI<br />
VCCSRAM_1P0<br />
VCCSRAM_1P0<br />
VCCSRAM_1P0<br />
VCCSRAM_1P0<br />
VCCPRIM_3P3<br />
VCCPRIM_1P0<br />
VCCAPLLEBB_1P0<br />
OMIT_TABLE<br />
U0500<br />
SKL-ULT-2+3E<br />
TBD<br />
BGA<br />
SYM 14 OF 20<br />
CPU POWER 3<br />
OMIT_TABLE<br />
U0500<br />
SKL-ULT-2+3E<br />
TBD<br />
BGA<br />
SYM 15 OF 20<br />
CPU POWER 4<br />
VCCIO<br />
VCCIO<br />
VCCIO<br />
VCCIO<br />
VCCIO<br />
VCCIO<br />
VCCIO<br />
VCCSA<br />
VCCSA<br />
VCCSA<br />
VCCSA<br />
VCCSA<br />
VCCSA<br />
VCCSA<br />
VCCSA<br />
VCCSA<br />
VCCSA<br />
VCCSA<br />
VCCSA<br />
VCCSA<br />
VCCSA<br />
VCCIO_SENSE<br />
VSSIO_SENSE<br />
VSSSA_SENSE<br />
VCCSA_SENSE<br />
VCCPGPPA<br />
VCCPGPPB<br />
VCCPGPPC<br />
VCCPGPPD<br />
VCCPGPPE<br />
VCCPGPPF<br />
VCCPGPPG<br />
VCCPRIM_3P3<br />
VCCPRIM_1P0<br />
VCCATS_1P8<br />
VCCRTCPRIM_3P3<br />
VCCRTC<br />
VCCRTC<br />
DCPRTC<br />
VCCCLK1<br />
VCCCLK2<br />
VCCCLK3<br />
VCCCLK4<br />
VCCCLK5<br />
VCCCLK6<br />
GPP_B0/CORE_VID0<br />
GPP_B1/CORE_VID1<br />
AK28<br />
AK30<br />
AL30<br />
AL42<br />
AM28<br />
AM30<br />
AM42<br />
AK23<br />
AK25<br />
G23<br />
G25<br />
G27<br />
G28<br />
J22<br />
J23<br />
J27<br />
K23<br />
K25<br />
K27<br />
K28<br />
K30<br />
AM23<br />
AM22<br />
H21<br />
H20<br />
AK15<br />
AG15<br />
Y16<br />
Y15<br />
T16<br />
AF16<br />
AD15<br />
V19<br />
T1<br />
AA1<br />
AK17<br />
AK19<br />
BB14<br />
BB10<br />
A14<br />
K19<br />
L21<br />
N20<br />
L19<br />
A10<br />
AN11<br />
AN13<br />
PPVCCIO_S0_CPU 5 8 100<br />
PPVCCSA_S0_CPU 8 55 100<br />
CPU_VCCIOSENSE_P<br />
CPU_VCCIOSENSE_N<br />
CPU_VCCSASENSE_N<br />
CPU_VCCSASENSE_P<br />
PP3V3_SUS 13 14 15 16 101<br />
PP3V3_SUS 12 101<br />
PP3V3_SUS 12 101<br />
PP3V3_SUS 101<br />
PP3V3_SUS 12 101<br />
PP1V8_SUS 14 19 100<br />
PP3V3_SUS 101<br />
PP3V3_SUS 5 8 12 101<br />
PP1V0_SUS 8 12 101<br />
PP1V8_SUS 12 100<br />
PP3V3_SUS 12 101<br />
PP3V0_G3H 12 14 15 100<br />
PPDCPRTC_PCH<br />
PP1V0_SUS 101<br />
PP1V_SUS_PCH_VCCCLK2_F 12<br />
PP1V0_SUS 101<br />
PP1V_SUS_PCH_VCCCLK4_F 12<br />
PP1V_SUS_PCH_VCCCLK5_F 12<br />
PP1V0_SUS 101<br />
NC_VCCPRIM_CORE_VID0<br />
NC_VCCPRIM_CORE_VID1<br />
100<br />
100<br />
8 PPVCCEDRAM_S0_CPU<br />
100 PPVCCEDRAM_S0_CPU<br />
100 PPVCCEDRAM_S0_CPU<br />
100<br />
100<br />
8<br />
8<br />
PP1V8_SUS<br />
PP1V8_SUS<br />
CPU_VCCOPCSENSE_P<br />
CPU_VCCOPCSENSE_N<br />
8 PPVCCEDRAM_S0_CPU<br />
100 PPVCCEDRAM_S0_CPU<br />
8<br />
8<br />
CPU_VCCEOPIOSENSE_P<br />
CPU_VCCEOPIOSENSE_N<br />
12<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
19<br />
OUT<br />
OUT<br />
8<br />
8<br />
8<br />
8<br />
19<br />
19<br />
75<br />
75<br />
67<br />
67<br />
104<br />
100<br />
100<br />
100<br />
100<br />
8<br />
55<br />
54<br />
100<br />
100<br />
100<br />
54<br />
NC<br />
NC<br />
5 PPVCCIO_S0_CPU<br />
8 PPVCCSA_S0_CPU<br />
8 PPVCCGT_S0_CPU<br />
8 PPVCCGT_S0_CPU<br />
8 PPVCCEDRAM_S0_CPU<br />
8 PPVCCEDRAM_S0_CPU<br />
8 PPVCC_S0_CPU<br />
PPVCC_S0_CPU 8 54 100 104<br />
A30<br />
A34<br />
A39<br />
A44<br />
AK33<br />
AK35<br />
AK37<br />
AK38<br />
AK40<br />
AL33<br />
AL37<br />
AL40<br />
AM32<br />
AM33<br />
AM35<br />
AM37<br />
AM38<br />
G30<br />
K32<br />
AK32<br />
AB62<br />
P62<br />
V62<br />
H63<br />
G61<br />
AC63<br />
AE63<br />
AE62<br />
AG62<br />
AL63<br />
AJ62<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
RSVD<br />
RSVD<br />
VCCOPC<br />
VCCOPC<br />
VCCOPC<br />
VCC_OPC_1P8<br />
VCC_OPC_1P8<br />
VCCOPC_SENSE<br />
VSSOPC_SENSE<br />
VCCEOPIO<br />
VCCEOPIO<br />
VCCEOPIO_SENSE<br />
VSSEOPIO_SENSE<br />
OMIT_TABLE<br />
U0500<br />
SKL-ULT-2+3E<br />
TBD<br />
BGA<br />
SYM 12 OF 20<br />
PLACE_NEAR=U0500.AM23:50.8MM<br />
R0801 1 2 100<br />
PLACE_NEAR=U0500.H20:50.8MM<br />
R0804 1 2 100<br />
PLACE_NEAR=U0500.J70:50.8MM<br />
R0811 1 2 100<br />
PLACE_NEAR=U0500.AK62:50.8MM<br />
R0813 1 2 100<br />
PLACE_NEAR=U0500.AC63:50.8MM<br />
R0821 1 2 100<br />
PLACE_NEAR=U0500.AL63:50.8MM<br />
R0823 1 2<br />
PLACE_NEAR=U0500.E32:50.8MM<br />
R0825 1 2<br />
PLACE_NEAR=U0500.AM22:50.8MM<br />
2 100<br />
5% 1/20W MF 201<br />
R0802 1<br />
PLACE_NEAR=U0500.H21:50.8MM<br />
2 100<br />
5% 1/20W MF 201<br />
R0803 1<br />
PLACE_NEAR=U0500.J69:50.8MM<br />
2 100<br />
5% 1/20W MF 201<br />
R0812 1<br />
PLACE_NEAR=U0500.AL61:50.8MM<br />
2 100<br />
5% 1/20W MF 201<br />
R0814 1<br />
PLACE_NEAR=U0500.AE63:50.8MM<br />
2 100<br />
5% 1/20W MF 201<br />
R0822 1<br />
PLACE_NEAR=U0500.AJ62:50.8MM<br />
2 100<br />
5% 1/20W MF 201<br />
R0824 1<br />
PLACE_NEAR=U0500.E33:50.8MM<br />
2 100<br />
5% 1/20W MF 201<br />
R0826 1<br />
G32<br />
G33<br />
G35<br />
G37<br />
G38<br />
G40<br />
G42<br />
J30<br />
J33<br />
J37<br />
J40<br />
K33<br />
K35<br />
K37<br />
K38<br />
K40<br />
K42<br />
K43<br />
E32<br />
E33<br />
B63<br />
A63<br />
D64<br />
G20<br />
100<br />
100<br />
5%<br />
5%<br />
1/20W<br />
CPU_VCCSENSE_P<br />
CPU_VCCSENSE_N<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
CPU_VIDALERT_R_L<br />
CPU_VIDSCLK_R<br />
CPU_VIDSOUT_R<br />
CPU_VCCIOSENSE_P<br />
CPU_VCCSASENSE_P<br />
CPU_VCCGTSENSE_P<br />
CPU_VCCGTXSENSE_P<br />
CPU_VCCOPCSENSE_P<br />
CPU_VCCGTXSENSE_N<br />
CPU_VCCOPCSENSE_N<br />
PP1V0_S0SW 6 8 10<br />
17 101<br />
100<br />
CPU_VCCEOPIOSENSE_P<br />
MF 201<br />
CPU_VCCSENSE_P<br />
1/20W MF 201<br />
CPU_VCCIOSENSE_N<br />
CPU_VCCSASENSE_N<br />
CPU_VCCGTSENSE_N<br />
CPU_VCCEOPIOSENSE_N<br />
CPU_VCCSENSE_N<br />
8<br />
8<br />
67<br />
67<br />
67 8<br />
67 8<br />
1%<br />
1/20W<br />
MF<br />
201<br />
54<br />
R0829<br />
220<br />
1 2<br />
R0831<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
8 PPVCCGT_S0_CPU<br />
0<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
8<br />
8<br />
8<br />
8<br />
8<br />
8<br />
8<br />
8<br />
8<br />
8<br />
8<br />
8<br />
8<br />
8<br />
CPU_VCCGTSENSE_P<br />
CPU_VCCGTSENSE_N<br />
PP1V0_S3 6 8 10 14 19 101<br />
1<br />
R0827<br />
56<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
R0830<br />
1 2<br />
75<br />
67<br />
67<br />
67<br />
75<br />
67<br />
67<br />
67<br />
1<br />
R0828<br />
100<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
CPU_VIDALERT_L<br />
CPU_VIDSCLK<br />
CPU_VIDSOUT<br />
A48<br />
A53<br />
A58<br />
A62<br />
A66<br />
AA63<br />
AA64<br />
AA66<br />
AA67<br />
AA69<br />
AA70<br />
AA71<br />
AC64<br />
AC65<br />
AC66<br />
AC67<br />
AC68<br />
AC69<br />
AC70<br />
AC71<br />
J43<br />
J45<br />
J46<br />
J48<br />
J50<br />
J52<br />
J53<br />
J55<br />
J56<br />
J58<br />
J60<br />
K48<br />
K50<br />
K52<br />
K53<br />
K55<br />
K56<br />
K58<br />
K60<br />
L62<br />
L63<br />
L64<br />
L65<br />
L66<br />
L67<br />
L68<br />
L69<br />
L70<br />
L71<br />
M62<br />
N63<br />
N64<br />
N66<br />
N67<br />
N69<br />
J70<br />
J69<br />
PLACE_NEAR=U0500.B63:12.7MM<br />
PLACE_NEAR=U0500.A63:12.7MM<br />
PLACE_NEAR=U0500.D64:12.7MM<br />
BOM_COST_GROUP=CPU & CHIPSET<br />
67<br />
67<br />
67<br />
OMIT_TABLE<br />
U0500<br />
SKL-ULT-2+3E<br />
TBD<br />
BGA<br />
SYM 13 OF 20<br />
CPU POWER 2<br />
SYNC_MASTER=J79_JSHAO<br />
N70<br />
N71<br />
R63<br />
R64<br />
R65<br />
R66<br />
R67<br />
R68<br />
R69<br />
R70<br />
R71<br />
T62<br />
U65<br />
U68<br />
U71<br />
W63<br />
W64<br />
W65<br />
W66<br />
W67<br />
W68<br />
W69<br />
W70<br />
W71<br />
Y62<br />
AK42<br />
AK43<br />
AK45<br />
AK46<br />
AK48<br />
AK50<br />
AK52<br />
AK53<br />
AK55<br />
AK56<br />
AK58<br />
AK60<br />
AK70<br />
AL43<br />
AL46<br />
AL50<br />
AL53<br />
AL56<br />
AL60<br />
AM48<br />
AM50<br />
AM52<br />
AM53<br />
AM56<br />
AM58<br />
AU58<br />
AU63<br />
BB57<br />
BB66<br />
AK62<br />
AL61<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
PPVCCGT_S0_CPU 8 100<br />
CPU_VCCGTXSENSE_P<br />
CPU_VCCGTXSENSE_N<br />
CPU & PCH Power<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
CPU POWER 1<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC<br />
VCC_SENSE<br />
VSS_SENSE<br />
VIDALERT*<br />
VIDSCK<br />
VIDSOUT<br />
VCCSTG<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT_SENSE<br />
VSSGT_SENSE<br />
OUT<br />
BI<br />
IN<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGT<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX<br />
VCCGTX_SENSE<br />
VSSGTX_SENSE<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
8<br />
8<br />
8 OF 145<br />
8 OF 119<br />
SYNC_DATE=03/14/2016<br />
SIZE<br />
D<br />
D<br />
C<br />
B<br />
A
9 OF 119<br />
9.0.0<br />
dvt-fab09-0<br />
9 OF 145<br />
NC_CPU_NCTFVSS_A70<br />
102<br />
NC_CPU_NCTFVSS_A5<br />
102<br />
NC_CPU_NCTFVSS_BA1<br />
102<br />
NC_CPU_NCTFVSS_B71<br />
102<br />
NC_CPU_NCTFVSS_BA71 102<br />
NC_CPU_NCTFVSS_C1 102<br />
NC_CPU_NCTFVSS_BB70 102<br />
NC_CPU_NCTFVSS_AV1<br />
102<br />
SYNC_DATE=05/12/2015<br />
SYNC_MASTER=J79_ALFRED<br />
CPU & PCH Grounds<br />
BOM_COST_GROUP=CPU & CHIPSET<br />
TBD<br />
SKL-ULT-2+3E<br />
BGA<br />
OMIT_TABLE<br />
U0500<br />
F8<br />
G5<br />
G6<br />
G10<br />
G22<br />
G43<br />
G45<br />
G48<br />
G52<br />
G55<br />
G58<br />
G60<br />
G63<br />
G66<br />
H15<br />
H18<br />
H71<br />
J8<br />
J11<br />
J13<br />
J25<br />
J28<br />
J32<br />
J35<br />
J38<br />
J42<br />
K16<br />
K18<br />
K22<br />
K61<br />
K63<br />
K64<br />
K65<br />
K66<br />
K67<br />
K68<br />
K70<br />
K71<br />
L2<br />
L4<br />
L8<br />
L11<br />
L16<br />
L17<br />
L18<br />
L20<br />
N6<br />
N10<br />
N13<br />
N19<br />
N21<br />
N65<br />
N68<br />
P17<br />
P19<br />
P20<br />
P21<br />
R6<br />
R13<br />
T2<br />
T4<br />
T15<br />
T17<br />
T18<br />
T21<br />
U10<br />
U63<br />
U64<br />
U66<br />
U67<br />
U69<br />
U70<br />
V16<br />
V17<br />
V18<br />
W6<br />
W9<br />
W13<br />
Y17<br />
Y19<br />
Y20<br />
Y21<br />
SKL-ULT-2+3E<br />
TBD<br />
BGA<br />
OMIT_TABLE<br />
U0500<br />
AT63<br />
AT68<br />
AT71<br />
AU10<br />
AU15<br />
AU20<br />
AU32<br />
AU38<br />
AV1<br />
AV68<br />
AV69<br />
AV70<br />
AV71<br />
AW6<br />
AW8<br />
AW10<br />
AW12<br />
AW14<br />
AW16<br />
AW18<br />
AW21<br />
AW23<br />
AW26<br />
AW28<br />
AW30<br />
AW32<br />
AW34<br />
AW36<br />
AW38<br />
AW41<br />
AW43<br />
AW45<br />
AW47<br />
AW49<br />
AW51<br />
AW53<br />
AW55<br />
AW57<br />
AW60<br />
AW62<br />
AW64<br />
AW66<br />
AY66<br />
B10<br />
B14<br />
B18<br />
B22<br />
B30<br />
B34<br />
B39<br />
B44<br />
B48<br />
B53<br />
B58<br />
B62<br />
B66<br />
B71<br />
BA1<br />
BA2<br />
BA6<br />
BA10<br />
BA14<br />
BA18<br />
BA23<br />
BA28<br />
BA32<br />
BA36<br />
BA41<br />
BA45<br />
BA49<br />
BA53<br />
BA57<br />
BA62<br />
BA66<br />
BA71<br />
BB6<br />
BB18<br />
BB26<br />
BB30<br />
BB34<br />
BB38<br />
BB43<br />
BB55<br />
BB60<br />
BB64<br />
BB67<br />
BB70<br />
C1<br />
C5<br />
C25<br />
D6<br />
D10<br />
D11<br />
D14<br />
D18<br />
D22<br />
D25<br />
D26<br />
D30<br />
D34<br />
D39<br />
D44<br />
D45<br />
D47<br />
D48<br />
D53<br />
D58<br />
D62<br />
D66<br />
D69<br />
E6<br />
E11<br />
E15<br />
E18<br />
E21<br />
E46<br />
E50<br />
E53<br />
E56<br />
E65<br />
E71<br />
F1<br />
F2<br />
F4<br />
F13<br />
F22<br />
F23<br />
F27<br />
F28<br />
F32<br />
F33<br />
F35<br />
F37<br />
F38<br />
F40<br />
F42<br />
F68<br />
TBD<br />
BGA<br />
SKL-ULT-2+3E<br />
OMIT_TABLE<br />
U0500<br />
A5<br />
A67<br />
A70<br />
AA2<br />
AA4<br />
AA65<br />
AA68<br />
AB8<br />
AB15<br />
AB16<br />
AB18<br />
AB21<br />
AD8<br />
AD13<br />
AD16<br />
AD19<br />
AD20<br />
AD21<br />
AD62<br />
AE64<br />
AE65<br />
AE66<br />
AE67<br />
AE68<br />
AE69<br />
AF1<br />
AF2<br />
AF4<br />
AF10<br />
AF15<br />
AF17<br />
AF63<br />
AG16<br />
AG17<br />
AG18<br />
AG19<br />
AG20<br />
AG21<br />
AG71<br />
AH6<br />
AH13<br />
AH63<br />
AH64<br />
AH67<br />
AJ4<br />
AJ15<br />
AJ18<br />
AJ20<br />
AK8<br />
AK11<br />
AK16<br />
AK18<br />
AK21<br />
AK22<br />
AK27<br />
AK63<br />
AK68<br />
AK69<br />
AL2<br />
AL4<br />
AL28<br />
AL32<br />
AL35<br />
AL38<br />
AL45<br />
AL48<br />
AL52<br />
AL55<br />
AL58<br />
AL64<br />
AL65<br />
AL66<br />
AM8<br />
AM13<br />
AM21<br />
AM25<br />
AM27<br />
AM43<br />
AM45<br />
AM46<br />
AM55<br />
AM60<br />
AM61<br />
AM68<br />
AM71<br />
AN20<br />
AN23<br />
AN28<br />
AN30<br />
AN32<br />
AN33<br />
AN35<br />
AN37<br />
AN38<br />
AN40<br />
AN42<br />
AN58<br />
AN63<br />
AP10<br />
AP18<br />
AP20<br />
AP23<br />
AP28<br />
AP32<br />
AP35<br />
AP38<br />
AP42<br />
AP58<br />
AP63<br />
AP68<br />
AP70<br />
AR5<br />
AR8<br />
AR11<br />
AR15<br />
AR16<br />
AR20<br />
AR23<br />
AR28<br />
AR35<br />
AR42<br />
AR43<br />
AR45<br />
AR46<br />
AR48<br />
AR50<br />
AR52<br />
AR53<br />
AR55<br />
AR58<br />
AR63<br />
AT2<br />
AT4<br />
AT20<br />
AT23<br />
AT28<br />
AT35<br />
AT42<br />
AT56<br />
AT58<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
3<br />
6<br />
BRANCH<br />
REVISION<br />
DRAWING NUMBER<br />
SIZE<br />
D<br />
R<br />
IV ALL RIGHTS RESERVED<br />
SHEET<br />
PAGE TITLE<br />
C<br />
A<br />
D<br />
2 1<br />
PAGE<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
A<br />
B<br />
C<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
D<br />
B<br />
8 7 5 4 2 1<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
Apple Inc.<br />
GND 3<br />
SYM 18 OF 20<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
GND2<br />
SYM 17 OF 20<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
SYM 16 OF 20<br />
GND1<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
<br />
<br />
051-00777
Primary<br />
Backside<br />
dvt-fab09-0<br />
9.0.0<br />
10 OF 145<br />
10 OF 119<br />
PPVCCEDRAM_S0_CPU<br />
100<br />
PP1V2_S3_CPUDDR<br />
100<br />
6 PP1V0_S3<br />
8<br />
14<br />
19<br />
101<br />
8 PP1V2_S0SW<br />
100<br />
PP1V0_S3<br />
8<br />
101 PP1V0_S0SW<br />
6<br />
8<br />
17<br />
101<br />
PP1V2_S3_CPUDDR<br />
100<br />
PPVCCIO_S0_CPU<br />
100<br />
PPVCCEDRAM_S0_CPU<br />
100<br />
PPVCC_S0_CPU<br />
100<br />
PPVCCSA_S0_CPU<br />
100<br />
CPU Core Decoupling<br />
BOM_COST_GROUP=CPU & CHIPSET<br />
SYNC_MASTER=J79_JSHAO<br />
SYNC_DATE=08/28/2015<br />
20UF<br />
20%<br />
X6S-CERM<br />
0402-1<br />
2.5V<br />
C1094<br />
1<br />
2<br />
1UF<br />
0201<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C10F3<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C10F2<br />
1<br />
2<br />
X6S-CERM<br />
0201<br />
1UF<br />
20%<br />
6.3V<br />
C10F1<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C10F0<br />
1<br />
2<br />
2.5V<br />
X6S-CERM<br />
0402-1<br />
20UF<br />
20%<br />
C10E1<br />
1<br />
2<br />
X6S-CERM<br />
20UF<br />
2.5V<br />
0402-1<br />
20%<br />
C10E0<br />
1<br />
2<br />
X6S-CERM<br />
0201<br />
1UF<br />
20%<br />
6.3V<br />
C10D1<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C10D2<br />
1<br />
2<br />
1UF<br />
X6S-CERM<br />
6.3V<br />
0201<br />
20%<br />
C10D3<br />
1<br />
2<br />
2.5V<br />
0402-1<br />
20UF<br />
X6S-CERM<br />
20%<br />
C10D0<br />
1<br />
2<br />
6.3V<br />
X6S-CERM<br />
1UF<br />
0201<br />
20%<br />
C10D4<br />
1<br />
2 X6S-CERM<br />
6.3V<br />
1UF<br />
0201<br />
20%<br />
C10D5<br />
1<br />
2<br />
1UF<br />
20%<br />
6.3V<br />
0201<br />
X6S-CERM<br />
C10D6<br />
1<br />
2<br />
2.5V<br />
X6S-CERM<br />
0402-1<br />
20UF<br />
20%<br />
C1091<br />
1<br />
2<br />
0402-1<br />
X6S-CERM<br />
2.5V<br />
20UF<br />
20%<br />
C1092<br />
1<br />
2<br />
2.5V<br />
0402-1<br />
20%<br />
X6S-CERM<br />
20UF<br />
C1093<br />
1<br />
2<br />
0402-1<br />
2.5V<br />
X6S-CERM<br />
20UF<br />
20%<br />
C1090<br />
1<br />
2<br />
2.5V<br />
X6S-CERM<br />
20UF<br />
20%<br />
0402-1<br />
C1080<br />
1<br />
2 X6S-CERM<br />
2.5V<br />
0402-1<br />
20UF<br />
20%<br />
C1081<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C1082<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C1083<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C1084<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C1085<br />
1<br />
2<br />
20%<br />
2.5V<br />
X6S-CERM<br />
0402-1<br />
20UF<br />
C1070<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
6.3V<br />
20%<br />
C1071<br />
1<br />
2<br />
2.5V<br />
X6S-CERM<br />
0402-1<br />
20UF<br />
20%<br />
C1066<br />
1<br />
2<br />
2.5V<br />
X6S-CERM<br />
0402-1<br />
20UF<br />
20%<br />
C1065<br />
1<br />
2<br />
2.5V<br />
X6S-CERM<br />
0402-1<br />
20UF<br />
20%<br />
C1064<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C1055<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C1054<br />
1<br />
2<br />
2.5V<br />
X6S-CERM<br />
0402-1<br />
20UF<br />
20%<br />
C1063<br />
1<br />
2<br />
X6S-CERM<br />
2.5V<br />
0402-1<br />
20UF<br />
20%<br />
C1062<br />
1<br />
2<br />
2.5V<br />
X6S-CERM<br />
0402-1<br />
20UF<br />
20%<br />
C1060<br />
1<br />
2<br />
0402-1<br />
20%<br />
X6S-CERM<br />
2.5V<br />
20UF<br />
C1061<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C1053<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C1052<br />
1<br />
2<br />
2.5V<br />
X6S-CERM<br />
0402-1<br />
20UF<br />
20%<br />
C1051<br />
1<br />
2<br />
20UF<br />
X6S-CERM<br />
0402-1<br />
2.5V<br />
20%<br />
C1050<br />
1<br />
2<br />
220UF<br />
20%<br />
2V<br />
ELEC<br />
SM-COMBO<br />
C10G1<br />
1<br />
2<br />
3<br />
220UF<br />
2V<br />
ELEC<br />
SM-COMBO<br />
20%<br />
C10G0<br />
1<br />
2<br />
3<br />
0402-1<br />
X6S-CERM<br />
2.5V<br />
20%<br />
20UF<br />
NOSTUFF<br />
C1010<br />
1<br />
2<br />
0201<br />
X6S-CERM<br />
1UF<br />
20%<br />
6.3V<br />
C100I<br />
1<br />
2<br />
6.3V<br />
0201<br />
X6S-CERM<br />
20%<br />
1UF<br />
C100J<br />
1<br />
2<br />
0201<br />
1UF<br />
20%<br />
6.3V<br />
X6S-CERM<br />
C100K<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C100L<br />
1<br />
2<br />
0201<br />
1UF<br />
20%<br />
6.3V<br />
X6S-CERM<br />
C100M<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C100N<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C100O<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C100P<br />
1<br />
2<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
0201<br />
C100Q<br />
1<br />
2<br />
1UF<br />
20%<br />
6.3V<br />
X6S-CERM<br />
0201<br />
C100R<br />
1<br />
2<br />
20%<br />
6.3V<br />
X6S-CERM<br />
0201<br />
1UF<br />
C100S<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C100T<br />
1<br />
2<br />
20%<br />
1UF<br />
6.3V<br />
0201<br />
X6S-CERM<br />
C100U<br />
1<br />
2<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
0201<br />
C100V<br />
1<br />
2<br />
0201<br />
1UF<br />
20%<br />
6.3V<br />
X6S-CERM<br />
C100W<br />
1<br />
2 X6S-CERM<br />
0201<br />
1UF<br />
20%<br />
6.3V<br />
C100X<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C100Y<br />
1<br />
2<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
0201<br />
C100C<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C100D<br />
1<br />
2<br />
0201<br />
X6S-CERM<br />
20%<br />
6.3V<br />
1UF<br />
C100E<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C100F<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C100G<br />
1<br />
2<br />
0201<br />
6.3V<br />
X6S-CERM<br />
1UF<br />
20%<br />
C100H<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C1006<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C1007<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C1008<br />
1<br />
2<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
0201<br />
C1009<br />
1<br />
2<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
0201<br />
C100A<br />
1<br />
2<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
0201<br />
C100B<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C1005<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C1004<br />
1<br />
2<br />
X6S-CERM<br />
0201<br />
1UF<br />
20%<br />
6.3V<br />
C1003<br />
1<br />
2<br />
1UF<br />
0201<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C1002<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C1001<br />
1<br />
2<br />
0201<br />
X6S-CERM<br />
20%<br />
6.3V<br />
1UF<br />
C1000<br />
1<br />
2<br />
220UF<br />
20%<br />
2V<br />
ELEC<br />
SM-COMBO<br />
C10H1<br />
1<br />
2<br />
3<br />
20%<br />
2V<br />
ELEC<br />
SM-COMBO<br />
220UF<br />
C10H0<br />
1<br />
2<br />
3<br />
2.5V<br />
X6S-CERM<br />
20%<br />
20UF<br />
0402-1<br />
NOSTUFF<br />
C10C0<br />
1<br />
2<br />
20%<br />
20UF<br />
2.5V<br />
NOSTUFF<br />
X6S-CERM<br />
0402-1<br />
C10C1<br />
1<br />
2 X6S-CERM<br />
0402-1<br />
2.5V<br />
20%<br />
NOSTUFF<br />
20UF<br />
C10C2<br />
1<br />
2<br />
20UF<br />
0402-1<br />
2.5V<br />
X6S-CERM<br />
20%<br />
NOSTUFF<br />
C10C3<br />
1<br />
2<br />
20UF<br />
0402-1<br />
2.5V<br />
X6S-CERM<br />
20%<br />
NOSTUFF<br />
C10C4<br />
1<br />
2<br />
20UF<br />
0402-1<br />
2.5V<br />
X6S-CERM<br />
20%<br />
NOSTUFF<br />
C10C5<br />
1<br />
2<br />
2.5V<br />
0402-1<br />
20UF<br />
X6S-CERM<br />
20%<br />
C10B5<br />
1<br />
2<br />
2.5V<br />
0402-1<br />
20UF<br />
X6S-CERM<br />
20%<br />
C10B4<br />
1<br />
2<br />
20UF<br />
2.5V<br />
0402-1<br />
X6S-CERM<br />
20%<br />
NOSTUFF<br />
C10B3<br />
1<br />
2<br />
20UF<br />
20%<br />
2.5V<br />
X6S-CERM<br />
0402-1<br />
NOSTUFF<br />
C10B2<br />
1<br />
2<br />
20UF<br />
2.5V<br />
0402-1<br />
X6S-CERM<br />
20%<br />
C10B1<br />
1<br />
2<br />
1UF<br />
20%<br />
6.3V<br />
X6S-CERM<br />
0201<br />
C10A0<br />
1<br />
2<br />
1UF<br />
0201<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C10A1<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
6.3V<br />
20%<br />
C10A2<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C10A3<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C10A4<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C10A5<br />
1<br />
2<br />
0201<br />
1UF<br />
X6S-CERM<br />
20%<br />
6.3V<br />
C10A6<br />
1<br />
2<br />
2.5V<br />
20UF<br />
20%<br />
X6S-CERM<br />
0402-1<br />
C10B0<br />
1<br />
2<br />
20UF<br />
20%<br />
0402-1<br />
X6S-CERM<br />
2.5V<br />
C1020<br />
1<br />
2<br />
0402-1<br />
X6S-CERM<br />
20%<br />
2.5V<br />
20UF<br />
C1021<br />
1<br />
2<br />
20%<br />
2.5V<br />
0402-1<br />
X6S-CERM<br />
20UF<br />
C1022<br />
1<br />
2<br />
2.5V<br />
0402-1<br />
20%<br />
X6S-CERM<br />
20UF<br />
C1023<br />
1<br />
2<br />
2.5V<br />
20UF<br />
X6S-CERM<br />
20%<br />
0402-1<br />
C1024<br />
1<br />
2<br />
2.5V<br />
0402-1<br />
20UF<br />
X6S-CERM<br />
20%<br />
C1029<br />
1<br />
2<br />
20%<br />
2.5V<br />
0402-1<br />
20UF<br />
X6S-CERM<br />
C1028<br />
1<br />
2<br />
20UF<br />
2.5V<br />
0402-1<br />
20%<br />
X6S-CERM<br />
C1027<br />
1<br />
2<br />
20UF<br />
2.5V<br />
0402-1<br />
20%<br />
X6S-CERM<br />
C1026<br />
1<br />
2<br />
20UF<br />
2.5V<br />
0402-1<br />
X6S-CERM<br />
20%<br />
C1025<br />
1<br />
2<br />
20UF<br />
0402-1<br />
2.5V<br />
20%<br />
X6S-CERM<br />
C1015<br />
1<br />
2<br />
0402-1<br />
2.5V<br />
X6S-CERM<br />
20%<br />
20UF<br />
NOSTUFF<br />
C1016<br />
1<br />
2<br />
0402-1<br />
20UF<br />
2.5V<br />
20%<br />
X6S-CERM<br />
C1017<br />
1<br />
2<br />
0402-1<br />
X6S-CERM<br />
20UF<br />
2.5V<br />
20%<br />
NOSTUFF<br />
C1018<br />
1<br />
2<br />
20UF<br />
0402-1<br />
2.5V<br />
X6S-CERM<br />
20%<br />
NOSTUFF<br />
C1019<br />
1<br />
2<br />
20UF<br />
20%<br />
X6S-CERM<br />
0402-1<br />
2.5V<br />
C1014<br />
1<br />
2<br />
0402-1<br />
2.5V<br />
X6S-CERM<br />
20%<br />
20UF<br />
C1013<br />
1<br />
2<br />
X6S-CERM<br />
0402-1<br />
20UF<br />
20%<br />
2.5V<br />
C1012<br />
1<br />
2<br />
X6S-CERM<br />
2.5V<br />
20%<br />
20UF<br />
0402-1<br />
C1011<br />
1<br />
2<br />
220UF<br />
20%<br />
2V<br />
ELEC<br />
SM-COMBO<br />
C10G3<br />
1<br />
2<br />
3<br />
2.5V<br />
X6S-CERM<br />
0402-1<br />
20UF<br />
20%<br />
C1095<br />
1<br />
2<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
3<br />
6<br />
BRANCH<br />
REVISION<br />
DRAWING NUMBER<br />
SIZE<br />
D<br />
R<br />
IV ALL RIGHTS RESERVED<br />
SHEET<br />
PAGE TITLE<br />
C<br />
A<br />
D<br />
2 1<br />
PAGE<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
A<br />
B<br />
C<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
D<br />
B<br />
8 7 5 4 2 1<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
Apple Inc.<br />
<br />
<br />
051-00777
dvt-fab09-0<br />
9.0.0<br />
11 OF 145<br />
11 OF 119<br />
PPVCCGT_S0_CPU<br />
100<br />
PPVCCGT_S0_CPU<br />
100<br />
CPU GT Decoupling<br />
BOM_COST_GROUP=CPU & CHIPSET<br />
SYNC_MASTER=J79_JSHAO<br />
SYNC_DATE=08/28/2015<br />
6.3V<br />
20%<br />
1UF<br />
0201<br />
X6S-CERM<br />
C110L<br />
1<br />
2<br />
6.3V<br />
20%<br />
1UF<br />
0201<br />
X6S-CERM<br />
C110K<br />
1<br />
2<br />
6.3V<br />
1UF<br />
0201<br />
X6S-CERM<br />
20%<br />
C1105<br />
1<br />
2<br />
0201<br />
20%<br />
1UF<br />
X6S-CERM<br />
6.3V<br />
C110J<br />
1<br />
2<br />
6.3V<br />
20%<br />
X6S-CERM<br />
0201<br />
1UF<br />
C1104<br />
1<br />
2<br />
0201<br />
X6S-CERM<br />
6.3V<br />
20%<br />
1UF<br />
C110I<br />
1<br />
2<br />
1UF<br />
6.3V<br />
20%<br />
0201<br />
X6S-CERM<br />
C1103<br />
1<br />
2<br />
X6S-CERM<br />
6.3V<br />
20%<br />
1UF<br />
0201<br />
C110H<br />
1<br />
2<br />
6.3V<br />
X6S-CERM<br />
20%<br />
1UF<br />
0201<br />
C1102<br />
1<br />
2<br />
6.3V<br />
20%<br />
1UF<br />
0201<br />
X6S-CERM<br />
C110G<br />
1<br />
2<br />
1UF<br />
X6S-CERM<br />
6.3V<br />
0201<br />
20%<br />
C1101<br />
1<br />
2<br />
X6S-CERM<br />
0201<br />
6.3V<br />
20%<br />
1UF<br />
C110F<br />
1<br />
2<br />
X6S-CERM<br />
6.3V<br />
20%<br />
1UF<br />
0201<br />
C1100<br />
1<br />
2<br />
1UF<br />
X6S-CERM<br />
6.3V<br />
20%<br />
0201<br />
C110E<br />
1<br />
2<br />
NOSTUFF<br />
2.0V<br />
20%<br />
220UF<br />
POLY-TANT<br />
D15T-D1L-COMBO<br />
C1161<br />
1<br />
2<br />
3<br />
220UF<br />
20%<br />
2V<br />
ELEC<br />
SM-COMBO<br />
C1164<br />
1<br />
2<br />
3<br />
20%<br />
220UF<br />
2V<br />
ELEC<br />
SM-COMBO<br />
C1191<br />
1<br />
2<br />
3<br />
NOSTUFF<br />
20%<br />
2.5V<br />
0402-1<br />
20UF<br />
X6S-CERM<br />
C1180<br />
1<br />
2<br />
NOSTUFF<br />
20%<br />
2.5V<br />
0402-1<br />
20UF<br />
X6S-CERM<br />
C1181<br />
1<br />
2<br />
NOSTUFF<br />
20%<br />
2.5V<br />
0402-1<br />
20UF<br />
X6S-CERM<br />
C1182<br />
1<br />
2<br />
NOSTUFF<br />
20%<br />
2.5V<br />
0402-1<br />
20UF<br />
X6S-CERM<br />
C1183<br />
1<br />
2<br />
20%<br />
2.5V<br />
0402-1<br />
20UF<br />
X6S-CERM<br />
C1184<br />
1<br />
2<br />
NOSTUFF<br />
20%<br />
2.5V<br />
0402-1<br />
20UF<br />
X6S-CERM<br />
C1185<br />
1<br />
2<br />
NOSTUFF<br />
20%<br />
2.5V<br />
0402-1<br />
20UF<br />
X6S-CERM<br />
C1186<br />
1<br />
2<br />
20%<br />
2.5V<br />
0402-1<br />
20UF<br />
X6S-CERM<br />
C1187<br />
1<br />
2<br />
20%<br />
X6S-CERM<br />
20UF<br />
0402-1<br />
2.5V<br />
C1177<br />
1<br />
2<br />
20%<br />
X6S-CERM<br />
20UF<br />
0402-1<br />
2.5V<br />
C1176<br />
1<br />
2<br />
20%<br />
X6S-CERM<br />
20UF<br />
0402-1<br />
2.5V<br />
C1175<br />
1<br />
2<br />
20%<br />
X6S-CERM<br />
20UF<br />
0402-1<br />
2.5V<br />
C1174<br />
1<br />
2<br />
20%<br />
X6S-CERM<br />
20UF<br />
0402-1<br />
2.5V<br />
C1173<br />
1<br />
2<br />
20%<br />
X6S-CERM<br />
20UF<br />
0402-1<br />
2.5V<br />
C1172<br />
1<br />
2<br />
20%<br />
X6S-CERM<br />
20UF<br />
0402-1<br />
2.5V<br />
C1171<br />
1<br />
2<br />
20%<br />
X6S-CERM<br />
20UF<br />
0402-1<br />
2.5V<br />
C1170<br />
1<br />
2<br />
20%<br />
X6S-CERM<br />
20UF<br />
0402-1<br />
2.5V<br />
NOSTUFF<br />
C1120<br />
1<br />
2<br />
20%<br />
NOSTUFF<br />
2.5V<br />
0402-1<br />
20UF<br />
X6S-CERM<br />
C1121<br />
1<br />
2<br />
2.5V<br />
20UF<br />
20%<br />
X6S-CERM<br />
0402-1<br />
NOSTUFF<br />
C1122<br />
1<br />
2<br />
20%<br />
2.5V<br />
0402-1<br />
20UF<br />
X6S-CERM<br />
NOSTUFF<br />
C1123<br />
1<br />
2<br />
20UF<br />
X6S-CERM<br />
0402-1<br />
20%<br />
2.5V<br />
C1124<br />
1<br />
2<br />
20%<br />
2.5V<br />
0402-1<br />
20UF<br />
X6S-CERM<br />
C1129<br />
1<br />
2<br />
X6S-CERM<br />
20%<br />
20UF<br />
2.5V<br />
0402-1<br />
C1128<br />
1<br />
2<br />
X6S-CERM<br />
20%<br />
2.5V<br />
0402-1<br />
20UF<br />
C1127<br />
1<br />
2<br />
20%<br />
2.5V<br />
0402-1<br />
20UF<br />
X6S-CERM<br />
C1126<br />
1<br />
2<br />
20%<br />
2.5V<br />
0402-1<br />
20UF<br />
X6S-CERM<br />
C1125<br />
1<br />
2<br />
NOSTUFF<br />
20UF<br />
0402-1<br />
20%<br />
X6S-CERM<br />
2.5V<br />
C1115<br />
1<br />
2<br />
20%<br />
X6S-CERM<br />
20UF<br />
0402-1<br />
2.5V<br />
C1116<br />
1<br />
2<br />
20%<br />
20UF<br />
0402-1<br />
X6S-CERM<br />
2.5V<br />
C1117<br />
1<br />
2<br />
0402-1<br />
X6S-CERM<br />
2.5V<br />
20%<br />
20UF<br />
C1118<br />
1<br />
2<br />
NOSTUFF<br />
20%<br />
20UF<br />
0402-1<br />
2.5V<br />
X6S-CERM<br />
C1119<br />
1<br />
2<br />
NOSTUFF<br />
2.5V<br />
20%<br />
20UF<br />
0402-1<br />
X6S-CERM<br />
C1114<br />
1<br />
2<br />
0402-1<br />
2.5V<br />
X6S-CERM<br />
20%<br />
20UF<br />
NOSTUFF<br />
C1113<br />
1<br />
2<br />
X6S-CERM<br />
0402-1<br />
2.5V<br />
20%<br />
20UF<br />
C1112<br />
1<br />
2<br />
20%<br />
0402-1<br />
X6S-CERM<br />
20UF<br />
2.5V<br />
C1111<br />
1<br />
2<br />
20%<br />
X6S-CERM<br />
20UF<br />
0402-1<br />
2.5V<br />
C1110<br />
1<br />
2<br />
20%<br />
220UF<br />
2V<br />
ELEC<br />
SM-COMBO<br />
C1190<br />
1<br />
2<br />
3<br />
20%<br />
220UF<br />
2V<br />
ELEC<br />
SM-COMBO<br />
C1163<br />
1<br />
2<br />
3<br />
220UF<br />
20%<br />
2V<br />
ELEC<br />
SM-COMBO<br />
C1162<br />
1<br />
2<br />
3<br />
6.3V<br />
20%<br />
1UF<br />
0201<br />
X6S-CERM<br />
C110V<br />
1<br />
2<br />
6.3V<br />
20%<br />
1UF<br />
0201<br />
X6S-CERM<br />
C110W<br />
1<br />
2<br />
0201<br />
6.3V<br />
X6S-CERM<br />
1UF<br />
20%<br />
C110X<br />
1<br />
2<br />
6.3V<br />
20%<br />
1UF<br />
0201<br />
X6S-CERM<br />
C110U<br />
1<br />
2<br />
6.3V<br />
20%<br />
1UF<br />
0201<br />
X6S-CERM<br />
C110T<br />
1<br />
2<br />
6.3V<br />
20%<br />
1UF<br />
0201<br />
X6S-CERM<br />
C110S<br />
1<br />
2<br />
6.3V<br />
20%<br />
1UF<br />
0201<br />
X6S-CERM<br />
C110D<br />
1<br />
2<br />
6.3V<br />
20%<br />
1UF<br />
0201<br />
X6S-CERM<br />
C110C<br />
1<br />
2<br />
6.3V<br />
20%<br />
1UF<br />
0201<br />
X6S-CERM<br />
C110R<br />
1<br />
2<br />
6.3V<br />
20%<br />
1UF<br />
0201<br />
X6S-CERM<br />
C110Q<br />
1<br />
2<br />
6.3V<br />
20%<br />
1UF<br />
0201<br />
X6S-CERM<br />
C110B<br />
1<br />
2<br />
6.3V<br />
20%<br />
1UF<br />
0201<br />
X6S-CERM<br />
C110A<br />
1<br />
2<br />
6.3V<br />
20%<br />
1UF<br />
0201<br />
X6S-CERM<br />
C110P<br />
1<br />
2<br />
6.3V<br />
X6S-CERM<br />
0201<br />
1UF<br />
20%<br />
C110O<br />
1<br />
2<br />
6.3V<br />
20%<br />
1UF<br />
0201<br />
X6S-CERM<br />
C1109<br />
1<br />
2<br />
20%<br />
1UF<br />
0201<br />
X6S-CERM<br />
6.3V<br />
C1108<br />
1<br />
2<br />
6.3V<br />
20%<br />
1UF<br />
0201<br />
X6S-CERM<br />
C110N<br />
1<br />
2<br />
6.3V<br />
20%<br />
1UF<br />
0201<br />
X6S-CERM<br />
C110M<br />
1<br />
2<br />
20%<br />
1UF<br />
0201<br />
X6S-CERM<br />
6.3V<br />
C1107<br />
1<br />
2<br />
6.3V<br />
20%<br />
1UF<br />
0201<br />
X6S-CERM<br />
C1106<br />
1<br />
2<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
3<br />
6<br />
BRANCH<br />
REVISION<br />
DRAWING NUMBER<br />
SIZE<br />
D<br />
R<br />
IV ALL RIGHTS RESERVED<br />
SHEET<br />
PAGE TITLE<br />
C<br />
A<br />
D<br />
2 1<br />
PAGE<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
A<br />
B<br />
C<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
D<br />
B<br />
8 7 5 4 2 1<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
Apple Inc.<br />
<br />
<br />
051-00777
SYNC_MASTER=J79_JSHAO<br />
SYNC_DATE=03/14/2016<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
78 8<br />
PP1V0_SUSFUSE<br />
BYPASS=U0500.AK20::10MM<br />
1<br />
2<br />
C1208<br />
1000PF<br />
10%<br />
25V<br />
X7R<br />
0201<br />
RAIL SIDE<br />
FILTER PLACEHOLDERS ONLY<br />
PCH SIDE<br />
D<br />
101<br />
101<br />
8<br />
8<br />
PP1V0_SUS<br />
PP1V0_SUS<br />
BYPASS=U0500.AB19::10MM<br />
1<br />
2<br />
C1200<br />
1000PF<br />
10%<br />
25V<br />
X7R<br />
0201<br />
101<br />
101<br />
8<br />
5<br />
8<br />
PP3V3_SUS<br />
PP3V3_SUS<br />
BYPASS=U0500.T16::3MM<br />
1<br />
2<br />
C1220<br />
1000PF<br />
10%<br />
25V<br />
X7R<br />
0201<br />
101<br />
PP1V0_SUSSW<br />
1<br />
2<br />
C1204<br />
1UF<br />
20%<br />
6.3V<br />
X6S-CERM<br />
0201<br />
OMIT_TABLE<br />
L1250<br />
2.2UH-240MA-0.221OHM<br />
1 2<br />
0603<br />
1<br />
CRITICAL<br />
NOSTUFF<br />
C1250<br />
47UF<br />
20% BYPASS=U0500.K15::3MM<br />
2 6.3V<br />
POLY-TANT<br />
0805<br />
MAKE_BASE=TRUE<br />
PP1V_SUSSW_PCH_VCCAMPHYPLL_F 8<br />
PP1V_SUSSW_PCH_VCCAMPHYPLL_F<br />
19<br />
D<br />
BYPASS=U0500.K17::3MM<br />
1<br />
2<br />
C1201<br />
1UF<br />
20%<br />
6.3V<br />
X6S-CERM<br />
0201<br />
BYPASS=U0500.AK17::3MM<br />
1<br />
2<br />
C1221<br />
1UF<br />
20%<br />
6.3V<br />
X6S-CERM<br />
0201<br />
1<br />
2<br />
C1222<br />
0.1UF<br />
10%<br />
10V<br />
X5R-CERM BYPASS=U0500.AK17::3MM<br />
0201<br />
C<br />
101<br />
101<br />
101<br />
8<br />
8<br />
8<br />
PP1V0_SUSSW<br />
BYPASS=U0500.N15::3MM<br />
PP1V0_SUSSW<br />
BYPASS=U0500.AF20::10MM<br />
PP1V0_SUSSW<br />
BYPASS=U0500.N18::3MM<br />
1<br />
2<br />
1<br />
2<br />
1<br />
2<br />
C1202<br />
1UF<br />
20%<br />
6.3V<br />
X6S-CERM<br />
0201<br />
C1205<br />
1000PF<br />
10%<br />
25V<br />
X7R<br />
0201<br />
C1206<br />
1UF<br />
20%<br />
6.3V<br />
X6S-CERM<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
NOSTUFF<br />
C1203<br />
47UF<br />
101 8<br />
20%<br />
6.3V BYPASS=U0500.N15::10MM<br />
POLY-TANT<br />
0805<br />
101 8<br />
101 8<br />
100 15 14 8<br />
PP3V3_SUS<br />
PP3V3_SUS<br />
PP3V3_SUS<br />
PP3V0_G3H<br />
BYPASS=U0500.AG15::3MM<br />
BYPASS=U0500.V19::10MM<br />
BYPASS=U0500.Y16::10MM<br />
BYPASS=U0500.AK19::3MM<br />
1<br />
2<br />
1<br />
2<br />
1<br />
2<br />
1<br />
2<br />
C1223<br />
1000PF<br />
10%<br />
25V<br />
X7R<br />
0201<br />
C1224<br />
1000PF<br />
10%<br />
25V<br />
X7R<br />
0201<br />
C1225<br />
1000PF<br />
10%<br />
25V<br />
X7R<br />
0201<br />
C1227<br />
1UF<br />
20%<br />
6.3V<br />
X6S-CERM<br />
0201<br />
1<br />
2<br />
C1228<br />
0.1UF<br />
10%<br />
10V<br />
X5R-CERM BYPASS=U0500.AK19::3MM<br />
0201<br />
2.2UH-240MA-0.221OHM<br />
101 PP1V0_SUS<br />
1 2 CRITICAL<br />
0603<br />
NOSTUFF<br />
PP1V_SUS_PCH_VCCCLK5_F 8<br />
PP1V_SUS_PCH_VCCCLK5_F<br />
101<br />
101<br />
PP1V0_SUS<br />
PP1V0_SUS<br />
OMIT_TABLE<br />
L1252<br />
OMIT_TABLE<br />
L1253<br />
2.2UH-240MA-0.221OHM<br />
1 2 CRITICAL<br />
0603<br />
NOSTUFF<br />
OMIT_TABLE<br />
L1254<br />
2.2UH-240MA-0.221OHM<br />
1 2<br />
0603<br />
1<br />
1<br />
1<br />
C1252<br />
47UF<br />
20%<br />
2 6.3V<br />
POLY-TANT<br />
0805<br />
C1253<br />
47UF<br />
20%<br />
2 6.3V<br />
POLY-TANT<br />
0805<br />
CRITICAL<br />
NOSTUFF<br />
C1254<br />
47UF<br />
20%<br />
2 6.3V<br />
POLY-TANT<br />
0805<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
PP1V_SUS_PCH_VCCCLK4_F 8<br />
PP1V_SUS_PCH_VCCCLK4_F<br />
PP1V_SUS_PCH_VCCCLK2_F 8<br />
PP1V_SUS_PCH_VCCCLK2_F<br />
19<br />
19<br />
19<br />
C<br />
B<br />
100<br />
55<br />
8<br />
PPVCCPRIMCORE_SUS_PCH<br />
BYPASS=U0500.AF18::10MM<br />
1<br />
2<br />
C1210<br />
1000PF<br />
10%<br />
25V<br />
X7R<br />
0201<br />
100<br />
8<br />
PP1V8_SUS<br />
BYPASS=U0500.AA1::10MM<br />
1<br />
2<br />
C1230<br />
1UF<br />
20%<br />
6.3V<br />
X6S-CERM<br />
0201<br />
PART NUMBER QTY DESCRIPTION<br />
REFERENCE DES CRITICAL BOM OPTION<br />
113S0022 4 RES,MF,1A MAX,0OHM,5%,0603 L1250,L1252,L1253,L1254<br />
B<br />
19 8<br />
PPDCPRTC_PCH<br />
19 8<br />
PP1V_S5_PCH_DCPDSW<br />
BYPASS=U0500.BB10::3MM<br />
1<br />
2<br />
C1231<br />
0.1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
BYPASS=U0500.AL1::3MM<br />
1<br />
2<br />
C1232<br />
1UF<br />
20%<br />
6.3V<br />
X6S-CERM<br />
0201<br />
100<br />
PP1V8_SUS<br />
NOSTUFF<br />
R1251<br />
0<br />
1 2<br />
1/20W 5%<br />
MF<br />
0201<br />
BYPASS=U0500.U11::10MM<br />
1<br />
2<br />
NOSTUFF<br />
C1251<br />
1UF<br />
20%<br />
6.3V<br />
X6S-CERM<br />
0201<br />
FOR FUTURE PRODUCT PER PDG<br />
PP1V8_SUS_PCH_VCC1P8 5<br />
PP1V8_SUS_PCH_VCC1P8 5<br />
PP1V8_SUS_PCH_VCC1P8<br />
MAKE_BASE=TRUE<br />
19<br />
100<br />
1<br />
2<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
PP1V8_S0<br />
C1264<br />
1<br />
2<br />
C1265<br />
2.9PF<br />
+/-0.05PF<br />
25V<br />
C0G-CERM<br />
0201<br />
R1260<br />
0<br />
1 2<br />
1/20W 5%<br />
MF<br />
0201<br />
C1226 1<br />
1000PF<br />
2<br />
10%<br />
25V<br />
X7R<br />
0201<br />
C1260 1<br />
2.9PF<br />
2<br />
+/-0.05PF<br />
25V<br />
C0G-CERM<br />
0201<br />
PP1V8_S0_PCH_VCCHDA_F 8<br />
PP1V8_S0_PCH_VCCHDA_F<br />
MAKE_BASE=TRUE<br />
BYPASS=U0500.AJ19::10MM<br />
19<br />
A<br />
101<br />
15<br />
PP1V0_SUS<br />
1<br />
2<br />
C1267<br />
2.9PF<br />
+/-0.05PF<br />
25V<br />
C0G-CERM<br />
0201<br />
R1261<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
BYPASS=U0500.AJ19::10MM<br />
C1261 1<br />
1000PF<br />
2<br />
10%<br />
25V<br />
X7R<br />
0201<br />
C1262 1<br />
2.9PF<br />
2<br />
+/-0.05PF<br />
25V<br />
C0G-CERM<br />
0201<br />
BYPASS=U0500.V15::10MM<br />
PP1V_SUS_PCH_VCCAPLL_F 8<br />
PP1V_SUS_PCH_VCCAPLL_F<br />
MAKE_BASE=TRUE<br />
BYPASS=U0500.V15::10MM<br />
19<br />
BOM_COST_GROUP=CPU & CHIPSET<br />
PAGE TITLE<br />
R<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
PCH Decoupling<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
IV ALL RIGHTS RESERVED<br />
Apple Inc.<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
12 OF 145<br />
12 OF 119<br />
SIZE<br />
D<br />
A<br />
8 7 6<br />
5 4 3<br />
2 1
TABLE_BOMGROUP_HEAD<br />
TABLE_BOMGROUP_ITEM<br />
SYNC_MASTER=J130_MLB<br />
SYNC_DATE=02/22/2016<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
60<br />
60<br />
60<br />
105 60<br />
60<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
OUT<br />
HDA_SYNC<br />
HDA_BIT_CLK<br />
HDA_SDOUT<br />
HDA_SDIN0<br />
HDA_RST_L<br />
PLACE_NEAR=U0500.BA22:10mm<br />
R1300 33<br />
1 2<br />
5% 1/20W<br />
PLACE_NEAR=U0500.AY22:10mm<br />
R1301 33<br />
1 2<br />
PLACE_NEAR=U0500.BB22:10mm<br />
R1302 33<br />
1 2<br />
5% 1/20W<br />
PLACE_NEAR=U0500.AW22:10mm<br />
R1303 33<br />
1 2<br />
MF 201<br />
5% 1/20W MF 201<br />
19<br />
19 18<br />
19<br />
5% 1/20W<br />
HDA_SYNC_R<br />
HDA_BIT_CLK_R<br />
HDA_SDOUT_R<br />
MF 201<br />
HDA_RST_R_L<br />
MF<br />
201<br />
17<br />
19<br />
28 13<br />
94 28 13<br />
19<br />
19<br />
19<br />
49<br />
OUT<br />
IN<br />
OUT<br />
BI<br />
IN<br />
13<br />
13<br />
IN<br />
IN<br />
IN<br />
XDP_PCH_OBSDATA_C0<br />
CKPLUS_WAIVE=CLK_DATA_CON<br />
PCH_DDPB_CTRLDATA<br />
JTAG_TBT_X_TMS<br />
JTAG_TBT_T_TMS<br />
PCH_DDPC_CTRLDATA<br />
MLB_RAMCFG0<br />
MLB_RAMCFG1<br />
NC_PCH_BSSB_CLK<br />
NC_PCH_BSSB_DATA<br />
PCH_STRP_TOPBLK_SWP_L<br />
NC<br />
NC<br />
NC<br />
BA22<br />
AY22<br />
BB22<br />
BA21<br />
AY21<br />
AW22<br />
D8<br />
AY20<br />
AW20<br />
L12<br />
L13<br />
N7<br />
N8<br />
U1<br />
U2<br />
P4<br />
P1<br />
AW5<br />
AUDIO<br />
HDA_SYNC/I2S0_SFRM<br />
HDA_BLK/I2S0_SCLK<br />
HDA_SDO/I2S0_TXD<br />
HDA_SDI0/I2S0_RXD<br />
HDA_SDI1/I2S1_RXD<br />
HDA_RST*/I2S1_SCLK<br />
GPP_D17/DMIC_CLK1<br />
I2S1_SFRM<br />
I2S1_TXD<br />
GPP_E19/DDPB_CTRLDATA<br />
GPP_E18/DDPB_CTRLCLK<br />
GPP_E20/DDPC_CTRLCLK<br />
GPP_E21/DDPC_CTRLDATA<br />
GPP_D13/ISH_UART0_RXD/<br />
SML0BDATA/I2C4B_SDA<br />
GPP_D14/ISH_UART0_TXD/<br />
SML0BCLK/I2C4B_SCL<br />
GPP_D11<br />
GPP_D12<br />
GPP_B14/SPKR<br />
(BSSB_CLK)<br />
(BSSB_DATA_IN)<br />
(STRAP)<br />
OMIT_TABLE<br />
SKL-ULT-2+3E<br />
TBD<br />
BGA<br />
SYM 7 OF 20<br />
(STRAP)<br />
(STRAP)<br />
U0500<br />
(1.8V)<br />
(1.8V)<br />
SDIO/SDXC<br />
GPP_F18/EMMC_DATA5<br />
GPP_F19/EMMC_DATA6<br />
GPP_F20/EMMC_DATA7<br />
GPP_F21/EMMC_RCLK<br />
GPP_F22/EMMC_CLK<br />
GPP_F23<br />
GPP_G0/SD_CMD<br />
GPP_G1/SD_DATA0<br />
GPP_A17/SD_PWR_EN*/ISH_GP7<br />
GPP_A16/SD_1P8_SEL<br />
SD_RCOMP<br />
GPP_F17/EMMC_DATA4<br />
AN2<br />
AM4<br />
AM1<br />
AM2<br />
AM3<br />
AF13<br />
AB11<br />
AB13<br />
BA9<br />
BB9<br />
AB7<br />
AN1<br />
SD_RCOMP<br />
ALL GPP_F* PINS ARE 1.8V ONLY!<br />
R1370 1<br />
200<br />
1%<br />
1/20W<br />
MF<br />
201 2<br />
PCH_SOC_DFU_STATUS 19 37<br />
SOC_PANIC_L 19 38<br />
SOC_S2R_ACK_L 19 38<br />
SOC_PCH_DBELL_L 19 38<br />
DEBUGUART_SEL_SOC<br />
OUT<br />
SSD_PWR_EN_L<br />
OUT<br />
TBT_X_CIO_PWR_EN<br />
OUT<br />
TBT_X_USB_PWR_EN<br />
NC_CAMERA_RESET_L<br />
CAMERA_PWR_EN<br />
PCH_SOC_WDOG<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
19<br />
91<br />
13<br />
13<br />
19<br />
19<br />
37<br />
104<br />
28<br />
28<br />
D<br />
PLACE_NEAR=U0500.AB7:12.7MM<br />
C<br />
59<br />
59<br />
59<br />
59 17<br />
59<br />
59 13<br />
19 13<br />
19 13<br />
19 13<br />
19 13<br />
48 13<br />
OUT<br />
BI<br />
BI<br />
BI<br />
BI<br />
OUT<br />
102<br />
102<br />
OUT<br />
OUT<br />
IN<br />
13<br />
13<br />
IN<br />
13<br />
IN<br />
SPI_CLK_R<br />
SPI_MISO<br />
SPI_MOSI_R<br />
SPI_IO<br />
SPI_IO<br />
SPI_CS0_R_L<br />
NC_SPI_CS1_L<br />
NC_SPI_CS2_L<br />
ALS_SOC_UART_R2D<br />
PD_LCD_PSR_EN<br />
PD_SSD_UART_CTS_L<br />
MLB_RAMCFG2<br />
MLB_RAMCFG3<br />
ALS_SOC_UART_D2R<br />
PU_PCH_RCIN_L<br />
LPC_SERIRQ<br />
NC<br />
NC<br />
NC<br />
AV2<br />
AW3<br />
AV3<br />
AW2<br />
AU4<br />
AU3<br />
AU2<br />
AU1<br />
AD2<br />
AD3<br />
AD4<br />
U3<br />
U4<br />
AD1<br />
G3<br />
G2<br />
G1<br />
AW13<br />
AY11<br />
SPI0_CLK<br />
SPI0_MISO<br />
SPI0_MOSI<br />
SPI0_IO2<br />
SPI0_IO3<br />
SPI0_CS0*<br />
SPI0_CS1*<br />
SPI0_CS2*<br />
IO1<br />
IO0<br />
GPP_C21/UART2_TXD<br />
GPP_C22/UART2_RTS*<br />
GPP_C23/UART2_CTS*<br />
GPP_D15/ISH_UART0_RTS*<br />
GPP_D16/ISH_UART0_CTS*/<br />
SML0BALERT*<br />
GPP_C20/UART2_RXD<br />
CL_CLK<br />
CL_DATA<br />
CL_RST*<br />
GPP_A0/RCIN*<br />
GPP_A6/SERIRQ<br />
OMIT_TABLE<br />
U0500<br />
SKL-ULT-2+3E<br />
TBD<br />
BGA<br />
SYM 5 OF 20<br />
SPI-FLASH<br />
SPI-TOUCH<br />
C LINK<br />
SMBUS,SMLINK<br />
(STRAP)<br />
LPC<br />
(STRAP)<br />
(STRAP)<br />
GPP_C0/SMBCLK<br />
GPP_C1/SMBDATA<br />
GPP_C2/SMBALERT*<br />
GPP_C3/SML0CLK<br />
GPP_C4/SML0DATA<br />
GPP_C5/SML0ALERT*<br />
GPP_C6/SML1CLK<br />
GPP_C7/SML1DATA<br />
GPP_B23/SML1ALERT*/PCHHOT*<br />
GPP_A1/LAD0/ESPI_IO0<br />
GPP_A2/LAD1/ESPI_IO1<br />
GPP_A3/LAD2/ESPI_IO2<br />
GPP_A4/LAD3/ESPI_IO3<br />
GPP_A5/LFRAME*/ESPI_CS*<br />
GPP_A14/SUS_STAT*/ESPI_RESET*<br />
GPP_A9/CLKOUT_LPC0/ESPI_CLK<br />
GPP_A10/CLKOUT_LPC1<br />
GPP_A8/CLKRUN*<br />
R7<br />
R8<br />
R10<br />
R9<br />
W2<br />
W1<br />
W3<br />
V3<br />
AM7<br />
AY13<br />
BA13<br />
BB13<br />
AY12<br />
BA12<br />
BA11<br />
AW9<br />
AY9<br />
AW11<br />
SMBUS_PCH_CLK<br />
SMBUS_PCH_DATA<br />
NC_PCH_STRP_TLSCONF 19<br />
SML_PCH_0_CLK<br />
SML_PCH_0_DATA<br />
NC_PCH_STRP_ESPI 19<br />
SMBUS_SMC_1_S0_SCL<br />
SMBUS_SMC_1_S0_SDA<br />
NC_PCH_STRP_BSSB_SEL_GPIO 19<br />
OUT<br />
BI<br />
OUT<br />
BI<br />
OUT<br />
BI<br />
51<br />
51<br />
51<br />
51<br />
51<br />
51<br />
R1320 1 2<br />
LPC_AD_R<br />
33<br />
LPC_AD<br />
BI 48<br />
5% 1/20W MF 201<br />
LPC_AD_R<br />
R1321 33 1 2<br />
LPC_AD<br />
BI 48<br />
LPC_AD_R<br />
33<br />
5% 1/20W MF 201<br />
R1322 1 2<br />
LPC_AD<br />
BI 48<br />
5% 1/20W MF 201<br />
LPC_AD_R<br />
R1323 33 1 2<br />
LPC_AD<br />
BI 48<br />
LPC_FRAME_R_L<br />
R1325 33<br />
5% 1/20W MF 201<br />
1 2<br />
LPC_FRAME_L<br />
OUT 48<br />
5% 1/20W MF 201<br />
LPC_PWRDWN_L<br />
OUT 48<br />
LPC_CLK24M_SMC_R R1327 22 1 2 LPC_CLK24M_SMC<br />
OUT 48<br />
5% 1/20W MF 201<br />
NC_PCH_CLKOUT_LPC1 105<br />
19<br />
LPC_CLKRUN_L<br />
BI<br />
13<br />
48<br />
C<br />
B<br />
B<br />
PP3V3_S0 5 14 16 19 94 101<br />
PP3V3_SUS 8 14 15 16 101<br />
PP3V3_SUS 8 101<br />
MEMORY CONFIGURATION STRAPS.<br />
A<br />
R1344 10K 1 2<br />
R1343 1K 1 2<br />
R1342 10K 1 2<br />
R1341 100K 1 2<br />
R1340 100K 1 2<br />
R1350 10K 1 2<br />
R1351 100K 1 2<br />
R1352 47K 1 2<br />
R1353 47K 1 2<br />
R1354 47K 1 2<br />
R1355 10K 1 2<br />
R1356 10K 1 2<br />
R1357 100K 1 2<br />
R1358 100K 1 2<br />
100K<br />
R1359 1 2<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
PU_PCH_RCIN_L<br />
13<br />
SPI_CS0_R_L<br />
13 59<br />
LPC_SERIRQ<br />
13 48<br />
BT_PWRRST_L<br />
6 105<br />
BT_TIMESTAMP<br />
6 35<br />
LPC_CLKRUN_L<br />
13 48<br />
CAMERA_PWR_EN<br />
19<br />
ALS_SOC_UART_D2R 13 19<br />
ALS_SOC_UART_R2D 13 19<br />
PD_SSD_UART_CTS_L 13 19<br />
JTAG_TBT_X_TMS 13 28<br />
JTAG_TBT_T_TMS 13 28 94<br />
TBT_X_CIO_PWR_EN<br />
13 28<br />
TBT_X_USB_PWR_EN<br />
13 28<br />
PD_LCD_PSR_EN 13 19<br />
BOM GROUP<br />
RAMCFG_SLOT<br />
13<br />
13<br />
13<br />
13<br />
6<br />
MLB_RAMCFG0<br />
MLB_RAMCFG1<br />
MLB_RAMCFG2<br />
MLB_RAMCFG3<br />
MLB_RAMCFG4<br />
PCH INTERNAL PULL-UPS ARE TO 3.3V.<br />
RAMCFG4_L<br />
1<br />
R1334<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
RAMCFG3_L<br />
1<br />
R1333<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
RAMCFG2_L<br />
1<br />
R1332<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
RAMCFG1_L<br />
1<br />
R1331<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
BOM OPTIONS<br />
RAMCFG0_L<br />
1<br />
R1330<br />
RAMCFG4_L,RAMCFG3_L,RAMCFG2_L,RAMCFG1_L,RAMCFG0_L<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
BOM_COST_GROUP=CPU & CHIPSET<br />
DESIGN: X502/MLB<br />
LAST CHANGE: Tue Feb 2 13:18:21 2016<br />
PCH Audio/LPC/SPI/SMBus<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
13 OF 145<br />
13 OF 119<br />
SIZE<br />
D<br />
A
SYNC_MASTER=J130_MLB<br />
SYNC_DATE=05/04/2016<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
PCH Reset Button<br />
101<br />
16<br />
15<br />
13<br />
8<br />
PP3V3_SUS<br />
101<br />
94<br />
19<br />
16<br />
14<br />
13<br />
5<br />
PP3V3_S0<br />
D<br />
101<br />
19<br />
10<br />
8<br />
6<br />
PP1V0_S3<br />
R1405 1<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
201 2<br />
NOSTUFF<br />
1<br />
R1407<br />
2.2K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
1<br />
R1408<br />
2.2K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
OMIT_TABLE<br />
U0500<br />
SKL-ULT-2+3E<br />
TBD<br />
BGA<br />
SYM 11 OF 20<br />
D<br />
48 17<br />
74<br />
48<br />
IN<br />
IN<br />
IN<br />
PM_SYSRST_L<br />
CPU_VCCST_PWRGD<br />
VCCST_PWRGD 1V TOLERANT<br />
PM_DSW_PWRGD<br />
R1403 1<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201 2<br />
R1406<br />
60.4<br />
1%<br />
1 2<br />
201 MF 1/20W<br />
PLACE_NEAR=U0500.B65:38mm<br />
50 OUT<br />
NO STUFF<br />
R14002 0<br />
5%<br />
1/20W<br />
MF<br />
0201 1<br />
104 35 19<br />
77 48 17<br />
104 73 48<br />
74<br />
18 14<br />
48 14<br />
OUT<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
SMC_PCH_SUSWARN_L<br />
SMC_PCH_SUSACK_L<br />
PCIE_WAKE_L<br />
SMC_WAKE_SCI_L<br />
102 NC_PCH_LANPHYPC<br />
NC_PCH_GPD7<br />
102<br />
PLT_RST_L<br />
PM_RSMRST_L<br />
TP_CPU_PWRGD<br />
CPU_VCCST_PWRGD_R<br />
PM_PCH_SYS_PWROK<br />
PM_PCH_PWROK<br />
AN10<br />
B5<br />
AY17<br />
A68<br />
B65<br />
B6<br />
BA20<br />
BB20<br />
AR13<br />
AP11<br />
BB15<br />
AM15<br />
AW17<br />
AT15<br />
GPP_B13/PLTRST*<br />
SYS_RESET*<br />
RSMRST*<br />
PROCPWRGD<br />
VCCST_PWRGD<br />
SYS_PWROK<br />
PCH_PWROK<br />
DSW_PWROK<br />
SYSTEM POWER MANAGEMENT<br />
(1V ONLY)<br />
GPP_A13/SUSWARN*/SUSPWRDNACK<br />
GPP_A15/SUSACK*<br />
WAKE*<br />
GPD2/LAN_WAKE*<br />
GPD11/LANPHYPC<br />
GPD7/RSVD<br />
GPP_B12/SLP_S0*<br />
GPD4/SLP_S3*<br />
GPD5/SLP_S4*<br />
GPD10/SLP_S5*<br />
SLP_SUS*<br />
SLP_LAN*<br />
GPD9/SLP_WLAN*<br />
GPD6/SLP_A*<br />
GPD3/PWRBTN*<br />
GPD1/ACPRESENT<br />
GPD0/BATLOW*<br />
GPP_A11/PME*<br />
INTRUDER*<br />
GPP_B11/EXT_PWR_GATE*<br />
GPP_B2/VRALERT*<br />
AT11<br />
AP15<br />
BA16<br />
AY16<br />
AN15<br />
AW15<br />
BB17<br />
AN16<br />
BA15<br />
AY15<br />
AU13<br />
AU11<br />
AP16<br />
AM10<br />
AM11<br />
NC<br />
PM_SLP_S0_L<br />
PM_SLP_S3_L<br />
PM_SLP_S4_L<br />
PM_SLP_S5_L<br />
PM_SLP_SUS_L<br />
NC_PCH_SLP_WLAN_L 102<br />
NC_PCH_SLP_A_L 102<br />
PM_PWRBTN_L<br />
SSD_SR_EN_L<br />
PM_BATLOW_L<br />
NC_PCH_PME_L 102<br />
PCH_INTRUDER_L<br />
PCH_HSIO_PWR_EN<br />
BT_LOW_PWR_L<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
OUT<br />
IN<br />
OUT<br />
OUT<br />
14<br />
14<br />
14<br />
14<br />
14<br />
14<br />
14<br />
14<br />
78<br />
14<br />
19 48<br />
19 26<br />
19 43<br />
19 48<br />
74 77<br />
50<br />
102<br />
28 48<br />
35<br />
74 104<br />
48 73 74<br />
48 74 77<br />
77 104<br />
104<br />
94<br />
77<br />
104<br />
80<br />
92<br />
104<br />
PP3V0_G3H 8 12 15 100<br />
1<br />
R1401<br />
1M<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
50<br />
IN<br />
C<br />
R1400 kept for debug purposes.<br />
C<br />
B<br />
A<br />
OMIT_TABLE<br />
U0500<br />
SKL-ULT-2+3E<br />
TBD<br />
BGA<br />
SYM 9 OF 20<br />
A36<br />
C37<br />
NC<br />
CSI2_DN0<br />
CSI2_CLKN0<br />
B36<br />
CSI-2<br />
NC<br />
D37<br />
NC<br />
CSI2_DP0<br />
CSI2_CLKP0 NC<br />
PP1V8_SUS 8 19 100<br />
C38<br />
C32<br />
NC<br />
CSI2_DN1<br />
CSI2_CLKN1 NC<br />
PP3V3_S5 8 101<br />
D38<br />
D32<br />
R1480 1 NC<br />
CSI2_DP1<br />
CSI2_CLKP1 NC<br />
PP3V3_S4 101<br />
C36<br />
C29<br />
100<br />
NC<br />
CSI2_DN2<br />
CSI2_CLKN2 NC<br />
1%<br />
PP3V3_S0 5 13 14 16 19 94 101<br />
D36<br />
D29<br />
1/20W<br />
NC<br />
CSI2_DP2<br />
CSI2_CLKP2 NC<br />
A38<br />
B26<br />
201<br />
2<br />
NC<br />
CSI2_DN3<br />
CSI2_CLKN3 NC<br />
B38<br />
A26<br />
NC<br />
CSI2_DP3<br />
CSI2_CLKP3 NC<br />
C31<br />
E13 CSI2_COMP<br />
NC<br />
CSI2_DN4<br />
CSI2_COMP<br />
PLACE_NEAR=U0500.E13:12.7MM<br />
D31<br />
M1<br />
NC_PCH_GPP_D0<br />
NC<br />
CSI2_DP4<br />
GPP_D0/SPI1_CS*<br />
102<br />
C33<br />
NC<br />
CSI2_DN5<br />
SOC_SWD_CLK D33<br />
ALL GPP_F* PINS ARE 1.8V ONLY!<br />
14 19 42<br />
5% 1/20W MF 201<br />
NC<br />
CSI2_DP5<br />
EMMC<br />
SSD_BOOT_L<br />
PCH_SWD_IO<br />
A31<br />
GPP_F7/I2C3_SCL<br />
AH12<br />
OUT 14 91 104<br />
14 42<br />
5% 1/20W MF 201<br />
NC<br />
CSI2_DN6<br />
NC_PCH_GPP_F8<br />
PCH_SWD_MUX_SEL<br />
B31<br />
GPP_F8/I2C4_SDA<br />
AF11<br />
102<br />
14 42<br />
(1.8V)<br />
5% 1/20W MF 201<br />
NC<br />
CSI2_DP6<br />
NC_PCH_GPP_F9<br />
PCH_SOC_DBELL A33<br />
GPP_F9/I2C4_SCL<br />
AF12<br />
102<br />
14 19 37<br />
5% 1/20W MF 201<br />
NC<br />
CSI2_DN7<br />
AD11<br />
NC_PCH_GPP_F10<br />
SSD_BOOT_L<br />
B33<br />
GPP_F10/I2C5_SDA/ISH_I2C2_SDA<br />
102<br />
14 91 104<br />
5% 1/20W MF 201<br />
NC<br />
CSI2_DP7<br />
GPP_F11/I2C5_SCL/ISH_I2C2_SCL<br />
AD12<br />
PCH_BT_ROM_BOOT 19 35<br />
BT_LOW_PWR_L<br />
14 35<br />
5% 1/20W MF 201<br />
A29<br />
AP4<br />
SOC_SWD_CLK<br />
14 19 42<br />
SSD_SR_EN_L<br />
NC<br />
CSI2_DN8<br />
GPP_F12/EMMC_CMD<br />
OUT<br />
14 102<br />
5% 1/20W MF 201<br />
B29<br />
AP2<br />
PCH_SWD_IO<br />
14 42<br />
PM_PWRBTN_L NC<br />
CSI2_DP8<br />
GPP_F13/EMMC_DATA0<br />
BI<br />
14 50<br />
5% 1/20W MF 201<br />
C28<br />
AP1<br />
PCH_SWD_MUX_SEL<br />
14 42<br />
PM_BATLOW_L<br />
NC<br />
CSI2_DN9<br />
GPP_F14/EMMC_DATA1<br />
OUT<br />
14 28 48 94<br />
5% 1/20W MF 201<br />
D28<br />
PCIE_WAKE_L<br />
NC<br />
CSI2_DP9<br />
AP3<br />
14 18<br />
A27<br />
GPP_F15/EMMC_DATA2<br />
PCH_SOC_DBELL 14 19 37<br />
5% 1/20W MF 201<br />
SMC_WAKE_SCI_L<br />
NC<br />
CSI2_DN10<br />
AN3<br />
14 48<br />
B27<br />
GPP_F16/EMMC_DATA3<br />
PCH_SOC_FORCE_DFU<br />
OUT 38<br />
5% 1/20W MF 201<br />
NC<br />
CSI2_DP10<br />
AH11<br />
C27<br />
GPP_F6/I2C3_SDA<br />
NC_UPC_I2C_INT_L<br />
IN 19<br />
NC<br />
CSI2_DN11<br />
PM_SLP_S5_L<br />
D27<br />
AT1<br />
14 19 48 77 104<br />
EMMC_RCOMP<br />
5% 1/20W MF 201<br />
NC<br />
CSI2_DP11<br />
EMMC_RCOMP<br />
DESIGN: X502/MLB<br />
PM_SLP_S4_L<br />
14 19 43 48 74 77 104<br />
5% 1/20W MF 201<br />
PM_SLP_S3_L<br />
LAST CHANGE: Tue May 3 17:45:28 2016<br />
5% 1/20W MF 201<br />
R1481 1 14 19 26 48 73 74 77 80 92 104<br />
PM_SLP_S0_L<br />
14 19 48 74 104<br />
200<br />
PAGE TITLE<br />
5% 1/20W MF 201<br />
1%<br />
PM_SLP_SUS_L<br />
14 74 77 104<br />
1/20W<br />
5% 1/20W MF 201<br />
PCH Power Management<br />
201<br />
2<br />
DRAWING NUMBER<br />
051-00777<br />
Apple Inc.<br />
NOTE: PM_SLP_S0_L HAS INTERNAL PULL-UP BEFORE RSMRST_L IS RELEASED.<br />
REVISION<br />
PLACE_NEAR=U0500.AT1:12.7MM<br />
R<br />
THIS CAUSES A VOLTAGE DIVIDER WITH THE PULL-DOWN HERE.<br />
9.0.0<br />
THE SIGNAL IS DRIVEN HI AFTER RSMRST_L IS RELEASED.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
BRANCH<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
PAGE<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
14 OF 145<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
SHEET<br />
R1446 1 2<br />
100K<br />
R1445 100K 1 2<br />
R1444 100K 1 2<br />
R1443 100K 1 2<br />
R1442 100K 1 2<br />
R1441 10K 1 2<br />
R1440 100K 1 2<br />
R1450 1K 1 2<br />
R1451 10K 1 2<br />
R1452 10K 1 2<br />
100K<br />
R1453 1 2<br />
R1454 1 2<br />
100K<br />
R1455 100K 1 2<br />
R1456 100K 1 2<br />
R1457 220K 1 2<br />
R1458 100K 1 2<br />
BOM_COST_GROUP=CPU & CHIPSET<br />
8 7 6<br />
5 4 3<br />
2 1<br />
IV ALL RIGHTS RESERVED<br />
dvt-fab09-0<br />
14 OF 119<br />
SIZE<br />
D<br />
B<br />
A
SYNC_MASTER=J130_MLB<br />
SYNC_DATE=06/23/2015<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
OMIT_TABLE<br />
D<br />
C<br />
B<br />
PCIe Port Assignments:<br />
SSD LANE 0<br />
SSD LANE 1<br />
SSD LANE 2<br />
SSD LANE 3<br />
Thunderbolt X lane 0<br />
Thunderbolt X lane 1<br />
Thunderbolt X lane 2<br />
Thunderbolt X lane 3<br />
AirPort<br />
CAMERA<br />
PLACE_NEAR=U0500.F5:12.7mm<br />
R1504 1<br />
100<br />
1%<br />
1/20W<br />
MF<br />
201 2<br />
Thunderbolt T lane 0<br />
Thunderbolt T lane 1<br />
105 91<br />
105 91<br />
105 91<br />
105 91<br />
105 81<br />
105 81<br />
105 84<br />
105 84<br />
105 81<br />
105 81<br />
105 84<br />
105 84<br />
105 81<br />
105 81<br />
105 84<br />
105 84<br />
105 28<br />
105 28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
35<br />
35<br />
35<br />
35<br />
102<br />
102<br />
102<br />
102<br />
17<br />
17<br />
48 15<br />
105 94<br />
105 94<br />
94<br />
94<br />
94<br />
94<br />
94<br />
94<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
PCIE_SSD_D2R_N<br />
PCIE_SSD_D2R_P<br />
PCIE_SSD_R2D_C_N<br />
PCIE_SSD_R2D_C_P<br />
PCIE_SSD_D2R_N<br />
PCIE_SSD_D2R_P<br />
PCIE_SSD_R2D_C_N<br />
PCIE_SSD_R2D_C_P<br />
PCIE_SSD_D2R_N<br />
PCIE_SSD_D2R_P<br />
PCIE_SSD_R2D_C_N<br />
PCIE_SSD_R2D_C_P<br />
PCIE_SSD_D2R_N<br />
PCIE_SSD_D2R_P<br />
PCIE_SSD_R2D_C_N<br />
PCIE_SSD_R2D_C_P<br />
PCIE_TBT_X_D2R_N<br />
PCIE_TBT_X_D2R_P<br />
PCIE_TBT_X_R2D_C_N<br />
PCIE_TBT_X_R2D_C_P<br />
PCIE_TBT_X_D2R_N<br />
PCIE_TBT_X_D2R_P<br />
PCIE_TBT_X_R2D_C_N<br />
PCIE_TBT_X_R2D_C_P<br />
PCIE_TBT_X_D2R_N<br />
PCIE_TBT_X_D2R_P<br />
PCIE_TBT_X_R2D_C_N<br />
PCIE_TBT_X_R2D_C_P<br />
PCIE_TBT_X_D2R_N<br />
PCIE_TBT_X_D2R_P<br />
PCIE_TBT_X_R2D_C_N<br />
PCIE_TBT_X_R2D_C_P<br />
PCIE_AP_D2R_N<br />
PCIE_AP_D2R_P<br />
PCIE_AP_R2D_C_N<br />
PCIE_AP_R2D_C_P<br />
NC_PCIE_CAMERA_D2R_N<br />
NC_PCIE_CAMERA_D2R_P<br />
NC_PCIE_CAMERA_R2D_C_N<br />
NC_PCIE_CAMERA_R2D_C_P<br />
PCH_PCIE_RCOMP_N<br />
PCH_PCIE_RCOMP_P<br />
XDP_CPU_PRDY_L<br />
XDP_CPU_PREQ_L<br />
SMC_RUNTIME_SCI_L<br />
PCIE_TBT_T_D2R_N<br />
PCIE_TBT_T_D2R_P<br />
PCIE_TBT_T_R2D_C_N<br />
PCIE_TBT_T_R2D_C_P<br />
PCIE_TBT_T_D2R_N<br />
PCIE_TBT_T_D2R_P<br />
PCIE_TBT_T_R2D_C_N<br />
PCIE_TBT_T_R2D_C_P<br />
H13<br />
G13<br />
B17<br />
A17<br />
G11<br />
F11<br />
D16<br />
C16<br />
H16<br />
G16<br />
D17<br />
C17<br />
G15<br />
F15<br />
B19<br />
A19<br />
F16<br />
E16<br />
C19<br />
D19<br />
G18<br />
F18<br />
D20<br />
C20<br />
F20<br />
E20<br />
B21<br />
A21<br />
G21<br />
F21<br />
D21<br />
C21<br />
E22<br />
E23<br />
B23<br />
A23<br />
F25<br />
E25<br />
D23<br />
C23<br />
F5<br />
E5<br />
D56<br />
D61<br />
BB11<br />
E28<br />
E27<br />
D24<br />
C24<br />
E30<br />
F30<br />
A25<br />
B25<br />
PCIE1_RXN/USB3_5_RXN<br />
PCIE1_RXP/USB3_5_RXP<br />
PCIE1_TXN/USB3_5_TXN<br />
PCIE1_TXP/USB3_5_TXP<br />
PCIE2_RXN/USB3_6_RXN<br />
PCIE2_RXP/USB3_6_RXP<br />
PCIE2_TXN/USB3_6_TXN<br />
PCIE2_TXP/USB3_6_TXP<br />
PCIE3_RXN<br />
PCIE3_RXP<br />
PCIE3_TXN<br />
PCIE3_TXP<br />
PCIE4_RXN<br />
PCIE4_RXP<br />
PCIE4_TXN<br />
PCIE4_TXP<br />
PCIE5_RXN<br />
PCIE5_RXP<br />
PCIE5_TXN<br />
PCIE5_TXP<br />
PCIE6_RXN<br />
PCIE6_RXP<br />
PCIE6_TXN<br />
PCIE6_TXP<br />
PCIE7_RXN/SATA0_RXN<br />
PCIE7_RXP/SATA0_RXP<br />
PCIE7_TXN/SATA0_TXN<br />
PCIE7_TXP/SATA0_TXP<br />
PCIE8_RXN/SATA1A_RXN<br />
PCIE8_RXP/SATA1A_RXP<br />
PCIE8_TXN/SATA1A_TXN<br />
PCIE8_TXP/SATA1A_TXP<br />
PCIE9_RXN<br />
PCIE9_RXP<br />
PCIE9_TXN<br />
PCIE9_TXP<br />
PCIE10_RXN<br />
PCIE10_RXP<br />
PCIE10_TXN<br />
PCIE10_TXP<br />
PCIE_RCOMPN<br />
PCIE_RCOMPP<br />
PROC_PRDY*<br />
PROC_PREQ*<br />
GPP_A7/PIRQA*<br />
PCIE11_RXN/SATA1B_RXN<br />
PCIE11_RXP/SATA1B_RXP<br />
PCIE11_TXN/SATA1B_TXN<br />
PCIE11_TXP/SATA1B_TXP<br />
PCIE12_RXN/SATA2_RXN<br />
PCIE12_RXP/SATA2_RXP<br />
PCIE12_TXN/SATA2_TXN<br />
PCIE12_TXP/SATA2_TXP<br />
U0500<br />
SKL-ULT-2+3E<br />
TBD<br />
BGA<br />
SYM 8 OF 20<br />
PCIE/USB3/SATA<br />
SSIC/USB3<br />
USB2<br />
OMIT_TABLE<br />
U0500<br />
SKL-ULT-2+3E<br />
TBD<br />
BGA<br />
SYM 10 OF 20<br />
USB3_1_RXN<br />
USB3_1_RXP<br />
USB3_1_TXN<br />
USB3_1_TXP<br />
USB3_2_RXN/SSIC_RXN<br />
USB3_2_RXP/SSIC_RXP<br />
USB3_2_TXN/SSIC_TXN<br />
USB3_2_TXP/SSIC_TXP<br />
USB3_3_RXN<br />
USB3_3_RXP<br />
USB3_3_TXN<br />
USB3_3_TXP<br />
USB3_4_RXN<br />
USB3_4_RXP<br />
USB3_4_TXN<br />
USB3_4_TXP<br />
USB2N_1<br />
USB2P_1<br />
USB2N_2<br />
USB2P_2<br />
USB2N_3<br />
USB2P_3<br />
USB2N_4<br />
USB2P_4<br />
USB2N_5<br />
USB2P_5<br />
USB2N_6<br />
USB2P_6<br />
USB2N_7<br />
USB2P_7<br />
USB2N_8<br />
USB2P_8<br />
USB2N_9<br />
USB2P_9<br />
USB2N_10<br />
USB2P_10<br />
USB2_COMP<br />
USB2_ID<br />
USB2_VBUSSENSE<br />
GPP_E3/CPU_GP0<br />
GPP_E4/DEVSLP0<br />
GPP_E5/DEVSLP1<br />
GPP_E6/DEVSLP2<br />
GPP_D22/SPI1_IO3<br />
GPP_D23/I2S_MCLK<br />
GPP_E0/SATAXPCIE0/SATAGP0<br />
GPP_D18/DMIC_DATA1<br />
GPP_D19/DMIC_CLK0<br />
GPP_D20/DMIC_DATA0<br />
GPP_E2/SATAXPCIE2/SATAGP2<br />
H8<br />
G8<br />
C13<br />
D13<br />
J6<br />
H6<br />
B13<br />
A13<br />
J10<br />
H10<br />
B15<br />
A15<br />
E10<br />
F10<br />
C15<br />
D15<br />
AB9<br />
AB10<br />
AD6<br />
AD7<br />
AH3<br />
AJ3<br />
AD9<br />
AD10<br />
AJ1<br />
AJ2<br />
AF6<br />
AF7<br />
AH1<br />
AH2<br />
AF8<br />
AF9<br />
AG1<br />
AG2<br />
AH7<br />
AH8<br />
AB6<br />
AG3<br />
AG4<br />
A6<br />
J1<br />
J2<br />
J3<br />
V2<br />
J5<br />
H2<br />
C8<br />
H5<br />
D7<br />
G4<br />
USB3_EXTA_D2R_N<br />
USB3_EXTA_D2R_P<br />
USB3_EXTA_R2D_C_N<br />
USB3_EXTA_R2D_C_P<br />
NC_USB3_EXTB_D2R_N<br />
NC_USB3_EXTB_D2R_P<br />
NC_USB3_EXTB_R2D_C_N<br />
NC_USB3_EXTB_R2D_C_P<br />
TP_USB3_03_D2RN<br />
TP_USB3_03_D2RP<br />
TP_USB3_03_R2DN<br />
TP_USB3_03_R2DP<br />
NC_USB3_04_D2RN 19<br />
NC_USB3_04_D2RP 19<br />
NC_USB3_04_R2DN 19<br />
NC_USB3_04_R2DP 19<br />
NC_USB_EXTA_N<br />
NC_USB_EXTA_P<br />
NC_USB_EXTB_N<br />
NC_USB_EXTB_P<br />
USB_CAMERA_DFR_N<br />
USB_CAMERA_DFR_P<br />
TP_USB_TESTERN<br />
TP_USB_TESTERP<br />
NC_USB2_05N<br />
NC_USB2_05P<br />
USB_UPC_PCH_XA_N 28<br />
USB_UPC_PCH_XA_P 28<br />
USB_UPC_PCH_TA_N 94<br />
USB_UPC_PCH_TA_P 94<br />
USB_UPC_PCH_XB_N 28<br />
USB_UPC_PCH_XB_P 28<br />
USB_UPC_PCH_TB_N 94<br />
USB_UPC_PCH_TB_P 94<br />
NC_USB2_10N<br />
NC_USB2_10P<br />
PCH_USB2_COMP<br />
PCH_USB2_VBUSSENSE<br />
XDP_PCH_OBSFN_C1<br />
XDP_JTAG_ISP_TCK<br />
XDP_JTAG_ISP_TDI<br />
XDP_PCH_OBSDATA_A2<br />
NC_SPKR_ID0<br />
XDP_PCH_OBSDATA_D0<br />
XDP_PCH_OBSDATA_D1<br />
XDP_PCH_OBSDATA_C1<br />
XDP_PCH_OBSDATA_C2<br />
XDP_PCH_OBSDATA_C3<br />
XDP_PCH_OBSDATA_D3<br />
104<br />
104<br />
104<br />
104<br />
104<br />
104<br />
19<br />
19<br />
19<br />
19<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
28<br />
28<br />
28<br />
28<br />
102<br />
102<br />
102<br />
102<br />
17<br />
17<br />
17<br />
17<br />
19<br />
17<br />
17<br />
17<br />
17<br />
17<br />
17<br />
102<br />
102<br />
102<br />
102<br />
38<br />
38<br />
105<br />
105<br />
EXT A (SS,DCI)<br />
EXT B (SS)<br />
EXT A (LS/FS/HS)<br />
EXT B (LS/FS/HS)<br />
CKPLUS_WAIVE=CLK_DATA_CON<br />
CKPLUS_WAIVE=CLK_DATA_CON<br />
GROUNDED PER SKYLAKE MOW 2015WW10.<br />
1<br />
R1503<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
PLACE_NEAR=U0500.AG4:12.7MM<br />
1<br />
R1501<br />
113<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
PLACE_NEAR=U0500.AB6:12.7MM<br />
D<br />
C<br />
B<br />
A<br />
PP3V3_SUS 8 13 14 16 101<br />
R1550 100K 1 2<br />
5% 1/20W MF 201<br />
ANY CLKREQ CAN MAP TO ANY CLK.<br />
ANY CLKREQ OR CLK CAN MAP TO ANY PCIE PORT.<br />
UNUSED CLKREQS AND CLKS SHOULD BE DISABLED.<br />
PER SKYLAKE PDG, SKYLAKE PCH EDS.<br />
SMC_RUNTIME_SCI_L<br />
15<br />
48<br />
91<br />
91<br />
19<br />
105 26<br />
105 26<br />
19<br />
105 92<br />
105 92<br />
19<br />
105 35<br />
105 35<br />
19<br />
102<br />
102<br />
19<br />
OUT<br />
OUT<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
19<br />
19<br />
19<br />
PCIE_CLK100M_SSD_N<br />
PCIE_CLK100M_SSD_P<br />
SSD_CLKREQ_L_R<br />
PCIE_CLK100M_TBT_X_N<br />
PCIE_CLK100M_TBT_X_P<br />
TBT_X_CLKREQ_L_R<br />
PCIE_CLK100M_TBT_T_N<br />
PCIE_CLK100M_TBT_T_P<br />
TBT_T_CLKREQ_L_R<br />
PCIE_CLK100M_AP_N<br />
PCIE_CLK100M_AP_P<br />
AP_CLKREQ_L_R<br />
NC_PCIE_CLK100M_CAMERA_N<br />
NC_PCIE_CLK100M_CAMERA_P<br />
NC_PCH_CLKREQ4_L<br />
NC_PCIE_CLK100M5N<br />
NC_PCIE_CLK100M5P<br />
NC_PCH_CLKREQ5_L<br />
D42<br />
C42<br />
AR10<br />
B42<br />
A42<br />
AT7<br />
D41<br />
C41<br />
AT8<br />
D40<br />
C40<br />
AT10<br />
B40<br />
A40<br />
AU8<br />
E40<br />
E38<br />
AU7<br />
CLKOUT_PCIE_N0<br />
CLKOUT_PCIE_P0<br />
GPP_B5/SRCCLKREQ0*<br />
CLKOUT_PCIE_N1<br />
CLKOUT_PCIE_P1<br />
GPP_B6/SRCCLKREQ1*<br />
CLKOUT_PCIE_N2<br />
CLKOUT_PCIE_P2<br />
GPP_B7/SRCCLKREQ2*<br />
CLKOUT_PCIE_N3<br />
CLKOUT_PCIE_P3<br />
GPP_B8/SRCCLKREQ3*<br />
CLKOUT_PCIE_N4<br />
CLKOUT_PCIE_P4<br />
GPP_B9/SRCCLKREQ4*<br />
CLKOUT_PCIE_N5<br />
CLKOUT_PCIE_P5<br />
GPP_B10/SRCCLKREQ5*<br />
CLOCK SIGNALS<br />
F43<br />
E43<br />
BA17<br />
E37<br />
E35<br />
E42<br />
AM18<br />
AM20<br />
AN18<br />
AM16<br />
NC_ITPXDP_CLK100M_N 19<br />
NC_ITPXDP_CLK100M_P 19<br />
PM_CLK32K_SUSCLK_R<br />
PCH_CLK24M_XTALIN<br />
NC_PCH_CLK24M_XTALOUT<br />
PCH_DIFFCLK_BIASREF<br />
SYSCLK_CLK32K_PCH<br />
NC_PCH_CLK32K_RTCX2<br />
PCH_SRTCRST_L<br />
RTC_RESET_L<br />
49<br />
19<br />
19<br />
19<br />
19<br />
PP1V0_SUS 12 101<br />
PLACE_NEAR=U0500.E42:2.54mm<br />
1<br />
R1520<br />
2.7K<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
R1530 1<br />
20K<br />
1/20W 1%<br />
MF<br />
201 2<br />
C1530 1<br />
1UF<br />
2<br />
20%<br />
6.3V<br />
X6S-CERM<br />
0201<br />
1<br />
R1531<br />
20K<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
C1531<br />
1UF<br />
20%<br />
6.3V<br />
X6S-CERM<br />
0201<br />
BOM_COST_GROUP=CPU & CHIPSET<br />
1<br />
2<br />
PP3V0_G3H 8 12 14 100<br />
DESIGN: X502/MLB<br />
LAST CHANGE: Thu Jun 18 20:05:18 2015<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
PCH PCIE/USB/CLKS<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
CLKOUT_ITPXDP_N<br />
CLKOUT_ITPXDP_P<br />
GPD8/SUSCLK<br />
XTAL24_IN<br />
XTAL24_OUT<br />
XCLK_BIASREF<br />
RTCX1<br />
RTCX2<br />
SRTCRST*<br />
RTCRST*<br />
OUT<br />
IN<br />
OUT<br />
IN<br />
OUT<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
15 OF 145<br />
15 OF 119<br />
SIZE<br />
D<br />
A
TABLE_5_HEAD<br />
TABLE_5_ITEM<br />
TABLE_5_ITEM<br />
TABLE_5_ITEM<br />
TABLE_5_ITEM<br />
TABLE_5_ITEM<br />
TABLE_5_ITEM<br />
TABLE_5_ITEM<br />
TABLE_5_ITEM<br />
TABLE_5_ITEM<br />
TABLE_5_ITEM<br />
TABLE_5_ITEM<br />
TABLE_5_ITEM<br />
TABLE_5_ITEM<br />
SYNC_MASTER=J130_MLB<br />
SYNC_DATE=12/08/2015<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
ALL GPP_F* PINS ARE 1.8V ONLY!<br />
D<br />
C<br />
19 16<br />
19 16<br />
19 16<br />
19 16<br />
43 16<br />
43 16<br />
43 16<br />
43 16<br />
35 16<br />
35 16<br />
35 16<br />
35 16<br />
18 16<br />
18 16<br />
28 16<br />
94 16<br />
19 16<br />
19 16<br />
19 16<br />
19 16<br />
104 91 19<br />
94 28 16<br />
OUT<br />
OUT<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
OUT<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
OUT<br />
IN<br />
IN<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
OUT<br />
19<br />
19<br />
19<br />
19<br />
PU_AUD_SPI_CS_L<br />
PD_AUD_SPI_CLK<br />
PD_AUD_SPI_MISO<br />
PU_AUD_SPI_MOSI<br />
TPAD_SPI_CS_L<br />
TPAD_SPI_CLK<br />
TPAD_SPI_MISO<br />
TPAD_SPI_MOSI<br />
PCH_BT_UART_D2R<br />
PCH_BT_UART_R2D<br />
PCH_BT_UART_RTS_L<br />
PCH_BT_UART_CTS_L<br />
AP_S0IX_WAKE_SEL<br />
AP_S0IX_WAKE_L<br />
TBT_X_CIO_PLUG_EVENT_L<br />
TBT_T_CIO_PLUG_EVENT_L<br />
PCH_SSD_SOC_UART_D2R<br />
PCH_SSD_SOC_UART_R2D<br />
PU_SOC_UART_RTS_L<br />
PD_SOC_UART_CTS_L<br />
SSD_RESET_L<br />
TBT_POC_RESET<br />
BT_I2S_CLK_1V8<br />
BT_I2S_SYNC_1V8<br />
BT_I2S_R2D_1V8<br />
BT_I2S_D2R_1V8<br />
AN8<br />
AP7<br />
AP8<br />
AR7<br />
AM5<br />
AN7<br />
AP5<br />
AN5<br />
AB1<br />
AB2<br />
W4<br />
AB3<br />
U7<br />
U6<br />
U8<br />
U9<br />
AC1<br />
AC2<br />
AC3<br />
AB4<br />
N11<br />
N12<br />
AK6<br />
AK7<br />
AK9<br />
AK10<br />
LPSS<br />
GPP_B15/GSPI0_CS*<br />
GPP_B16/GSPI0_CLK<br />
GPP_B17/GSPI0_MISO<br />
GPP_B18/GSPI0_MOSI<br />
GPP_B19/GSPI1_CS*<br />
GPP_B20/GSPI1_CLK<br />
GPP_B21/GSPI1_MISO<br />
GPP_B22/GSPI1_MOSI<br />
GPP_C8/UART0_RXD<br />
GPP_C9/UART0_TXD<br />
GPP_C10/UART0_RTS*<br />
GPP_C11/UART0_CTS*<br />
GPP_C16/I2C0_SDA<br />
GPP_C17/I2C0_SCL<br />
GPP_C18/I2C1_SDA<br />
GPP_C19/I2C1_SCL<br />
(1.8V)<br />
(STRAP)<br />
(STRAP)<br />
GPP_C12/UART1_RXD/ISH_UART1_RXD<br />
GPP_C13/UART1_TXD/ISH_UART1_TXD<br />
GPP_C14/UART1_RTS*/ISH_UART1_RTS*<br />
GPP_C15/UART1_CTS*/ISH_UART1_CTS*<br />
GPP_E22<br />
GPP_E23<br />
GPP_F0/I2S2_SCLK<br />
GPP_F1/I2S2_SFRM<br />
GPP_F2/I2S2_TXD<br />
GPP_F3/I2S2_RXD<br />
OMIT_TABLE<br />
U0500<br />
SKL-ULT-2+3E<br />
TBD<br />
BGA<br />
SYM 6 OF 20<br />
(1.8V)<br />
(1.8V)<br />
ISH<br />
GPP_D5/ISH_I2C0_SDA<br />
GPP_D6/ISH_I2C0_SCL<br />
GPP_D7/ISH_I2C1_SDA<br />
GPP_D8/ISH_I2C1_SCL<br />
GPP_D1/SPI1_CLK<br />
GPP_D2/SPI1_MISO<br />
GPP_D3/SPI1_MOSI<br />
GPP_D4/FLASHTRIG<br />
GPP_F4/I2C2_SDA<br />
GPP_F5/I2C2_SCL<br />
GPP_G6/SD_CLK<br />
GPP_D9<br />
GPP_D10<br />
GPP_G7/SD_WP<br />
GPP_G2/SD_DATA1<br />
GPP_G3/SD_DATA2<br />
GPP_G4/SD_DATA3<br />
GPP_G5/SD_CD*<br />
GPP_A18/ISH_GP0<br />
GPP_A19/ISH_GP1<br />
GPP_A20/ISH_GP2<br />
GPP_A21/ISH_GP3<br />
GPP_A22/ISH_GP4<br />
GPP_A23/ISH_GP5<br />
SX_EXIT_HOLDOFF*/GPP_A12/<br />
BM_BUSY*/ISH_GP6<br />
M4<br />
N3<br />
N1<br />
N2<br />
M2<br />
M3<br />
J4<br />
B7<br />
AH9<br />
AH10<br />
W8<br />
P2<br />
P3<br />
W7<br />
AB12<br />
W12<br />
W11<br />
W10<br />
AY8<br />
BA8<br />
BB7<br />
BA7<br />
AY7<br />
AW7<br />
AP13<br />
MLB_BOARD_ID0<br />
MLB_BOARD_ID1<br />
MLB_BOARD_ID2<br />
MLB_BOARD_ID3<br />
NC_PCH_GPP_D1 102<br />
NC_SPKR_ID1 19<br />
NC_PCH_GPP_D3 102<br />
NC_PCH_GPP_D4 102<br />
NC_I2C_UPC_SDA<br />
NC_I2C_UPC_SCL<br />
AP_RESET_L<br />
MLB_BOARD_ID4<br />
NC_MLB_DEV_L<br />
PD_AP_DEV_WAKE<br />
TBT_T_CIO_PWR_EN<br />
TBT_T_USB_PWR_EN<br />
TBT_X_PCI_RESET_L<br />
TBT_T_PCI_RESET_L<br />
SPIROM_USE_MLB<br />
LCD_IRQ_L<br />
DDI1_MUX_SEL<br />
DDI2_MUX_SEL<br />
TPAD_SPI_IF_EN<br />
TPAD_SPI_INT_L<br />
AUD_PWR_EN<br />
16<br />
16<br />
16<br />
16<br />
16<br />
BI<br />
OUT<br />
OUT<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
OUT<br />
IN<br />
OUT<br />
19<br />
19<br />
19 35<br />
19<br />
16 19<br />
94<br />
94<br />
19<br />
19<br />
16 59<br />
16 80<br />
28<br />
28<br />
16 43<br />
16 43<br />
16 61<br />
36<br />
104<br />
C<br />
PP3V3_S0 5 13 14 19 94 101<br />
16 OF 145<br />
PP3V3_SUS 8 13 14 15 101<br />
MLB ID STRAPS.<br />
B<br />
A<br />
R1643 1 2<br />
47K<br />
R1642 47K 1 2<br />
R1641 47K 1 2<br />
47K<br />
R1640 1 2<br />
R1650 100K 1 2<br />
R1652 1 2<br />
100K<br />
R1653 47K 1 2<br />
R1654 47K 1 2<br />
R1655 47K 1 2<br />
1K<br />
R1656 1 2<br />
R1657 1 2<br />
47K<br />
R1658 47K 1 2<br />
R1659 47K 1 2<br />
R1660 150K 1 2<br />
R1674 100K 1 2<br />
R1676 10K 1 2<br />
R1673 100K 1 2<br />
100K<br />
R1675 1 2<br />
R1661 47K 1 2<br />
R1662 47K 1 2<br />
R1663 47K 1 2<br />
R1664 47K 1 2<br />
R1665 1 2<br />
100K<br />
R1666 100K 1 2<br />
R1667 100K 1 2<br />
R1669 100K 1 2<br />
R1668 1 2<br />
100K<br />
R1671 100K 1 2<br />
R1672 100K 1 2<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W<br />
MF<br />
201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201 NOSTUFF<br />
NOSTUFF<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
NOSTUFF<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
PCH_SSD_SOC_UART_D2R 16 19<br />
PCH_SSD_SOC_UART_R2D 16 19<br />
PU_SOC_UART_RTS_L 16 19<br />
PD_SOC_UART_CTS_L 16 19<br />
SPIROM_USE_MLB<br />
AUD_PWR_EN<br />
16 61<br />
PU_AUD_SPI_CS_L 16 19<br />
PD_AUD_SPI_CLK 16 19<br />
PD_AUD_SPI_MISO 16 19<br />
PU_AUD_SPI_MOSI 16 19<br />
TPAD_SPI_CS_L<br />
TPAD_SPI_CLK<br />
TPAD_SPI_MISO<br />
TPAD_SPI_MOSI<br />
TPAD_SPI_INT_L<br />
TPAD_SPI_IF_EN<br />
PCH_BT_UART_D2R<br />
PCH_BT_UART_R2D<br />
PCH_BT_UART_RTS_L<br />
PCH_BT_UART_CTS_L<br />
AP_S0IX_WAKE_SEL<br />
16 18<br />
AP_S0IX_WAKE_L<br />
16 18<br />
PD_AP_DEV_WAKE 16 19<br />
LCD_IRQ_L<br />
DRIVEN PUSH PULL FROM SWITCHED RAIL.<br />
TBT_X_CIO_PLUG_EVENT_L 16 28<br />
TBT_T_CIO_PLUG_EVENT_L 16 94<br />
TBT_POC_RESET<br />
16<br />
16<br />
16<br />
16<br />
16<br />
16<br />
16<br />
16<br />
16<br />
16<br />
16<br />
16<br />
16<br />
59<br />
43<br />
43<br />
43<br />
43<br />
43<br />
43<br />
35<br />
35<br />
35<br />
35<br />
80<br />
28<br />
104<br />
94<br />
16<br />
16<br />
16<br />
16<br />
16<br />
MLB_BOARD_ID0<br />
MLB_BOARD_ID1<br />
MLB_BOARD_ID2<br />
MLB_BOARD_ID3<br />
MLB_BOARD_ID4<br />
PART#<br />
117S0006<br />
117S0006<br />
117S0006<br />
117S0006<br />
PCH INTERNAL PULL-UPS ARE TO VCCGPPD = 3.3V.<br />
0 RES,MF,1/20W/1K OHM,5,0201,SMD<br />
1<br />
117S0006 1<br />
117S0006<br />
117S0006 1<br />
117S0006<br />
117S0006<br />
117S0006<br />
117S0006<br />
117S0006<br />
2<br />
2<br />
3<br />
RES,MF,1/20W/1K OHM,5,0201,SMD<br />
RES,MF,1/20W/1K OHM,5,0201,SMD<br />
RES,MF,1/20W/1K OHM,5,0201,SMD<br />
RES,MF,1/20W/1K OHM,5,0201,SMD<br />
RES,MF,1/20W/1K OHM,5,0201,SMD<br />
117S0006 1 RES,MF,1/20W/1K OHM,5,0201,SMD<br />
R1690<br />
R1691<br />
2 RES,MF,1/20W/1K OHM,5,0201,SMD<br />
R1691,R1690<br />
RES,MF,1/20W/1K OHM,5,0201,SMD<br />
R1692<br />
2 RES,MF,1/20W/1K OHM,5,0201,SMD<br />
R1692,R1690<br />
2<br />
OMIT_TABLE<br />
1<br />
R1694<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
QTY<br />
DESCRIPTION<br />
OMIT_TABLE<br />
1<br />
R1693<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
RES,MF,1/20W/1K OHM,5,0201,SMD<br />
OMIT_TABLE<br />
1<br />
R1692<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
R1692,R1691<br />
3 RES,MF,1/20W/1K OHM,5,0201,SMD<br />
R1692,R1691,R1690<br />
1K<br />
REFERENCE DESIGNATOR(S)<br />
1 RES,MF,1/20W/1K OHM,5,0201,SMD<br />
R1693<br />
R1693,R1690<br />
R1693,R1691<br />
R1693,R1691,R1690<br />
R1694<br />
OMIT_TABLE<br />
1<br />
R1691<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
BOARD_ID:0<br />
BOARD_ID:1<br />
BOARD_ID:2<br />
BOARD_ID:3<br />
BOARD_ID:4<br />
BOARD_ID:5<br />
BOARD_ID:6<br />
BOARD_ID:7<br />
BOARD_ID:8<br />
BOARD_ID:9<br />
BOARD_ID:10<br />
BOARD_ID:11<br />
BOARD_ID:16<br />
OMIT_TABLE<br />
1<br />
R1690<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
CODE<br />
<br />
<br />
<br />
<br />
<br />
<br />
<br />
<br />
<br />
<br />
<br />
<br />
<br />
BOM_COST_GROUP=CPU & CHIPSET<br />
DESIGN: X502/MLB<br />
LAST CHANGE: Wed Oct 28 12:50:22 2015<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
PCH SPI/UART/GPIO<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
BOM OPTION<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
16 OF 119<br />
SIZE<br />
D<br />
B<br />
A
SYNC_MASTER=J130_MLB<br />
SYNC_DATE=12/08/2015<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
C<br />
77 48 14<br />
50 48<br />
17 6<br />
6<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
PM_RSMRST_L<br />
PM_PWRBTN_L<br />
XDP_CPU_TCK<br />
PCH_JTAGX<br />
XDP:YES<br />
R1800 1K 1 2<br />
PLACE_NEAR=U0500.AY17:18MM<br />
XDP:YES<br />
R1802 10 1 2<br />
PLACE_NEAR=U0500.BA15:2.54MM<br />
XDP:YES<br />
R1835 0 1 2<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 0201<br />
PLACE_NEAR=J1800.58:28MM<br />
15<br />
15<br />
6<br />
6<br />
6<br />
6<br />
6<br />
6<br />
6<br />
6<br />
17 6<br />
BI<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
OUT<br />
PULL CFG LOW<br />
WHEN XDP PRESENT<br />
XDP_PRESENT_CPU<br />
XDP_CPU_PREQ_L<br />
XDP_CPU_PRDY_L<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
XDP_PM_RSMRST_L<br />
XDP_CPU_PWRBTN_L<br />
XDP_PCH_TCK<br />
PLACE_NEAR=U0500.D67:2.54MM<br />
XDP:YES<br />
C1804 1<br />
0.1UF<br />
2<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
101<br />
XDP:YES<br />
R1801 1<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
201 2<br />
Primary / Merged (CPU/PCH) Micro2-XDP<br />
PP1V0_SUS<br />
NO_XNET_CONNECTION<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
PLACE_NEAR=J1800.42:28MM<br />
XDP_PIN_1<br />
OBSFN_A0<br />
OBSFN_A1<br />
OBSDATA_A0<br />
OBSDATA_A1<br />
OBSDATA_A2<br />
OBSDATA_A3<br />
OBSFN_B0<br />
OBSFN_B1<br />
OBSDATA_B0<br />
OBSDATA_B1<br />
OBSDATA_B2<br />
OBSDATA_B3<br />
HOOK0<br />
HOOK1<br />
VCC_OBS_AB<br />
HOOK2<br />
HOOK3<br />
SDA<br />
SCL<br />
TCK1<br />
TCK0<br />
XDP:YES<br />
C1800 1<br />
0.1UF<br />
2<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
XDP_CONN:YES<br />
J1800<br />
DF40RC-60DP-0.4V<br />
M-ST-SM1<br />
62<br />
2<br />
4<br />
6<br />
8<br />
10<br />
12<br />
14<br />
16<br />
18<br />
20<br />
22<br />
24<br />
26<br />
28<br />
30<br />
32<br />
34<br />
36<br />
38<br />
40<br />
42<br />
44<br />
46<br />
48<br />
50<br />
52<br />
54<br />
56<br />
58<br />
60<br />
64<br />
PLACE_NEAR=J1800.44:28MM<br />
61<br />
1<br />
3<br />
5<br />
7<br />
9<br />
11<br />
13<br />
15<br />
17<br />
19<br />
21<br />
23<br />
25<br />
27<br />
29<br />
31<br />
33<br />
35<br />
37<br />
39<br />
41<br />
43<br />
45<br />
47<br />
49<br />
51<br />
53<br />
55<br />
57<br />
59<br />
63<br />
518S0847<br />
1<br />
2<br />
NOTE: This is not the standard XDP pinout.<br />
Use with 921-0133 Adapter Flex to<br />
support chipset debug.<br />
OBSFN_C0<br />
OBSFN_C1<br />
OBSDATA_C0<br />
OBSDATA_C1<br />
OBSDATA_C2<br />
OBSDATA_C3<br />
OBSFN_D0<br />
OBSFN_D1<br />
OBSDATA_D0<br />
OBSDATA_D1<br />
OBSDATA_D2<br />
OBSDATA_D3<br />
ITPCLK/HOOK4<br />
ITPCLK#/HOOK5<br />
VCC_OBS_CD<br />
RESET#/HOOK6<br />
DBR#/HOOK7<br />
TDO<br />
TRSTn<br />
TDI<br />
TMS<br />
XDP_PRESENT#<br />
XDP:YES<br />
C1801<br />
0.1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
NC<br />
NC<br />
PLACE_NEAR=J1800.43:28MM<br />
PLACE_NEAR=J1800.47:28MM<br />
1<br />
2<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
CPU_CFG<br />
ITP_PMODE<br />
XDP_DBRESET_L<br />
XDP:YES<br />
C1806<br />
0.1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
6<br />
6<br />
6<br />
6<br />
6<br />
6<br />
6<br />
6<br />
6<br />
6<br />
6<br />
6<br />
1<br />
R1830<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
PLACE_NEAR=J1800.57:2.54MM<br />
6<br />
XDP_PCH_TDO<br />
XDP_PCH_TDI<br />
XDP_PCH_TMS<br />
XDP_CPU_TDO<br />
XDP_CPU_TCK<br />
XDP_PCH_TCK<br />
PLACE_NEAR=U0500.E8:2.54MM<br />
ROUTE IN STAR TOPOLOGY FROM XDP CONNECTOR.<br />
R1821 1 2<br />
0<br />
XDP:YES<br />
R1822 0 1 2<br />
PLACE_NEAR=J1800.51:2.54MM 5% 1/20W<br />
PLACE_NEAR=J1800.53:2.54MM XDP:YES<br />
IN<br />
R1823 1 2<br />
0<br />
XDP:YES<br />
R1824 0 1 2<br />
PLACE_NEAR=J1800.55:2.54MM<br />
17 6<br />
17 6<br />
17 6<br />
17 6<br />
17 6<br />
17 6<br />
XDP:YES<br />
5% 1/20W<br />
5% 1/20W<br />
5% 1/20W MF<br />
XDP:YES<br />
R1806<br />
0<br />
XDP_CPU_TDO<br />
MF<br />
XDP_CPU_TRST_L<br />
MF<br />
XDP_CPU_TDI<br />
MF<br />
XDP_CPU_TMS<br />
101<br />
10<br />
8<br />
PM_SYSRST_L<br />
6 PP1V0_S0SW<br />
1 2<br />
BI 14 48<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
0201<br />
0201<br />
0201<br />
0201<br />
XDP:YES<br />
R1890 51 2 1<br />
PLACE_NEAR=U0500.A56:28MM 5% 1/20W<br />
XDP:YES<br />
R1891 51 2 1<br />
PLACE_NEAR=U0500.D59:28MM 5% 1/20W<br />
XDP:YES<br />
R1892 51 2 1<br />
PLACE_NEAR=U0500.C59:28MM 5% 1/20W<br />
XDP:YES<br />
R1810 51 2 1<br />
PLACE_NEAR=U0500.A61:28MM 5% 1/20W<br />
XDP:YES<br />
R1813 51 2 1<br />
PLACE_NEAR=U0500.B61:28MM 5% 1/20W<br />
NOSTUFF<br />
R1897 51 2 1<br />
PLACE_NEAR=U0500.C61:28MM 5% 1/20W<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
6<br />
6<br />
6<br />
6<br />
17<br />
MF 201<br />
MF 201<br />
MF 201<br />
MF 201<br />
MF 201<br />
MF 201<br />
D<br />
C<br />
B<br />
A<br />
15<br />
15<br />
15<br />
5<br />
5<br />
13<br />
15<br />
15<br />
15<br />
15<br />
15<br />
6<br />
15<br />
15<br />
28 5<br />
28 5<br />
94 5<br />
94 5<br />
IN<br />
IN<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
PCH XDP Signals<br />
These signals do not connect to the Primary (Merged) XDP connector in this architecture.<br />
The PDG puts them on a secondary XDP connector that is only needed in some PCH debugging situation.<br />
They are listed here to show their secondary XDP functions and to provide test points for signals that are not used elsewhere.<br />
PCH/XDP Signals<br />
XDP_JTAG_ISP_TCK<br />
XDP_JTAG_ISP_TDI<br />
XDP_PCH_OBSDATA_A2<br />
XDP_PCH_OBSDATA_A3<br />
XDP_PCH_OBSDATA_B0<br />
XDP_PCH_OBSDATA_C0<br />
XDP_PCH_OBSDATA_C1<br />
XDP_PCH_OBSDATA_C2<br />
XDP_PCH_OBSDATA_C3<br />
XDP_PCH_OBSDATA_D0<br />
XDP_PCH_OBSDATA_D1<br />
XDP_PCH_OBSDATA_D2<br />
XDP_PCH_OBSDATA_D3<br />
XDP_PCH_OBSFN_C1<br />
XDP_USB_EXTA_OC_L<br />
XDP_USB_EXTB_OC_L<br />
XDP_USB_EXTC_OC_L<br />
XDP_USB_EXTD_OC_L<br />
Unused GPIOs have TPs.<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
TP<br />
TP1870<br />
TP-P6<br />
TP<br />
TP1871<br />
TP-P6<br />
TP<br />
TP1872<br />
TP-P6<br />
TP<br />
TP1873<br />
TP-P6<br />
TP<br />
TP1874<br />
TP-P6<br />
TP<br />
TP1875<br />
TP-P6<br />
TP<br />
TP1876<br />
TP-P6<br />
TP<br />
TP1877<br />
TP-P6<br />
TP<br />
TP1878<br />
TP-P6<br />
TP<br />
TP1879<br />
TP-P6<br />
TP<br />
TP1880<br />
TP-P6<br />
TP<br />
TP1881<br />
TP-P6<br />
USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.<br />
JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.<br />
1<br />
1<br />
1<br />
1<br />
1<br />
1<br />
1<br />
1<br />
1<br />
1<br />
1<br />
1<br />
Non-XDP Signals<br />
XDP_JTAG_ISP_TCK<br />
XDP_JTAG_ISP_TDI<br />
XDP_USB_EXTA_OC_L<br />
XDP_USB_EXTB_OC_L<br />
XDP_USB_EXTC_OC_L<br />
XDP_USB_EXTD_OC_L<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
IN<br />
IN<br />
94<br />
94<br />
105<br />
105<br />
105<br />
105<br />
101<br />
77<br />
17<br />
PP3V3_SUS<br />
XDP:YES<br />
R1850 1<br />
100K 5%<br />
1/20W<br />
MF<br />
201 2<br />
101<br />
77<br />
17<br />
PP3V3_SUS<br />
XDP:YES<br />
6<br />
U1830<br />
74AUP1G07GF<br />
SOT891<br />
NEED TO CONNECT TO VCCST, *STG POWER LOGIC<br />
1<br />
2<br />
XDP:YES<br />
C1830<br />
0.1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
SPI_IO2_STRAP_L<br />
XDP_PRESENT_L<br />
BOM_COST_GROUP=DEBUG<br />
XDP_PCH_TDO<br />
XDP_PCH_TRST_L<br />
XDP_PCH_TDI<br />
XDP_PCH_TMS<br />
SPI_IO<br />
2 A<br />
Y 4 1 2<br />
OUT 13 59<br />
(OD)<br />
5%<br />
1 NC<br />
NC 5<br />
NOSTUFF<br />
1/20W<br />
NC<br />
MF<br />
1<br />
R1832<br />
201<br />
GND<br />
(STRAP TO PCH)<br />
0<br />
PLACE_NEAR=U0500.AW2:10MM<br />
5%<br />
1/20W<br />
NO_XNET_CONNECTION=1<br />
MF<br />
2<br />
0201<br />
PULL STRAP LOW WHEN XDP IS PLUGGED IN.<br />
(UNDOCUMENTED STRAP FUNCTION)<br />
3<br />
77<br />
XDP:YES<br />
R1831<br />
1.5K<br />
DESIGN: X502/MLB<br />
LAST CHANGE: Thu Oct 22 19:53:09 2015<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
6<br />
6<br />
6<br />
6<br />
17<br />
17<br />
17<br />
CPU/PCH Merged XDP<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
NC<br />
VCC<br />
OUT<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
OUT<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
IN<br />
OUT<br />
OUT<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
18 OF 145<br />
17 OF 119<br />
SIZE<br />
D<br />
B<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
System 32kHz / 12MHz / 24MHz Clock Generator<br />
PCH ME Disable Strap<br />
D<br />
CRITICAL<br />
C1907<br />
9.5PF<br />
1 2<br />
+/-0.1PF<br />
50V<br />
CER-C0G<br />
0201<br />
SYSCLK_CLK24M_X2<br />
R1900<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
100 35 19<br />
101 19<br />
19<br />
19<br />
48<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
100<br />
PP3V3_G3H<br />
PP1V8_S4<br />
PP1V0_SUS<br />
NC_PPVIOE_CAMCLK<br />
PD_PPVIOE_SSDCLK<br />
SMC_CLK12M_EN<br />
SYSCLK_CLK24M_X2_R<br />
12<br />
2<br />
5<br />
15<br />
8<br />
19<br />
20<br />
1<br />
VIO_32K_B<br />
VIOE_24M_A<br />
VIOE_24M_B<br />
VIOE_24M_C<br />
OE_12M<br />
X2<br />
X1<br />
VDD<br />
11<br />
U1900<br />
SLG3AP3444<br />
STQFN<br />
GND<br />
VRTC<br />
VOUT<br />
1<br />
2<br />
32.768K_A<br />
32.768K_B<br />
24M_A<br />
24M_B<br />
24M_C<br />
12M<br />
BYPASS=U1900.11:18:5MM<br />
C1901<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
17<br />
10<br />
13<br />
3<br />
6<br />
16<br />
7<br />
PP2V9_SYSCLK<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=2.9V<br />
BYPASS=U1900.17:18:5MM<br />
C1900<br />
2.2UF<br />
20%<br />
6.3V<br />
X5R-CERM<br />
0201<br />
SYSCLK_CLK32K_PCH<br />
19<br />
SYSCLK_CLK32K_CAMERA_BT_AP_SOC 19<br />
SYSCLK_CLK24M_PCH<br />
19<br />
NC_SYSCLK_CLK24M_CAMERA 19<br />
SYSCLK_CLK24M_SSD<br />
81<br />
SYSCLK_CLK12M_SMC<br />
1<br />
2<br />
48<br />
100<br />
IN<br />
PP1V8_S0<br />
2<br />
S<br />
1<br />
G<br />
Q1930<br />
DMP31D0UFB4<br />
DFN1006H4-3<br />
SPI_DESCRIPTOR_OVERRIDE_L<br />
SPI_DESCRIPTOR_OVERRIDE<br />
PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.<br />
If high, ME is disabled. This allows for full re-flashing of SPI ROM.<br />
SMC controls strap enable to allow in-field control of strap setting.<br />
***** Circuit does not support HDA voltage >3.3V.<br />
D<br />
3<br />
IN<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
48<br />
1<br />
R1930<br />
1K<br />
HDA_SDOUT_R<br />
PCH IPD = 9-50k<br />
OUT<br />
13<br />
19<br />
D<br />
2 4<br />
1 3<br />
CRITICAL<br />
Y1900<br />
24MHZ-10PPM-8PF-40OHM<br />
2.5X2.0MM-SM<br />
NO STUFF<br />
1<br />
R1901<br />
1M<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
4<br />
9<br />
14<br />
18<br />
C<br />
CRITICAL<br />
C1908<br />
9.5PF<br />
1 2<br />
SYSCLK_CLK24M_X1<br />
C<br />
+/-0.1PF<br />
50V<br />
CER-C0G<br />
0201<br />
NOTE: 30 PPM or better required for SKL PCH<br />
PCIe Wake Muxing<br />
B<br />
35<br />
IN<br />
101<br />
PP3V3_S5<br />
1<br />
R1910<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
C1910 1<br />
0.1UF<br />
2<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
AP_PCIE_WAKE_L<br />
6 SEL<br />
1 VCC<br />
CRITICAL<br />
U1910<br />
PI5A3157B<br />
DFN<br />
B1 2<br />
1<br />
GND 5<br />
0<br />
3 A<br />
B0 4<br />
AP_S0IX_WAKE_SEL<br />
SEL OUTPUT<br />
L PCIE_WAKE_L (B0)<br />
H AP_S0IX_WAKE_L (B1)<br />
AP_S0IX_WAKE_L<br />
PCIE_WAKE_L<br />
IN<br />
OUT<br />
OUT<br />
16<br />
16<br />
14<br />
B<br />
VER 1<br />
A<br />
BOM_COST_GROUP=CPU & CHIPSET<br />
SYNC_MASTER=J79_GREG<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
Chipset Support 1<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
19 OF 145<br />
18 OF 119<br />
SYNC_DATE=09/09/2015<br />
SIZE<br />
D<br />
A
SYNC_MASTER=J79_GREG<br />
SYNC_DATE=07/05/2016<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
C<br />
B<br />
A<br />
104 35 14<br />
101<br />
A<br />
K<br />
2<br />
2<br />
Platform Reset Connections<br />
PCIE CLKREQS<br />
ENABLE DDPB DDPC INTERFACES<br />
Power State Debug LEDs<br />
(For development only)<br />
PP3V3_S5<br />
PLT_RST_L<br />
2.2K R2050<br />
PP3V3_S0 5 13 14 16 19 94 101<br />
PP3V3_S0 5 13 14 16 19 94 101<br />
Unbuffered<br />
100K R2000<br />
TBT_T_CLKREQ_L<br />
T208 PCH GPIO PUs/PDs & ALIASES<br />
HDA_SYNC_R<br />
DBGLED_S5<br />
SOC_SWD_CLK<br />
Desense Decoupling Caps on HDA Lines<br />
104 77 48 14<br />
104 77 74 48 43 14<br />
104 92 80 77 74 73 48 26 14<br />
1<br />
MF 201 1/20W 5%<br />
2.2K R2051<br />
1<br />
2<br />
IN<br />
R2080 47K 1 2<br />
R2081 47K 1 2<br />
R2082 47K 1 2<br />
R2083 47K 1 2<br />
1<br />
MF<br />
104 74 48 14<br />
201 1/20W 5%<br />
PCH_DDPB_CTRLDATA<br />
PCH_DDPC_CTRLDATA<br />
PP1V8_SUS 8 14 100<br />
R2054 100K 1 2<br />
R2055 100K 1 2<br />
R2056 100K 1 2<br />
R2053 100K 1 2<br />
NOSTUFF<br />
C2020<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
DBGLED<br />
D2090<br />
DBGLED<br />
R2090 1<br />
20K<br />
5%<br />
1/20W<br />
MF<br />
201 2<br />
GRN-90MCD-5MA-2.85V<br />
0402<br />
PLACE_SIDE=BOTTOM<br />
SILK_PART=S5_ON<br />
IN<br />
IN<br />
IN<br />
IN<br />
5% 1/20W MF<br />
PM_SLP_S5_L<br />
PM_SLP_S4_L<br />
PM_SLP_S3_L<br />
PM_SLP_S0_L<br />
SSD_CLKREQ_L<br />
TBT_X_CLKREQ_L<br />
AP_CLKREQ_L<br />
5% 1/20W MF 201<br />
5%<br />
5% 1/20W<br />
5%<br />
NOSTUFF<br />
1<br />
C2050<br />
100PF<br />
5%<br />
2<br />
25V<br />
C0G<br />
0201<br />
DBGLED_S4<br />
1/20W MF<br />
1<br />
2<br />
DBGLED_S4_D<br />
DBGLED<br />
37<br />
42<br />
14<br />
14<br />
HDA_SDOUT_R<br />
NOSTUFF<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
MF<br />
C2021<br />
201<br />
1/20W MF 201<br />
5% 1/20W MF 201<br />
5%<br />
5% 1/20W MF 201<br />
2<br />
2<br />
2<br />
1/20W MF<br />
100K<br />
100K<br />
100K<br />
100K<br />
201<br />
201<br />
201<br />
1<br />
1<br />
1<br />
R2001<br />
5% 1/20W<br />
R2002<br />
28<br />
94<br />
5% 1/20W MF 201<br />
R2003<br />
1/20W MF<br />
R2004<br />
5% 1/20W MF<br />
SOC_PANIC_L<br />
SOC_PCH_DBELL_L<br />
PCH_SOC_DBELL<br />
13 13 18<br />
A<br />
K<br />
DBGLED<br />
D2091<br />
2<br />
DBGLED<br />
R2091 1<br />
20K 5%<br />
1/20W<br />
MF<br />
201 2<br />
GRN-90MCD-5MA-2.85V<br />
0402<br />
PLACE_SIDE=BOTTOM<br />
SILK_PART=STBY_ON<br />
Q2090<br />
DMN5L06VK-7<br />
SOT563<br />
2<br />
2<br />
VER 3<br />
G<br />
D<br />
S<br />
1<br />
1<br />
6<br />
DBGLED_S3<br />
26<br />
92<br />
SOC_S2R_ACK_L<br />
SOC_TO_STOCKHOLM_EN<br />
1<br />
5%<br />
5%<br />
13<br />
13<br />
A<br />
K<br />
1/20W MF 201<br />
5%<br />
5%<br />
MF<br />
TBT_X_PCI_RESET_L<br />
TBT_T_PCI_RESET_L<br />
AP_RESET_L<br />
PCH_SOC_DFU_STATUS<br />
SSD_RESET_L<br />
SMC_LRESET_L<br />
R2086 1K<br />
1 2<br />
5% 1/20W MF<br />
5% 1/20W MF<br />
DBGLED<br />
D2092<br />
201<br />
201<br />
201<br />
R2084 1K<br />
1 2<br />
1/20W MF 201<br />
R2085 1K<br />
1 2<br />
1/20W MF 201<br />
HDA_RST_R_L<br />
1<br />
2<br />
201<br />
R2087 1K<br />
1 2<br />
201<br />
NOSTUFF<br />
C2022<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
DBGLED<br />
R2092 1<br />
20K<br />
5%<br />
1/20W<br />
MF<br />
201 2<br />
GRN-90MCD-5MA-2.85V<br />
0402<br />
PLACE_SIDE=BOTTOM<br />
SILK_PART=S3_ON<br />
DBGLED_S3_D<br />
DBGLED<br />
Q2090<br />
DMN5L06VK-7<br />
SOT563<br />
VER 3<br />
5<br />
G<br />
13<br />
13<br />
13<br />
38<br />
38<br />
37<br />
37<br />
D<br />
S<br />
38<br />
3<br />
4<br />
15<br />
15<br />
15<br />
15<br />
SSD_CLKREQ_L_R<br />
TBT_X_CLKREQ_L_R<br />
TBT_T_CLKREQ_L_R<br />
AP_CLKREQ_L_R<br />
MAKE_BASE=TRUE<br />
SOC_PCH_DBELL_L<br />
MAKE_BASE=TRUE<br />
PCH_SOC_DBELL<br />
MAKE_BASE=TRUE<br />
SOC_SWD_CLK<br />
A<br />
K<br />
DBGLED_S0I3<br />
DBGLED_S0I3_D<br />
DBGLED<br />
MAKE_BASE=TRUE<br />
TBT_X_PCI_RESET_L<br />
MAKE_BASE=TRUE<br />
TBT_T_PCI_RESET_L<br />
CATERR PU<br />
PP1V0_S3 6 8 10 14 101<br />
R2059 51 1 2<br />
WIFI GPIO PD<br />
R2058 100K 1 2<br />
13<br />
DBGLED<br />
D2093<br />
16<br />
16<br />
48<br />
35<br />
91<br />
36<br />
104<br />
GRN-90MCD-5MA-2.85V<br />
0402<br />
OUT<br />
OUT<br />
OUT<br />
PLACE_SIDE=BOTTOM<br />
SILK_PART=S0I3_ON<br />
Q2091<br />
DMN5L06VK-7<br />
SOT563<br />
DBGLED<br />
R20931 20K<br />
5%<br />
1/20W<br />
MF<br />
201 2<br />
VER 3<br />
2<br />
G<br />
D<br />
S<br />
6<br />
1<br />
MAKE_BASE=TRUE<br />
SSD_CLKREQ_L_R<br />
MAKE_BASE=TRUE<br />
TBT_X_CLKREQ_L_R<br />
MAKE_BASE=TRUE<br />
TBT_T_CLKREQ_L_R<br />
MAKE_BASE=TRUE<br />
AP_CLKREQ_L_R<br />
5%<br />
1/20W<br />
DBGLED_S0<br />
CPU_CATERR_L<br />
MF<br />
16<br />
16<br />
201<br />
PCH_BT_ROM_BOOT<br />
5% 1/20W MF 201<br />
A<br />
K<br />
DBGLED<br />
D2095<br />
0402<br />
DBGLED<br />
R20951 20K<br />
5%<br />
1/20W<br />
MF<br />
201 2<br />
GRN-90MCD-5MA-2.85V<br />
PLACE_SIDE=BOTTOM<br />
SILK_PART=S0_ON<br />
OUT<br />
OUT<br />
DBGLED_S0_D<br />
DBGLED<br />
Q2091<br />
DMN5L06VK-7<br />
SOT563<br />
VER 3<br />
5<br />
G<br />
D<br />
S<br />
3<br />
4<br />
6<br />
14<br />
48<br />
35<br />
104 88 87 86 85 84 82 81<br />
16<br />
35<br />
16<br />
16<br />
18<br />
18<br />
18<br />
NO_TEST=1<br />
BT_I2S_SYNC_1V8<br />
BT_I2S_R2D_1V8<br />
BT_I2S_D2R_1V8<br />
BT_I2S_CLK_1V8<br />
MAKE_BASE=TRUE<br />
NC_PPVIOE_CAMCLK<br />
MAKE_BASE=TRUE<br />
PP1V8_SSD_COLD<br />
GREENCLK VIOEs<br />
GREENCLK CLOCK OUT ALIASES<br />
MAKE_BASE=TRUE<br />
SYSCLK_CLK32K_PCH<br />
NC_PCH_CLK32K_RTCX2<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
SYSCLK_CLK24M_PCH<br />
MAKE_BASE=TRUE<br />
SYSCLK_CLK32K_CAMERA_BT_AP_SOC<br />
SYSCLK_CLK32K_CAMERA_BT_AP_SOC<br />
SYSCLK_CLK32K_OSC_OUT<br />
100<br />
PP1V8_S0<br />
PCH_SSD_SOC_UART_D2R PCH_SSD_SOC_UART_D2R<br />
PCH_SSD_SOC_UART_R2D PCH_SSD_SOC_UART_R2D<br />
DEBUGUART_SEL_SOC<br />
101<br />
106<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
NOSTUFF<br />
R2010<br />
NOSTUFF<br />
R2044<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
100<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
0<br />
0<br />
1 2<br />
1 2<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
PP3V3_S0<br />
100<br />
101<br />
PP1V8_S0<br />
BT_I2S_R2D_1V8<br />
BT_I2S_D2R_1V8<br />
MAKE_BASE=TRUE<br />
BT_I2S_CLK_1V8<br />
35<br />
BT_I2S_SYNC_1V8<br />
18<br />
18<br />
NC_PPVIOE_CAMCLK 18<br />
PP1V0_SUS<br />
PP1V8_S4<br />
PD_PPVIOE_SSDCLK 18 19<br />
PCH_CLK:GRNCLK<br />
R2066 1<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
1<br />
2<br />
SYSCLK_CLK32K_PCH<br />
NC_PCH_CLK32K_RTCX2<br />
R2024<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
PCH_CLK24M_XTALIN<br />
SYSCLK_CLK32K_WIFIBT<br />
SOC_PMU_CLK_32K<br />
x100 I2S Level Translator<br />
12<br />
2<br />
3<br />
4<br />
5<br />
NOSTUFF<br />
C2002<br />
0.1UF<br />
PLACE_NEAR=U1900.3:5MM<br />
NOSTUFF<br />
R2042<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
R2043<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
1<br />
2<br />
0<br />
C2010<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
BYPASS=U1900.02:18:5MM<br />
BYPASS=U1900.12:18:5MM<br />
BYPASS=U1900.15:18:5MM<br />
1<br />
U2010<br />
NLSX5014MU_G<br />
UQFN<br />
6<br />
11<br />
C2001<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
BT/SSD DEBUG UART MUX<br />
1<br />
2<br />
1<br />
2<br />
10<br />
C2060<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
5% 1/20W<br />
MF<br />
5% 1/20W MF<br />
9<br />
0201<br />
R2068 1<br />
0 2<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
U2060<br />
PI3USB102EZLE<br />
TQFN<br />
3<br />
PP3V3_S0 101<br />
10<br />
9<br />
8<br />
7<br />
R2060 1<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
NO STUFF<br />
0<br />
R2067 1 2<br />
5<br />
4<br />
7<br />
6<br />
8<br />
NO STUFF<br />
1<br />
C2011 1<br />
0.1UF<br />
10%<br />
2<br />
6.3V<br />
CERM-X5R<br />
0201<br />
C2000<br />
0.1UF<br />
10%<br />
2<br />
6.3V<br />
CERM-X5R<br />
0201<br />
15<br />
BT_I2S_SYNC<br />
BT_I2S_R2D<br />
16 IN<br />
OUT 35<br />
BT_I2S_D2R<br />
16 OUT<br />
IN 35<br />
BT_I2S_CLK<br />
16 BI<br />
BI 35<br />
13<br />
BI<br />
IN<br />
IN<br />
IN<br />
IN<br />
1<br />
R2061<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
15<br />
15<br />
35<br />
37<br />
41<br />
SSD_DBG_UART_D2R<br />
SSD_DBG_UART_R2D_R<br />
SOC_DBG_UART_D2R<br />
SOC_DBG_UART_R2D<br />
35<br />
R2062 1<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
12<br />
12<br />
12 8<br />
12<br />
12<br />
12<br />
12<br />
12 8<br />
VOLTAGE=1.0V<br />
BOM_COST_GROUP=CPU & CHIPSET<br />
Voltage Props<br />
PP1V_SUS_PCH_VCCCLK2_F<br />
VOLTAGE=1.0V<br />
PP1V_SUS_PCH_VCCCLK4_F<br />
VOLTAGE=1.0V<br />
PP1V_SUS_PCH_VCCCLK5_F<br />
VOLTAGE=1.0V<br />
PP1V_S5_PCH_DCPDSW<br />
VOLTAGE=1.0V<br />
PP1V_SUS_PCH_VCCAPLL_F<br />
VOLTAGE=1.0V<br />
PP1V_SUSSW_PCH_VCCAMPHYPLL_F<br />
VOLTAGE=1.8V<br />
PP1V8_SUS_PCH_VCC1P8<br />
VOLTAGE=1.8V<br />
PP1V8_S0_PCH_VCCHDA_F<br />
VOLTAGE=3.0V<br />
PPDCPRTC_PCH<br />
12 IN<br />
15<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
16<br />
16<br />
16<br />
16<br />
16<br />
13<br />
13<br />
16<br />
16<br />
1<br />
R2063<br />
100K<br />
84<br />
88<br />
42<br />
42<br />
88<br />
104<br />
PD_AP_DEV_WAKE<br />
PU_AUD_SPI_CS_L<br />
PD_AUD_SPI_CLK<br />
PD_AUD_SPI_MISO<br />
PU_AUD_SPI_MOSI<br />
PD_LCD_PSR_EN<br />
PD_SSD_UART_CTS_L<br />
PU_SOC_UART_RTS_L<br />
PD_SOC_UART_CTS_L<br />
13<br />
19<br />
5<br />
13<br />
13<br />
15<br />
15<br />
14<br />
15 NC_SPKR_ID0<br />
15<br />
15<br />
15<br />
15<br />
16<br />
16<br />
16<br />
18<br />
13<br />
13<br />
8<br />
Unused GPIOs with PUs/PDs<br />
NC_USB3_04_D2RP<br />
NC_USB3_04_R2DN<br />
NC_USB3_04_R2DP<br />
NC_PCH_STRP_TLSCONF<br />
NC_PCH_STRP_BSSB_SEL_GPIO<br />
NC_PCH_CLKOUT_LPC1<br />
13<br />
8<br />
13<br />
18<br />
13<br />
13<br />
13<br />
15<br />
15<br />
15<br />
15<br />
16<br />
15<br />
PD_PPVIOE_SSDCLK<br />
ALS_SOC_UART_R2D<br />
NC_PCH_CLKREQ4_L<br />
NC_PCIE_CLK100M5N<br />
NC_PCIE_CLK100M5P<br />
NC_PCH_CLKREQ5_L<br />
NC_PCH_BSSB_DATA<br />
NC_ITPXDP_CLK100M_N<br />
NC_UPC_I2C_INT_L<br />
NC_I2C_UPC_SCL<br />
NC_PCH_STRP_ESPI<br />
NC_VCCPRIM_CORE_VID0<br />
NC_VCCPRIM_CORE_VID1<br />
NC_CAMERA_RESET_L<br />
SIGNAL ALIASES<br />
NC_SPKR_ID1<br />
NC_PCH_CLK24M_XTALOUT<br />
NC_PCH_GPP_E15<br />
NC_PCH_BSSB_CLK<br />
NC_USB3_04_D2RN<br />
NC_I2C_UPC_SDA<br />
CAMERA_PWR_EN<br />
ALS_SOC_UART_D2R<br />
NC_ITPXDP_CLK100M_P<br />
NC_MLB_DEV_L<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
NC_SYSCLK_CLK24M_CAMERA<br />
15<br />
15<br />
15<br />
NC SIGNAL ALIASES<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY lovehuongs@yahoo.com APPLE<br />
INC. THE POSESSOR AGREES TO THE<br />
I TO thienhuong nguyen DOCUMENT IN CONFIDENCE<br />
NO TEST<br />
PD_AP_DEV_WAKE<br />
PU_AUD_SPI_CS_L<br />
PD_AUD_SPI_CLK<br />
PD_AUD_SPI_MISO<br />
PU_AUD_SPI_MOSI<br />
PD_LCD_PSR_EN<br />
PD_SSD_UART_CTS_L<br />
PU_SOC_UART_RTS_L<br />
PD_SOC_UART_CTS_L<br />
MAKE_BASE=TRUE<br />
PD_PPVIOE_SSDCLK<br />
MAKE_BASE=TRUE<br />
CAMERA_PWR_EN<br />
MAKE_BASE=TRUE<br />
ALS_SOC_UART_D2R<br />
MAKE_BASE=TRUE<br />
ALS_SOC_UART_R2D<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
NC_USB3_04_R2DN<br />
MAKE_BASE=TRUE<br />
NC_USB3_04_R2DP<br />
MAKE_BASE=TRUE<br />
NC_I2C_UPC_SDA<br />
MAKE_BASE=TRUE<br />
NC_I2C_UPC_SCL<br />
MAKE_BASE=TRUE<br />
NC_MLB_DEV_L<br />
MAKE_BASE=TRUE<br />
NC_PCH_STRP_TLSCONF<br />
MAKE_BASE=TRUE<br />
NC_PCH_STRP_ESPI<br />
MAKE_BASE=TRUE<br />
NC_PCH_CLKOUT_LPC1<br />
MAKE_BASE=TRUE<br />
NC_CAMERA_RESET_L<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NC_PCH_CLKREQ4_L<br />
MAKE_BASE=TRUE<br />
NC_PCIE_CLK100M5N<br />
MAKE_BASE=TRUE<br />
NC_PCIE_CLK100M5P<br />
MAKE_BASE=TRUE<br />
NC_PCH_CLKREQ5_L<br />
MAKE_BASE=TRUE<br />
NC_SPKR_ID1<br />
MAKE_BASE=TRUE<br />
NC_PCH_CLK24M_XTALOUT<br />
MAKE_BASE=TRUE<br />
NC_PCH_GPP_E15<br />
MAKE_BASE=TRUE<br />
NC_PCH_BSSB_CLK<br />
MAKE_BASE=TRUE<br />
NC_PCH_BSSB_DATA<br />
MAKE_BASE=TRUE<br />
NC_ITPXDP_CLK100M_N<br />
MAKE_BASE=TRUE<br />
NC_ITPXDP_CLK100M_P<br />
MAKE_BASE=TRUE<br />
NC_UPC_I2C_INT_L<br />
MAKE_BASE=TRUE<br />
NC_SPKR_ID0<br />
MAKE_BASE=TRUE<br />
NC_USB3_04_D2RN<br />
MAKE_BASE=TRUE<br />
NC_USB3_04_D2RP<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
NC_USB2_10N<br />
NC_USB2_10P<br />
NC_USB2_05N<br />
NC_USB2_05P<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NC_SYSCLK_CLK24M_CAMERA<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NC_PCH_STRP_BSSB_SEL_GPIO<br />
MAKE_BASE=TRUE<br />
NC_VCCPRIM_CORE_VID0<br />
MAKE_BASE=TRUE<br />
NC_VCCPRIM_CORE_VID1<br />
Chipset Support 2<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
EN<br />
IOLV[1]<br />
IOLV[2]<br />
IOLV[3]<br />
IOLV[4]<br />
Y+<br />
Y-<br />
SEL<br />
VL<br />
GND<br />
VCC<br />
GND<br />
VCC<br />
IOVCC[1]<br />
IOVCC[2]<br />
IOVCC[3]<br />
IOVCC[4]<br />
M+<br />
M-<br />
D+<br />
D-<br />
OE*<br />
OUT<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
BI<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
OUT<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
IN<br />
IN<br />
IN<br />
IN<br />
REVISION<br />
BRANCH<br />
13<br />
42<br />
42<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
DRAWING NUMBER<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
20 OF 145<br />
19 OF 119<br />
SIZE<br />
D<br />
D<br />
C<br />
B<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
D<br />
CPU-Based Margining<br />
VRef Dividers<br />
PP1V2_S3 100<br />
C<br />
B<br />
7<br />
7<br />
7<br />
IN<br />
IN<br />
IN<br />
CPU_DIMMA_VREFDQ<br />
CPU_DIMMB_VREFDQ<br />
CPU_DIMM_VREFCA<br />
NOTE: CPU has single output for VREFCA.<br />
VREFCA. Connected to 4 DRAMs.<br />
1<br />
2<br />
1<br />
2<br />
1<br />
2<br />
R2223<br />
10<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
C2220<br />
0.022UF<br />
10%<br />
6.3V<br />
X5R-CERM<br />
0201<br />
MEM_VREFDQ_A_RC<br />
R2243<br />
10<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
C2240<br />
0.022UF<br />
10%<br />
6.3V<br />
X5R-CERM<br />
0201<br />
MEM_VREFDQ_B_RC<br />
R2263<br />
5.1<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
0201<br />
C2260<br />
0.022UF<br />
10%<br />
6.3V<br />
X5R-CERM<br />
0201<br />
MEM_VREFCA_RC<br />
PLACE_NEAR=R2221.2:1mm<br />
R22221 8.2K<br />
1%<br />
1/20W<br />
201<br />
MF<br />
2<br />
R2220<br />
24.9<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
PLACE_NEAR=R2241.2:1mm<br />
R2242 1<br />
8.2K<br />
1%<br />
1/20W<br />
201<br />
MF<br />
2<br />
R2240<br />
24.9<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
PLACE_NEAR=R2261.2:1mm<br />
R2262 1<br />
8.2K<br />
1%<br />
1/20W<br />
MF<br />
201 2<br />
R2260<br />
24.9<br />
1 2<br />
1/20W 1%<br />
MF<br />
201<br />
1<br />
R2221<br />
8.2K<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
PP0V6_S3_MEM_VREFDQ_A 100<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
1<br />
R2241<br />
8.2K<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
PP0V6_S3_MEM_VREFDQ_B 100<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
1<br />
R2261<br />
8.2K<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
PP0V6_S3_MEM_VREFCA_A 100<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
C<br />
B<br />
A<br />
BOM_COST_GROUP=CPU & CHIPSET<br />
SYNC_MASTER=J52_MLB<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
LPDDR3 VREF Margining<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
SYNC_DATE=05/12/2015<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
22 OF 145<br />
20 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
LPDDR3 CHANNEL A (0-31)<br />
D<br />
C<br />
B<br />
R2300 1<br />
243<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
R2301 1<br />
243<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
C2340 1 2<br />
0.047UF<br />
10%<br />
6.3V<br />
X5R<br />
201<br />
1<br />
2<br />
100<br />
24<br />
23<br />
25 22 7<br />
25 22 7<br />
25 22 7<br />
22<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
0.047UF<br />
10%<br />
6.3V<br />
X5R<br />
201<br />
100 22<br />
100 22<br />
C2341<br />
21<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
PP1V2_S3<br />
MEM_A_CAA<br />
MEM_A_CAA<br />
MEM_A_CAA<br />
MEM_A_CAA<br />
MEM_A_CAA<br />
MEM_A_CAA<br />
MEM_A_CAA<br />
MEM_A_CAA<br />
MEM_A_CAA<br />
MEM_A_CAA<br />
MEM_A_CKE<br />
MEM_A_CKE<br />
MEM_A_CLK_P<br />
MEM_A_CLK_N<br />
MEM_A_CS_L<br />
MEM_A_CS_L<br />
MEM_A_ODT<br />
MEM_A_ZQ<br />
MEM_A_ZQ<br />
PP0V6_S3_MEM_VREFCA_A<br />
PP0V6_S3_MEM_VREFDQ_A<br />
1<br />
2<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
R2<br />
P2<br />
N2<br />
N3<br />
M3<br />
F3<br />
E3<br />
E2<br />
D2<br />
C2<br />
K3<br />
K4<br />
J3<br />
J2<br />
L3<br />
L4<br />
L8<br />
G8<br />
P8<br />
D8<br />
J8<br />
B3<br />
B4<br />
H4<br />
J11<br />
A1<br />
A2<br />
A12<br />
A13<br />
B1<br />
B13<br />
T1<br />
T13<br />
U1<br />
U2<br />
U12<br />
U13<br />
C2300<br />
0.1UF<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
CA0<br />
CA1<br />
CA2<br />
CA3<br />
CA4<br />
CA5<br />
CA6<br />
CA7<br />
CA8<br />
CA9<br />
CKE0<br />
CKE1<br />
CK_T<br />
CK_C<br />
CS0*<br />
CS1*<br />
DM0<br />
DM1<br />
DM2<br />
DM3<br />
ODT<br />
ZQ0<br />
ZQ1<br />
VREFCA<br />
VREFDQ<br />
NU<br />
1<br />
2<br />
U2300<br />
LPDDR3-1600-32GB<br />
EDFB232A1MA<br />
FBGA<br />
SYM 1 OF 2<br />
OMIT_TABLE<br />
CRITICAL<br />
C2301<br />
0.1UF<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
1<br />
1UF<br />
DQ0<br />
DQ1<br />
DQ2<br />
DQ3<br />
DQ4<br />
DQ5<br />
DQ6<br />
DQ7<br />
DQ8<br />
DQ9<br />
DQ10<br />
DQ11<br />
DQ12<br />
DQ13<br />
DQ14<br />
DQ15<br />
DQ16<br />
DQ17<br />
DQ18<br />
DQ19<br />
DQ20<br />
DQ21<br />
DQ22<br />
DQ23<br />
DQ24<br />
DQ25<br />
DQ26<br />
DQ27<br />
DQ28<br />
DQ29<br />
DQ30<br />
DQ31<br />
DQS0_C<br />
DQS1_C<br />
DQS2_C<br />
DQS3_C<br />
DQS0_T<br />
DQS1_T<br />
DQS2_T<br />
DQS3_T<br />
NC<br />
C2302<br />
P9<br />
N9<br />
N10<br />
N11<br />
M8<br />
M9<br />
M10<br />
M11<br />
F11<br />
F10<br />
F9<br />
F8<br />
E11<br />
E10<br />
E9<br />
D9<br />
T8<br />
T9<br />
T10<br />
T11<br />
R8<br />
R9<br />
R10<br />
R11<br />
C11<br />
C10<br />
C9<br />
C8<br />
B11<br />
B10<br />
B9<br />
B8<br />
L11<br />
G11<br />
P11<br />
D11<br />
L10<br />
G10<br />
P10<br />
D10<br />
C4<br />
K9<br />
R3<br />
1<br />
NC<br />
NC<br />
NC<br />
C2303<br />
1UF<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQS_N<br />
MEM_A_DQS_N<br />
MEM_A_DQS_N<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P<br />
MEM_A_DQS_P<br />
MEM_A_DQS_P<br />
MEM_A_DQS_P<br />
1<br />
C2304<br />
1UF<br />
20%<br />
20%<br />
20%<br />
20%<br />
20%<br />
20%<br />
2<br />
10V<br />
10V<br />
2<br />
10V<br />
2<br />
10V<br />
X5R<br />
2 X5R<br />
X5R<br />
X5R<br />
2<br />
10V<br />
10V<br />
X5R-CERM<br />
2 X5R-CERM<br />
0201<br />
0201<br />
0201<br />
0201<br />
0402-7<br />
0402-7<br />
1<br />
1UF<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
C2305<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
1<br />
C2306<br />
10UF<br />
1<br />
100<br />
100<br />
100<br />
100<br />
10UF<br />
24<br />
24<br />
24<br />
24<br />
C2307<br />
23<br />
23<br />
23<br />
23<br />
22<br />
22<br />
22<br />
22<br />
21<br />
21<br />
21<br />
21<br />
1<br />
2<br />
PP1V8_S3_MEM<br />
PP1V2_S3<br />
PP1V2_S3<br />
PP1V2_S3<br />
CRITICAL<br />
C2334<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
A3<br />
A4<br />
A5<br />
A6<br />
A10<br />
U3<br />
U4<br />
U5<br />
U6<br />
U10<br />
A8<br />
A9<br />
D4<br />
D5<br />
D6<br />
G5<br />
H5<br />
H6<br />
H12<br />
J5<br />
J6<br />
K5<br />
K6<br />
K12<br />
L5<br />
P4<br />
P5<br />
P6<br />
U8<br />
U9<br />
F2<br />
G2<br />
H3<br />
L2<br />
M2<br />
A11<br />
C12<br />
E8<br />
E12<br />
G12<br />
H8<br />
H9<br />
H11<br />
J9<br />
J10<br />
K8<br />
K11<br />
L12<br />
N8<br />
N12<br />
R12<br />
U11<br />
U2300<br />
LPDDR3-1600-32GB<br />
EDFB232A1MA<br />
FBGA<br />
SYM 2 OF 2<br />
VDD1<br />
VSS<br />
OMIT_TABLE<br />
CRITICAL<br />
VDD2<br />
VSSCA<br />
VDDCA<br />
VSSQ<br />
VDDQ<br />
B2<br />
B5<br />
C5<br />
E4<br />
E5<br />
F5<br />
J12<br />
K2<br />
L6<br />
M5<br />
N4<br />
N5<br />
R4<br />
R5<br />
T2<br />
T3<br />
T4<br />
T5<br />
H2<br />
C3<br />
D3<br />
F4<br />
G3<br />
G4<br />
P3<br />
M4<br />
J4<br />
B6<br />
B12<br />
C6<br />
D12<br />
E6<br />
F6<br />
F12<br />
G6<br />
G9<br />
H10<br />
K10<br />
L9<br />
M6<br />
M12<br />
N6<br />
P12<br />
R6<br />
T6<br />
T12<br />
C<br />
B<br />
100<br />
24<br />
23<br />
22<br />
21<br />
PP1V2_S3<br />
1<br />
2<br />
C2320<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
1<br />
2<br />
C2321<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
1<br />
2<br />
C2322<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
1<br />
C2323<br />
10UF<br />
C2324<br />
10UF<br />
20%<br />
20%<br />
2<br />
10V<br />
X5R-CERM<br />
2<br />
10V<br />
X5R-CERM<br />
0402-7<br />
0402-7<br />
1<br />
1<br />
2<br />
CRITICAL<br />
C2335<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C2336<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C2337<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
A<br />
100<br />
100<br />
24<br />
24<br />
23<br />
23<br />
22<br />
22<br />
21<br />
21<br />
PP1V2_S3<br />
PP1V8_S3_MEM<br />
1<br />
2<br />
1<br />
C2310<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
C2330<br />
1UF<br />
1<br />
1<br />
C2311<br />
1UF<br />
20%<br />
2<br />
10V<br />
X5R<br />
0201<br />
C2331<br />
1UF<br />
C2332<br />
10UF<br />
20%<br />
20%<br />
20%<br />
2<br />
10V<br />
X5R<br />
2<br />
10V<br />
X5R<br />
2<br />
10V<br />
X5R-CERM<br />
0201<br />
0201<br />
0402-7<br />
1<br />
2<br />
1<br />
C2312<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
1<br />
2<br />
C2333<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
1<br />
2<br />
PLACEMENT_NOTE:<br />
10uF caps are shared between DRAM.<br />
Distribute evenly.<br />
CRITICAL<br />
C2338<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C2339<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
BOM_COST_GROUP=DRAM<br />
SYNC_MASTER=J52_MLB<br />
SYNC_DATE=05/12/2015<br />
LPDDR3 DRAM Channel A (00-31)<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
23 OF 145<br />
21 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
LPDDR3 CHANNEL A (32-63)<br />
D<br />
C<br />
B<br />
R2400 1<br />
243<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
R2401 1<br />
243<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
C2440 1 2<br />
0.047UF<br />
10%<br />
6.3V<br />
X5R<br />
201<br />
1<br />
2<br />
100<br />
10%<br />
6.3V<br />
X5R<br />
201<br />
24<br />
23<br />
25 21 7<br />
25 21 7<br />
22<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 21 7<br />
100 21<br />
100 21<br />
C2441<br />
0.047UF<br />
21<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
PP1V2_S3<br />
MEM_A_CAB<br />
MEM_A_CAB<br />
MEM_A_CAB<br />
MEM_A_CAB<br />
MEM_A_CAB<br />
MEM_A_CAB<br />
MEM_A_CAB<br />
MEM_A_CAB<br />
MEM_A_CAB<br />
MEM_A_CAB<br />
MEM_A_CKE<br />
MEM_A_CKE<br />
MEM_A_CLK_P<br />
MEM_A_CLK_N<br />
MEM_A_CS_L<br />
MEM_A_CS_L<br />
MEM_A_ODT<br />
MEM_A_ZQ<br />
MEM_A_ZQ<br />
PP0V6_S3_MEM_VREFCA_A<br />
PP0V6_S3_MEM_VREFDQ_A<br />
1<br />
2<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
C2400<br />
0.1UF<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
R2<br />
P2<br />
N2<br />
N3<br />
M3<br />
F3<br />
E3<br />
E2<br />
D2<br />
C2<br />
K3<br />
K4<br />
J3<br />
J2<br />
L3<br />
L4<br />
L8<br />
G8<br />
P8<br />
D8<br />
J8<br />
B3<br />
B4<br />
H4<br />
J11<br />
A1<br />
A2<br />
A12<br />
A13<br />
B1<br />
B13<br />
T1<br />
T13<br />
U1<br />
U2<br />
U12<br />
U13<br />
CA0<br />
CA1<br />
CA2<br />
CA3<br />
CA4<br />
CA5<br />
CA6<br />
CA7<br />
CA8<br />
CA9<br />
CKE0<br />
CKE1<br />
CK_T<br />
CK_C<br />
CS0*<br />
CS1*<br />
DM0<br />
DM1<br />
DM2<br />
DM3<br />
ODT<br />
ZQ0<br />
ZQ1<br />
VREFCA<br />
VREFDQ<br />
NU<br />
1<br />
2<br />
LPDDR3-1600-32GB<br />
EDFB232A1MA<br />
OMIT_TABLE<br />
CRITICAL<br />
C2401<br />
0.1UF<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
U2400<br />
FBGA<br />
SYM 1 OF 2<br />
1<br />
2<br />
C2402<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
DQ0<br />
DQ1<br />
DQ2<br />
DQ3<br />
DQ4<br />
DQ5<br />
DQ6<br />
DQ7<br />
DQ8<br />
DQ9<br />
DQ10<br />
DQ11<br />
DQ12<br />
DQ13<br />
DQ14<br />
DQ15<br />
DQ16<br />
DQ17<br />
DQ18<br />
DQ19<br />
DQ20<br />
DQ21<br />
DQ22<br />
DQ23<br />
DQ24<br />
DQ25<br />
DQ26<br />
DQ27<br />
DQ28<br />
DQ29<br />
DQ30<br />
DQ31<br />
DQS0_C<br />
DQS1_C<br />
DQS2_C<br />
DQS3_C<br />
DQS0_T<br />
DQS1_T<br />
DQS2_T<br />
DQS3_T<br />
NC<br />
P9<br />
N9<br />
N10<br />
N11<br />
M8<br />
M9<br />
M10<br />
M11<br />
F11<br />
F10<br />
F9<br />
F8<br />
E11<br />
E10<br />
E9<br />
D9<br />
T8<br />
T9<br />
T10<br />
T11<br />
R8<br />
R9<br />
R10<br />
R11<br />
C11<br />
C10<br />
C9<br />
C8<br />
B11<br />
B10<br />
B9<br />
B8<br />
L11<br />
G11<br />
P11<br />
D11<br />
L10<br />
G10<br />
P10<br />
D10<br />
C4<br />
K9<br />
R3<br />
1<br />
2<br />
NC<br />
NC<br />
NC<br />
C2403<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQS_N<br />
MEM_A_DQS_N<br />
MEM_A_DQS_N<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P<br />
MEM_A_DQS_P<br />
MEM_A_DQS_P<br />
MEM_A_DQS_P<br />
1<br />
2<br />
C2404<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
1<br />
2<br />
C2405<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
1<br />
2<br />
C2406<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
1<br />
2<br />
100<br />
100<br />
100<br />
100<br />
10UF<br />
24<br />
24<br />
24<br />
24<br />
C2407<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
23<br />
23<br />
23<br />
23<br />
22<br />
22<br />
22<br />
22<br />
21<br />
21<br />
21<br />
21<br />
PP1V8_S3_MEM<br />
PP1V2_S3<br />
PP1V2_S3<br />
PP1V2_S3<br />
A3<br />
A4<br />
A5<br />
A6<br />
A10<br />
U3<br />
U4<br />
U5<br />
U6<br />
U10<br />
A8<br />
A9<br />
D4<br />
D5<br />
D6<br />
G5<br />
H5<br />
H6<br />
H12<br />
J5<br />
J6<br />
K5<br />
K6<br />
K12<br />
L5<br />
P4<br />
P5<br />
P6<br />
U8<br />
U9<br />
F2<br />
G2<br />
H3<br />
L2<br />
M2<br />
A11<br />
C12<br />
E8<br />
E12<br />
G12<br />
H8<br />
H9<br />
H11<br />
J9<br />
J10<br />
K8<br />
K11<br />
L12<br />
N8<br />
N12<br />
R12<br />
U11<br />
U2400<br />
LPDDR3-1600-32GB<br />
EDFB232A1MA<br />
FBGA<br />
SYM 2 OF 2<br />
VDD1<br />
VSS<br />
OMIT_TABLE<br />
CRITICAL<br />
VDD2<br />
VSSCA<br />
VDDCA<br />
VSSQ<br />
VDDQ<br />
B2<br />
B5<br />
C5<br />
E4<br />
E5<br />
F5<br />
J12<br />
K2<br />
L6<br />
M5<br />
N4<br />
N5<br />
R4<br />
R5<br />
T2<br />
T3<br />
T4<br />
T5<br />
H2<br />
C3<br />
D3<br />
F4<br />
G3<br />
G4<br />
P3<br />
M4<br />
J4<br />
B6<br />
B12<br />
C6<br />
D12<br />
E6<br />
F6<br />
F12<br />
G6<br />
G9<br />
H10<br />
K10<br />
L9<br />
M6<br />
M12<br />
N6<br />
P12<br />
R6<br />
T6<br />
T12<br />
C<br />
B<br />
100<br />
24<br />
23<br />
22<br />
21<br />
PP1V2_S3<br />
1<br />
2<br />
C2420<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
1<br />
2<br />
C2421<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
1<br />
2<br />
C2422<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
1<br />
2<br />
C2423<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
1<br />
2<br />
C2424<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
1<br />
2<br />
CRITICAL<br />
C2434<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C2435<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C2436<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
A<br />
100<br />
100<br />
24<br />
24<br />
23<br />
23<br />
22<br />
22<br />
21<br />
21<br />
PP1V2_S3<br />
PP1V8_S3_MEM<br />
1<br />
2<br />
1<br />
2<br />
C2410<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
C2430<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
1<br />
2<br />
1<br />
2<br />
C2411<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
C2431<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
1<br />
C2412<br />
10UF<br />
20%<br />
2<br />
10V<br />
X5R-CERM<br />
0402-7<br />
1<br />
2<br />
C2432<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
1<br />
2<br />
C2433<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
1<br />
2<br />
PLACEMENT_NOTE:<br />
10uF caps are shared between DRAM.<br />
Distribute evenly.<br />
CRITICAL<br />
C2437<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
BOM_COST_GROUP=DRAM<br />
SYNC_MASTER=J52_MLB<br />
SYNC_DATE=05/12/2015<br />
LPDDR3 DRAM Channel A (32-63)<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
24 OF 145<br />
22 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
LPDDR3 CHANNEL B (0-31)<br />
D<br />
C<br />
B<br />
R2500 1<br />
243<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
R2501 1<br />
243<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
C2540 1 2<br />
0.047UF<br />
10%<br />
6.3V<br />
X5R<br />
201<br />
1<br />
2<br />
100<br />
24<br />
100<br />
10%<br />
6.3V<br />
X5R<br />
201<br />
23<br />
25 24 7<br />
25 24 7<br />
24<br />
22<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 24 7<br />
100 24<br />
C2541<br />
0.047UF<br />
PP0V6_S3_MEM_VREFCA_A<br />
PP0V6_S3_MEM_VREFDQ_B<br />
21<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
PP1V2_S3<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_CKE<br />
MEM_B_CKE<br />
MEM_B_CLK_P<br />
MEM_B_CLK_N<br />
MEM_B_CS_L<br />
MEM_B_CS_L<br />
MEM_B_ODT<br />
MEM_B_ZQ<br />
MEM_B_ZQ<br />
1<br />
2<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
C2500<br />
0.1UF<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
R2<br />
P2<br />
N2<br />
N3<br />
M3<br />
F3<br />
E3<br />
E2<br />
D2<br />
C2<br />
K3<br />
K4<br />
J3<br />
J2<br />
L3<br />
L4<br />
L8<br />
G8<br />
P8<br />
D8<br />
J8<br />
B3<br />
B4<br />
H4<br />
J11<br />
A1<br />
A2<br />
A12<br />
A13<br />
B1<br />
B13<br />
T1<br />
T13<br />
U1<br />
U2<br />
U12<br />
U13<br />
CA0<br />
CA1<br />
CA2<br />
CA3<br />
CA4<br />
CA5<br />
CA6<br />
CA7<br />
CA8<br />
CA9<br />
CKE0<br />
CKE1<br />
CK_T<br />
CK_C<br />
CS0*<br />
CS1*<br />
DM0<br />
DM1<br />
DM2<br />
DM3<br />
ODT<br />
ZQ0<br />
ZQ1<br />
VREFCA<br />
VREFDQ<br />
NU<br />
1<br />
2<br />
LPDDR3-1600-32GB<br />
EDFB232A1MA<br />
OMIT_TABLE<br />
CRITICAL<br />
C2501<br />
0.1UF<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
U2500<br />
FBGA<br />
SYM 1 OF 2<br />
1<br />
2<br />
C2502<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
DQ0<br />
DQ1<br />
DQ2<br />
DQ3<br />
DQ4<br />
DQ5<br />
DQ6<br />
DQ7<br />
DQ8<br />
DQ9<br />
DQ10<br />
DQ11<br />
DQ12<br />
DQ13<br />
DQ14<br />
DQ15<br />
DQ16<br />
DQ17<br />
DQ18<br />
DQ19<br />
DQ20<br />
DQ21<br />
DQ22<br />
DQ23<br />
DQ24<br />
DQ25<br />
DQ26<br />
DQ27<br />
DQ28<br />
DQ29<br />
DQ30<br />
DQ31<br />
DQS0_C<br />
DQS1_C<br />
DQS2_C<br />
DQS3_C<br />
DQS0_T<br />
DQS1_T<br />
DQS2_T<br />
DQS3_T<br />
NC<br />
P9<br />
N9<br />
N10<br />
N11<br />
M8<br />
M9<br />
M10<br />
M11<br />
F11<br />
F10<br />
F9<br />
F8<br />
E11<br />
E10<br />
E9<br />
D9<br />
T8<br />
T9<br />
T10<br />
T11<br />
R8<br />
R9<br />
R10<br />
R11<br />
C11<br />
C10<br />
C9<br />
C8<br />
B11<br />
B10<br />
B9<br />
B8<br />
L11<br />
G11<br />
P11<br />
D11<br />
L10<br />
G10<br />
P10<br />
D10<br />
C4<br />
K9<br />
R3<br />
1<br />
2<br />
NC<br />
NC<br />
NC<br />
C2503<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQS_N<br />
MEM_B_DQS_N<br />
MEM_B_DQS_N<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQS_P<br />
MEM_B_DQS_P<br />
MEM_B_DQS_P<br />
1<br />
2<br />
C2504<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
1<br />
2<br />
C2505<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
1<br />
2<br />
C2506<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
1<br />
2<br />
100 24 23<br />
100 24 23<br />
100 24 23<br />
100 24 23<br />
C2507<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
22<br />
22<br />
22<br />
22<br />
21<br />
21<br />
21<br />
21<br />
PP1V8_S3_MEM<br />
PP1V2_S3<br />
PP1V2_S3<br />
PP1V2_S3<br />
A3<br />
A4<br />
A5<br />
A6<br />
A10<br />
U3<br />
U4<br />
U5<br />
U6<br />
U10<br />
A8<br />
A9<br />
D4<br />
D5<br />
D6<br />
G5<br />
H5<br />
H6<br />
H12<br />
J5<br />
J6<br />
K5<br />
K6<br />
K12<br />
L5<br />
P4<br />
P5<br />
P6<br />
U8<br />
U9<br />
F2<br />
G2<br />
H3<br />
L2<br />
M2<br />
A11<br />
C12<br />
E8<br />
E12<br />
G12<br />
H8<br />
H9<br />
H11<br />
J9<br />
J10<br />
K8<br />
K11<br />
L12<br />
N8<br />
N12<br />
R12<br />
U11<br />
VDD1<br />
VDD2<br />
VDDCA<br />
VDDQ<br />
U2500<br />
LPDDR3-1600-32GB<br />
EDFB232A1MA<br />
FBGA<br />
SYM 2 OF 2<br />
OMIT_TABLE<br />
CRITICAL<br />
VSS<br />
VSSCA<br />
VSSQ<br />
B2<br />
B5<br />
C5<br />
E4<br />
E5<br />
F5<br />
J12<br />
K2<br />
L6<br />
M5<br />
N4<br />
N5<br />
R4<br />
R5<br />
T2<br />
T3<br />
T4<br />
T5<br />
H2<br />
C3<br />
D3<br />
F4<br />
G3<br />
G4<br />
P3<br />
M4<br />
J4<br />
B6<br />
B12<br />
C6<br />
D12<br />
E6<br />
F6<br />
F12<br />
G6<br />
G9<br />
H10<br />
K10<br />
L9<br />
M6<br />
M12<br />
N6<br />
P12<br />
R6<br />
T6<br />
T12<br />
C<br />
B<br />
100<br />
24<br />
23<br />
22<br />
21<br />
PP1V2_S3<br />
1<br />
2<br />
C2520<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
1<br />
2<br />
C2521<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
1<br />
2<br />
C2522<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
1<br />
2<br />
C2523<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
1<br />
2<br />
C2524<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
1<br />
2<br />
CRITICAL<br />
C2534<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C2535<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C2536<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
A<br />
100<br />
100<br />
24<br />
24<br />
23<br />
23<br />
22<br />
22<br />
21<br />
21<br />
PP1V2_S3<br />
PP1V8_S3_MEM<br />
1<br />
2<br />
1<br />
2<br />
C2510<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
C2530<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
1<br />
2<br />
1<br />
2<br />
C2511<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
C2531<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
1<br />
C2512<br />
10UF<br />
20%<br />
2<br />
10V<br />
X5R-CERM<br />
0402-7<br />
1<br />
2<br />
C2532<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
1<br />
2<br />
C2533<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
1<br />
2<br />
PLACEMENT_NOTE:<br />
10uF caps are shared between DRAM.<br />
Distribute evenly.<br />
CRITICAL<br />
C2537<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
BOM_COST_GROUP=DRAM<br />
SYNC_MASTER=J52_MLB<br />
SYNC_DATE=05/12/2015<br />
LPDDR3 DRAM Channel B (00-31)<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
25 OF 145<br />
23 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
LPDDR3 CHANNEL B (32-63)<br />
D<br />
C<br />
B<br />
R2600 1<br />
243<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
R2601 1<br />
243<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
C2640 1 2<br />
0.047UF<br />
10%<br />
6.3V<br />
X5R<br />
201<br />
1<br />
2<br />
100<br />
24<br />
100<br />
10%<br />
6.3V<br />
X5R<br />
201<br />
23<br />
25 23 7<br />
25 23 7<br />
23<br />
22<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 7<br />
25 23 7<br />
100 23<br />
C2641<br />
0.047UF<br />
PP0V6_S3_MEM_VREFCA_A<br />
PP0V6_S3_MEM_VREFDQ_B<br />
21<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
PP1V2_S3<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CKE<br />
MEM_B_CKE<br />
MEM_B_CLK_P<br />
MEM_B_CLK_N<br />
MEM_B_CS_L<br />
MEM_B_CS_L<br />
MEM_B_ODT<br />
MEM_B_ZQ<br />
MEM_B_ZQ<br />
1<br />
2<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
C2600<br />
0.1UF<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
R2<br />
P2<br />
N2<br />
N3<br />
M3<br />
F3<br />
E3<br />
E2<br />
D2<br />
C2<br />
K3<br />
K4<br />
J3<br />
J2<br />
L3<br />
L4<br />
L8<br />
G8<br />
P8<br />
D8<br />
J8<br />
B3<br />
B4<br />
H4<br />
J11<br />
A1<br />
A2<br />
A12<br />
A13<br />
B1<br />
B13<br />
T1<br />
T13<br />
U1<br />
U2<br />
U12<br />
U13<br />
CA0<br />
CA1<br />
CA2<br />
CA3<br />
CA4<br />
CA5<br />
CA6<br />
CA7<br />
CA8<br />
CA9<br />
CKE0<br />
CKE1<br />
CK_T<br />
CK_C<br />
CS0*<br />
CS1*<br />
DM0<br />
DM1<br />
DM2<br />
DM3<br />
ODT<br />
ZQ0<br />
ZQ1<br />
VREFCA<br />
VREFDQ<br />
NU<br />
1<br />
2<br />
LPDDR3-1600-32GB<br />
EDFB232A1MA<br />
C2601<br />
0.1UF<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
U2600<br />
FBGA<br />
SYM 1 OF 2<br />
OMIT_TABLE<br />
CRITICAL<br />
1<br />
2<br />
C2602<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
DQ0<br />
DQ1<br />
DQ2<br />
DQ3<br />
DQ4<br />
DQ5<br />
DQ6<br />
DQ7<br />
DQ8<br />
DQ9<br />
DQ10<br />
DQ11<br />
DQ12<br />
DQ13<br />
DQ14<br />
DQ15<br />
DQ16<br />
DQ17<br />
DQ18<br />
DQ19<br />
DQ20<br />
DQ21<br />
DQ22<br />
DQ23<br />
DQ24<br />
DQ25<br />
DQ26<br />
DQ27<br />
DQ28<br />
DQ29<br />
DQ30<br />
DQ31<br />
DQS0_C<br />
DQS1_C<br />
DQS2_C<br />
DQS3_C<br />
DQS0_T<br />
DQS1_T<br />
DQS2_T<br />
DQS3_T<br />
NC<br />
P9<br />
N9<br />
N10<br />
N11<br />
M8<br />
M9<br />
M10<br />
M11<br />
F11<br />
F10<br />
F9<br />
F8<br />
E11<br />
E10<br />
E9<br />
D9<br />
T8<br />
T9<br />
T10<br />
T11<br />
R8<br />
R9<br />
R10<br />
R11<br />
C11<br />
C10<br />
C9<br />
C8<br />
B11<br />
B10<br />
B9<br />
B8<br />
L11<br />
G11<br />
P11<br />
D11<br />
L10<br />
G10<br />
P10<br />
D10<br />
C4<br />
K9<br />
R3<br />
1<br />
2<br />
NC<br />
NC<br />
NC<br />
C2603<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQS_N<br />
MEM_B_DQS_N<br />
MEM_B_DQS_N<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQS_P<br />
MEM_B_DQS_P<br />
MEM_B_DQS_P<br />
1<br />
2<br />
C2604<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
1<br />
2<br />
C2605<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
103<br />
1<br />
2<br />
C2606<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
1<br />
2<br />
100 24 23<br />
100 24 23<br />
100 24 23<br />
100 24 23<br />
C2607<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
22<br />
22<br />
22<br />
22<br />
21<br />
21<br />
21<br />
21<br />
PP1V8_S3_MEM<br />
PP1V2_S3<br />
PP1V2_S3<br />
PP1V2_S3<br />
A3<br />
A4<br />
A5<br />
A6<br />
A10<br />
U3<br />
U4<br />
U5<br />
U6<br />
U10<br />
A8<br />
A9<br />
D4<br />
D5<br />
D6<br />
G5<br />
H5<br />
H6<br />
H12<br />
J5<br />
J6<br />
K5<br />
K6<br />
K12<br />
L5<br />
P4<br />
P5<br />
P6<br />
U8<br />
U9<br />
F2<br />
G2<br />
H3<br />
L2<br />
M2<br />
A11<br />
C12<br />
E8<br />
E12<br />
G12<br />
H8<br />
H9<br />
H11<br />
J9<br />
J10<br />
K8<br />
K11<br />
L12<br />
N8<br />
N12<br />
R12<br />
U11<br />
VDD1<br />
VDD2<br />
VDDCA<br />
VDDQ<br />
U2600<br />
LPDDR3-1600-32GB<br />
EDFB232A1MA<br />
FBGA<br />
SYM 2 OF 2<br />
OMIT_TABLE<br />
CRITICAL<br />
VSS<br />
VSSCA<br />
VSSQ<br />
B2<br />
B5<br />
C5<br />
E4<br />
E5<br />
F5<br />
J12<br />
K2<br />
L6<br />
M5<br />
N4<br />
N5<br />
R4<br />
R5<br />
T2<br />
T3<br />
T4<br />
T5<br />
H2<br />
C3<br />
D3<br />
F4<br />
G3<br />
G4<br />
P3<br />
M4<br />
J4<br />
B6<br />
B12<br />
C6<br />
D12<br />
E6<br />
F6<br />
F12<br />
G6<br />
G9<br />
H10<br />
K10<br />
L9<br />
M6<br />
M12<br />
N6<br />
P12<br />
R6<br />
T6<br />
T12<br />
C<br />
B<br />
100<br />
24<br />
23<br />
22<br />
21<br />
PP1V2_S3<br />
1<br />
2<br />
C2620<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
1<br />
2<br />
C2621<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
1<br />
2<br />
C2622<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
1<br />
2<br />
C2623<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
1<br />
2<br />
C2624<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
1<br />
2<br />
CRITICAL<br />
C2634<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C2635<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C2636<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
A<br />
100<br />
100<br />
24<br />
24<br />
23<br />
23<br />
22<br />
22<br />
21<br />
21<br />
PP1V2_S3<br />
PP1V8_S3_MEM<br />
1<br />
2<br />
1<br />
2<br />
C2610<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
C2630<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
1<br />
2<br />
1<br />
2<br />
C2611<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
C2631<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
1<br />
2<br />
1<br />
2<br />
C2612<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
C2632<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
1<br />
2<br />
C2633<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
1<br />
2<br />
PLACEMENT_NOTE:<br />
10uF caps are shared between DRAM.<br />
Distribute evenly.<br />
CRITICAL<br />
C2637<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
BOM_COST_GROUP=DRAM<br />
SYNC_MASTER=J52_MLB<br />
SYNC_DATE=05/12/2015<br />
LPDDR3 DRAM Channel B (32-63)<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
26 OF 145<br />
24 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
Intel recommends 68 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK<br />
100<br />
PP0V6_S0_DDRVTT<br />
100<br />
PP0V6_S0_DDRVTT<br />
D<br />
C<br />
21 7<br />
21 7<br />
21 7<br />
21 7<br />
21 7<br />
21 7<br />
21 7<br />
21 7<br />
21 7<br />
21 7<br />
21 7<br />
21 7<br />
21 7<br />
21 7<br />
22 7<br />
22 7<br />
22 7<br />
22 7<br />
22 7<br />
22 7<br />
22 7<br />
22 7<br />
22 7<br />
22 7<br />
22 7<br />
22 7<br />
22 7<br />
22 7<br />
22 21 7<br />
22 21 7<br />
22 21 7<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
MEM_A_CAA<br />
MEM_A_CAA<br />
MEM_A_CAA<br />
MEM_A_CAA<br />
MEM_A_CAA<br />
MEM_A_CLK_P<br />
MEM_A_CLK_N<br />
MEM_A_CKE<br />
MEM_A_CKE<br />
MEM_A_CAA<br />
MEM_A_CAA<br />
MEM_A_CAA<br />
MEM_A_CAA<br />
MEM_A_CAA<br />
MEM_A_CAB<br />
MEM_A_CAB<br />
MEM_A_CAB<br />
MEM_A_CAB<br />
MEM_A_CAB<br />
MEM_A_CLK_P<br />
MEM_A_CLK_N<br />
MEM_A_CKE<br />
MEM_A_CKE<br />
MEM_A_CAB<br />
MEM_A_CAB<br />
MEM_A_CAB<br />
MEM_A_CAB<br />
MEM_A_CAB<br />
MEM_A_CS_L<br />
MEM_A_CS_L<br />
MEM_A_ODT<br />
R2700 1 2<br />
68<br />
R2701 68 1 2<br />
R2702 68 1 2<br />
R2703 68 1 2<br />
R2704 68 1 2<br />
R2705 39 1 2<br />
R2706 39 1 2<br />
R2707 82 1 2<br />
R2708 82 1 2<br />
R2709 68 1 2<br />
R2710 68 1 2<br />
R2711 68 1 2<br />
R2712 68 1 2<br />
R2713 68 1 2<br />
R2714 68 1 2<br />
R2715 68 1 2<br />
R2716 68 1 2<br />
R2717 68 1 2<br />
R2718 68 1 2<br />
R2719 39 1 2<br />
R2720 39 1 2<br />
R2721 82 1 2<br />
R2722 82 1 2<br />
R2723 68 1 2<br />
R2724 68 1 2<br />
R2725 68 1 2<br />
R2726 68 1 2<br />
R2727 68 1 2<br />
R2728 82 1 2<br />
R2729 82 1 2<br />
82<br />
R2730 1 2<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1<br />
1<br />
2<br />
1<br />
2<br />
1<br />
1<br />
1<br />
2<br />
C2700<br />
0.47UF<br />
20%<br />
2<br />
4V<br />
CERM-X5R-1<br />
201<br />
C2701<br />
0.47UF<br />
20%<br />
4V<br />
CERM-X5R-1<br />
201<br />
C2703<br />
0.47UF<br />
20%<br />
4V<br />
CERM-X5R-1<br />
201<br />
C2705<br />
0.47UF<br />
C2707<br />
0.47UF<br />
20%<br />
2<br />
4V<br />
CERM-X5R-1<br />
201<br />
C2709<br />
0.47UF<br />
20%<br />
4V<br />
CERM-X5R-1<br />
201<br />
1<br />
1<br />
C2730<br />
12PF<br />
5%<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
C2706<br />
0.47UF<br />
20%<br />
20%<br />
2<br />
4V<br />
CERM-X5R-1 2<br />
4V<br />
CERM-X5R-1<br />
201<br />
201<br />
1<br />
2<br />
1<br />
2<br />
1<br />
C2702<br />
0.47UF<br />
20%<br />
4V<br />
CERM-X5R-1<br />
201<br />
C2704<br />
0.47UF<br />
20%<br />
4V<br />
CERM-X5R-1<br />
201<br />
C2708<br />
0.47UF<br />
20%<br />
2<br />
4V<br />
CERM-X5R-1<br />
201<br />
23 7<br />
23 7<br />
23 7<br />
23 7<br />
23 7<br />
23 7<br />
23 7<br />
23 7<br />
23 7<br />
23 7<br />
23 7<br />
23 7<br />
23 7<br />
23 7<br />
24 7<br />
24 7<br />
24 7<br />
24 7<br />
24 7<br />
24 7<br />
24 7<br />
24 7<br />
24 7<br />
24 7<br />
24 7<br />
24 7<br />
24 7<br />
24 7<br />
24 23 7<br />
24 23 7<br />
24 23 7<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_CLK_P<br />
MEM_B_CLK_N<br />
MEM_B_CKE<br />
MEM_B_CKE<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_CAA<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CLK_N<br />
MEM_B_CLK_P<br />
MEM_B_CKE<br />
MEM_B_CKE<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CAB<br />
MEM_B_CS_L<br />
MEM_B_CS_L<br />
MEM_B_ODT<br />
R2740 1 2<br />
68<br />
R2741 68 1 2<br />
R2742 68 1 2<br />
R2743 68 1 2<br />
R2744 68 1 2<br />
R2745 39 1 2<br />
R2746 39 1 2<br />
R2747 82 1 2<br />
R2748 82 1 2<br />
R2749 68 1 2<br />
R2750 68 1 2<br />
R2751 68 1 2<br />
R2752 68 1 2<br />
R2753 68 1 2<br />
R2754 68 1 2<br />
R2755 68 1 2<br />
R2756 68 1 2<br />
R2757 68 1 2<br />
R2758 68 1 2<br />
R2759 39 1 2<br />
R2760 39 1 2<br />
R2761 82 1 2<br />
R2762 82 1 2<br />
R2763 68 1 2<br />
R2764 68 1 2<br />
R2765 68 1 2<br />
R2766 68 1 2<br />
R2767 68 1 2<br />
R2768 82 1 2<br />
R2769 82 1 2<br />
82<br />
R2770 1 2<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1% 1/20W 201 MF<br />
1<br />
2<br />
1<br />
2<br />
1<br />
2<br />
1<br />
2<br />
1<br />
2<br />
1<br />
2<br />
C2710<br />
0.47UF<br />
20%<br />
4V<br />
CERM-X5R-1<br />
201<br />
C2711<br />
0.47UF<br />
20%<br />
4V<br />
CERM-X5R-1<br />
201<br />
C2713<br />
0.47UF<br />
20%<br />
4V<br />
CERM-X5R-1<br />
201<br />
C2715<br />
0.47UF<br />
20%<br />
4V<br />
CERM-X5R-1<br />
201<br />
C2717<br />
0.47UF<br />
20%<br />
4V<br />
CERM-X5R-1<br />
201<br />
C2719<br />
0.47UF<br />
20%<br />
4V<br />
CERM-X5R-1<br />
201<br />
1<br />
2<br />
1<br />
2<br />
1<br />
2<br />
1<br />
2<br />
1<br />
C2731<br />
12PF<br />
5%<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
C2712<br />
0.47UF<br />
20%<br />
4V<br />
CERM-X5R-1<br />
201<br />
C2714<br />
0.47UF<br />
20%<br />
4V<br />
CERM-X5R-1<br />
201<br />
C2716<br />
0.47UF<br />
20%<br />
4V<br />
CERM-X5R-1<br />
201<br />
C2718<br />
0.47UF<br />
20%<br />
4V<br />
CERM-X5R-1<br />
201<br />
C<br />
1<br />
2<br />
CRITICAL<br />
C2720<br />
20UF<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402<br />
1<br />
2<br />
C2722<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C2740<br />
20UF<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402<br />
1<br />
2<br />
C2742<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
B<br />
B<br />
A<br />
BOM_COST_GROUP=DRAM<br />
SYNC_MASTER=J52_MLB<br />
SYNC_DATE=05/12/2015<br />
LPDDR3 DRAM Termination<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
27 OF 145<br />
25 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
PP3V3_UPC_XB_LDO 28<br />
D<br />
1<br />
R2890<br />
3.3K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
28<br />
28<br />
26<br />
TBT_X_ROM_HOLD_L<br />
R2891 1<br />
3.3K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
TBT_X_SPI_CLK<br />
TBT_X_SPI_CS_L<br />
TBT_X_ROM_WP_L<br />
1<br />
R2893<br />
2<br />
3.3K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
6<br />
1<br />
3<br />
7<br />
CLK<br />
CS*<br />
WP*(IO2)<br />
HOLD*(IO3)<br />
8<br />
U2890<br />
8MBIT-3.0V<br />
R2892 1<br />
3.3K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
W25Q80DVUXIE<br />
USON DI(IO0)<br />
DO(IO1)<br />
OMIT_TABLE<br />
CRITICAL<br />
GND<br />
VCC<br />
EPAD<br />
5<br />
2<br />
1<br />
2<br />
C2890<br />
1UF<br />
10%<br />
6.3V<br />
CERM<br />
402<br />
TBT_X_SPI_MOSI<br />
TBT_X_SPI_MISO<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
PCIE_TBT_X_R2D_P<br />
PCIE_TBT_X_R2D_N<br />
PCIE_TBT_X_R2D_P<br />
PCIE_TBT_X_R2D_N<br />
PCIE_TBT_X_R2D_P<br />
PCIE_TBT_X_R2D_N<br />
PCIE_TBT_X_R2D_P<br />
PCIE_TBT_X_R2D_N<br />
Y23<br />
Y22<br />
T23<br />
T22<br />
M23<br />
M22<br />
H23<br />
H22<br />
PCIE_RX0_P<br />
PCIE_RX0_N<br />
PCIE_RX1_P<br />
PCIE_RX1_N<br />
PCIE_RX2_P<br />
PCIE_RX2_N<br />
PCIE_RX3_P<br />
PCIE_RX3_N<br />
U2800<br />
TBT-AR-4C-CNTRL<br />
SYM 1 OF 2<br />
FCBGA<br />
OMIT_TABLE<br />
CRITICAL<br />
PCIE GEN3<br />
PCIE_TX0_P<br />
PCIE_TX0_N<br />
PCIE_TX1_P<br />
PCIE_TX1_N<br />
PCIE_TX2_P<br />
PCIE_TX2_N<br />
PCIE_TX3_P<br />
PCIE_TX3_N<br />
V23<br />
V22<br />
P23<br />
P22<br />
K23<br />
K22<br />
F23<br />
F22<br />
PCIE_TBT_X_D2R_C_P<br />
PCIE_TBT_X_D2R_C_N<br />
PCIE_TBT_X_D2R_C_P<br />
PCIE_TBT_X_D2R_C_N<br />
PCIE_TBT_X_D2R_C_P<br />
PCIE_TBT_X_D2R_C_N<br />
PCIE_TBT_X_D2R_C_P<br />
PCIE_TBT_X_D2R_C_N<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
D<br />
4<br />
9<br />
C<br />
B<br />
A<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
BI<br />
BI<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
BI<br />
BI<br />
100K<br />
1 2<br />
100K<br />
DP_X_SNK0_ML_C_P<br />
DP_X_SNK0_ML_C_N<br />
DP_X_SNK0_ML_C_P<br />
DP_X_SNK0_ML_C_N<br />
DP_X_SNK0_ML_C_P<br />
DP_X_SNK0_ML_C_N<br />
DP_X_SNK0_ML_C_P<br />
DP_X_SNK0_ML_C_N<br />
DP_X_SNK0_AUXCH_C_P<br />
DP_X_SNK0_AUXCH_C_N<br />
DP_X_SNK1_ML_C_P<br />
DP_X_SNK1_ML_C_N<br />
DP_X_SNK1_ML_C_P<br />
DP_X_SNK1_ML_C_N<br />
DP_X_SNK1_ML_C_P<br />
DP_X_SNK1_ML_C_N<br />
DP_X_SNK1_ML_C_P<br />
DP_X_SNK1_ML_C_N<br />
DP_X_SNK1_AUXCH_C_P<br />
DP_X_SNK1_AUXCH_C_N<br />
R2872<br />
1 2<br />
5% 1/20W MF 201<br />
1M<br />
1 2<br />
5%<br />
1M<br />
1 2<br />
5%<br />
1M<br />
R2862<br />
5% 1/20W MF<br />
R2860<br />
1/20W<br />
R2861<br />
1/20W<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
201<br />
MF 201<br />
MF<br />
201<br />
1 2<br />
5% 1/20W MF 201<br />
1M<br />
R2870<br />
R2871<br />
1 2<br />
5% 1/20W MF 201<br />
DP_XA_HPD<br />
DP_XB_HPD<br />
TBT_XA_LSTX<br />
TBT_XA_LSRX<br />
TBT_XB_LSTX<br />
TBT_XB_LSRX<br />
SNK0 AC Coupling<br />
C2<strong>820</strong> 1 2<br />
0.1UF<br />
C2821 1 2<br />
0.1UF<br />
C2822 1 2<br />
0.1UF<br />
C2823 1 2<br />
0.1UF<br />
C2824 1 2<br />
0.1UF<br />
C2825 1 2<br />
0.1UF<br />
C2826 1 2<br />
0.1UF<br />
C2827 1 2<br />
0.1UF<br />
C2828 1 2<br />
0.1UF<br />
C2829 1 2<br />
0.1UF<br />
SNK1 AC Coupling<br />
C2830 1 2<br />
0.1UF<br />
C2831 1 2<br />
0.1UF<br />
C2832 1 2<br />
0.1UF<br />
C2833 1 2<br />
0.1UF<br />
C2834 1 2<br />
0.1UF<br />
C2835 1 2<br />
0.1UF<br />
C2836 1 2<br />
0.1UF<br />
C2837 1 2<br />
0.1UF<br />
C2838 1 2<br />
0.1UF<br />
C2839 1 2<br />
0.1UF<br />
26<br />
26<br />
26<br />
26<br />
29<br />
29<br />
30<br />
30<br />
26<br />
26<br />
28<br />
30<br />
29<br />
10% 16V<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
DP_X_SNK0_ML_P<br />
0201<br />
DP_X_SNK0_ML_N<br />
0201<br />
10% 16V 0201<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
DP_X_SNK0_ML_P<br />
DP_X_SNK0_ML_N<br />
0201<br />
10% 16V 0201<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
DP_X_SNK0_ML_P<br />
DP_X_SNK0_ML_N<br />
0201<br />
DP_X_SNK0_ML_P<br />
0201<br />
10% 16V 0201<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
DP_X_SNK0_ML_N<br />
DP_X_SNK0_AUXCH_P<br />
0201<br />
DP_X_SNK0_AUXCH_N<br />
0201<br />
DP_X_SNK1_ML_P<br />
0201<br />
DP_X_SNK1_ML_N<br />
0201<br />
DP_X_SNK1_ML_P<br />
0201<br />
DP_X_SNK1_ML_N<br />
0201<br />
DP_X_SNK1_ML_P<br />
0201<br />
DP_X_SNK1_ML_N<br />
0201<br />
DP_X_SNK1_ML_P<br />
0201<br />
DP_X_SNK1_ML_N<br />
0201<br />
DP_X_SNK1_AUXCH_P<br />
0201<br />
10% 16V 0201<br />
X5R-CERM<br />
DP_X_SNK1_AUXCH_N<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
29<br />
29<br />
BI<br />
BI<br />
PLACE_NEAR=U2800.H6:2MM<br />
PLACE_NEAR=U2800.J6:2MM<br />
DP_XA_AUXCH_P<br />
DP_XA_AUXCH_N<br />
34 28<br />
2<br />
0201 16V 10%<br />
X5R-CERM<br />
10K PU ON CLOCKS PAGE<br />
34 28<br />
OUT<br />
R2831 1<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
TF<br />
OUT<br />
1 2<br />
1/20W<br />
R2855<br />
GND_VOID=TRUE<br />
C2810<br />
0.1UF<br />
C2811<br />
2 1<br />
0201 16V 10%<br />
X5R-CERM 0.1UF<br />
GND_VOID=TRUE<br />
PLACE_NEAR=U2800.H19:2MM<br />
R2830 1<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201 2<br />
1<br />
R2854 1<br />
499<br />
1%<br />
1/20W<br />
MF 2<br />
201<br />
4.75K<br />
0.5%<br />
0201<br />
105 15<br />
105 15<br />
19<br />
28<br />
28<br />
28<br />
28<br />
2 1<br />
14K 1% 201 MF<br />
1/20W<br />
R2850<br />
31<br />
31<br />
31<br />
31<br />
28<br />
28<br />
PCIE_CLK100M_TBT_X_P<br />
PCIE_CLK100M_TBT_X_N<br />
TBT_X_CLKREQ_L<br />
94 92 28<br />
DP_X_SNK0_ML_P<br />
DP_X_SNK0_ML_N<br />
DP_X_SNK0_ML_P<br />
DP_X_SNK0_ML_N<br />
DP_X_SNK0_ML_P<br />
DP_X_SNK0_ML_N<br />
DP_X_SNK0_ML_P<br />
DP_X_SNK0_ML_N<br />
DP_X_SNK0_AUXCH_P<br />
DP_X_SNK0_AUXCH_N<br />
DP_X_SNK0_HPD<br />
DP_X_SNK0_DDC_CLK<br />
DP_X_SNK0_DDC_DATA<br />
DP_X_SNK1_ML_P<br />
DP_X_SNK1_ML_N<br />
DP_X_SNK1_ML_P<br />
DP_X_SNK1_ML_N<br />
DP_X_SNK1_ML_P<br />
DP_X_SNK1_ML_N<br />
DP_X_SNK1_ML_P<br />
DP_X_SNK1_ML_N<br />
DP_X_SNK1_AUXCH_P<br />
DP_X_SNK1_AUXCH_N<br />
DP_X_SNK1_HPD<br />
DP_X_SNK1_DDC_CLK<br />
DP_X_SNK1_DDC_DATA<br />
94 92<br />
94 92<br />
DP_X_SNK_RBIAS<br />
JTAG_TBT_TDI<br />
IN<br />
JTAG_TBT_X_TMS<br />
IN<br />
JTAG_TBT_TCK<br />
IN<br />
JTAG_ISP_TDO<br />
OUT<br />
TBT_X_RBIAS<br />
TBT_X_RSENSE<br />
USBC_XA_D2R_P<br />
USBC_XA_D2R_N<br />
USBC_XA_R2D_C_P<br />
USBC_XA_R2D_C_N<br />
USBC_XA_R2D_C_P<br />
USBC_XA_R2D_C_N<br />
USBC_XA_D2R_P<br />
USBC_XA_D2R_N<br />
DP_XA_AUXCH_C_P<br />
DP_XA_AUXCH_C_N<br />
USB_UPC_XA_P<br />
USB_UPC_XA_N<br />
29 26 TBT_XA_LSTX<br />
OUT<br />
29 26 TBT_XA_LSRX<br />
IN<br />
29 28 26 DP_XA_HPD<br />
IN<br />
TBT_XA_USB2_RBIAS<br />
56<br />
31<br />
31<br />
31<br />
31<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
BI<br />
IN<br />
BI<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
BI<br />
BI<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
28<br />
TBTTHMSNS_D1_P<br />
USE NEAREST GND BALL<br />
(AC22) FOR THERM_D_N<br />
V19<br />
T19<br />
AC5<br />
AB7<br />
AC7<br />
AB9<br />
AC9<br />
AB11<br />
AC11<br />
AB13<br />
AC13<br />
Y11<br />
W11<br />
AA2<br />
Y5<br />
R4<br />
AB15<br />
AC15<br />
AB17<br />
AC17<br />
AB19<br />
AC19<br />
AB21<br />
AC21<br />
Y12<br />
W12<br />
Y6<br />
Y8<br />
N4<br />
Y18<br />
PLACE_NEAR=U2800.Y18:2MM<br />
Y4<br />
V4<br />
T4<br />
W4<br />
H6<br />
J6<br />
A15<br />
B15<br />
A17<br />
B17<br />
A19<br />
B19<br />
B21<br />
A21<br />
Y15<br />
W15<br />
E20<br />
D20<br />
A5<br />
A4<br />
M4<br />
H19<br />
AC23<br />
AB23<br />
V18<br />
AC1<br />
L15<br />
N15<br />
C23<br />
C22<br />
PCIE_REFCLK_100_IN_P<br />
PCIE_REFCLK_100_IN_N<br />
PCIE_CLKREQ*<br />
L4<br />
N16<br />
R2<br />
R1<br />
N2<br />
N1<br />
L2<br />
L1<br />
J2<br />
J1<br />
W19<br />
Y19<br />
G1<br />
N6<br />
U1<br />
U2<br />
V1<br />
V2<br />
W1<br />
W2<br />
Y1<br />
Y2<br />
AA1<br />
J4<br />
E2<br />
D4<br />
H4<br />
F2<br />
D2<br />
F1<br />
E1<br />
AB5<br />
F4<br />
D22<br />
D23<br />
AB3<br />
AC4<br />
AC3<br />
AB4<br />
B7<br />
A7<br />
A9<br />
B9<br />
A11<br />
B11<br />
A13<br />
B13<br />
Y16<br />
W16<br />
E19<br />
D19<br />
B4<br />
B5<br />
G2<br />
F19<br />
D6<br />
A23<br />
B23<br />
E18<br />
W13<br />
W18<br />
AB2<br />
TBT_X_PCI_RESET_L<br />
TBT_X_PCIE_BIAS<br />
NC_DP_X_SRC_ML_P<br />
NC_DP_X_SRC_ML_N<br />
NC_DP_X_SRC_ML_P<br />
NC_DP_X_SRC_ML_N<br />
NC_DP_X_SRC_ML_P<br />
NC_DP_X_SRC_ML_N<br />
NC_DP_X_SRC_ML_P<br />
NC_DP_X_SRC_ML_N<br />
NC_DP_X_SRC_AUX_P<br />
NC_DP_X_SRC_AUX_N<br />
DP_X_SRC_HPD<br />
DP_X_SRC_RBIAS<br />
I2C_TBT_X_SDA<br />
I2C_TBT_X_SCL<br />
TBT_X_ROM_WP_L<br />
26<br />
TBT_X_TMU_CLK_OUT<br />
SMC_PME_S4_DARK_L<br />
TBT_X_CIO_PLUG_EVENT_L<br />
DDI1_MUX_SEL<br />
DDI2_MUX_SEL<br />
TBT_X_TMU_CLK_IN<br />
I2C_TBT_XA_INT_L<br />
I2C_TBT_XB_INT_L<br />
TBT_X_USB_PWR_EN<br />
TBT_X_FORCE_PWR<br />
PM_BATLOW_L<br />
PM_SLP_S3_L<br />
TBT_X_CIO_PWR_EN<br />
TBT_X_TEST_EN<br />
TBT_X_TEST_PWR_GOOD<br />
USBC_X_RESET_L<br />
TBT_X_XTAL25M_IN<br />
TBT_X_XTAL25M_OUT<br />
UPC_X_SPI_MOSI 28<br />
UPC_X_SPI_MISO 28<br />
UPC_X_SPI_CS_L 28<br />
UPC_X_SPI_CLK 28<br />
USBC_XB_D2R_P<br />
USBC_XB_D2R_N<br />
USBC_XB_R2D_C_P<br />
USBC_XB_R2D_C_N<br />
USBC_XB_R2D_C_P<br />
USBC_XB_R2D_C_N<br />
USBC_XB_D2R_P<br />
USBC_XB_D2R_N<br />
DP_XB_AUXCH_C_P<br />
DP_XB_AUXCH_C_N<br />
USB_UPC_XB_P<br />
USB_UPC_XB_N<br />
TBT_XB_LSTX<br />
TBT_XB_LSRX<br />
DP_XB_HPD<br />
TBT_XB_USB2_RBIAS<br />
BOM_COST_GROUP=TBT<br />
28<br />
28<br />
28<br />
28<br />
PLACE_NEAR=U2800.F19:2MM<br />
1<br />
R2853<br />
499<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
28<br />
26<br />
26<br />
26<br />
30<br />
30<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
32<br />
To SPI Flash<br />
30<br />
31<br />
31<br />
31<br />
31<br />
31<br />
31<br />
31<br />
31<br />
19<br />
28<br />
28<br />
28<br />
28<br />
34<br />
94<br />
28<br />
28<br />
14<br />
28<br />
29<br />
PLACE_NEAR=<br />
U2800.N6:2MM<br />
R2852<br />
1<br />
1/20W MF 201<br />
2<br />
1%<br />
34<br />
92<br />
29<br />
19<br />
30<br />
30<br />
PU at PCH<br />
48<br />
14K<br />
73<br />
PU at PCH<br />
1<br />
R2829<br />
100<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
GND_VOID=TRUE<br />
C2812 1 2<br />
0.1UF<br />
C2813 1 2<br />
0.1UF<br />
74<br />
GND_VOID=TRUE<br />
3.01K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
77<br />
80<br />
SYNC_MASTER=J79_GREG<br />
PLACE_NEAR=U2800.N16:2MM<br />
R2851<br />
1 2<br />
PP3V3_S5_TBT_X_SW 26 32<br />
1<br />
R2836<br />
2.2K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
92<br />
104<br />
1<br />
R2825<br />
100<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
DP_XB_AUXCH_P<br />
10% 16V<br />
X5R-CERM<br />
DP_XB_AUXCH_N<br />
10% 16V<br />
X5R-CERM<br />
28<br />
0201<br />
0201<br />
PP3V3_S5_TBT_X_SW 26 32<br />
1<br />
R2834<br />
2.2K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
1<br />
R2837<br />
2.2K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
28<br />
not used<br />
1<br />
R2827<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
1<br />
R2835<br />
2.2K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
LAST_MODIFIED=Tue Aug 30 11:06:20 2016<br />
USB-C HIGH SPEED 1<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
NC<br />
DPSNK0_ML0_P<br />
DPSNK0_ML0_N<br />
DPSNK0_ML1_P<br />
DPSNK0_ML1_N<br />
DPSNK0_ML2_P<br />
DPSNK0_ML2_N<br />
DPSNK0_ML3_P<br />
DPSNK0_ML3_N<br />
DPSNK0_AUX_P<br />
DPSNK0_AUX_N<br />
DPSNK0_HPD<br />
DPSNK0_DDC_CLK<br />
DPSNK0_DDC_DATA<br />
DPSNK1_ML0_P<br />
DPSNK1_ML0_N<br />
DPSNK1_ML1_P<br />
DPSNK1_ML1_N<br />
DPSNK1_ML2_P<br />
DPSNK1_ML2_N<br />
DPSNK1_ML3_P<br />
DPSNK1_ML3_N<br />
DPSNK1_AUX_P<br />
DPSNK1_AUX_N<br />
DPSNK1_HPD<br />
DPSNK1_DDC_CLK<br />
DPSNK1_DDC_DATA<br />
DPSNK_RBIAS<br />
TDI<br />
TMS<br />
TCK<br />
TDO<br />
RBIAS<br />
RSENSE<br />
PA_RX1_P<br />
PA_RX1_N<br />
PA_TX1_P<br />
PA_TX1_N<br />
PA_TX0_P<br />
PA_TX0_N<br />
PA_RX0_P<br />
PA_RX0_N<br />
PA_DPSRC_AUX_P<br />
PA_DPSRC_AUX_N<br />
PA_USB2_D_P<br />
PA_USB2_D_N<br />
PA_LSTX<br />
PA_LSRX<br />
PA_DPSRC_HPD<br />
PA_USB2_RBIAS<br />
THERMDA<br />
THERMDA<br />
PCIE_ATEST<br />
TEST_EDM<br />
FUSE_VQPS_64<br />
FUSE_VQPS_128<br />
MONDC_CIO_0<br />
MONDC_CIO_1<br />
SINK PORT 0<br />
SINK PORT 1<br />
PORT A<br />
TBT PORTS<br />
DEBUG<br />
MISC<br />
SOURCE PORT 0<br />
PORT B POC GPIO LC GPIO<br />
PERST*<br />
PCIE_RBIAS<br />
DPSRC_ML0_P<br />
DPSRC_ML0_N<br />
DPSRC_ML1_P<br />
DPSRC_ML1_N<br />
DPSRC_ML2_P<br />
DPSRC_ML2_N<br />
DPSRC_ML3_P<br />
DPSRC_ML3_N<br />
DPSRC_AUX_P<br />
DPSRC_AUX_N<br />
DPSRC_HPD<br />
DPSRC_RBIAS<br />
GPIO_0<br />
GPIO_1<br />
GPIO_2<br />
GPIO_3<br />
GPIO_4<br />
GPIO_5<br />
GPIO_6<br />
GPIO_7<br />
GPIO_8<br />
POC_GPIO_0<br />
POC_GPIO_1<br />
POC_GPIO_2<br />
POC_GPIO_3<br />
POC_GPIO_4<br />
POC_GPIO_5<br />
POC_GPIO_6<br />
TEST_EN<br />
TEST_PWR_GOOD<br />
RESET*<br />
XTAL_25_IN<br />
XTAL_25_OUT<br />
EE_DI<br />
EE_DO<br />
EE_CS*<br />
EE_CLK<br />
PB_RX1_P<br />
PB_RX1_N<br />
PB_TX1_P<br />
PB_TX1_N<br />
PB_TX0_P<br />
PB_TX0_N<br />
PB_RX0_P<br />
PB_RX0_N<br />
PB_DPSRC_AUX_P<br />
PB_DPSRC_AUX_N<br />
PB_USB2_D_P<br />
PB_USB2_D_N<br />
PB_LSTX<br />
PB_LSRX<br />
PB_DPSRC_HPD<br />
PB_USB2_RBIAS<br />
MONDC_SVR<br />
ATEST_P<br />
ATEST_N<br />
USB2_ATEST<br />
MONDC_DPSNK_0<br />
MONDC_DPSNK_1<br />
MONDC_DPSRC<br />
NC<br />
NC<br />
NC<br />
BI<br />
BI<br />
OUT<br />
IN<br />
IN<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
BI<br />
OUT<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
DRAWING<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
IN<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
IN<br />
BI<br />
28<br />
BI<br />
BI<br />
30<br />
30<br />
BI<br />
28<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
SYNC_DATE=07/27/2015<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
28 OF 145<br />
26 OF 119<br />
SIZE<br />
D<br />
C<br />
B<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
C<br />
B<br />
A<br />
1<br />
2<br />
C2930<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
1<br />
2<br />
C2931<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
1<br />
2<br />
1<br />
C2945 1<br />
1.0UF<br />
20%<br />
6.3V<br />
2<br />
X5R<br />
0201-1<br />
C2932<br />
1.0UF<br />
20%<br />
2<br />
6.3V<br />
X5R<br />
0201-1<br />
C2984<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
1<br />
2<br />
1<br />
2<br />
1<br />
2<br />
C2933<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
C2964<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
C2985<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
C2946 1<br />
1.0UF<br />
20%<br />
6.3V<br />
2<br />
X5R<br />
0201-1<br />
1<br />
SOURCED BY INTERNAL SWITCH<br />
1<br />
2<br />
C2947 1<br />
1.0UF<br />
20%<br />
6.3V<br />
2<br />
X5R<br />
0201-1<br />
C2934<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
C2965<br />
1.0UF<br />
20%<br />
20%<br />
2<br />
6.3V<br />
X5R<br />
2<br />
6.3V<br />
X5R<br />
0201-1<br />
0201-1<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
SOURCED BY INTERNAL SWITCH<br />
SOURCED BY INTERNAL SWITCH<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
1<br />
1<br />
2<br />
C2935<br />
C2966<br />
1.0UF<br />
1<br />
2<br />
C2936<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
PP0V9_TBT_X_DP<br />
SOURCED BY INTERNAL SWITCH<br />
1<br />
2<br />
1<br />
2<br />
SOURCED BY INTERNAL SWITCH<br />
C2920<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
28<br />
C2967<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
28<br />
28<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=0.9V<br />
PP0V9_TBT_X_PCIE<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=0.9V<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=0.9V<br />
PP0V9_TBT_X_USB<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=0.9V<br />
PP0V9_TBT_X_CIO<br />
PP3V3_TBT_X_ANA_PCIE<br />
PP3V3_TBT_X_ANA_USB2<br />
1<br />
2<br />
C2921<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
SOURCED BY<br />
INTERNAL SWITCH<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
L8<br />
L11<br />
L12<br />
M8<br />
T11<br />
T12<br />
L6<br />
M6<br />
V11<br />
V12<br />
V13<br />
M13<br />
M15<br />
M16<br />
L19<br />
N19<br />
L18<br />
M18<br />
N18<br />
R15<br />
R16<br />
R8<br />
R9<br />
R11<br />
R12<br />
L16<br />
J16<br />
A6<br />
A8<br />
A10<br />
A12<br />
A14<br />
A16<br />
A18<br />
A20<br />
A22<br />
B6<br />
B8<br />
B10<br />
B12<br />
B14<br />
B16<br />
B18<br />
B20<br />
B22<br />
D8<br />
D9<br />
D11<br />
D12<br />
D13<br />
D15<br />
D16<br />
D18<br />
E8<br />
E9<br />
E11<br />
E15<br />
E16<br />
E22<br />
E23<br />
F9<br />
F20<br />
F16<br />
G22<br />
G23<br />
H1<br />
H2<br />
H12<br />
H13<br />
H15<br />
H16<br />
H20<br />
J5<br />
J19<br />
J20<br />
J18<br />
J22<br />
J23<br />
K1<br />
K2<br />
L5<br />
L20<br />
L22<br />
L23<br />
M1<br />
M2<br />
M5<br />
M19<br />
M20<br />
N5<br />
N20<br />
N22<br />
N23<br />
P1<br />
P2<br />
R5<br />
R18<br />
R19<br />
R20<br />
R22<br />
VCC0P9_DP<br />
VCC0P9_DP<br />
VCC0P9_DP<br />
VCC0P9_DP<br />
VCC0P9_DP<br />
VCC0P9_DP<br />
VCC0P9_ANA_DPSRC<br />
VCC0P9_ANA_DPSRC<br />
VCC0P9_ANA_DPSNK<br />
VCC0P9_ANA_DPSNK<br />
VCC0P9_ANA_DPSNK<br />
VCC0P9_PCIE<br />
VCC0P9_PCIE<br />
VCC0P9_PCIE<br />
VCC0P9_ANA_PCIE_1<br />
VCC0P9_ANA_PCIE_1<br />
VCC0P9_ANA_PCIE_2<br />
VCC0P9_ANA_PCIE_2<br />
VCC0P9_ANA_PCIE_2<br />
VCC0P9_USB<br />
VCC0P9_USB<br />
VCC0P9_CIO<br />
VCC0P9_CIO<br />
VCC0P9_CIO<br />
VCC0P9_CIO<br />
VCC3P3_ANA_PCIE<br />
VCC3P3_ANA_USB2<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
U2800<br />
TBT-AR-4C-CNTRL<br />
SYM 2 OF 2<br />
FCBGA<br />
OMIT_TABLE<br />
CRITICAL<br />
GND VCC<br />
VCC3P3_LC<br />
VCC3P3_SX<br />
VCC3P3_S0<br />
VCC3P3A<br />
VCC3P3_SVR<br />
VCC3P3_SVR<br />
VCC3P3_SVR<br />
VCC0P9_SVR<br />
VCC0P9_SVR<br />
VCC0P9_SVR_ANA<br />
VCC0P9_SVR_ANA<br />
VCC0P9_SVR_ANA<br />
VCC0P9_SVR_ANA<br />
VCC0P9_SVR_ANA<br />
VCC0P9_SVR_ANA<br />
VCC0P9_SVR_SENSE<br />
SVR_IND<br />
SVR_IND<br />
SVR_IND<br />
SVR_VSS<br />
SVR_VSS<br />
SVR_VSS<br />
VCC0P9_LVR<br />
VCC0P9_LVR<br />
VCC0P9_LVR<br />
VCC0P9_LVR_SENSE<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
R6<br />
F8<br />
R13<br />
H9<br />
A2<br />
A3<br />
B3<br />
L9<br />
M9<br />
E12<br />
E13<br />
F11<br />
F12<br />
F13<br />
F15<br />
J9<br />
C1<br />
C2<br />
D1<br />
A1<br />
B1<br />
B2<br />
F18<br />
H18<br />
J11<br />
H11<br />
R23<br />
T1<br />
T2<br />
T5<br />
T20<br />
U23<br />
U22<br />
V5<br />
V6<br />
V8<br />
V9<br />
V15<br />
V16<br />
V20<br />
W5<br />
W6<br />
W8<br />
W9<br />
W20<br />
W22<br />
W23<br />
Y9<br />
Y13<br />
Y20<br />
AA22<br />
AA23<br />
AB6<br />
AB8<br />
AB10<br />
AB12<br />
AB14<br />
AB16<br />
AB18<br />
AB20<br />
AB22<br />
AC6<br />
AC8<br />
AC10<br />
AC12<br />
AC14<br />
AC16<br />
AC18<br />
AC20<br />
AC22<br />
D5<br />
E4<br />
E5<br />
E6<br />
F5<br />
F6<br />
H5<br />
H8<br />
J8<br />
J12<br />
J13<br />
J15<br />
L13<br />
M12<br />
N8<br />
N9<br />
N11<br />
N12<br />
N13<br />
T6<br />
T8<br />
T9<br />
T13<br />
T15<br />
T16<br />
T18<br />
AB1<br />
AC2<br />
M11<br />
PP3V3_TBT_X_LC<br />
PP3V3_S5_TBT_X_SW<br />
1<br />
2<br />
C2975<br />
10UF<br />
20%<br />
20%<br />
6.3V<br />
2<br />
6.3V<br />
CERM-X5R CERM-X5R<br />
0402-4<br />
0402-4<br />
BYPASS=U2800.A2:A1:3MM<br />
PP0V9_TBT_X_SVR<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=0.9V<br />
PP0V9_TBT_X_LVR<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=0.9V<br />
1<br />
Add XW or alias on<br />
support page<br />
XW<br />
VOLTAGE=3.3V<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
SOURCED BY<br />
INTERNAL SWITCH<br />
TBTTHMSNS_D1_N<br />
PP3V3_TBT_X_F<br />
1<br />
1.0UF<br />
1.0UF<br />
20%<br />
20%<br />
6.3V<br />
2<br />
6.3V<br />
X5R<br />
X5R<br />
0201-1<br />
0201-1<br />
DIDT=TRUE<br />
0.68UH-20%-6.1A-0.020OHM<br />
SWITCH_NODE=TRUE<br />
VR0V9_IND_TBT_X<br />
1 2<br />
C2992 1<br />
1.0UF<br />
2<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
XW2900<br />
SM<br />
1 2<br />
C2991<br />
C2976<br />
10UF<br />
C2993 1<br />
1.0UF<br />
2<br />
6.3V 20%<br />
X5R<br />
0201-1<br />
PLACE_NEAR=U2800.AC22:2MM<br />
NO_XNET_CONNECTION=1<br />
28<br />
1<br />
2<br />
CRITICAL<br />
L2950<br />
1210<br />
C2977<br />
10UF<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402-4<br />
C2954 1<br />
10UF<br />
2<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402-4<br />
1<br />
2<br />
C2978<br />
10UF<br />
C2990 1 2<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402-4<br />
2x 10uF outside BGA area<br />
P0V9_TBT_X_SVR_AGND<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=0V<br />
56<br />
1<br />
2<br />
1<br />
C2917<br />
12PF<br />
5%<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
C2950<br />
47UF<br />
20%<br />
6.3V<br />
CER-X5R<br />
0603<br />
C2955 1<br />
10UF<br />
20%<br />
6.3V<br />
2<br />
CERM-X5R<br />
0402-4<br />
C2994 1<br />
47UF<br />
2<br />
20%<br />
6.3V<br />
CER-X5R<br />
0603<br />
1<br />
2<br />
1<br />
2<br />
47UF<br />
20%<br />
6.3V<br />
CER-X5R<br />
0603<br />
C2995 1<br />
47UF<br />
2<br />
20%<br />
6.3V<br />
CER-X5R<br />
0603<br />
C2910<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
C2951<br />
1<br />
2<br />
C2911<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
BOM_COST_GROUP=TBT<br />
1<br />
2<br />
C2952<br />
47UF<br />
1 2<br />
20%<br />
6.3V<br />
CER-X5R<br />
0603<br />
0603<br />
L2990<br />
1.0UH-20%-2.1A-0.128OHM<br />
CRITICAL<br />
1<br />
2<br />
C2912<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
1<br />
28 32<br />
FROM USB-C PORT<br />
CONTROLLER (UPC)<br />
C2981<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
INTERNAL SWITCHING VR OUTPUT<br />
1<br />
2<br />
PP3V3_TBT_X_S0 28 101<br />
C2913<br />
1.0UF<br />
20%<br />
2<br />
6.3V<br />
X5R<br />
0201-1<br />
SYNC_MASTER=J79_GREG<br />
1<br />
2<br />
C2914<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
1<br />
2<br />
C2980<br />
0.1UF<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
ISOLATE GND OF SVR_IND CAPS<br />
AND GND OF VCC3P3_SVR CAPS<br />
FROM SYSTEM GND IN LAYOUT<br />
(SEE INTEL LAYOUT GUIDELINES)<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
1<br />
2<br />
C2915<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
USB-C HIGH SPEED 2<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
OUT<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
28<br />
1<br />
SOURCED BY<br />
INTERNAL SWITCH<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
C2916<br />
1.0UF<br />
20%<br />
2<br />
6.3V<br />
X5R<br />
0201-1<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
SYNC_DATE=09/09/2015<br />
9.0.0<br />
dvt-fab09-0<br />
29 OF 145<br />
27 OF 119<br />
SIZE<br />
D<br />
D<br />
C<br />
B<br />
A
SYNC_MASTER=J79_GREG<br />
SYNC_DATE=08/08/2016<br />
D<br />
C<br />
B<br />
A<br />
TMU CLKs<br />
26 TBT_X_TMU_CLK_OUT<br />
15<br />
1 2<br />
TBT_T_TMU_CLK_IN 92<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
5%<br />
TBT_X_TMU_CLK_OUT<br />
1/20W<br />
TBT_T_TMU_CLK_IN<br />
MF<br />
201<br />
R3024 100K<br />
1 2<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
30<br />
Ridge 0.9V SVR XW<br />
26<br />
26<br />
DP SRC OPTIONS<br />
29<br />
IF DP SRC NOT USED<br />
NC_DP_X_SRC_ML_P<br />
NC_DP_X_SRC_ML_P<br />
NC_DP_X_SRC_ML_P<br />
NC_DP_X_SRC_ML_P<br />
NC_DP_X_SRC_ML_N<br />
NC_DP_X_SRC_ML_N<br />
NC_DP_X_SRC_ML_N<br />
NC_DP_X_SRC_ML_N<br />
NC_DP_X_SRC_AUX_P<br />
NC_DP_X_SRC_AUX_N<br />
AR xtal<br />
IN<br />
OUT<br />
28 26<br />
34 26<br />
34 26<br />
29 26<br />
28<br />
27<br />
1<br />
Ridge<br />
PDs<br />
P0V9_TBT_X_SVR_AGND<br />
TBT_X_XTAL25M_OUT<br />
1M<br />
27<br />
R3006<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
8<br />
NOSTUFF<br />
TBT_X_XTAL25M_IN<br />
TBT_X_CIO_PLUG_EVENT_L<br />
DP_X_SNK0_HPD<br />
DP_X_SNK1_HPD<br />
DP_XA_HPD<br />
TBT_POC_RESET<br />
PP3V3_TBT_X_LC<br />
15<br />
15<br />
IN<br />
IN<br />
RIDGE DEBUG CONN<br />
26 DP_X_SNK0_DDC_CLK<br />
MAKE_BASE=TRUE<br />
DP_X_SNK0_DDC_CLK<br />
DP_X_SNK0_DDC_DATA<br />
MAKE_BASE=TRUE<br />
DP_X_SNK0_DDC_DATA<br />
26<br />
26<br />
26<br />
USBC_DBG<br />
DP_X_SNK1_DDC_CLK<br />
MAKE_BASE=TRUE<br />
DP_X_SNK1_DDC_CLK<br />
DP_X_SNK1_DDC_DATA<br />
MAKE_BASE=TRUE<br />
DP_X_SNK1_DDC_DATA<br />
USB3_EXTA_R2D_C_P<br />
DCI<br />
PCH USB3<br />
R3025<br />
25MHZ-25PPM-20PF-50OHM<br />
USB3_EXTA_R2D_C_N<br />
26<br />
5%<br />
XW3000<br />
SHORT-L6-SM<br />
1 2<br />
DP_X_SRC_HPD<br />
NC_DP_X_SRC_ML_P<br />
NC_DP_X_SRC_ML_P<br />
NC_DP_X_SRC_ML_P<br />
NC_DP_X_SRC_ML_P<br />
NC_DP_X_SRC_ML_N<br />
NC_DP_X_SRC_ML_N<br />
NC_DP_X_SRC_ML_N<br />
NC_DP_X_SRC_ML_N<br />
NC_DP_X_SRC_AUX_P<br />
NC_DP_X_SRC_AUX_N<br />
R3007<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
J3001<br />
201<br />
MF<br />
CRITICAL<br />
Y3000<br />
2.00X1.60-SM<br />
505070-1220<br />
M-ST-SM<br />
13 14<br />
1 2<br />
3 4<br />
5 6<br />
7 8<br />
9 10<br />
11 12<br />
15 16<br />
PLACE_NEAR=U2800.V2:5mm<br />
1/20W MF 201<br />
TBT_X_XTAL25M_OUT_R<br />
2 4<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
TBT_X_PCI_RESET_L 19 26<br />
USBC_X_RESET_L<br />
26 32<br />
PP3V3_S5_TBT_X_SW 27 32<br />
PP0V9_TBT_X_PCIE<br />
27<br />
PP0V9_TBT_X_USB<br />
27<br />
PP0V9_TBT_X_CIO<br />
C3020<br />
0.1UF<br />
1 2<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
C3021<br />
0.1UF<br />
1 2<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
1 3<br />
5% 1/20W MF 201<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
R3067 100K<br />
1 2<br />
5% 1/20W MF 201<br />
R3068 100K<br />
1 2<br />
5% 1/20W MF 201<br />
5%<br />
7<br />
NO_XNET_CONNECTION=1<br />
R3069 100K<br />
1 2<br />
R3070 100K<br />
1 2<br />
1/20W<br />
R3040<br />
MF<br />
1M<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201 MAKE_BASE=TRUE<br />
NO_TEST=1<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
1<br />
2<br />
2<br />
1<br />
201<br />
15<br />
15<br />
C3002<br />
20PF<br />
5%<br />
25V<br />
C0G<br />
0201<br />
0201<br />
C0G<br />
25V<br />
5%<br />
20PF<br />
C3003<br />
27<br />
OUT<br />
OUT<br />
29<br />
30<br />
28<br />
DCI ALIASES<br />
X ACE-SMC I2C SERIES R'S<br />
I2C_UPC_X_SDA2<br />
I2C_UPC_X_SCL2<br />
33<br />
29 SMBUS_SMC_4_G3H_SCL 51<br />
5% 1/20W MF 201<br />
SMBUS_SMC_4_G3H_SCL 51<br />
I2C_UPC_X_SCL2<br />
30<br />
28<br />
29<br />
29<br />
30<br />
30<br />
33 28<br />
I2C_UPC_X_SDA2<br />
ACE A/B RPD STRAPPING<br />
USBC_XA_CC1<br />
USBC_XA_CC2<br />
USBC_XB_CC1<br />
USBC_XB_CC2<br />
ACE PDs<br />
FUSES FOR UPC<br />
29<br />
30<br />
28<br />
28<br />
MAKE_BASE=TRUE<br />
USB3_EXTA_D2R_P<br />
MAKE_BASE=TRUE<br />
USB3_EXTA_D2R_N<br />
MAKE_BASE=TRUE<br />
USB3_EXTA_R2D_P<br />
MAKE_BASE=TRUE<br />
USB3_EXTA_R2D_N<br />
MAKE_BASE=TRUE<br />
I2C_UPC_X_SDA2<br />
28 26<br />
MAKE_BASE=TRUE<br />
I2C_UPC_X_SCL2<br />
28<br />
28<br />
94 51 48<br />
28<br />
30 29<br />
UPC_X_5V_EN<br />
6<br />
5%<br />
I2C_TBT_XB_INT_L<br />
I2C_UPC_X_SCL2<br />
I2C_UPC_X_SDA2<br />
SMC_USBC_INT_L<br />
TBT_X_SPI_CLK_DBG<br />
UPC_XA_UART_TX<br />
PP20V_USBC_XA_VBUS<br />
PP20V_USBC_XB_VBUS<br />
USB3_EXTA_D2R_P<br />
USB3_EXTA_D2R_N<br />
USB3_EXTA_R2D_P<br />
USB3_EXTA_R2D_N<br />
MAKE_BASE=TRUE<br />
USBC_XA_CC1<br />
MAKE_BASE=TRUE<br />
USBC_XA_CC2<br />
MAKE_BASE=TRUE<br />
USBC_XB_CC1<br />
MAKE_BASE=TRUE<br />
USBC_XB_CC2<br />
ACE Debug Support<br />
DCI<br />
Ace<br />
USB2 AR PDs<br />
GND ALIASES<br />
NC ALIASES / NO TEST<br />
SIGNAL ALIASES<br />
MAKE_BASE=TRUE<br />
29 UPC_X_5V_EN<br />
UPC_X_5V_EN<br />
28 33<br />
29 UPC_XA_DBG_UART_TX<br />
R3032 30<br />
1<br />
100K 2<br />
OMIT<br />
UPC_X_5V_EN<br />
MAKE_BASE=TRUE<br />
201<br />
R3089 1 30 29 26 TBT_X_CIO_PWR_EN<br />
TBT_X_CIO_PWR_EN<br />
13<br />
NOSTUFF<br />
MAKE_BASE=TRUE<br />
NONE<br />
NONE<br />
30 29 26 TBT_X_USB_PWR_EN<br />
TBT_X_USB_PWR_EN<br />
13<br />
NONE<br />
MAKE_BASE=TRUE<br />
402<br />
2<br />
26 PM_BATLOW_L<br />
PM_BATLOW_L<br />
14 48 94<br />
MAKE_BASE=TRUE<br />
29 UPC_XA_DBG_UART_RX<br />
92 26 SMC_PME_S4_DARK_L<br />
SMC_PME_S4_DARK_L<br />
48 49 50<br />
96 95 30 29 SMC_PME_S4_DARK_L<br />
30 UPC_XB_DBG_UART_TX<br />
MAKE_BASE=TRUE<br />
OMIT<br />
28 26 UPC_X_SPI_CLK<br />
UPC_X_SPI_CLK<br />
MAKE_BASE=TRUE<br />
R3088 1 28 26 UPC_X_SPI_CS_L<br />
UPC_X_SPI_CS_L<br />
NOSTUFF<br />
MAKE_BASE=TRUE<br />
NONE<br />
NONE<br />
28 26 UPC_X_SPI_MOSI<br />
UPC_X_SPI_MOSI<br />
NONE<br />
MAKE_BASE=TRUE<br />
402<br />
2<br />
28 26 UPC_X_SPI_MISO<br />
UPC_X_SPI_MISO<br />
MAKE_BASE=TRUE<br />
30 UPC_XB_DBG_UART_RX<br />
94 92 UPC_T_SPI_CLK<br />
UPC_T_SPI_CLK<br />
MAKE_BASE=TRUE<br />
94 92 UPC_T_SPI_CS_L<br />
UPC_T_SPI_CS_L<br />
MAKE_BASE=TRUE<br />
94 92 UPC_T_SPI_MOSI<br />
UPC_T_SPI_MOSI<br />
MAKE_BASE=TRUE<br />
94 92<br />
J3000<br />
UPC_T_SPI_MISO<br />
UPC_T_SPI_MISO<br />
MAKE_BASE=TRUE<br />
505070-1220<br />
M-ST-SM<br />
94 92 26 JTAG_ISP_TDO<br />
JTAG_ISP_TDO<br />
5 94<br />
MAKE_BASE=TRUE<br />
13 14<br />
30 29 28 TBT_POC_RESET<br />
TBT_POC_RESET<br />
16 94<br />
MAKE_BASE=TRUE<br />
1 2 I2C_TBT_XA_INT_L<br />
26 28<br />
106 34 DDI1_MUX_SEL<br />
DDI1_MUX_SEL 16<br />
MAKE_BASE=TRUE<br />
26<br />
3 4 I2C_TBT_X_SDA<br />
26 28<br />
106 34 DDI2_MUX_SEL<br />
DDI2_MUX_SEL 16<br />
5 6 I2C_TBT_X_SCL<br />
26 28<br />
MAKE_BASE=TRUE<br />
7 8 I2C_UPC_XA_DBG_CTL_SDA<br />
29<br />
16 TBT_X_CIO_PLUG_EVENT_L<br />
TBT_X_CIO_PLUG_EVENT_L<br />
26 28<br />
26<br />
9 10<br />
MAKE_BASE=TRUE<br />
I2C_UPC_XA_DBG_CTL_SCL<br />
29<br />
29 XDP_USB_EXTA_OC_L<br />
XDP_USB_EXTA_OC_L 5 17<br />
11 12 UPC_XA_UART_RX<br />
29 30<br />
MAKE_BASE=TRUE<br />
26<br />
30 XDP_USB_EXTB_OC_L<br />
XDP_USB_EXTB_OC_L 5 17<br />
MAKE_BASE=TRUE<br />
15 16<br />
13 JTAG_TBT_X_TMS<br />
JTAG_TBT_X_TMS<br />
26<br />
MAKE_BASE=TRUE<br />
26<br />
94 13 JTAG_TBT_T_TMS<br />
JTAG_TBT_T_TMS<br />
92 94<br />
MAKE_BASE=TRUE<br />
30 SMC_DEBUGPRT_TX_L<br />
SMC_DEBUGPRT_TX_L<br />
48 49 104<br />
26<br />
MAKE_BASE=TRUE<br />
PLACE_NEAR=Q3100:5MM<br />
30 SMC_DEBUGPRT_RX_L<br />
SMC_DEBUGPRT_RX_L<br />
48 49 104<br />
MAKE_BASE=TRUE<br />
CRITICAL<br />
26<br />
0603<br />
29 NC_USBC_XA_RESET_L<br />
NC_USBC_XA_RESET_L 102<br />
MAKE_BASE=TRUE<br />
F3000<br />
15 USB_UPC_PCH_XA_N<br />
USB_UPC_PCH_XA_N<br />
26<br />
6AMP-32V-0.0095OHM<br />
29 USB_UPC_PCH_XA_N<br />
1 2<br />
MAKE_BASE=TRUE<br />
PP20V_USBC_XA_VBUS_F<br />
29<br />
15 USB_UPC_PCH_XA_P<br />
USB_UPC_PCH_XA_P<br />
PLACE_NEAR=Q3200:5MM<br />
29 USB_UPC_PCH_XA_P<br />
CRITICAL<br />
MAKE_BASE=TRUE<br />
15<br />
0603 740S0135<br />
15 USB_UPC_PCH_XB_N<br />
USB_UPC_PCH_XB_N<br />
F3001<br />
30 USB_UPC_PCH_XB_N<br />
MAKE_BASE=TRUE<br />
6AMP-32V-0.0095OHM<br />
15<br />
15 USB_UPC_PCH_XB_P<br />
USB_UPC_PCH_XB_P<br />
1 2 PP20V_USBC_XB_VBUS_F<br />
30<br />
30 USB_UPC_PCH_XB_P<br />
15<br />
5% 1/20W MF<br />
ACE DEBUG CONN<br />
USBC_DBG<br />
PLACE_NEAR=U5000:5mm<br />
R3041 1<br />
33 2<br />
1/20W MF<br />
201<br />
PLACE_NEAR=U5000:5mm<br />
R3042 1 2<br />
SMBUS_SMC_4_G3H_SDA 51<br />
SMBUS_SMC_4_G3H_SDA 51<br />
29<br />
29<br />
30<br />
30<br />
31<br />
31<br />
31<br />
31<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
104<br />
104<br />
104<br />
104<br />
29<br />
29<br />
29<br />
29<br />
<br />
5<br />
96<br />
95<br />
30<br />
30<br />
29 GND<br />
29 GND<br />
30 GND<br />
29 GND<br />
GND<br />
30 GND<br />
GND<br />
29 GND<br />
GND<br />
30 GND<br />
GND<br />
GND<br />
29<br />
29<br />
29<br />
29<br />
101<br />
29<br />
30<br />
29<br />
29<br />
29<br />
26<br />
30<br />
30<br />
30<br />
29<br />
30<br />
33<br />
27<br />
28<br />
28<br />
NO_TEST=1<br />
NC_UPC_XB_I2C_ADDR<br />
PP3V3_UPC_XA_LDO<br />
PP3V3_UPC_XA_LDO<br />
PP3V3_UPC_XA_LDO<br />
PP3V3_UPC_XB_LDO<br />
PP3V3_UPC_XB_LDO<br />
PP3V3_UPC_XB_LDO<br />
PP3V3_UPC_XB_LDO<br />
PP20V_USBC_XA_VBUS<br />
PP20V_USBC_XB_VBUS<br />
PP5V_S4_X_USBC<br />
PP5V_S4_X_USBC<br />
PP5V_S4_X_USBC<br />
PP3V3_TBT_X_S0<br />
26<br />
26<br />
26<br />
26<br />
USB_UPC_XA_P<br />
USB_UPC_XA_N<br />
USB_UPC_XB_P<br />
USB_UPC_XB_N<br />
POWER ALIASES<br />
29<br />
5%<br />
MAKE_BASE=TRUE<br />
PP3V3_UPC_XA_LDO<br />
MAKE_BASE=TRUE<br />
PP3V3_UPC_XB_LDO<br />
MAKE_BASE=TRUE<br />
PP20V_USBC_XA_VBUS<br />
MAKE_BASE=TRUE<br />
PP20V_USBC_XB_VBUS<br />
MAKE_BASE=TRUE<br />
PP5V_S4_X_USBC<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=5V<br />
MAKE_BASE=TRUE<br />
PP3V3_TBT_X_S0<br />
R3020 1<br />
0 2<br />
5% 1/20W MF<br />
R3021 1<br />
0 2<br />
1/20W<br />
R3022 1<br />
0 2<br />
5% 1/20W MF<br />
R3023 1<br />
0 2<br />
5% 1/20W<br />
MF<br />
MF<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
201<br />
201<br />
201<br />
201<br />
29<br />
31<br />
31<br />
30<br />
26<br />
26<br />
26<br />
26<br />
15<br />
15<br />
15<br />
15<br />
15<br />
AR/ACE SPI BUS SERIES R'S<br />
TBT_X_SPI_CLK<br />
TBT_X_SPI_CS_L<br />
TBT_X_SPI_MOSI<br />
TBT_X_SPI_MISO<br />
ROM<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
TBT<br />
Alpine Ridge U2800<br />
(MASTER)<br />
26<br />
28<br />
26<br />
28<br />
26<br />
28<br />
26<br />
28<br />
I2C_TBT_X_SCL<br />
I2C_TBT_X_SDA<br />
I2C_TBT_XA_INT_L<br />
I2C_TBT_XB_INT_L<br />
PCIE_TBT_X_D2R_C_P<br />
PCIE_TBT_X_D2R_C_N<br />
PCIE_TBT_X_D2R_C_P<br />
PCIE_TBT_X_D2R_C_N<br />
PCIE_TBT_X_D2R_C_N<br />
PCIE_TBT_X_R2D_C_N<br />
PCIE_TBT_X_R2D_C_N<br />
PCIE_TBT_X_R2D_C_P<br />
PCIE_TBT_X_R2D_C_N<br />
TBT to ACE<br />
Ridge PCIE Caps<br />
D2R<br />
PCIE_TBT_X_D2R_C_P<br />
2 1<br />
0201 X5R 6.3V 20% 0.22UF<br />
PCIE_TBT_X_D2R_C_P<br />
PCIE_TBT_X_D2R_C_N<br />
PCIE_TBT_X_R2D_C_P<br />
PCIE_TBT_X_R2D_C_N<br />
PCIE_TBT_X_R2D_C_P<br />
PCIE_TBT_X_R2D_C_P<br />
BOM_COST_GROUP=TBT<br />
GND_VOID=TRUE<br />
2<br />
0201 X5R 6.3V 20%<br />
GND_VOID=TRUE<br />
2<br />
0201 X5R 6.3V 20%<br />
GND_VOID=TRUE<br />
2<br />
0201 X5R 6.3V 20%<br />
GND_VOID=TRUE<br />
2<br />
0201 X5R 6.3V 20%<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
2<br />
0201 X5R 6.3V 20%<br />
GND_VOID=TRUE<br />
2<br />
0201 X5R 6.3V 20%<br />
GND_VOID=TRUE<br />
2<br />
0201 X5R 6.3V 20%<br />
R2D<br />
C3055<br />
0.22UF<br />
GND_VOID=TRUE<br />
2 1<br />
0201 X5R 6.3V 20%<br />
GND_VOID=TRUE<br />
0.22UF<br />
2 1<br />
0201 X5R 6.3V 20%<br />
GND_VOID=TRUE<br />
0.22UF<br />
2 1<br />
0201 X5R 6.3V 20%<br />
GND_VOID=TRUE<br />
0.22UF<br />
2 1<br />
0201 X5R 6.3V 20%<br />
GND_VOID=TRUE<br />
0.22UF<br />
2 1<br />
0201 X5R 6.3V 20%<br />
GND_VOID=TRUE<br />
0.22UF<br />
2 1<br />
0201 X5R 6.3V 20%<br />
GND_VOID=TRUE<br />
0.22UF<br />
2 1<br />
0201 X5R 6.3V 20%<br />
GND_VOID=TRUE<br />
0.22UF<br />
2 1<br />
0201 X5R 6.3V 20% 0.22UF<br />
1<br />
1<br />
1<br />
100<br />
R3094 1 2<br />
R3095 1<br />
15<br />
2<br />
R3096 1<br />
15<br />
2<br />
R3097 1<br />
15<br />
2<br />
R3098 1<br />
15<br />
2<br />
R3090 1<br />
15<br />
2<br />
R3091 1<br />
15<br />
2<br />
R3092 1<br />
15<br />
2<br />
R3093 1<br />
15<br />
2<br />
1<br />
C3050<br />
C3054<br />
C3056<br />
0.22UF<br />
C3057<br />
0.22UF<br />
C3040<br />
C3041<br />
C3042<br />
C3043<br />
C3044<br />
C3045<br />
C3046<br />
C3047<br />
USBC DEBUG CONN<br />
TBT_X_SPI_CLK_DBG<br />
UPC_XB_SPI_CLK<br />
5% 1/20W MF 201<br />
UPC_XB_SPI_CS_L<br />
UPC_XB_SPI_MOSI<br />
UPC_XB_SPI_MISO<br />
UPC_X_SPI_CLK<br />
UPC_X_SPI_CS_L<br />
UPC_X_SPI_MOSI<br />
UPC_X_SPI_MISO<br />
Pri ACE<br />
U3100<br />
(Write: 0x70 Read: 0x71)<br />
I2C_TBT_X_SCL 29<br />
I2C_TBT_X_SDA 29<br />
I2C_TBT_XA_INT_L 29<br />
Sec ACE<br />
U3200<br />
(Write: 0x7E Read: 0x7F)<br />
I2C_TBT_X_SCL 30<br />
I2C_TBT_X_SDA 30<br />
I2C_TBT_XB_INT_L 30<br />
PCIE_TBT_X_D2R_P<br />
26 IN<br />
OUT 15 105<br />
1<br />
1<br />
1<br />
0.22UF<br />
C3051<br />
0.22UF<br />
C3052<br />
0.22UF<br />
C3053<br />
0.22UF<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
5%<br />
5% 1/20W MF<br />
5% 1/20W MF 201<br />
5% 1/20W MF<br />
5%<br />
1/20W<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
MF<br />
201<br />
201<br />
201<br />
1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
PCIE_TBT_X_D2R_N<br />
PCIE_TBT_X_D2R_P<br />
PCIE_TBT_X_D2R_N<br />
PCIE_TBT_X_D2R_P<br />
PCIE_TBT_X_D2R_N<br />
PCIE_TBT_X_D2R_P<br />
PCIE_TBT_X_D2R_N<br />
PCIE_TBT_X_R2D_P<br />
PCIE_TBT_X_R2D_N<br />
PCIE_TBT_X_R2D_P<br />
PCIE_TBT_X_R2D_N<br />
PCIE_TBT_X_R2D_P<br />
PCIE_TBT_X_R2D_N<br />
PCIE_TBT_X_R2D_P<br />
PCIE_TBT_X_R2D_N<br />
USB-C Support<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
IN<br />
4<br />
3<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
REVISION<br />
BRANCH<br />
28<br />
DRAWING NUMBER<br />
PAGE<br />
SHEET<br />
IN<br />
IN<br />
IN<br />
OUT<br />
IN<br />
IN<br />
IN<br />
OUT<br />
30<br />
30<br />
30<br />
30<br />
26<br />
26<br />
26<br />
26<br />
9.0.0<br />
28<br />
28<br />
28<br />
28<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
051-00777<br />
30 OF 145<br />
28 OF 119<br />
Ace<br />
AR<br />
15<br />
15<br />
15<br />
15<br />
15<br />
15<br />
15<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
dvt-fab09-0<br />
105<br />
SIZE<br />
D<br />
D<br />
C<br />
B<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
PRIMARY ACE USB-C PORT CONTROLLER (UPC)<br />
D<br />
CRITICAL<br />
Q3100<br />
FDPC4044<br />
PWR-CLIP-33<br />
D<br />
S2<br />
G2<br />
G1<br />
S1<br />
C<br />
B<br />
A<br />
PULL R3109 AND R3108 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES<br />
PULL R3109 AND R3108 DOWN TO GND FOR 2ND RIDGE'S ACES<br />
PP3V3_UPC_XA_LDO 28<br />
1M<br />
1 2<br />
5% 1/20W MF 201<br />
1M<br />
1 2<br />
5% 1/20W MF 201<br />
1M<br />
R3109<br />
R3108<br />
R3105<br />
1 2<br />
5% 1/20W MF<br />
I2C_UPC_XA_DBG_CTL_SCL<br />
I2C_UPC_XA_DBG_CTL_SDA<br />
201<br />
UPC_XA_UART_RX<br />
28<br />
28<br />
28<br />
28<br />
BI<br />
BI<br />
29<br />
29<br />
28<br />
PU to PP3V3_S4 if convenient<br />
for layout.<br />
Otherwise PU to PP3V3_UPC_XA_LDO<br />
NO_XNET_CONNECTION=1<br />
CAP FOR PP_5V0 ON VR PAGE<br />
TESTPOINTS MUST BE<br />
PRESENT FOR GPIO0, GPIO1<br />
(EVEN IN PRODUCTION)<br />
USE GPIO2 FOR USB-C ANALOG AUDIO SUPPORT<br />
ON DESIGNS WITHOUT AN AUDIO JACK CONNECTOR<br />
USB_UPC_PCH_XA_P<br />
USB_UPC_PCH_XA_N<br />
28<br />
29<br />
30<br />
PP3V3_UPC_XA_LDO<br />
USE GPIO3 FOR POWER_GATE_EN<br />
ON BANSURI DESIGNS<br />
REAR PORT:<br />
CONNECT UPC SPI TO ROM<br />
FRONT PORT:<br />
GROUND UPC SPI<br />
1<br />
L3100<br />
90-OHM-0.1A<br />
EXCX4CE<br />
2 3<br />
PLACE_NEAR=U3100:5mm<br />
26<br />
26<br />
BI<br />
BI<br />
NO_XNET_CONNECTION=1<br />
SYM_VER-1<br />
4<br />
1<br />
R3110<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
1<br />
R3111<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
96<br />
95<br />
CRITICAL<br />
30<br />
R3103 1<br />
15K<br />
0.1%<br />
1/20W<br />
TF-LF<br />
0201<br />
2<br />
TO SMC<br />
28<br />
28<br />
28<br />
28<br />
100<br />
PP20V_USBC_XA_VBUS<br />
PP3V3_UPC_XA_LDO<br />
PP3V3_G3H<br />
GND<br />
PP5V_S4_X_USBC<br />
30 28<br />
28<br />
28<br />
28<br />
30 28 26<br />
30 28 26<br />
28 26<br />
28<br />
28<br />
96 95 30 28<br />
28<br />
28<br />
GND I2C_ADDR<br />
PRIMARY ONLY<br />
28<br />
28<br />
28<br />
28<br />
28<br />
51<br />
28<br />
28<br />
28<br />
28<br />
30 29 28<br />
30 28<br />
26<br />
26<br />
28<br />
28<br />
28<br />
28<br />
IN<br />
OUT<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
29 28<br />
29 28<br />
BI<br />
BI<br />
OUT<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
OUT<br />
IN<br />
OUT<br />
IN<br />
OUT<br />
BI<br />
BI<br />
BI<br />
BI<br />
TBT_POC_RESET<br />
NC_USBC_XA_RESET_L<br />
UPC_XA_DBG_UART_TX<br />
UPC_XA_DBG_UART_RX<br />
TBT_X_CIO_PWR_EN<br />
TBT_X_USB_PWR_EN<br />
DP_XA_HPD<br />
GND<br />
UPC_X_5V_EN<br />
SMC_PME_S4_DARK_L<br />
XDP_USB_EXTA_OC_L<br />
GND<br />
GND<br />
UPC_XA_R_OSC<br />
I2C_UPC_XA_DBG_CTL_SCL<br />
I2C_UPC_XA_DBG_CTL_SDA<br />
I2C_TBT_X_SDA<br />
I2C_TBT_X_SCL<br />
I2C_TBT_XA_INT_L<br />
I2C_UPC_X_SDA2<br />
I2C_UPC_X_SCL2<br />
SMC_USBC_INT_L<br />
GND<br />
GND<br />
GND<br />
GND<br />
TP_UPC_XA_SWD_DATA<br />
TP_UPC_XA_SWD_CLK<br />
UPC_XA_UART_RX<br />
UPC_XA_UART_TX<br />
TBT_XA_LSTX<br />
TBT_XA_LSRX<br />
USB_UPC_XA_F_P<br />
USB_UPC_XA_F_N<br />
DP_XA_AUXCH_P<br />
DP_XA_AUXCH_N<br />
USB3_EXTA_D2R_P<br />
USB3_EXTA_D2R_N<br />
USB3_EXTA_R2D_P<br />
USB3_EXTA_R2D_N<br />
1<br />
2<br />
FUSE<br />
Add on<br />
support page<br />
C3100<br />
10UF<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402-1<br />
E11<br />
F11<br />
B2<br />
C2<br />
D10<br />
G11<br />
C10<br />
E10<br />
G10<br />
D7<br />
H6<br />
F10<br />
F1<br />
G2<br />
E4<br />
D5<br />
D1<br />
D2<br />
C1<br />
A5<br />
B5<br />
B6<br />
A3<br />
B4<br />
A4<br />
B3<br />
F4<br />
G4<br />
F2<br />
E2<br />
L4<br />
K4<br />
L5<br />
K5<br />
J1<br />
J2<br />
L2<br />
K2<br />
L3<br />
K3<br />
28<br />
MRESET<br />
RESET*<br />
GPIO0<br />
GPIO1<br />
GPIO2<br />
GPIO3<br />
GPIO4<br />
GPIO5<br />
GPIO6<br />
GPIO7<br />
GPIO8<br />
BUSPOWERZ<br />
I2C_ADDR<br />
R_OSC<br />
DEBUG_CTL1<br />
DEBUG_CTL2<br />
I2C_SDA1<br />
I2C_SCL1<br />
I2C_IRQ1*<br />
I2C_SDA2<br />
I2C_SCL2<br />
I2C_IRQ2*<br />
SPI_CLK<br />
SPI_MOSI<br />
SPI_MISO<br />
SPI_SSZ<br />
SWD_DATA<br />
SWD_CLK<br />
UART_RX<br />
UART_TX<br />
LSX_R2P<br />
LSX_P2R<br />
USB_RP_P<br />
USB_RP_N<br />
AUX_P<br />
AUX_N<br />
DEBUG1<br />
DEBUG2<br />
DEBUG3<br />
DEBUG4<br />
PP20V_USBC_XA_VBUS_F<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=20V<br />
A11<br />
B11<br />
C11<br />
D11<br />
PP_5V0<br />
PP_5V0<br />
PP_5V0<br />
PP_5V0<br />
1<br />
2<br />
PRIMARY ONLY<br />
PRIMARY ONLY<br />
C3101<br />
1UF<br />
10%<br />
35V<br />
X5R<br />
0402<br />
A6<br />
A7<br />
A8<br />
B7<br />
PP_HV<br />
PP_HV<br />
PP_HV<br />
PP_HV<br />
H10<br />
H11<br />
J10<br />
J11<br />
K11<br />
U3100<br />
CD3215A<br />
BGA<br />
GND 28<br />
CRITICAL<br />
OMIT_TABLE<br />
A1<br />
D6<br />
E5<br />
E6<br />
E7<br />
F5<br />
G5<br />
H4<br />
H5<br />
G8<br />
H8<br />
L1<br />
B8<br />
D8<br />
E8<br />
F6<br />
F7<br />
F8<br />
G6<br />
G7<br />
5<br />
4<br />
H1<br />
B1<br />
G1<br />
PIN D6 IS UNDOCUMENTED RESET<br />
CAN GROUND PIN D6 IN PRODUCTION<br />
3<br />
2<br />
H2<br />
UPC_XA_GATE1<br />
TP_Q3100_DRAIN<br />
UPC_XA_GATE2<br />
K1<br />
A2<br />
1<br />
E1<br />
8<br />
H7<br />
B10<br />
A10<br />
B9<br />
A9<br />
L9<br />
L10<br />
K9<br />
K10<br />
K6<br />
L6<br />
K7<br />
L7<br />
K8<br />
L8<br />
L11<br />
USBC_XA_CC1<br />
USBC_XA_CC2<br />
USBC_XA_CC1<br />
USBC_XA_CC2<br />
USBC_XA_SBU1<br />
USBC_XA_SBU2<br />
PP1V8_UPC_XA_LDOA<br />
PP1V8_UPC_XA_LDOD<br />
PP1V1_UPC_XA_LDO_BMC<br />
UPC_XA_SS<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.1V<br />
USBC_XA_USB_DBG_TOP_P<br />
USBC_XA_USB_DBG_TOP_N<br />
USBC_XA_USB_DBG_BOT_P<br />
USBC_XA_USB_DBG_BOT_N<br />
GROUND<br />
NC or GND to dissipate heat<br />
C3109<br />
1<br />
0.47UF<br />
10%<br />
2<br />
6.3V<br />
CERM-X5R<br />
0201<br />
28<br />
28<br />
31<br />
31<br />
BOM_COST_GROUP=USB-C<br />
1<br />
PPDCIN_G3H 30 94 95 96 100<br />
C3104<br />
2.2UF<br />
20%<br />
2<br />
4V<br />
X5R-CERM<br />
0201<br />
31<br />
31<br />
31<br />
31<br />
MAX 100uF TOTAL ON RAIL<br />
1<br />
1<br />
2<br />
P3V3_TBT_X_SX_EN_R 32<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.8V<br />
C3105<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
C3114<br />
220PF<br />
10%<br />
2<br />
16V<br />
CER-X7R<br />
0201<br />
1<br />
2<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.2000<br />
C3113<br />
220PF<br />
10%<br />
16V<br />
CER-X7R<br />
0201<br />
SYNC_MASTER=J79_GREG<br />
28<br />
104 31<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
PP3V3_UPC_XA_LDO<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.8V<br />
1<br />
2<br />
C3106<br />
0.47UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.2000<br />
C3108<br />
10UF<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402-1<br />
USB-C PORT CONTROLLER A<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PP_CABLE<br />
VBUS<br />
VBUS<br />
VBUS<br />
VBUS<br />
PORT MUX DIGITAL CORE I/O AND CONTROL<br />
HV FET/SENSE<br />
TYPE-C<br />
VIN_3V3<br />
VDDIO<br />
NC<br />
LDO_3V3<br />
VOUT_3V3<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
LDO_1V8A<br />
LDO_1V8D<br />
GND<br />
GND<br />
LDO_BMC<br />
SS<br />
SENSEP<br />
SENSEN<br />
HV_GATE1<br />
HV_GATE2<br />
C_CC1<br />
C_CC2<br />
RPD_G1<br />
RPD_G2<br />
C_USB_TP<br />
C_USB_TN<br />
C_USB_BP<br />
C_USB_BN<br />
C_SBU1<br />
C_SBU2<br />
NC<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
1<br />
2<br />
28<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
31 OF 145<br />
29 OF 119<br />
SYNC_DATE=08/08/2016<br />
SIZE<br />
D<br />
C<br />
B<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
SECONDARY ACE USB-C PORT CONTROLLER (UPC)<br />
D<br />
CRITICAL<br />
Q3200<br />
FDPC4044<br />
PWR-CLIP-33<br />
D<br />
S2<br />
G2<br />
G1<br />
S1<br />
28<br />
PP20V_USBC_XB_VBUS<br />
FUSE<br />
Add on<br />
support page<br />
28<br />
PP20V_USBC_XB_VBUS_F<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=20V<br />
1<br />
2<br />
C3201<br />
1UF<br />
10%<br />
35V<br />
X5R<br />
0402<br />
5<br />
4<br />
3<br />
2<br />
NC<br />
1<br />
8<br />
UPC_XB_GATE1<br />
TP_Q3200_DRAIN<br />
UPC_XB_GATE2<br />
PPDCIN_G3H 29 94 95 96 100<br />
MAX 100uF TOTAL ON RAIL<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
PP3V3_UPC_XB_LDO<br />
28<br />
C<br />
B<br />
PULL R3209 AND R3208 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES<br />
PULL R3209 AND R3208 DOWN TO GND FOR 2ND RIDGE'S ACES<br />
PP3V3_UPC_XB_LDO 28<br />
1M<br />
1 2<br />
5%<br />
1M<br />
1 2<br />
5%<br />
1M<br />
1 2<br />
5%<br />
R3209<br />
1/20W MF 201<br />
R3208<br />
1/20W<br />
R3205<br />
I2C_UPC_XB_DBG_CTL_SCL<br />
I2C_UPC_XB_DBG_CTL_SDA<br />
MF<br />
201<br />
1/20W MF 201<br />
UPC_XA_UART_TX<br />
28<br />
USB_UPC_PCH_XB_P<br />
USB_UPC_PCH_XB_N<br />
L3200<br />
90-OHM-0.1A<br />
EXCX4CE<br />
TESTPOINTS MUST BE<br />
PRESENT FOR GPIO0, GPIO1<br />
(EVEN IN PRODUCTION)<br />
96<br />
95<br />
REAR PORT:<br />
CONNECT UPC SPI TO ROM<br />
FRONT PORT:<br />
GROUND UPC SPI<br />
29<br />
28<br />
28<br />
100<br />
28<br />
TO SMC<br />
1<br />
4<br />
28 PLACE_NEAR=U3200.L5:5mm<br />
BI<br />
BI<br />
30<br />
30<br />
28<br />
29<br />
30<br />
SYM_VER-1<br />
2 3<br />
CRITICAL<br />
R3203 1<br />
15K<br />
0.1%<br />
1/20W<br />
TF-LF<br />
0201<br />
2<br />
NEED 0.1%<br />
PLACE_NEAR=U3200.K5:5mm<br />
PP3V3_UPC_XB_LDO<br />
PP3V3_G3H<br />
GND<br />
PP5V_S4_X_USBC<br />
CAP FOR PP_5V0 ON VR PAGE<br />
29 28<br />
32<br />
29 28 26<br />
29 28 26<br />
IN<br />
OUT<br />
IN<br />
IN<br />
28<br />
28<br />
26<br />
28<br />
28<br />
96 95 29 28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
28<br />
30<br />
30<br />
28<br />
51<br />
28<br />
28<br />
28<br />
28<br />
30 29 28<br />
29 28<br />
26<br />
26<br />
TBT_POC_RESET<br />
USBC_X_RESET_L_R<br />
UPC_XB_DBG_UART_TX<br />
UPC_XB_DBG_UART_RX<br />
TBT_X_CIO_PWR_EN<br />
TBT_X_USB_PWR_EN<br />
DP_XB_HPD<br />
GND<br />
UPC_X_5V_EN<br />
SMC_PME_S4_DARK_L<br />
XDP_USB_EXTB_OC_L<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
GND<br />
NC_UPC_XB_I2C_ADDR<br />
UPC_XB_R_OSC<br />
I2C_UPC_XB_DBG_CTL_SCL<br />
I2C_UPC_XB_DBG_CTL_SDA<br />
BI<br />
BI<br />
OUT<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
OUT<br />
IN<br />
OUT<br />
IN<br />
OUT<br />
I2C_TBT_X_SDA<br />
I2C_TBT_X_SCL<br />
I2C_TBT_XB_INT_L<br />
I2C_UPC_X_SDA2<br />
I2C_UPC_X_SCL2<br />
SMC_USBC_INT_L<br />
UPC_XB_SPI_CLK<br />
UPC_XB_SPI_MOSI<br />
UPC_XB_SPI_MISO<br />
UPC_XB_SPI_CS_L<br />
TP_UPC_XB_SWD_DATA<br />
TP_UPC_XB_SWD_CLK<br />
UPC_XA_UART_TX<br />
UPC_XA_UART_RX<br />
TBT_XB_LSTX<br />
TBT_XB_LSRX<br />
USB_UPC_XB_F_P<br />
USB_UPC_XB_F_N<br />
DP_XB_AUXCH_P<br />
DP_XB_AUXCH_N<br />
1<br />
2<br />
C3200<br />
10UF<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402-1<br />
E11<br />
F11<br />
B2<br />
C2<br />
D10<br />
G11<br />
C10<br />
E10<br />
G10<br />
D7<br />
H6<br />
F10<br />
F1<br />
G2<br />
E4<br />
D5<br />
D1<br />
D2<br />
C1<br />
A5<br />
B5<br />
B6<br />
A3<br />
B4<br />
A4<br />
B3<br />
F4<br />
G4<br />
F2<br />
E2<br />
L4<br />
K4<br />
L5<br />
K5<br />
J1<br />
J2<br />
MRESET<br />
RESET*<br />
GPIO0<br />
GPIO1<br />
GPIO2<br />
GPIO3<br />
GPIO4<br />
GPIO5<br />
GPIO6<br />
GPIO7<br />
GPIO8<br />
BUSPOWERZ<br />
I2C_ADDR<br />
R_OSC<br />
DEBUG_CTL1<br />
DEBUG_CTL2<br />
I2C_SDA1<br />
I2C_SCL1<br />
I2C_IRQ1*<br />
I2C_SDA2<br />
I2C_SCL2<br />
I2C_IRQ2*<br />
SPI_CLK<br />
SPI_MOSI<br />
SPI_MISO<br />
SPI_SSZ<br />
SWD_DATA<br />
SWD_CLK<br />
UART_RX<br />
UART_TX<br />
LSX_R2P<br />
LSX_P2R<br />
USB_RP_P<br />
USB_RP_N<br />
AUX_P<br />
AUX_N<br />
A11<br />
B11<br />
C11<br />
D11<br />
PP_5V0<br />
PP_5V0<br />
PP_5V0<br />
PP_5V0<br />
A6<br />
A7<br />
A8<br />
B7<br />
PP_HV<br />
PP_HV<br />
PP_HV<br />
PP_HV<br />
H10<br />
PP_CABLE<br />
H11<br />
J10<br />
J11<br />
K11<br />
VBUS<br />
VBUS<br />
VBUS<br />
VBUS<br />
U3200<br />
CD3215A<br />
PORT MUX DIGITAL CORE I/O AND CONTROL<br />
BGA<br />
HV FET/SENSE<br />
TYPE-C<br />
H1<br />
VIN_3V3<br />
B1<br />
VDDIO<br />
G1<br />
H2<br />
LDO_3V3<br />
VOUT_3V3<br />
CRITICAL<br />
OMIT_TABLE<br />
K1<br />
A2<br />
LDO_1V8A<br />
LDO_1V8D<br />
E1<br />
LDO_BMC<br />
SS<br />
SENSEP<br />
SENSEN<br />
HV_GATE1<br />
HV_GATE2<br />
C_CC1<br />
C_CC2<br />
RPD_G1<br />
RPD_G2<br />
C_USB_TP<br />
C_USB_TN<br />
C_USB_BP<br />
C_USB_BN<br />
C_SBU1<br />
C_SBU2<br />
NC<br />
H7<br />
B10<br />
A10<br />
B9<br />
A9<br />
L9<br />
L10<br />
K9<br />
K10<br />
K6<br />
L6<br />
K7<br />
L7<br />
K8<br />
L8<br />
L11<br />
USBC_XB_CC1<br />
USBC_XB_CC2<br />
USBC_XB_CC1<br />
USBC_XB_CC2<br />
USBC_XB_USB_TOP_P<br />
USBC_XB_USB_TOP_N<br />
USBC_XB_USB_BOT_P<br />
USBC_XB_USB_BOT_N<br />
USBC_XB_SBU1<br />
USBC_XB_SBU2<br />
GROUND<br />
PP1V8_UPC_XB_LDOA<br />
PP1V8_UPC_XB_LDOD<br />
PP1V1_UPC_XB_LDO_BMC<br />
UPC_XB_SS<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.1V<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
NC or GND to dissipate heat<br />
1<br />
2<br />
C3209<br />
0.47UF<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
28<br />
28<br />
31<br />
31<br />
31<br />
31<br />
31<br />
31<br />
1<br />
2<br />
1<br />
2<br />
C3204<br />
2.2UF<br />
20%<br />
4V<br />
X5R-CERM<br />
0201<br />
C3214<br />
220PF<br />
10%<br />
16V<br />
CER-X7R<br />
0201<br />
1<br />
2<br />
P3V3_TBT_X_SX_EN_R 32<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.8V<br />
1<br />
C3205<br />
1.0UF<br />
20%<br />
2<br />
6.3V<br />
X5R<br />
0201-1<br />
BI<br />
BI<br />
C3213<br />
220PF<br />
10%<br />
16V<br />
CER-X7R<br />
0201<br />
28<br />
28<br />
31<br />
31<br />
104<br />
104<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.2000<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.2000<br />
1<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
C3206<br />
0.47UF<br />
10%<br />
2<br />
6.3V<br />
CERM-X5R<br />
0201<br />
1<br />
2<br />
C3208<br />
10UF<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402-1<br />
C<br />
B<br />
PU to PP3V3_S4 if convenient<br />
for layout.<br />
Otherwise PU to PP3V3_UPC_XB_LDO<br />
NO_XNET_CONNECTION=1<br />
28<br />
PP3V3_UPC_XB_LDO<br />
1<br />
R3210<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
42<br />
42<br />
28<br />
28<br />
BI<br />
BI<br />
BI<br />
BI<br />
SOC_SWCLK_DBG<br />
SOC_SWDIO_DBG<br />
SMC_DEBUGPRT_TX_L<br />
SMC_DEBUGPRT_RX_L<br />
L2<br />
K2<br />
L3<br />
K3<br />
DEBUG1<br />
DEBUG2<br />
DEBUG3<br />
DEBUG4<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
A<br />
26<br />
26<br />
BI<br />
BI<br />
NO_XNET_CONNECTION=1<br />
R3211 1<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
A1<br />
D6<br />
E5<br />
E6<br />
E7<br />
F5<br />
G5<br />
H4<br />
H5<br />
G8<br />
H8<br />
L1<br />
B8<br />
D8<br />
E8<br />
F6<br />
F7<br />
F8<br />
G6<br />
G7<br />
GND 28<br />
PIN D6 IS UNDOCUMENTED RESET<br />
CAN GROUND PIN D6 IN PRODUCTION<br />
BOM_COST_GROUP=USB-C<br />
SYNC_MASTER=J79_GREG<br />
USB-C PORT CONTROLLER B<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
SYNC_DATE=02/28/2016<br />
dvt-fab09-0<br />
32 OF 145<br />
30 OF 119<br />
SIZE<br />
D<br />
A
SYNC_MASTER=J79_GREG<br />
SYNC_DATE=07/05/2016<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
C<br />
B<br />
CC1<br />
TBT_R2D0<br />
TBT_D2R0<br />
SBU2<br />
USB2 BOT<br />
USB2 BOT<br />
SBU1<br />
TBT_R2D1<br />
TBT_D2R1<br />
CC2<br />
104 30 28<br />
CRITICAL<br />
26<br />
26<br />
26<br />
26<br />
30<br />
30<br />
30<br />
29<br />
104 29 28<br />
28<br />
29<br />
29<br />
26<br />
26<br />
26<br />
26<br />
D3300<br />
USBC_XB_CC1<br />
VOLTAGE=20V<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DSN2<br />
NSR20F40NX_G<br />
BI<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
BI<br />
K<br />
A<br />
USBC_XB_R2D_C_N<br />
USBC_XB_R2D_C_P<br />
USBC_XB_D2R_N<br />
USBC_XB_D2R_P<br />
USBC_XB_SBU2<br />
USBC_XB_USB_BOT_N<br />
USBC_XB_USB_BOT_P<br />
USBC_XA_R2D_C_P<br />
USBC_XA_R2D_C_N<br />
USBC_XA_D2R_P<br />
USBC_XA_D2R_N<br />
USBC_XA_CC2<br />
VOLTAGE=20V<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
USBC_XA_USB_DBG_BOT_N<br />
USBC_XA_USB_DBG_BOT_P<br />
USBC_XA_SBU1<br />
PP20V_USBC_XA_VBUS<br />
OMIT_TABLE<br />
C3304 1<br />
1UF<br />
10%<br />
25V<br />
2<br />
X5R<br />
402<br />
28<br />
GND_VOID=TRUE<br />
D3354<br />
DZ3301<br />
0201-THICKSTNCL<br />
5.5V-6.2PF<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
2<br />
1<br />
K<br />
A<br />
PP20V_USBC_XB_VBUS<br />
2<br />
1<br />
D3327<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
XW3300<br />
SM<br />
2 1<br />
1610<br />
ESDA25P35-1U1M<br />
D3301<br />
CRITICAL<br />
D3370<br />
DSN2<br />
NSR20F40NX_G<br />
GND_VOID=TRUE<br />
2<br />
1<br />
GND_VOID=TRUE<br />
C3391<br />
1 2<br />
GND_VOID=TRUE<br />
C3390<br />
1 2<br />
ESD8011<br />
D3349<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
2<br />
1<br />
X3DFN2-THICKSTNCL<br />
GND_VOID=TRUE<br />
C3373<br />
1 2<br />
GND_VOID=TRUE<br />
C3372<br />
1 2<br />
2<br />
1<br />
DZ3350<br />
0201-THICKSTNCL<br />
5.5V-6.2PF<br />
10%<br />
D3326<br />
K<br />
A<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
GND_VOID=TRUE<br />
0.22UF<br />
10% 6.3V X5R-CERM 0201<br />
0.22UF<br />
10% 6.3V X5R-CERM<br />
2<br />
1<br />
0.22UF<br />
6.3V<br />
OMIT_TABLE<br />
C3354 1<br />
1UF<br />
2<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
X5R-CERM<br />
GND_VOID=TRUE<br />
0.22UF<br />
10% 6.3V X5R-CERM<br />
D3325<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
D3353<br />
USBC_XA_R2D_P<br />
USBC_XA_R2D_N<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
VOLTAGE=20V<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
2<br />
1<br />
10%<br />
25V<br />
X5R<br />
402<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
0201<br />
0201<br />
2<br />
1<br />
0201<br />
D3324<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
PP20V_USBC_XA_VBUS_CONN<br />
2<br />
1<br />
2<br />
1<br />
K<br />
A<br />
D3352<br />
XW3350<br />
SM<br />
2 1<br />
1610<br />
ESDA25P35-1U1M<br />
D3302<br />
USBC_XB_R2D_N<br />
USBC_XB_R2D_P<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
DZ3303<br />
0201-THICKSTNCL<br />
5.5V-6.2PF<br />
BYPASS=J3300.59::2MM<br />
1<br />
2<br />
1<br />
2<br />
2<br />
1<br />
CRITICAL<br />
C3300<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
CRITICAL<br />
C3306<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
D3351<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
D3312<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
2<br />
1<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
BYPASS=J3300.59::2MM<br />
1<br />
2<br />
1<br />
2<br />
2<br />
1<br />
CRITICAL<br />
C3301<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
CRITICAL<br />
C3307<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
2<br />
1<br />
2<br />
1<br />
VOLTAGE=20V<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
ESD8011<br />
D3350<br />
X3DFN2-THICKSTNCL<br />
D3328<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
BYPASS=J3300.59::2MM<br />
1<br />
2<br />
1<br />
2<br />
PP20V_USBC_XB_VBUS_CONN<br />
PLACE VBUS CAP NEAR EACH VBUS PIN<br />
CRITICAL<br />
C3302<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
CRITICAL<br />
C3308<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
DZ3352<br />
0201-THICKSTNCL<br />
5.5V-6.2PF<br />
2<br />
1<br />
BYPASS=J3300.59::2MM<br />
CRITICAL<br />
C3303<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
BYPASS=J3300.59::2MM<br />
1<br />
2<br />
CRITICAL<br />
C3312<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
CRITICAL<br />
C3305<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
BYPASS=J3300.59::2MM<br />
BYPASS=J3300.59::2MM<br />
BYPASS=J3300.59::2MM<br />
BYPASS=J3300.59::2MM<br />
BYPASS=J3300.59::2MM<br />
1<br />
2<br />
1<br />
2<br />
CRITICAL<br />
C3309<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
1<br />
2<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
J3300<br />
20759-056E-02<br />
F-ST-SM<br />
57 58<br />
PWR<br />
1<br />
SIGNAL<br />
2<br />
3 4<br />
5 6<br />
7 8<br />
9 10<br />
11 12<br />
13 14<br />
15 16<br />
17 18<br />
19 20<br />
21 22<br />
23 24<br />
25 26<br />
27 28<br />
29 30<br />
31 32<br />
33 34<br />
35 36<br />
37 38<br />
39 40<br />
41 42<br />
43 44<br />
45 46<br />
47 48<br />
49 50<br />
51 52<br />
53 54<br />
55 56<br />
PWR<br />
59 60<br />
61<br />
GND<br />
62<br />
63 64<br />
65 66<br />
67 68<br />
69 70<br />
71 72<br />
73 74<br />
75 76<br />
77 78<br />
79 80<br />
81 82<br />
83 84<br />
85 86<br />
TP_USBC_PP20V_XB<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
NC_USBC_PP20V_XA<br />
DZ3300<br />
0201-THICKSTNCL<br />
5.5V-6.2PF<br />
OUT<br />
104<br />
DZ3351<br />
0201-THICKSTNCL<br />
5.5V-6.2PF<br />
2<br />
1<br />
NC_USBC_PP20V_XA<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
D3321<br />
PLACE VBUS CAP NEAR EACH VBUS PIN<br />
BYPASS=J3300.58::2MM<br />
BYPASS=J3300.58::2MM<br />
BYPASS=J3300.58::2MM<br />
BYPASS=J3300.58::2MM<br />
BYPASS=J3300.58::2MM<br />
D3355<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
PP20V_USBC_XA_VBUS_CONN<br />
2<br />
1<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
2<br />
1<br />
1<br />
2<br />
1<br />
2<br />
CRITICAL<br />
C3350<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
CRITICAL<br />
C3360<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
2<br />
1<br />
D3320<br />
2<br />
1<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
1<br />
D3356<br />
1<br />
2<br />
C3366<br />
3.0PF<br />
+/-0.1PF<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
D3304<br />
CRITICAL<br />
C3351<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
USBC_XB_R2D_N<br />
USBC_XB_R2D_P<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
0.01UF<br />
BYPASS=J3300.58::2MM<br />
C3356<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
BYPASS=J3300.58::2MM<br />
2<br />
1<br />
1<br />
2<br />
1<br />
2<br />
CRITICAL<br />
C3357<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
D3358<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
USBC_XA_R2D_P<br />
USBC_XA_R2D_N<br />
2<br />
1<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
2<br />
1<br />
1<br />
2<br />
1<br />
1<br />
2<br />
CRITICAL<br />
C3361<br />
12PF<br />
5%<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
C3352<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
CRITICAL<br />
C3358<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
BYPASS=J3300.58::2MM<br />
31<br />
104<br />
1<br />
2<br />
2<br />
1<br />
D3329<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
1<br />
2<br />
D3360<br />
C3363<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
ESD8011<br />
D3323<br />
1<br />
CRITICAL<br />
D3359<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
1<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
C3364<br />
12PF<br />
5%<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
C3392<br />
1 2<br />
C3393<br />
1 2<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
2<br />
1<br />
GND_VOID=TRUE<br />
C3370<br />
1 2<br />
GND_VOID=TRUE<br />
C3371<br />
1 2<br />
2<br />
1<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
X3DFN2-THICKSTNCL<br />
C3353<br />
0.01UF<br />
10%<br />
2<br />
25V<br />
X5R-CERM<br />
0201<br />
BYPASS=J3300.58::2MM<br />
1<br />
2<br />
CRITICAL<br />
C3359<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
2<br />
1<br />
2<br />
1<br />
1<br />
2<br />
ESD8011<br />
D3322<br />
CRITICAL<br />
1<br />
2<br />
C3365<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
10% 6.3V X5R-CERM<br />
GND_VOID=TRUE<br />
0.22UF<br />
10% 6.3V<br />
D3357<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
DZ3353<br />
0201-THICKSTNCL<br />
5.5V-6.2PF<br />
X3DFN2-THICKSTNCL<br />
DZ3302<br />
0201-THICKSTNCL<br />
5.5V-6.2PF<br />
USBC_XB_CC2<br />
10% 6.3V X5R-CERM 0201<br />
GND_VOID=TRUE<br />
10%<br />
BYPASS=J3300.58::2MM<br />
C3362<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
GND_VOID=TRUE<br />
0.22UF<br />
GND_VOID=TRUE<br />
0.22UF<br />
0.22UF<br />
X5R-CERM 0201<br />
6.3V X5R-CERM 0201<br />
USBC_XB_R2D_C_N<br />
USBC_XB_R2D_C_P<br />
USBC_XB_USB_TOP_P<br />
USBC_XB_USB_TOP_N<br />
USBC_XB_D2R_N<br />
USBC_XB_D2R_P<br />
USBC_XB_SBU1<br />
USBC_XA_SBU2<br />
USBC_XA_R2D_C_P<br />
USBC_XA_R2D_C_N<br />
USBC_XA_USB_DBG_TOP_P<br />
USBC_XA_USB_DBG_TOP_N<br />
USBC_XA_D2R_P<br />
USBC_XA_D2R_N<br />
USBC_XA_CC1<br />
2<br />
1<br />
1<br />
2<br />
CRITICAL<br />
2<br />
1<br />
C3355<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
0201<br />
BI<br />
IN<br />
IN<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
IN<br />
IN<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
BI<br />
26<br />
26<br />
26<br />
26<br />
28<br />
30<br />
30<br />
30<br />
26<br />
26<br />
26<br />
26<br />
29<br />
29<br />
29<br />
30<br />
104 28 29<br />
104<br />
CC2<br />
TBT_R2D1<br />
USB2 TOP<br />
TBT_D2R1<br />
SBU1<br />
SBU2<br />
TBT_R2D0<br />
USB2 BOT<br />
TBT_D2R0<br />
CC1<br />
D<br />
C<br />
B<br />
1<br />
2<br />
C3310<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
C3316<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
C3311<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
C3313<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
C3314<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
C3315<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
PART NUMBER QTY DESCRIPTION<br />
REFERENCE DES CRITICAL BOM OPTION<br />
138S0683 2 CAP,CER,X5R,1UF,10%,25V,0402<br />
C3304, C3354 CRITICAL<br />
NOSTUFF<br />
A<br />
BOM_COST_GROUP=USB-C<br />
LAST CHANGE: Wed Apr 1 22:57:37 2015<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
USB-C CONNECTOR A<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
33 OF 145<br />
31 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
D<br />
TBT X "POC" Power-up Reset<br />
MAKE_BASE=TRUE<br />
P3V3_TBT_X_SX_EN_R<br />
NOSTUFF<br />
R3400<br />
0 402<br />
1 2<br />
MF-LF<br />
5% 1/16W<br />
C<br />
29<br />
30<br />
IN<br />
IN<br />
P3V3_TBT_X_SX_EN_R<br />
P3V3_TBT_X_SX_EN_R<br />
1<br />
R3404<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
R3401<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
P3V3_TBT_X_SX_EN<br />
30<br />
IN<br />
USBC_X_RESET_L_R<br />
1<br />
ON<br />
CRITICAL<br />
U3400<br />
SLG5AP1449V<br />
STDFN<br />
GND<br />
4<br />
1<br />
R3402<br />
100K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
D<br />
S<br />
2<br />
3<br />
MAKE_BASE=TRUE<br />
USBC_X_RESET_L_R<br />
TBTXPOCRST_SNS<br />
PP3V3_S5 101<br />
1<br />
3<br />
CRITICAL<br />
ENABLE<br />
SENSE<br />
6<br />
VCC<br />
U3401<br />
TPS3895ADRY<br />
USON<br />
SENSE_OUT<br />
MAKE_BASE=TRUE<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
PP3V3_S5_TBT_X_SW<br />
PP3V3_S5_TBT_X_SW 27 28<br />
PP3V3_S5_TBT_X_SW 26<br />
U3401<br />
CT<br />
4<br />
5<br />
Output<br />
Delay<br />
Vth<br />
Push-pull<br />
440us +/- 20us<br />
2.508V nominal<br />
USBC_X_RESET_L<br />
TBTXPOCRST_CT<br />
OUT<br />
26<br />
28<br />
C<br />
1<br />
R3403<br />
24.9K<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
GND<br />
2<br />
C3400 1<br />
100PF<br />
2<br />
5%<br />
25V<br />
C0G<br />
0201<br />
B<br />
NOSTUFF<br />
NOSTUFF<br />
R3431<br />
10K<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
D3400<br />
SC2<br />
K<br />
A<br />
DSF01S30SCAP<br />
1<br />
2<br />
C3431<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
NOSTUFF<br />
B<br />
A<br />
BOM_COST_GROUP=USB-C<br />
DESIGN: X502/DEV_MLB_U<br />
LAST CHANGE: Wed Feb 18 17:12:24 2015<br />
SYNC_MASTER=J79_GREG<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
USB-C CONNECTOR B<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
.<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
SYNC_DATE=03/24/2016<br />
dvt-fab09-0<br />
34 OF 145<br />
32 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
33<br />
28<br />
PP5V_S4_X_USBC<br />
101<br />
PP5V_S4<br />
100<br />
99<br />
PPBUS_G3H<br />
D<br />
SM<br />
R3503 1<br />
27.4K<br />
0.1%<br />
1/20W<br />
MF<br />
0201<br />
2<br />
NO_XNET_CONNECTION=1<br />
2<br />
XW3502<br />
1<br />
2<br />
XW3501<br />
1<br />
SM<br />
P5VUSBC_X_SENSE_DIV_XW<br />
P5VUSBC_X_RTN_DIV_XW<br />
1<br />
R3531<br />
27.4K<br />
0.1%<br />
1/20W<br />
MF<br />
2<br />
0201<br />
NO_XNET_CONNECTION=1<br />
1<br />
R3517<br />
191K<br />
0.1%<br />
1/20W<br />
MF<br />
0201<br />
2<br />
1<br />
2<br />
C3517<br />
22PF<br />
5%<br />
50V<br />
C0G<br />
0201<br />
PP5V_USBC_X_VCC<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=5V<br />
1<br />
2<br />
28<br />
C3522<br />
2.2UF<br />
10%<br />
10V<br />
X6S-CERM<br />
0402<br />
IN<br />
33<br />
UPC_X_5V_EN<br />
P5VUSBC_X_SENSE_DIV<br />
P5VUSBC_X_SREF<br />
P5VUSBC_X_VO<br />
P5VUSBC_X_OCSET<br />
P5VUSBC_X_PGOOD<br />
P5VUSBC_X_RTN_DIV<br />
P5VUSBC_X_FSEL<br />
15<br />
10<br />
7<br />
12<br />
11<br />
14<br />
4<br />
13<br />
EN<br />
FB<br />
R3501 1<br />
2.2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
SREF<br />
VO<br />
OCSET<br />
PGOOD<br />
RTN<br />
FSEL<br />
19<br />
VCC<br />
20<br />
U3500<br />
ISL95870AH<br />
UTQFN<br />
CRITICAL<br />
1<br />
R3506<br />
2.2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
PVCC<br />
PP5V_USBC_X_PVCC<br />
BOOT<br />
UGATE<br />
PHASE<br />
LGATE<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=5V<br />
1<br />
18<br />
17<br />
16<br />
1<br />
C3521<br />
10UF<br />
20%<br />
2<br />
10V<br />
X5R-CERM<br />
0402-7<br />
R3509 1<br />
2.2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
P5VUSBC_X_VBST<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
GATE_NODE=TRUE<br />
MIN_NECK_WIDTH=0.0520<br />
MIN_LINE_WIDTH=0.0900<br />
P5VUSBC_X_DRVH<br />
P5VUSBC_X_LL<br />
MIN_LINE_WIDTH=0.0900<br />
DIDT=TRUE<br />
MIN_NECK_WIDTH=0.0520<br />
SWITCH_NODE=TRUE<br />
DIDT=TRUE<br />
P5VUSBC_X_DRVL<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
GATE_NODE=TRUE<br />
DIDT=TRUE<br />
P5VUSBC_X_BOOT_RC<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
1<br />
2<br />
C3516<br />
0.1UF<br />
10%<br />
16V<br />
X7R-CERM<br />
0402<br />
R3539<br />
GATE_NODE=TRUE<br />
MIN_NECK_WIDTH=0.0520<br />
0 MIN_LINE_WIDTH=0.0900<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
P5VUSBC_X_DRVH_R<br />
1<br />
2<br />
3<br />
4<br />
C3504 1<br />
33UF<br />
2<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
HSG<br />
Q3501<br />
FDPC1012S<br />
LLP<br />
SW<br />
C3503 1 33UF<br />
2<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
V+<br />
V+<br />
LSG<br />
8<br />
9<br />
7<br />
C3502 1<br />
33UF<br />
2<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
1<br />
2<br />
C3500<br />
2.2UF<br />
20%<br />
25V<br />
X5R-CERM<br />
0402-1<br />
L3500<br />
1.5UH-20%-12.5A-0.017OHM<br />
1 2<br />
PIMB062D-SM<br />
1<br />
2<br />
C3501<br />
2.2UF<br />
20%<br />
25V<br />
X5R-CERM<br />
0402-1<br />
P5VUSBC_X_R<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=5V<br />
P5VUSBC_X_POS<br />
CRITICAL<br />
2<br />
4<br />
R3530<br />
0.002<br />
1%<br />
1/2W<br />
MF<br />
0306<br />
1<br />
3<br />
C3505 1 2.2UF<br />
2<br />
20%<br />
25V<br />
X5R-CERM<br />
0402-1<br />
1<br />
2<br />
2.4G DESENSE<br />
C3506 1<br />
2.2UF<br />
2<br />
20%<br />
25V<br />
X5R-CERM<br />
0402-1<br />
CRITICAL<br />
C3510<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
PP5V_S4_X_USBC 28 33<br />
1<br />
2<br />
5G DESENSE<br />
C3508<br />
150UF<br />
20%<br />
6.3V<br />
TANT-POLY<br />
CASE-B1S-1<br />
CRITICAL<br />
C3511<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
C3507<br />
150UF<br />
20%<br />
6.3V<br />
TANT-POLY<br />
CASE-B1S-1<br />
D<br />
C<br />
1<br />
2<br />
C3526<br />
10PF<br />
5%<br />
50V<br />
C0G<br />
0201<br />
1<br />
R3504<br />
10K<br />
2<br />
0.1%<br />
1/20W<br />
MF<br />
0201-1<br />
1<br />
R3502<br />
10K<br />
0.1%<br />
1/20W<br />
MF<br />
2<br />
0201-1<br />
1<br />
2<br />
C3523 1<br />
0.1UF<br />
10%<br />
16V<br />
X5R-CERM<br />
2<br />
0201<br />
C3515<br />
10PF<br />
5%<br />
50V<br />
C0G<br />
0201<br />
1<br />
R3518<br />
95.3K<br />
0.1%<br />
1/20W<br />
MF<br />
2<br />
0201<br />
P5VUSBC_X_SET_R<br />
R3500<br />
11K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
NOSTUFF<br />
R3513 1<br />
0<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
P5VUSBC_X_SET0<br />
P5VUSBC_X_SET1<br />
P5VUSBC_X_AGND<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=0V<br />
8<br />
9<br />
6<br />
5<br />
SET0<br />
SET1<br />
VID0<br />
VID1<br />
3<br />
XW3500<br />
SM<br />
GND<br />
1 2<br />
PLACE_NEAR=U3500.2:1mm<br />
PGND<br />
2<br />
33<br />
P5VUSBC_X_PGOOD<br />
GND<br />
GND<br />
GND<br />
5<br />
6<br />
10<br />
P2MM<br />
SM<br />
1<br />
PP<br />
PP3500<br />
R35211 2.55K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
C3570<br />
2200PF<br />
2<br />
1<br />
10%<br />
25V<br />
CER-X7R<br />
0201<br />
P5VUSBC_X_NEG<br />
1<br />
R3572<br />
2.55K<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
Vout = 5.036V<br />
Freq = 500 kHz<br />
Max OCP = 13.05A<br />
Nom OCP = 10.84A<br />
Min OCP = 7.94A<br />
IccMax = 6.6A<br />
1<br />
2<br />
C3509<br />
150UF<br />
20%<br />
6.3V<br />
TANT-POLY<br />
CASE-B1S-1<br />
C<br />
B<br />
B<br />
A<br />
BOM_COST_GROUP=USB-C<br />
SYNC_MASTER=J79_JSHAO<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
TBT 5V REGULATOR<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
35 OF 145<br />
33 OF 119<br />
SYNC_DATE=12/18/2015<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
106<br />
101<br />
34<br />
PP3V3_S0<br />
D<br />
C<br />
OUTPUT CONNECTIONS SWAPPED<br />
COMPARED TO ARCHITECTURE<br />
SEL LOGIC INVERTED TO MAINTAIN<br />
CORRECT PAK LOGIC<br />
MANUAL STRAPS<br />
106 101 34<br />
PP3V3_S0<br />
TOWARDS AR T<br />
SNK1<br />
TOWARDS AR X<br />
SNK0<br />
R3604 1<br />
100K<br />
2<br />
5%<br />
1/20W<br />
201<br />
MF<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
94 92 34<br />
34 28 26<br />
IN<br />
DP_T_SNK1_ML_C_P<br />
DP_T_SNK1_ML_C_N<br />
DP_T_SNK1_ML_C_P<br />
DP_T_SNK1_ML_C_N<br />
DP_T_SNK1_ML_C_P<br />
DP_T_SNK1_ML_C_N<br />
DP_T_SNK1_ML_C_P<br />
DP_T_SNK1_ML_C_N<br />
DP_T_SNK1_AUXCH_C_P<br />
DP_T_SNK1_AUXCH_C_N<br />
DP_T_SNK1_HPD<br />
DP_X_SNK0_ML_C_P<br />
DP_X_SNK0_ML_C_N<br />
DP_X_SNK0_ML_C_P<br />
DP_X_SNK0_ML_C_N<br />
DP_X_SNK0_ML_C_P<br />
DP_X_SNK0_ML_C_N<br />
DP_X_SNK0_ML_C_P<br />
DP_X_SNK0_ML_C_N<br />
DP_X_SNK0_AUXCH_C_P<br />
DP_X_SNK0_AUXCH_C_N<br />
IN<br />
DP_X_SNK0_HPD<br />
DDI1_MUX_SEL_INV<br />
DDI1_MUX_EN<br />
NC<br />
NC<br />
NC<br />
NC<br />
B4<br />
A4<br />
B5<br />
A5<br />
B6<br />
A6<br />
A8<br />
A9<br />
H9<br />
J9<br />
H8<br />
J8<br />
J2<br />
B8<br />
B9<br />
D8<br />
D9<br />
E8<br />
E9<br />
F8<br />
F9<br />
H6<br />
J6<br />
H5<br />
J5<br />
H3<br />
A1<br />
B7<br />
D0+A<br />
D0-A<br />
D1+A<br />
D1-A<br />
D2+A<br />
D2-A<br />
D3+A<br />
D3-A<br />
AUX+A<br />
AUX-A<br />
SCL_A<br />
SDA_A<br />
HPD_A<br />
D0+B<br />
D0-B<br />
D1+B<br />
D1-B<br />
D2+B<br />
D2-B<br />
D3+B<br />
D3-B<br />
AUX+B<br />
AUX-B<br />
SCL_B<br />
SDA_B<br />
HPD_B<br />
GPU_SEL<br />
OE<br />
A2<br />
J4<br />
VDD<br />
VDD<br />
U3600<br />
PI3WVR12612NEE<br />
BGA<br />
CRITICAL<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
D0+<br />
D0-<br />
D1+<br />
D1-<br />
D3+<br />
D3-<br />
D2+<br />
D2-<br />
AUX+<br />
AUX-<br />
HPD<br />
SCL<br />
SDA<br />
DDC_AUX_SEL<br />
B2<br />
B1<br />
D2<br />
D1<br />
E2<br />
E1<br />
F2<br />
F1<br />
H2<br />
H1<br />
J1<br />
J3<br />
J7<br />
C2<br />
1<br />
2<br />
C3600<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
BYPASS=U3600.J4::5MM<br />
NC<br />
NC<br />
DP_DDI1_ML_C_P<br />
DP_DDI1_ML_C_N<br />
DP_DDI1_ML_C_P<br />
DP_DDI1_ML_C_N<br />
DP_DDI1_ML_C_P<br />
DP_DDI1_ML_C_N<br />
DP_DDI1_ML_C_P<br />
DP_DDI1_ML_C_N<br />
DP_DDI1_AUXCH_C_P<br />
DP_DDI1_AUXCH_C_N<br />
DP_DDPB_HPD<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
BI<br />
BI<br />
1<br />
2<br />
5<br />
5<br />
5<br />
5<br />
5<br />
5<br />
5<br />
5<br />
5<br />
5<br />
OUT<br />
105<br />
105<br />
5<br />
R3600<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
FROM CPU<br />
D<br />
C<br />
92<br />
26<br />
OUT<br />
OUT<br />
DDI1_MUX_SEL<br />
DDI1_MUX_SEL<br />
MAKE_BASE=TRUE<br />
DDI1_MUX_SEL<br />
R3602 1<br />
100K<br />
2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
DISP MUX GPU_SEL<br />
0 = TBT T<br />
1 = TBT X<br />
106<br />
101<br />
34<br />
PP3V3_S0<br />
B3<br />
C8<br />
G8<br />
H4<br />
H7<br />
G2<br />
B<br />
A<br />
94 92 34<br />
94 92 34<br />
34 28 26<br />
34 28 26<br />
IN<br />
IN<br />
IN<br />
IN<br />
106<br />
101<br />
34<br />
DP_T_SNK0_HPD<br />
DP_T_SNK1_HPD<br />
DP_X_SNK0_HPD<br />
DP_X_SNK1_HPD<br />
PP3V3_S0<br />
BYPASS=U3620.1::5MM<br />
26<br />
92<br />
OUT<br />
OUT<br />
3<br />
2<br />
5<br />
4<br />
C3620 1<br />
0.1UF<br />
2<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
HPD_T0<br />
HPD_T1<br />
HPD_X0<br />
HPD_X1<br />
1<br />
U3620<br />
SLG4AP4971<br />
STQFN<br />
OMIT_TABLE<br />
11<br />
VDD<br />
GND<br />
DDI2_MUX_SEL<br />
DDI2_MUX_SEL<br />
R3621 1<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
SEL_GM0<br />
SEL_GM1<br />
SEL_GM0_INV<br />
SEL_GM1_INV<br />
OE_GM_0<br />
OE_GM_1<br />
FLAG<br />
NC<br />
10<br />
9<br />
12<br />
13<br />
8<br />
7<br />
6<br />
14<br />
15<br />
16<br />
17<br />
18<br />
19<br />
20<br />
TP_DPMUX_SAK_13<br />
TP_DPMUX_SAK_6<br />
106<br />
106<br />
NC_DPMUX_SAK_14 102<br />
NC_DPMUX_SAK_15 102<br />
NC_DPMUX_SAK_16 102<br />
NC_DPMUX_SAK_17 102<br />
NC_DPMUX_SAK_18 102<br />
NC_DPMUX_SAK_19 102<br />
NC_DPMUX_SAK_20 102<br />
TOWARDS AR T<br />
SNK0<br />
TOWARDS AR X<br />
SNK1<br />
R3611 1<br />
100K<br />
2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
26<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
94 92 34<br />
34 28 26<br />
R3612 1<br />
100K<br />
2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
IN<br />
DP_T_SNK0_ML_C_P<br />
DP_T_SNK0_ML_C_N<br />
DP_T_SNK0_ML_C_P<br />
DP_T_SNK0_ML_C_N<br />
DP_T_SNK0_ML_C_P<br />
DP_T_SNK0_ML_C_N<br />
DP_T_SNK0_ML_C_P<br />
DP_T_SNK0_ML_C_N<br />
DP_T_SNK0_AUXCH_C_P<br />
DP_T_SNK0_AUXCH_C_N<br />
DP_T_SNK0_HPD<br />
DP_X_SNK1_ML_C_P<br />
DP_X_SNK1_ML_C_N<br />
DP_X_SNK1_ML_C_P<br />
DP_X_SNK1_ML_C_N<br />
DP_X_SNK1_ML_C_P<br />
DP_X_SNK1_ML_C_N<br />
DP_X_SNK1_ML_C_P<br />
DP_X_SNK1_ML_C_N<br />
DP_X_SNK1_AUXCH_C_P<br />
DP_X_SNK1_AUXCH_C_N<br />
IN<br />
DP_X_SNK1_HPD<br />
MAKE_BASE=TRUE<br />
DDI2_MUX_SEL<br />
DDI2_MUX_EN<br />
DISP MUX GPU_SEL<br />
0 = TBT T<br />
1 = TBT X<br />
NC<br />
NC<br />
NC<br />
NC<br />
B4<br />
A4<br />
B5<br />
A5<br />
B6<br />
A6<br />
A8<br />
A9<br />
H9<br />
J9<br />
H8<br />
J8<br />
J2<br />
B8<br />
B9<br />
D8<br />
D9<br />
E8<br />
E9<br />
F8<br />
F9<br />
H6<br />
J6<br />
H5<br />
J5<br />
H3<br />
A1<br />
B7<br />
D0+A<br />
D0-A<br />
D1+A<br />
D1-A<br />
D2+A<br />
D2-A<br />
D3+A<br />
D3-A<br />
AUX+A<br />
AUX-A<br />
SCL_A<br />
SDA_A<br />
HPD_A<br />
D0+B<br />
D0-B<br />
D1+B<br />
D1-B<br />
D2+B<br />
D2-B<br />
D3+B<br />
D3-B<br />
AUX+B<br />
AUX-B<br />
SCL_B<br />
SDA_B<br />
HPD_B<br />
GPU_SEL<br />
OE<br />
A2<br />
J4<br />
VDD<br />
VDD<br />
U3610<br />
PI3WVR12612NEE<br />
BGA<br />
CRITICAL<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
B3<br />
C8<br />
G8<br />
H4<br />
H7<br />
G2<br />
D0+<br />
D0-<br />
D1+<br />
D1-<br />
D3+<br />
D3-<br />
D2+<br />
D2-<br />
AUX+<br />
AUX-<br />
HPD<br />
SCL<br />
SDA<br />
DDC_AUX_SEL<br />
B2<br />
B1<br />
D2<br />
D1<br />
E2<br />
E1<br />
F2<br />
F1<br />
H2<br />
H1<br />
J1<br />
J3<br />
J7<br />
C2<br />
1<br />
2<br />
C3610<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
BYPASS=U3610.J4::5MM<br />
NC<br />
NC<br />
DP_DDI2_ML_C_P<br />
DP_DDI2_ML_C_N<br />
DP_DDI2_ML_C_P<br />
DP_DDI2_ML_C_N<br />
DP_DDI2_ML_C_P<br />
DP_DDI2_ML_C_N<br />
DP_DDI2_ML_C_P<br />
DP_DDI2_ML_C_N<br />
DP_DDI2_AUXCH_C_P<br />
DP_DDI2_AUXCH_C_N<br />
DP_DDPC_HPD<br />
105<br />
BOM_COST_GROUP=GRAPHICS<br />
1<br />
2<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
BI<br />
BI<br />
5<br />
5<br />
5<br />
5<br />
5<br />
5<br />
5<br />
5<br />
5<br />
5<br />
OUT<br />
105<br />
5<br />
R3610<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
FROM CPU<br />
SYNC_MASTER=J79_GREG<br />
PAGE TITLE<br />
R<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
Display Mux<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
IV ALL RIGHTS RESERVED<br />
Apple Inc.<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
36 OF 145<br />
34 OF 119<br />
SYNC_DATE=02/28/2016<br />
SIZE<br />
D<br />
B<br />
A<br />
8 7 6<br />
5 4 3<br />
2 1
SYNC_MASTER=J79_METE<br />
SYNC_DATE=05/17/2016<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
C<br />
B<br />
A<br />
101<br />
102<br />
103<br />
104<br />
105<br />
106<br />
107<br />
108<br />
109<br />
110<br />
111<br />
112<br />
113<br />
114<br />
115<br />
116<br />
117<br />
118<br />
119<br />
120<br />
121<br />
122<br />
123<br />
124<br />
125<br />
126<br />
127<br />
128<br />
129<br />
130<br />
131<br />
132<br />
133<br />
134<br />
135<br />
136<br />
137<br />
138<br />
139<br />
140<br />
141<br />
142<br />
143<br />
144<br />
145<br />
146<br />
147<br />
148<br />
149<br />
150<br />
151<br />
152<br />
153<br />
154<br />
155<br />
156<br />
157<br />
158<br />
159<br />
160<br />
161<br />
162<br />
163<br />
164<br />
165<br />
166<br />
167<br />
168<br />
169<br />
170<br />
171<br />
172<br />
173<br />
174<br />
175<br />
176<br />
177<br />
178<br />
179<br />
180<br />
181<br />
182<br />
183<br />
184<br />
185<br />
186<br />
187<br />
188<br />
189<br />
190<br />
191<br />
192<br />
193<br />
194<br />
195<br />
196<br />
THRM_PAD<br />
U3730<br />
LBEE5UQ1HG-844<br />
LGA<br />
SYM 2 OF 2<br />
THRM_PAD<br />
197<br />
198<br />
199<br />
200<br />
201<br />
202<br />
203<br />
204<br />
205<br />
206<br />
207<br />
208<br />
209<br />
210<br />
211<br />
212<br />
213<br />
214<br />
215<br />
216<br />
217<br />
218<br />
219<br />
220<br />
221<br />
222<br />
223<br />
224<br />
225<br />
226<br />
227<br />
228<br />
229<br />
230<br />
231<br />
232<br />
233<br />
234<br />
235<br />
236<br />
237<br />
238<br />
239<br />
240<br />
241<br />
242<br />
243<br />
244<br />
245<br />
246<br />
247<br />
248<br />
249<br />
250<br />
251<br />
252<br />
253<br />
254<br />
255<br />
256<br />
257<br />
258<br />
259<br />
260<br />
261<br />
262<br />
263<br />
264<br />
265<br />
266<br />
267<br />
268<br />
269<br />
270<br />
271<br />
272<br />
273<br />
274<br />
275<br />
276<br />
277<br />
278<br />
279<br />
280<br />
281<br />
282<br />
283<br />
284<br />
285<br />
286<br />
287<br />
288<br />
289<br />
290<br />
291<br />
292<br />
101<br />
PP3V3_S4_BT<br />
MAKE_BASE=TRUE<br />
35<br />
35<br />
35<br />
1<br />
2<br />
19 14<br />
SPROM_DOUT<br />
SPROM_CS<br />
SPROM_CLK<br />
PP3V3_S4_BT<br />
C3761<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
FEM SUPPLY SHUNT CAPACITORS<br />
PLACE ON THE TOP SIDE CLOSE TO U3730<br />
SROM_STRAPS<br />
PP3V3_S4_WLAN_SW<br />
NOSTUFF<br />
R3731 1<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
WLAN_STRAP_0<br />
STRAP_0 HI:SROM (Default)<br />
STRAP_1 LO:16kb SROM<br />
35<br />
35<br />
35<br />
1<br />
2<br />
PP3V3_S4_BT<br />
BT_SPI2_CSN<br />
C3740<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
35<br />
R3751 1<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
PP3V3_S4_WLAN_SW<br />
PP3V3_S4_BT 35<br />
PP3V3_S4_BT 35<br />
WLAN SERIAL EEPROM<br />
VOLTAGE=3.3V<br />
PP3V3_S4_BT 35 PP3V3_S4_WLAN_SW 35<br />
WLAN_STRAP_1<br />
PCH_BT_ROM_BOOT<br />
U3710<br />
CAS93C86B<br />
3 UDFN8<br />
DI<br />
DO 4<br />
1 CS<br />
6<br />
2<br />
ORG<br />
SK<br />
7 PE<br />
OMIT_TABLE<br />
GND EPAD<br />
5<br />
8<br />
9<br />
1<br />
2<br />
R3734 1<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
C3736<br />
10UF<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402-4<br />
R3752 1<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
1<br />
2<br />
1<br />
2<br />
1<br />
2<br />
C3762<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
R3754<br />
1K<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
0.1UF<br />
10%<br />
35V<br />
CER-X5R<br />
0201<br />
106 53 36 35<br />
SPROM_DIN<br />
WIFI_SROM_ORG<br />
Q3701<br />
DMN32D2LFB4<br />
DFN1006H4-3<br />
3<br />
R3753 1<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
C3711<br />
1<br />
2<br />
BT_SFLASH_HOLD_L<br />
35 35<br />
35<br />
35<br />
IN<br />
NC<br />
VCC<br />
G<br />
S<br />
PP3V3_S4_WLAN_SW<br />
3.0PF<br />
NOSTUFF<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
MAKE_BASE=TRUE<br />
35<br />
C3763<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
R3701<br />
PP3V3_S4_WLAN_SW<br />
BLUETOOTH SERIAL FLASH<br />
BT_SFLASH_WP_L<br />
R3712<br />
2<br />
35<br />
SYM_VER_3<br />
D<br />
10K<br />
5%<br />
MF<br />
201<br />
1<br />
35<br />
1<br />
C3742<br />
12PF<br />
5%<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
R3759<br />
270K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
BT_SPI2_CLK<br />
BT_SFLASH_CS_L<br />
1<br />
2<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
WLAN_JTAG_SEL<br />
WLAN_EXT_POR_L<br />
35<br />
35 13 6<br />
IN<br />
35<br />
35<br />
35<br />
35<br />
35<br />
35<br />
35<br />
PP3V3_S4_WLAN_SW 35<br />
PP3V3_S4_WLAN_SW 35<br />
C3741<br />
8<br />
VCC<br />
OMIT_TABLE<br />
WLAN_STRAP_0<br />
WLAN_STRAP_1<br />
SPROM_CLK<br />
SPROM_DOUT<br />
SPROM_CS<br />
SPROM_DIN<br />
BT_SPI2_MOSI<br />
BT_SPI2_CSN<br />
BT_SPI2_MISO<br />
BT_SPI2_CLK<br />
BT_ROM_BOOT_L<br />
BT_TIMESTAMP<br />
U3750<br />
2MBIT<br />
PP1V8_S4 18 19 100<br />
PRECISION ELPO<br />
WLAN_UART_RX<br />
WLAN_UART_TX<br />
WLAN_JTAG_TDI<br />
WLAN_JTAG_TMS<br />
WLAN_JTAG_TCK<br />
WLAN_JTAG_TRST_L<br />
CORE2_5G_CTL2_WLAN_JTAG_TDO<br />
USON<br />
6 SCLK<br />
SI/SIO0 5<br />
MX25L2006EZUI-12G<br />
4<br />
VCC<br />
CRITICAL<br />
4<br />
U3780<br />
9<br />
SO/SIO1 2<br />
32.768KHZ-25PPM-15PF-5.5V<br />
2.50X2.00-SM-COMBO<br />
1 EN/DIS OUT 3<br />
GND<br />
2<br />
1<br />
2<br />
C3737<br />
10UF<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402-4<br />
1<br />
1<br />
2<br />
36<br />
36<br />
36<br />
36<br />
36<br />
36<br />
C3780<br />
0.1UF<br />
C3738<br />
10UF<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402-4<br />
SYSCLK_CLK32K_OSC_OUT<br />
FOR JTAG MODE REMOVE R3735<br />
C3756<br />
0.1UF<br />
10%<br />
35V<br />
CER-X5R<br />
0201<br />
50_G_0_MATCH<br />
50_G_1_MATCH<br />
50_G_2_MATCH<br />
50_A_0_MATCH<br />
50_A_1_MATCH<br />
50_A_2_MATCH<br />
BT_SPI2_MOSI<br />
BT_SPI2_MISO<br />
10%<br />
2<br />
10V<br />
X5R-CERM<br />
0201<br />
BYPASS=U3780.4::5MM<br />
1<br />
2<br />
R3780<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
NO_XNET_CONNECTION=1<br />
R3735<br />
2<br />
0<br />
5%<br />
1/20W<br />
MF<br />
201<br />
SYSCLK_CLK32K_WIFIBT<br />
1<br />
WLAN_1P2V_EN<br />
45<br />
47<br />
63<br />
78<br />
61<br />
74<br />
85<br />
22<br />
23<br />
93<br />
72<br />
71<br />
70<br />
94<br />
21<br />
92<br />
91<br />
90<br />
97<br />
98<br />
99<br />
100<br />
58<br />
59<br />
65<br />
66<br />
29<br />
28<br />
27<br />
35 WLAN_JTAG_TCK<br />
35 WLAN_JTAG_TMS<br />
35 WLAN_JTAG_TDI<br />
CORE2_5G_CTL2_WLAN_JTAG_TDO<br />
35 WLAN_JTAG_TRST_L<br />
WLAN_JTAG_SEL<br />
35<br />
SMC_WIFI_PWR_EN<br />
WLAN_UART_TX<br />
WLAN_UART_RX<br />
AP_CLKREQ_L<br />
AP_RESET_L<br />
AP_PCIE_WAKE_L<br />
PP3V3_S4_WLAN_SW<br />
PP3V3_S4_BT 35<br />
BT_SPI2_CLK 1 2 BT_SPI2_CLK_R BT_SPI2_MISO<br />
WIFI_DBG<br />
BT_SPI2_CSN<br />
95<br />
2<br />
1<br />
3<br />
5<br />
8<br />
11<br />
14<br />
18<br />
20<br />
26<br />
R3781<br />
0<br />
5%<br />
1/20W<br />
MF<br />
201<br />
WIFI_DBG<br />
89<br />
96<br />
R3782<br />
0<br />
88<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
68<br />
1<br />
2<br />
81<br />
55<br />
U3730<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
BT_SPI2_CSN_R<br />
C3758<br />
LBEE5UQ1HG-844<br />
LGA<br />
CRITICAL<br />
24<br />
32<br />
30<br />
C3757<br />
12PF<br />
DEBUG CONNECTOR<br />
WIFI_DBG<br />
1<br />
J3701<br />
AA25D-S038VA1<br />
F-ST-SM<br />
39 40<br />
1 2<br />
3 4<br />
5 6<br />
7 8<br />
9 10<br />
11 12<br />
13 14<br />
15 16<br />
17 18<br />
19 20<br />
21 22<br />
23 24<br />
25 26<br />
27 28<br />
29 30<br />
31 32<br />
33 34<br />
35 36<br />
37 38<br />
41 42<br />
5%<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
WIFI_DBG<br />
BT_SPI2_MOSI<br />
C3704<br />
10UF<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402-4<br />
38<br />
39<br />
40<br />
44<br />
46<br />
48<br />
51<br />
54<br />
60<br />
62<br />
64<br />
67<br />
69<br />
73<br />
75<br />
76<br />
77<br />
79<br />
80<br />
82<br />
83<br />
84<br />
86<br />
87<br />
19<br />
WIFI_DBG<br />
BT_LOW_PWR_L 35<br />
SMC_PME_S4_DARK_L 35 50<br />
SMC_BT_PWR_EN<br />
BT_UART_D2R<br />
BT_UART_R2D<br />
BT_UART_CTS_R2D_L<br />
BT_UART_RTS_D2R_L<br />
BT_SPI2_CLK_R<br />
BT_SPI2_CSN_R<br />
BT_SPI2_MISO_R<br />
BT_SPI2_MOSI_R<br />
BT_ROM_BOOT_L<br />
BT_TIMESTAMP<br />
BT_SWDIO<br />
BT_SWDCLK<br />
SYSCLK_CLK32K_WIFIBT<br />
1<br />
2<br />
R3783<br />
PP3V3_S4_WLAN_SW 35<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
6<br />
7<br />
10<br />
9<br />
13<br />
12<br />
15<br />
16<br />
17<br />
43<br />
41<br />
42<br />
36<br />
37<br />
57<br />
56<br />
4<br />
25<br />
33<br />
35<br />
49<br />
50<br />
52<br />
53<br />
31<br />
34<br />
1<br />
PP3V3_S4_WLAN_SW 35<br />
PCIE_AP_R2D_P<br />
PCIE_AP_R2D_N<br />
PCIE_AP_D2R_P<br />
PCIE_AP_D2R_N<br />
PCIE_CLK100M_AP_P<br />
PCIE_CLK100M_AP_N<br />
AP_PCIE_WAKE_L<br />
AP_CLKREQ_L<br />
AP_RESET_CONN_L<br />
BT_UART_CTS_R2D_L<br />
BT_UART_RTS_D2R_L<br />
BT_UART_R2D<br />
BT_UART_D2R<br />
BT_SWDIO<br />
BT_SWDCLK<br />
WL_CLK32K<br />
35<br />
BT_RX_ACTIVE<br />
SMC_PME_S4_DARK_L<br />
BT_LOW_PWR_L<br />
BT_I2S_SYNC<br />
BT_I2S_R2D<br />
BT_I2S_D2R<br />
BT_I2S_CLK<br />
BT_ROM_BOOT_L<br />
BT_TIMESTAMP<br />
SMC_BT_PWR_EN<br />
BT_SPI2_MISO_R<br />
R3784<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
C3705<br />
0.1UF<br />
10%<br />
2<br />
35V<br />
CER-X5R<br />
0201<br />
C3739 1<br />
10UF<br />
2<br />
35 19<br />
35<br />
1 CS*<br />
3 WP*<br />
7 HOLD*<br />
35<br />
35<br />
35<br />
35<br />
NC<br />
35<br />
35<br />
50 35<br />
50 35<br />
GND<br />
THRM<br />
PAD<br />
19<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
NC<br />
35<br />
35<br />
35 35 35<br />
35<br />
BT_RF1<br />
2G_ANT_CORE0<br />
2G_ANT_CORE1<br />
2G_ANT_CORE2<br />
5G_ANT_CORE0<br />
5G_ANT_CORE1<br />
5G_ANT_CORE2<br />
19<br />
1P2V_EN<br />
WL_GPIO_6/UART_RX<br />
WL_GPIO_7/UART_TX<br />
WL_JTAG_TDI/GPIO_3<br />
WL_JTAG_TMS<br />
WL_JTAG_TCK<br />
WL_JTAG_TRST*<br />
WL_JTAG_SEL<br />
WLAN_EXT_POR*<br />
WL_JTAG_TDO<br />
C0_FEMCTRL_2/STRAP_0<br />
C2_FEMCTRL_2/STRAP_1<br />
SPROM_CLK<br />
SPROM_DOUT<br />
SPROM_CS<br />
SPROM_DIN<br />
BT_SPI2_MOSI<br />
BT_SPI2_CSN<br />
BT_SPI2_MISO<br />
BT_SPI2_CLK<br />
35<br />
35<br />
VDD3P3<br />
BT_GPIO_2/BT_JTAG_TRST_N<br />
BT_GPIO_3<br />
BT_GPIO_4<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
VDD3P3_PAD<br />
VDD3P3_REG1P2<br />
50 48 36<br />
50 35<br />
50 35<br />
35<br />
35 18<br />
VDD3P3_REG1P8<br />
35 19<br />
36 19 16<br />
VDD3P3_FEM_CORE1<br />
VDD3P3_FEM_CORE2<br />
VDD3P3_FEM_CORE0<br />
SYM 1 OF 2<br />
VDD_BT<br />
35<br />
BT_RX_ACTIVE/BT_GPIO_5<br />
BT_UART_CTS*/BT_JTAG_TMS<br />
BT_UART_RTS*/BT_JTAG_TCK<br />
BT_UART_RXD/BT_JTAG_TDI<br />
BT_UART_TXD/BT_JTAG_TDO<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
BT_VDDIO<br />
BT_OTP_VDD3P3V<br />
WL_VDDIO<br />
PCIE_RDP<br />
PCIE_RDN<br />
PCIE_TDP<br />
PCIE_TDN<br />
PCIE_REFCLK_PC<br />
PCIE_REFCLK_NC<br />
PCIE_WAKE_CL<br />
PCIE_CLKREQ*<br />
PCIE_PRST*<br />
BT_SWDIO<br />
BT_SWDCLK<br />
WL_XTAL32<br />
BT_XTAL32<br />
BT_HOST_WAKE/BT_HOST_WAKE*<br />
BT_DEV_WAKE<br />
BT_PCM_SYNC<br />
BT_PCM_IN<br />
BT_PCM_OUT<br />
BT_PCM_CLK<br />
BT_RST*<br />
BT_JTAG_SEL<br />
GND<br />
GND<br />
35<br />
35<br />
35<br />
48<br />
35<br />
35<br />
35<br />
35<br />
19<br />
35<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402-4<br />
BT_SPI2_MOSI_R<br />
104 35 19 14<br />
35 35<br />
35<br />
35<br />
35<br />
35<br />
NC<br />
BOM_COST_GROUP=WIRELESS<br />
35<br />
6<br />
13<br />
19<br />
19<br />
19<br />
35<br />
35<br />
35<br />
48<br />
35<br />
35<br />
35<br />
35<br />
16<br />
16<br />
104 35 19 14<br />
35<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
OUT<br />
BI<br />
IN<br />
PP3V3_S4_BT 35<br />
1<br />
2<br />
GND_VOID=TRUE<br />
15<br />
15<br />
15<br />
15<br />
18<br />
36<br />
35<br />
19<br />
C3701<br />
0.1UF<br />
10%<br />
35V<br />
CER-X5R<br />
0201<br />
105<br />
105<br />
35<br />
35<br />
PP3V3_S4_WLAN_SW<br />
Q3702<br />
BT_LOW_PWR_L<br />
MAKE_BASE=TRUE<br />
IN<br />
IN<br />
IN<br />
IN<br />
35<br />
35<br />
DMN32D2LFB4<br />
1<br />
2<br />
C3759<br />
G<br />
S<br />
0.1UF<br />
2<br />
10%<br />
6.3V<br />
X7R<br />
0201<br />
R3762<br />
2<br />
1<br />
GND_VOID=TRUE<br />
10K<br />
5%<br />
MF<br />
201<br />
1<br />
DFN1006H4-3<br />
IN<br />
3<br />
14<br />
PP3V3_S4_BT 35<br />
BT_UART_CTS_R2D_L<br />
BT_UART_RTS_D2R_L<br />
BT_UART_R2D<br />
BT_UART_D2R<br />
PP3V3_S4_WLAN_SW 35<br />
BT UART TX & RTS ISOLATION CIRCUIT<br />
BT_UART_RTS_D2R_L<br />
BT_UART_D2R<br />
PLT_RST_L<br />
GND_VOID=TRUE<br />
SYM_VER_3<br />
D<br />
BT UART RX & CTS ISOLATION CIRCUIT<br />
PCH_BT_UART_RTS_L<br />
PCH_BT_UART_R2D<br />
PLT_RST_L<br />
PAGE TITLE<br />
35<br />
C3760<br />
0.1UF<br />
2<br />
1<br />
10%<br />
6.3V<br />
X7R<br />
0201<br />
36<br />
R<br />
35<br />
35<br />
35<br />
53<br />
35<br />
106<br />
2<br />
1<br />
5<br />
7<br />
2<br />
1<br />
5<br />
7<br />
1<br />
C3703<br />
0.1UF<br />
10%<br />
2<br />
35V<br />
CER-X5R<br />
0201<br />
GND_VOID=TRUE<br />
35<br />
PCIE_AP_R2D_C_P<br />
PCIE_AP_R2D_C_N<br />
50<br />
35<br />
U3760<br />
35<br />
8<br />
8<br />
U3770<br />
PP3V3_S4_BT<br />
74LVC2G126<br />
X2-DFN2010<br />
A1CRITICAL<br />
Y1<br />
1OE<br />
A2<br />
Y2<br />
2OE<br />
4<br />
PP3V3_S4_BT<br />
74LVC2G126<br />
X2-DFN2010<br />
A1CRITICAL<br />
Y1<br />
1OE<br />
A2<br />
Y2<br />
2OE<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
4<br />
R3766<br />
R3767<br />
R3776<br />
R3777<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
SYSCLK_CLK32K_WIFIBT<br />
PCH_BT_UART_CTS_L<br />
PCH_BT_UART_D2R<br />
BT_UART_CTS_R2D_L<br />
BT_UART_R2D<br />
WIFI/BT: MODULE 1<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
IV ALL RIGHTS RESERVED<br />
OUT<br />
VCC<br />
GND<br />
VCC<br />
GND<br />
Apple Inc.<br />
6<br />
3<br />
6<br />
3<br />
1<br />
C3702<br />
0.1UF<br />
10%<br />
2<br />
35V<br />
CER-X5R<br />
0201<br />
2<br />
2<br />
2<br />
2<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
IN<br />
IN 15<br />
1<br />
2<br />
1<br />
2<br />
1<br />
1<br />
1<br />
1<br />
15<br />
0.1UF<br />
10%<br />
35V<br />
CER-X5R<br />
0201<br />
0.1UF<br />
10%<br />
35V<br />
CER-X5R<br />
0201<br />
PP3V3_S4_BT 35<br />
C3764<br />
C3774<br />
DRAWING NUMBER<br />
9.0.0<br />
dvt-fab09-0<br />
37 OF 145<br />
35 OF 119<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
35<br />
35<br />
OUT<br />
OUT<br />
051-00777<br />
19<br />
16<br />
16<br />
35<br />
SIZE<br />
D<br />
D<br />
C<br />
B<br />
A<br />
8 7 6<br />
5 4 3<br />
2 1
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
CRITICAL<br />
L3811<br />
2.7NH+/-0.1NH-0.6A<br />
CORE0 DIPLEXER AND MATCHING<br />
50_G_0_DIPLEXER<br />
NO STUFF<br />
C3812 1<br />
0.2PF<br />
2<br />
+/-0.05PF<br />
25V<br />
COG-CERM<br />
0201<br />
1 2<br />
0201<br />
1<br />
2<br />
50_G_0_MATCH<br />
NO STUFF<br />
C3810<br />
0.2PF<br />
+/-0.05PF<br />
25V<br />
COG-CERM<br />
0201<br />
35<br />
D<br />
WLAN Power Switch<br />
PP3V3_S4 36 101 106<br />
CRITICAL<br />
J3810<br />
20449-001E-03<br />
F-ST-SM<br />
2<br />
3<br />
4<br />
1<br />
50_0_ANT<br />
NO STUFF<br />
C3817 1<br />
0.2PF<br />
2<br />
+/-0.05PF<br />
25V<br />
COG-CERM<br />
0201<br />
CRITICAL<br />
L3810<br />
1.2NH-+/-0.05NH-1.1A-0.04OHM<br />
1 2<br />
0201<br />
1<br />
CRITICAL<br />
C3816<br />
0.2PF<br />
+/-0.05PF<br />
25V<br />
COG-CERM<br />
0201<br />
50_0_COM<br />
U3810<br />
LFD212G45MJCD900<br />
LLP<br />
2<br />
P3<br />
GND<br />
50_A_0_DIPLEXER<br />
2<br />
0.2PF<br />
5<br />
3<br />
1<br />
P1<br />
P2<br />
4<br />
6<br />
NO STUFF<br />
C3815 1 2<br />
+/-0.05PF<br />
25V<br />
COG-CERM<br />
0201<br />
CRITICAL<br />
L3814<br />
1.0NH-+/-0.05NH-1.1A-0.04OHM<br />
1 2<br />
0201<br />
1<br />
50_A_0_MATCH<br />
CRITICAL<br />
L3813<br />
5.1NH-3%-0.4A<br />
0201<br />
35<br />
D<br />
1<br />
WIFI_SW_CAP<br />
VDD<br />
U3840<br />
SLG5AP1443V<br />
TDFN<br />
7 CAP<br />
D 3<br />
2<br />
50 48 36 35<br />
SMC_WIFI_PWR_EN<br />
1<br />
2<br />
C3841<br />
4700PF<br />
10%<br />
10V<br />
X7R<br />
201<br />
2 ON<br />
S 5<br />
GND<br />
8<br />
PP3V3_S4_WLAN_SW_R<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
53<br />
CRITICAL<br />
L3821<br />
2.7NH+/-0.1NH-0.6A<br />
C<br />
Supervisor & CLKREQ# Isolation<br />
Delay = 130ms +/- 20%<br />
CRITICAL<br />
J3<strong>820</strong><br />
20449-001E-03<br />
F-ST-SM<br />
2<br />
3<br />
4<br />
1<br />
50_1_ANT<br />
NO STUFF<br />
C3827 1<br />
0.2PF<br />
2<br />
+/-0.05PF<br />
25V<br />
COG-CERM<br />
0201<br />
CORE1 DIPLEXER AND MATCHING<br />
CRITICAL<br />
L3<strong>820</strong><br />
1.2NH-+/-0.05NH-1.1A-0.04OHM<br />
1 2<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C3826<br />
0.2PF<br />
+/-0.05PF<br />
25V<br />
COG-CERM<br />
0201<br />
50_1_COM<br />
U3<strong>820</strong><br />
LFD212G45MJCD900<br />
LLP<br />
2<br />
P3<br />
GND<br />
P1<br />
P2<br />
1<br />
3<br />
5<br />
4<br />
6<br />
50_G_1_DIPLEXER<br />
NO STUFF<br />
C3822 1<br />
0.2PF<br />
2<br />
+/-0.05PF<br />
25V<br />
COG-CERM<br />
0201<br />
50_A_1_DIPLEXER<br />
NO STUFF<br />
C3825 1<br />
0.2PF<br />
+/-0.05PF<br />
25V<br />
2<br />
COG-CERM<br />
0201<br />
1 2<br />
0201<br />
CRITICAL<br />
L3824<br />
1.2NH-+/-0.05NH-1.1A-0.04OHM<br />
1 2<br />
0201<br />
1<br />
2<br />
50_G_1_MATCH<br />
1<br />
2<br />
NO STUFF<br />
C3<strong>820</strong><br />
0.2PF<br />
+/-0.05PF<br />
25V<br />
COG-CERM<br />
0201<br />
50_A_1_MATCH<br />
CRITICAL<br />
L3823<br />
5.1NH-3%-0.4A<br />
0201<br />
35<br />
35<br />
C<br />
B<br />
35<br />
OUT<br />
AP_RESET_CONN_L<br />
106 53 35<br />
NOSTUFF<br />
R3859<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
PP3V3_S4_WLAN_SW<br />
NOSTUFF<br />
R3856 1<br />
232K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
NOSTUFF<br />
WLAN_3V3_VMON<br />
AP_RESET_CONN_R_L<br />
2<br />
4<br />
7<br />
NOSTUFF<br />
U3850<br />
SLG4AP041V<br />
SENSE<br />
VREF<br />
RESET*<br />
IN<br />
THRM<br />
PAD<br />
9<br />
1<br />
VDD<br />
TDFN<br />
+<br />
-<br />
PP3V3_S4 36 101 106<br />
DLY<br />
GND<br />
5<br />
MR*<br />
1<br />
2<br />
3<br />
EN 6<br />
OUT 8<br />
(OD)<br />
NOSTUFF<br />
C3851<br />
0.1UF<br />
10%<br />
25V<br />
X6S-CERM<br />
0201<br />
AP_RESET_L<br />
SMC_WIFI_PWR_EN<br />
NC<br />
IN<br />
35<br />
50<br />
36<br />
48<br />
IN<br />
16<br />
19<br />
35<br />
CRITICAL<br />
J3830<br />
20449-001E-03<br />
F-ST-SM<br />
2<br />
3<br />
4<br />
1<br />
50_2_ANT<br />
NO STUFF<br />
C3837 1<br />
0.2PF<br />
2<br />
+/-0.05PF<br />
25V<br />
COG-CERM<br />
0201<br />
CORE2 DIPLEXER AND MATCHING<br />
CRITICAL<br />
L3830<br />
1.2NH-+/-0.05NH-1.1A-0.04OHM<br />
1 2<br />
0201<br />
50_2_COM<br />
CRITICAL<br />
1<br />
C3836<br />
0.2PF<br />
+/-0.05PF<br />
2<br />
25V<br />
COG-CERM<br />
0201<br />
U3830<br />
LFD212G45MJCD900<br />
LLP<br />
2<br />
P3<br />
GND<br />
5<br />
3<br />
1<br />
P1<br />
P2<br />
4<br />
6<br />
50_G_2_DIPLEXER<br />
C3832 1<br />
0.2PF<br />
+/-0.05PF<br />
25V<br />
2<br />
COG-CERM<br />
0201<br />
NO STUFF<br />
50_A_2_DIPLEXER<br />
NO STUFF<br />
C3835 1<br />
0.2PF<br />
+/-0.05PF<br />
25V<br />
2<br />
COG-CERM<br />
0201<br />
CRITICAL<br />
L3831<br />
2.9NH+/-0.1NH-0.6A<br />
1 2<br />
0201<br />
CRITICAL<br />
L3834<br />
1.2NH-+/-0.05NH-1.1A-0.04OHM<br />
1 2<br />
0201<br />
1<br />
2<br />
1<br />
NO STUFF<br />
C3830<br />
0.2PF<br />
+/-0.05PF<br />
25V<br />
COG-CERM<br />
0201<br />
CRITICAL<br />
L3833<br />
0201<br />
50_G_2_MATCH<br />
50_A_2_MATCH<br />
5.1NH-3%-0.4A<br />
35<br />
35<br />
B<br />
R3857 1<br />
100K<br />
1/20W<br />
5%<br />
201<br />
MF<br />
2<br />
2<br />
A<br />
R3854<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
BOM_COST_GROUP=WIRELESS<br />
SYNC_MASTER=J79_METE<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
WIFI/BT: MODULE 2<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
SYNC_DATE=03/02/2016<br />
9.0.0<br />
dvt-fab09-0<br />
38 OF 145<br />
36 OF 119<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
SIZE<br />
D<br />
A
SYNC_MASTER=J80_MLB_BAFFIN<br />
TABLE_5_HEAD<br />
TABLE_5_ITEM<br />
SYNC_DATE=07/22/2016<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
PART NUMBER QTY DESCRIPTION<br />
REFERENCE DES CRITICAL BOM OPTION<br />
PART NUMBER QTY DESCRIPTION<br />
REFERENCE DES CRITICAL BOM OPTION<br />
D<br />
C<br />
B<br />
343S00135<br />
41 PP1V1_SLEEP1_SW2<br />
unstuff R3951 and stuff R3952 to enable boundary scan<br />
PP1V8_SLEEP2_SW3A<br />
R3952<br />
R3951<br />
41 19<br />
41<br />
IN<br />
1 2<br />
1 2<br />
IN<br />
GREENCLK<br />
SOC PMU<br />
41<br />
41<br />
NOSTUFF<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
SOC_JTAG_SEL<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
39<br />
38<br />
41<br />
37<br />
39<br />
M7 needed stronger PU but should be fixed on M8<br />
42 37<br />
41 37<br />
PP1V8_AWAKE_SW3C<br />
PP1V8_SLEEP2_SW3A<br />
32K CLK OPTION<br />
SOC_PMU_CLK_32K<br />
PMU_TO_SOC_CLK_32K<br />
PP1V1_SLEEP1_SW2<br />
1 IC,M8+512MB 20NM DDR,A12,S,SCK,BGA700<br />
CRITICAL<br />
SOC_SWDIO<br />
PMU_TO_SOC_RESET_L<br />
L3900<br />
120-OHM-0.1A-1.5-OHM<br />
0<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
1 2<br />
0201<br />
PLACE_NEAR=U3900.AA22:3mm<br />
R3901<br />
R3953<br />
1 2<br />
R3973<br />
R3990<br />
1 2<br />
NOSTUFF<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
1 2<br />
1<br />
2<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
C3960<br />
100PF<br />
5%<br />
25V<br />
C0G<br />
0201<br />
SOC_CLK_32K<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
PLACE_NEAR=U3900.AA22:3mm<br />
1 2<br />
40<br />
37<br />
41<br />
R3925<br />
0<br />
1 2<br />
240<br />
1%<br />
1/20W<br />
MF<br />
201<br />
NOSTUFF<br />
R3902<br />
41 37<br />
41<br />
SOC<br />
1<br />
2<br />
VOLTAGE=1.1V<br />
C3900<br />
0.22UF<br />
10%<br />
6.3V<br />
X5R-CERM<br />
0201<br />
41<br />
SOC_PAD_ZQ_A<br />
SOC_DDR_RREF<br />
PMU_TO_SOC_SLEEP1_PWRGD<br />
IN<br />
PMU_TO_SOC_SYS_ALIVE<br />
IN<br />
1 2<br />
240<br />
1%<br />
1/20W<br />
MF<br />
201<br />
37<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
T208<br />
U3900 CRITICAL SE:DEV<br />
PP1V1_SLEEP1_PLL_DDR_FILT<br />
PP1V1_SLEEP3_BUCK2<br />
L25<br />
L26<br />
N26<br />
N27<br />
P26<br />
P25<br />
M26<br />
M27<br />
M25<br />
L27<br />
J26<br />
V27<br />
E26<br />
F26<br />
G26<br />
H26<br />
G27<br />
K25<br />
H27<br />
K26<br />
AA25<br />
Y25<br />
W25<br />
Y26<br />
V26<br />
U26<br />
T26<br />
T27<br />
E27<br />
F27<br />
W26<br />
W27<br />
R26<br />
M24<br />
N24<br />
L24<br />
P24<br />
DDR0_CA_0<br />
DDR0_CA_1<br />
DDR0_CA_2<br />
DDR0_CA_3<br />
DDR0_CA_4<br />
DDR0_CA_5<br />
DDR0_CK_P<br />
DDR0_CK_N<br />
DDR0_CKE<br />
DDR0_CS<br />
DDR0_DMI_0<br />
DDR0_DMI_1<br />
DDR0_DQ_0<br />
DDR0_DQ_1<br />
DDR0_DQ_2<br />
DDR0_DQ_3<br />
DDR0_DQ_4<br />
DDR0_DQ_5<br />
DDR0_DQ_6<br />
DDR0_DQ_7<br />
DDR0_DQ_8<br />
DDR0_DQ_9<br />
DDR0_DQ_10<br />
DDR0_DQ_11<br />
DDR0_DQ_12<br />
DDR0_DQ_13<br />
DDR0_DQ_14<br />
DDR0_DQ_15<br />
DDR0_DQS_P_0<br />
DDR0_DQS_N_0<br />
DDR0_DQS_P_1<br />
DDR0_DQS_N_1<br />
PAD_ZQ_A<br />
DDR0_RESET_N<br />
DDR0_RREF<br />
DDR0_RET_N<br />
DDR0_SYS_ALIVE<br />
N25<br />
VDDIO11_RET_DDR<br />
U21<br />
VDDIO11_PLL_DDR<br />
OMIT_TABLE<br />
U3900<br />
M8-LPDDR4-H-A-FUSE<br />
UFBGA<br />
(1 OF 7)<br />
DDR0<br />
41<br />
39<br />
38<br />
39<br />
37<br />
38<br />
41<br />
37<br />
SEP_ROM_WC<br />
1<br />
R3970<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
38 37<br />
IN<br />
AOP_DETECT_0<br />
AOP_DETECT_1<br />
AOP_PDM_CLK<br />
AOP_PDM_DAT<br />
AOP_PLED_0<br />
AOP_PLED_1<br />
AOP_PLED_2<br />
AOP_PLED_3<br />
AOP_PLED_4<br />
AOP_PLED_5<br />
AOP_PLED_6<br />
AOP_PLED_7<br />
AOP_PSENSE_CTRL_4<br />
AOP_PSENSE_CTRL_5<br />
AOP_PSENSE_CTRL_6<br />
AOP_PSENSE_CTRL_7<br />
AOP_PSPI_CS_TRIG_3<br />
AOP_PSPI_CS_TRIG_4<br />
AOP_PSPI_MISO<br />
AOP_PSPI_MOSI<br />
AOP_PSPI_SCLK<br />
AOP_SPI0_MISO<br />
AOP_SPI0_MOSI<br />
AOP_SPI0_SCLK<br />
AOP_MON_0<br />
AOP_MON_1<br />
AOP_MON_2<br />
AOP_MON_3<br />
AOP_MON_4<br />
AOP_MON_5<br />
AOP_MON_6<br />
AOP_MON_7<br />
AOP_I2S0_MCK<br />
AOP_I2S1_MCK<br />
AOP_SWD_TCK_OUT<br />
AOP_SWD_TMS0<br />
AOP_SWD_TMS1<br />
AOP_I2C0_SCL<br />
AOP_I2C0_SDA<br />
AOP_I2C1_SCL<br />
AOP_I2C1_SDA<br />
PP1V8_AWAKE_SW3C<br />
PP1V8_AWAKE_SW3C<br />
SEP_I2C_SCL<br />
AD26<br />
AD27<br />
AA10<br />
AB10<br />
AC10<br />
Y10<br />
AC14<br />
AA13<br />
AD12<br />
AD13<br />
AC15<br />
AB14<br />
AA24<br />
W24<br />
AA21<br />
Y24<br />
AD22<br />
AD23<br />
AD24<br />
Y20<br />
AB21<br />
AC22<br />
AC23<br />
AD21<br />
AE13<br />
AE14<br />
AB15<br />
Y14<br />
AE15<br />
AD15<br />
AA14<br />
AC16<br />
AA9<br />
AB9<br />
AE16<br />
AD16<br />
AB16<br />
AB20<br />
AE26<br />
AE27<br />
AA19<br />
1<br />
2<br />
C3903<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
DFR_TOUCH_RESET_L<br />
TP_SOC_CLKOUT<br />
DFR_TOUCH_SPI_CS_L<br />
DFR_TOUCH_SPI_MISO<br />
DFR_TOUCH_SPI_MOSI<br />
DFR_TOUCH_SPI_CLK<br />
SOC_TO_STOCKHOLM_DWLD_REQ<br />
PCH_SOC_DBELL<br />
NC<br />
PMU_TO_SOC_IRQ_L<br />
3<br />
2<br />
1<br />
7<br />
MESA_I2C_SCL<br />
MESA_I2C_SDA<br />
ALS_SCL_I2C_1V8<br />
ALS_SDA_I2C_1V8<br />
U3901<br />
M24128<br />
EEPROM<br />
MLP<br />
SEP ROM<br />
6 5<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
E2<br />
E1<br />
E0<br />
WC*<br />
SCL<br />
NC<br />
NC<br />
NC<br />
VSS<br />
4<br />
41 37<br />
IN<br />
41 38<br />
41 37<br />
8<br />
VCC<br />
OUT<br />
42 37<br />
41<br />
14<br />
42<br />
42<br />
41 37<br />
19<br />
41 40 38 37<br />
OUT<br />
BI<br />
OUT<br />
BI<br />
PLACE_NEAR=U3901.8:2mm<br />
THM_P<br />
IN<br />
IN<br />
OUT<br />
IN<br />
SDA<br />
47<br />
47<br />
37<br />
9<br />
104<br />
BI<br />
IN<br />
OUT<br />
SEP_I2C_SDA<br />
SOC_JTAG_SEL<br />
TP_SOC_JTAG_TRST_L<br />
SOC_SWDIO<br />
SOC_SWCLK<br />
TP_SOC_JTAG_TDI<br />
TP_SOC_JTAG_TDO<br />
PMU_TO_SOC_RESET_L<br />
PMU_TO_SOC_SLEEP1_PWRGD<br />
42<br />
104<br />
SOC_SLEEP1_REQ<br />
SOC_WDOG_RST<br />
SOC_VDD_HI_LO<br />
SOC_CLK_32K<br />
PMU_TO_SOC_AWAKE_PWRGD<br />
SOC_AWAKE_REQ<br />
PMU_TO_SOC_RESET_L<br />
37<br />
41<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
104<br />
104<br />
42<br />
42<br />
42<br />
37<br />
41<br />
42<br />
42<br />
41<br />
OUT<br />
37<br />
37<br />
OUT<br />
37<br />
NC<br />
NC<br />
PP1V8_AWAKE_SW3C<br />
1<br />
R3904<br />
2.2K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
AB12<br />
AB11<br />
AC13<br />
AD10<br />
AD9<br />
AA11<br />
AE10<br />
Y12<br />
AB13<br />
AE11<br />
AE12<br />
AC11<br />
AC12<br />
AA22<br />
AB24<br />
AD11<br />
AA12<br />
1<br />
R3905<br />
2.2K<br />
2<br />
BI<br />
40 38 37<br />
41<br />
5%<br />
1/20W<br />
MF<br />
201<br />
37<br />
38<br />
JTAG_SEL<br />
JTAG_TRSTN<br />
JTAG_TMS<br />
JTAG_TCK<br />
JTAG_TDI<br />
JTAG_TDO<br />
CFSB_AOP<br />
AOP_DDR_PWRGOOD<br />
AOP_DDR_REQ<br />
WDOG<br />
SOC_VDD_HI_LO<br />
AOP_DOCK_ATTENTION<br />
AOP_DOCK_CONNECT<br />
RT_CLK32768<br />
AWAKE_PWRGOOD<br />
AWAKE_REQ<br />
COLD_RESETN<br />
I2C Pullups<br />
PP1V8_AWAKE_SW3C<br />
338S00147 1<br />
IC,RTM2,DEV,PN549A1,P61D0 U3905<br />
338S00097<br />
AA23<br />
OMIT_TABLE<br />
U3900<br />
UFBGA<br />
(2 OF 7)<br />
PP1V8_SLEEP2_LPPLL_FILT<br />
1<br />
VOLTAGE=1.8V<br />
M8-LPDDR4-H-A-FUSE<br />
1<br />
R3911<br />
2.2K<br />
2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
VDD18_LPPLL<br />
104 42 37<br />
106<br />
1<br />
R3912<br />
2.2K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
1<br />
2<br />
PP1V8_S0SW_DFR<br />
IC,RTM2,MP,PN549A1,P61D0 U3905<br />
CRITICAL SE:PROD<br />
C3902<br />
0.47UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
AOP_LSPI_MISO<br />
AOP_LSPI_MOSI<br />
AOP_LSPI_SCLK<br />
AOP_SPI_CS_TRIG_0<br />
AOP_SPI_CS_TRIG_1<br />
AOP_SPI_CS_TRIG_2<br />
AOP_SPI_CS_TRIG_3<br />
AOP_SPI_CS_TRIG_4<br />
AOP_SPI_CS_TRIG_5<br />
AOP_SPI_CS_TRIG_6<br />
AOP_SPI_CS_TRIG_7<br />
AOP_SPI_CS_TRIG_8<br />
AOP_SPI_CS_TRIG_9<br />
AOP_SPI_CS_TRIG_10<br />
AOP_SPI_CS_TRIG_11<br />
AOP_SPI_CS_TRIG_12<br />
AOP_SPI_CS_TRIG_13<br />
AOP_SPI_CS_TRIG_14<br />
AOP_SPI_CS_TRIG_15<br />
AOP_UART0_CTSN<br />
AOP_UART0_RTSN<br />
AOP_UART0_RXD<br />
AOP_UART0_TXD<br />
AOP_UART1_CTSN<br />
AOP_UART1_RTSN<br />
AOP_UART1_RXD<br />
AOP_UART1_TXD<br />
AOP_UART2_RXD<br />
AOP_UART2_TXD<br />
AA20<br />
AB22<br />
AD25<br />
AE20<br />
AB17<br />
AB18<br />
AE21<br />
AD19<br />
AA17<br />
AC19<br />
AE22<br />
AE23<br />
AB19<br />
AA18<br />
AE24<br />
AD20<br />
AC21<br />
Y18<br />
AE25<br />
AC17<br />
AE18<br />
AE17<br />
AA15<br />
AA16<br />
AE19<br />
AD17<br />
AC18<br />
AD18<br />
Y16<br />
R3900<br />
499<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
1%<br />
1/20W<br />
MF<br />
201<br />
PP1V8_SLEEP2_SW3A 41<br />
38 19<br />
NC R3943 1<br />
NC 78.7K<br />
1%<br />
NC 1/20W<br />
MF<br />
201<br />
2<br />
NC<br />
MESA_PWR_EN<br />
OUT 47<br />
SOC_TO_STOCKHOLM_DEV_WAKE<br />
1<br />
R3915<br />
2.2K<br />
SOC_SPI_BOOT_STATUS<br />
1<br />
R3916<br />
2.2K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
38<br />
38<br />
38<br />
38<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
IN<br />
OUT<br />
IN<br />
OUT<br />
IN<br />
37<br />
37<br />
SOC_TO_STOCKHOLM_DWLD_REQ<br />
UART_SOC_TO_STOCKHOLM_TXD<br />
UART_STOCKHOLM_TO_SOC_TXD<br />
UART_SOC_TO_STOCKHOLM_RTS_L<br />
UART_STOCKHOLM_TO_SOC_RTS_L<br />
41 40 38 37<br />
1<br />
R3941<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
41 40 38 37<br />
37<br />
SOC_TO_STOCKHOLM_EN<br />
37<br />
101 PP3V3_S0<br />
PP1V8_AWAKE_SW3C<br />
PPSVDD_STOCKHOLM<br />
PP1V8_AWAKE_SW3C<br />
1<br />
R3942<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
42 IN<br />
38<br />
1<br />
2<br />
IN<br />
1<br />
2<br />
C3919<br />
4.7UF<br />
20%<br />
6.3V<br />
X5R<br />
402<br />
C3918<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
SOC_ROM_SPI_CLK_R<br />
SOC_ROM_SPI_CS_L<br />
SOC_ROM_SPI_WP_L<br />
SOC_ROM_SPI_RST_L<br />
D1<br />
A5<br />
B2<br />
A2<br />
A3<br />
C1<br />
B1<br />
D2<br />
A1<br />
E1<br />
E3<br />
E4<br />
F4<br />
B3<br />
B4<br />
E6<br />
C3<br />
1<br />
2<br />
STOCKHOLM<br />
IRQ<br />
SVDD_REQ<br />
DWL<br />
CLK_REQ<br />
NFC_CLK_XTAL1<br />
RX<br />
TX<br />
CTS<br />
RTS<br />
VEN<br />
SMX_RST*<br />
SMX_CLK<br />
ESE_IO1<br />
SPIM_MOSI<br />
SPIM_MISO<br />
SPIM_SCK<br />
XTAL2<br />
VSS<br />
E2<br />
C3920<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
4MB SPI ROM<br />
U3906<br />
4MX8-1.8V<br />
UFDFPN<br />
N25Q032A11E<br />
PP_STOCKHOLM_TVDD<br />
PPVDD_STOCKHOLM<br />
VOLTAGE=1.8V<br />
PPSVDD_STOCKHOLM<br />
OMIT_TABLE<br />
6 C<br />
DQ0 5<br />
1<br />
3<br />
7<br />
C6<br />
C7<br />
B5<br />
D3<br />
VDD<br />
VBAT<br />
NC<br />
SIM_PMU_VCC<br />
PVDD<br />
OMIT_TABLE<br />
U3905<br />
PN66VEU3-A101D004<br />
UFLGA<br />
AVSS<br />
AVSS<br />
AVSS<br />
D4<br />
D6<br />
F3<br />
S*<br />
W*/VPP/DQ2<br />
HOLD*/DQ3<br />
G2<br />
E7<br />
B6<br />
C4<br />
8<br />
4<br />
VUP<br />
TVDD<br />
DVSS<br />
DVSS<br />
VCC<br />
VSS<br />
D7<br />
9<br />
10<br />
37<br />
AVDD<br />
G4<br />
C2<br />
B7<br />
DQ1<br />
THRM_PAD<br />
C5<br />
SVDD<br />
ESE_VDD<br />
SPIM_IRQ<br />
SIM_SWIO<br />
GPIO0<br />
SPIM_NSS<br />
TX_PWR_REQ<br />
ESE_DWPM_DBG<br />
ESE_DWPS_DBG<br />
TVSS<br />
PVSS<br />
RXP<br />
RXN<br />
TX1<br />
TX2<br />
WKUP_REQ<br />
VMID<br />
SE2_PWR_REQ<br />
SE2_SVDD_IN<br />
2<br />
F1<br />
A4<br />
A7<br />
A6<br />
D5<br />
G7<br />
G6<br />
F6<br />
F5<br />
G3<br />
G5<br />
E5<br />
F7<br />
F2<br />
G1<br />
VOLTAGE=1.8V<br />
1<br />
2<br />
PP_STOCKHOLM_VMID<br />
1<br />
VOLTAGE=1.8V<br />
SOC_ROM_SPI_MISO_R<br />
VOLTAGE=1.8V<br />
SOC_TO_STOCKHOLM_DEV_WAKE<br />
SOC_ROM_SPI_MOSI_R<br />
2<br />
1<br />
2<br />
1<br />
C3916<br />
0.1UF<br />
10%<br />
2<br />
6.3V<br />
CERM-X5R<br />
0201<br />
C3915<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
C3925<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
1<br />
2<br />
C3926<br />
0.1UF<br />
C3917<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
IN<br />
OUT<br />
42<br />
42<br />
37<br />
D<br />
C<br />
B<br />
A<br />
37<br />
38 IN<br />
DFU_STATUS<br />
SOC_SPI_BOOT_STATUS<br />
100<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
42<br />
R3981<br />
0<br />
1 2<br />
R3980<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
38<br />
37<br />
NOSTUFF<br />
T208 DFU_STATUS Isolation<br />
PP1V8_S0<br />
DFU_SPI_STATUS<br />
5<br />
6<br />
A<br />
B<br />
DFU_STATUS can be driven high outside of S0<br />
U3910 creates version that is only high in S0<br />
8 74LVC2G08GT/S505<br />
SOT833<br />
3 PCH_SOC_DFU_STATUS<br />
U3910 Y<br />
08<br />
4<br />
37<br />
100<br />
OUT<br />
42<br />
13<br />
38<br />
19<br />
37<br />
SOC_WDOG_RST<br />
PP1V8_S0<br />
1<br />
2<br />
C3950<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
1<br />
R3972<br />
300K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
T208 WDOG Isolation<br />
1<br />
2<br />
A<br />
B<br />
SOC_WDOG_RESET can be driven high outside of S0<br />
U3910 creates version that is only high in S0<br />
8 74LVC2G08GT/S505<br />
SOT833<br />
7<br />
U3910 PCH_SOC_WDOG<br />
Y<br />
08<br />
4<br />
1<br />
R3971<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
OUT<br />
13<br />
100<br />
42 37<br />
42 37<br />
42<br />
38 37<br />
38 37<br />
PP1V8_S0<br />
SEP_I2C_SCL<br />
SEP_I2C_SDA<br />
ALS_SCL_I2C_1V8<br />
ALS_SDA_I2C_1V8<br />
1<br />
R3960<br />
3.0K<br />
2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
1<br />
R3961<br />
3.0K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
41 38<br />
41 38<br />
100<br />
104 80 38<br />
104 80 38<br />
SOC_PMU_I2C_SCL<br />
SOC_PMU_I2C_SDA<br />
PP1V8_S0<br />
I2C_CAM_SCL<br />
I2C_CAM_SDA<br />
1<br />
R3906<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
104 42 38<br />
42 38<br />
104<br />
1<br />
R3907<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
104 42 38<br />
DFR_TOUCH_ROM_I2C_SCL<br />
42 37<br />
106 104<br />
42 38<br />
104<br />
DFR_TOUCH_ROM_I2C_SDA<br />
PP1V8_S0SW_DFR<br />
DFRDRV_I2C_SCL<br />
DFRDRV_I2C_SDA<br />
1<br />
R3917<br />
4.7K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
37<br />
1<br />
R3918<br />
4.7K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
PART#<br />
QTY<br />
335S00203 1 IC,FLASH,SERIAL,SPI,4MX8,4X3MM,DFN8 U3906<br />
SOC_TO_STOCKHOLM_DWLD_REQ<br />
DESCRIPTION<br />
NOSTUFF<br />
1<br />
R3940<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
BOM_COST_GROUP=T151<br />
PAGE TITLE<br />
REFERENCE DESIGNATOR(S)<br />
R<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
CRITICAL<br />
Camera/DFR 1<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
IV ALL RIGHTS RESERVED<br />
Apple Inc.<br />
BOM OPTION<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
39 OF 145<br />
37 OF 119<br />
SIZE<br />
D<br />
A<br />
8 7 6<br />
5 4 3<br />
2 1
SYNC_MASTER=J79_ANDREW<br />
SYNC_DATE=03/22/2016<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
41 PP1V8_AWAKE_SW3C<br />
41<br />
PP1V8_AWAKE_SW3C<br />
PP1V1_SLEEP1_SW2<br />
41<br />
D<br />
100 42 PP1V8_S4<br />
38 37<br />
41 39<br />
PP1V8_AWAKE_SW3C<br />
SOC_BOOT:DFU<br />
1<br />
R4035<br />
47K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
38<br />
SOC_FORCE_DFU<br />
1<br />
R4023<br />
100K<br />
5%<br />
1/20W<br />
41<br />
MF<br />
IN<br />
2<br />
201<br />
41 37 IN<br />
SOC_BOOT:SPI<br />
C<br />
B<br />
1<br />
2<br />
C4002<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
41<br />
39<br />
R4017<br />
2.2K<br />
5%<br />
1/20W<br />
NOSTUFF<br />
1 2<br />
41 37<br />
41 37<br />
104 42 37<br />
104 42 37<br />
MF<br />
201<br />
OUT<br />
BI<br />
OUT<br />
BI<br />
38<br />
104 42 37<br />
104 42 37<br />
37<br />
SOC_XTAL_24M_I<br />
PP1V8_AWAKE_SW3C<br />
37<br />
PMU_TO_SOC_AWAKE_PWRGD<br />
41<br />
SOC_REQUEST_DFU1<br />
SOC_REQUEST_DFU2<br />
TP_SOC_TST_CKOUT<br />
DFR_CLKIN_RESET_L<br />
NC<br />
SOC_BOARD_ID_3<br />
SOC_BOARD_REV_0<br />
SOC_BOARD_REV_1<br />
SOC_BOARD_REV_2<br />
PP1V8_AWAKE_SW3C<br />
DFR_DISP_RST_L<br />
DFR_TOUCH_INT_L<br />
MESA_SNSR_INT<br />
SOC_TO_STOCKHOLM_EN<br />
DFR_DISP_INT<br />
SOC_PMU_I2C_SCL<br />
SOC_PMU_I2C_SDA<br />
DFR_TOUCH_ROM_I2C_SCL<br />
DFR_TOUCH_ROM_I2C_SDA<br />
DFRDRV_I2C_SCL<br />
DFRDRV_I2C_SDA<br />
SOC_ROM_SPI_MISO<br />
SOC_ROM_SPI_MOSI<br />
SOC_ROM_SPI_CLK<br />
SOC_ROM_SPI_CS_L<br />
PP1V1_SLEEP1_SW2<br />
DFU_STATUS<br />
PMU_TO_SOC_VDD_OK<br />
NC<br />
SOC_BOOT_CONFIG_0<br />
104 42<br />
42<br />
104 42<br />
47<br />
37 19<br />
OUT<br />
BI<br />
39<br />
39<br />
39<br />
39<br />
39<br />
IN<br />
42 39<br />
42 39<br />
42 39<br />
37<br />
47<br />
42<br />
42<br />
IN<br />
IN<br />
OUT<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
OUT<br />
1<br />
2<br />
OUT<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
OUT<br />
OUT<br />
C4001<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
38<br />
38<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
1<br />
2<br />
OUT<br />
C4000<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
MESA_SPI_MISO<br />
MESA_SPI_MOSI<br />
MESA_SPI_CLK<br />
NC<br />
NC<br />
NC<br />
P1<br />
F4<br />
E3<br />
D1<br />
R3<br />
D3<br />
C3<br />
T6<br />
A3<br />
E2<br />
C23<br />
F20<br />
C22<br />
E20<br />
D25<br />
C24<br />
D21<br />
C25<br />
E19<br />
D20<br />
C21<br />
A22<br />
B22<br />
B23<br />
D19<br />
F18<br />
C19<br />
B21<br />
B8<br />
C8<br />
A8<br />
D8<br />
E8<br />
B7<br />
C7<br />
A7<br />
E10<br />
D10<br />
B10<br />
A10<br />
A9<br />
C9<br />
B9<br />
E9<br />
AA8<br />
AB8<br />
DFU_STATUS<br />
FORCE_DFU<br />
REQUEST_DFU1<br />
REQUEST_DFU2<br />
DROOP_N<br />
CFSB<br />
HOLD_RESET<br />
TST_CLKOUT<br />
TESTMODE<br />
CLK32K_OUT<br />
GPIO_0<br />
GPIO_1<br />
GPIO_2<br />
GPIO_3<br />
GPIO_4<br />
GPIO_5<br />
GPIO_6<br />
GPIO_7<br />
GPIO_8<br />
GPIO_9<br />
GPIO_10<br />
GPIO_11<br />
GPIO_12<br />
GPIO_13<br />
GPIO_14<br />
GPIO_15<br />
GPIO_16<br />
GPIO_17<br />
I2C0_SCL<br />
I2C0_SDA<br />
I2C1_SCL<br />
I2C1_SDA<br />
I2C2_0_SCL<br />
I2C2_0_SDA<br />
I2C2_1_SCL<br />
I2C2_1_SDA<br />
SPI0_MISO<br />
SPI0_MOSI<br />
SPI0_SCLK<br />
SPI0_SSIN<br />
SPI1_MISO<br />
SPI1_MOSI<br />
SPI1_SCLK<br />
SPI1_SSIN<br />
XI0<br />
XO0<br />
J12<br />
H12<br />
VDD11_PLL_SOC0<br />
VDD11_PLL_SOC1<br />
H10<br />
VDD11_UVD<br />
J22<br />
VDD18_TSADC<br />
U3900<br />
M8-LPDDR4-H-A-FUSE<br />
UFBGA<br />
(3 OF 7)<br />
OMIT_TABLE<br />
J6<br />
VDD18_USB<br />
H3<br />
VDD30_USB<br />
J5<br />
VDD_FIXED_USB<br />
Y8<br />
VDD11_XTAL<br />
PP1V1_SLEEP1_XTAL_FILT<br />
USB_DP<br />
USB_DM<br />
USB_VBUS<br />
USB_ID<br />
USB_REXT<br />
TMR32_PWM0<br />
TMR32_PWM1<br />
TMR32_PWM2<br />
UART0_RXD<br />
UART0_TXD<br />
UART1_RTSN<br />
UART1_CTSN<br />
UART1_RXD<br />
UART1_TXD<br />
UART2_RTSN<br />
UART2_CTSN<br />
UART2_RXD<br />
UART2_TXD<br />
UART3_RTXD<br />
UART4_RXD<br />
UART4_TXD<br />
UART5_RXD<br />
UART5_TXD<br />
I2S0_BCLK<br />
I2S0_LRCK<br />
I2S0_DIN<br />
I2S0_DOUT<br />
I2S1_BCLK<br />
I2S1_LRCK<br />
I2S1_DIN<br />
I2S1_DOUT<br />
I2S2_BCLK<br />
I2S2_LRCK<br />
I2S2_DIN<br />
I2S2_DOUT<br />
G1<br />
G2<br />
K6<br />
J3<br />
H4<br />
D18<br />
E18<br />
A23<br />
A6<br />
D7<br />
D5<br />
B3<br />
C4<br />
B4<br />
E6<br />
A4<br />
B5<br />
D6<br />
E7<br />
A5<br />
B6<br />
C5<br />
C6<br />
B17<br />
C15<br />
E15<br />
A17<br />
C14<br />
B16<br />
E14<br />
A16<br />
B15<br />
F14<br />
D13<br />
A15<br />
1<br />
2<br />
VOLTAGE=1.1V<br />
C4050<br />
0.22UF<br />
10%<br />
6.3V<br />
X5R-CERM<br />
0201<br />
USB_CAMERA_DFR_P<br />
USB_CAMERA_DFR_N<br />
SOC_USB_VBUS<br />
NC<br />
41<br />
PCH_TO_SOC_UART_TXD<br />
SOC_TO_PCH_UART_TXD<br />
NC<br />
PCH_ALS_TO_SOC_UART_TXD<br />
SOC_TO_PCH_ALS_UART_TXD<br />
1<br />
2<br />
UART_SOC_TO_STOCKHOLM_RTS_L<br />
UART_STOCKHOLM_TO_SOC_RTS_L<br />
UART_STOCKHOLM_TO_SOC_TXD<br />
UART_SOC_TO_STOCKHOLM_TXD<br />
38<br />
PP3V0_AWAKE_LDO7<br />
41<br />
0201<br />
R4001<br />
200<br />
SOC_USB_REXT<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
PLACE_NEAR=U3900.H4:2mm<br />
PP0V8_SLEEP1_SW1<br />
L4010<br />
120-OHM-0.2A-0.5-OHM<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
C4004<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
1 2<br />
NC<br />
NC<br />
NC<br />
NC<br />
BI<br />
BI<br />
15<br />
15<br />
1<br />
2<br />
105<br />
105<br />
C4005<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
PP1V1_SLEEP1_SW2 41<br />
To/From PCH for logging/debug<br />
IN<br />
OUT<br />
To/From PCH for ALS<br />
IN<br />
OUT<br />
42<br />
42<br />
42<br />
42<br />
OUT<br />
IN<br />
IN<br />
OUT<br />
PP3V0_AWAKE_LDO7 38 41<br />
1<br />
R4022<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
37<br />
37<br />
37<br />
37<br />
1<br />
2<br />
C4003<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
PP3V3_S4_SOC_PMU 42 101<br />
1<br />
R4042<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
NOSTUFF<br />
PLACE_NEAR=U3900.K1:2mm<br />
1<br />
2<br />
C4006<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
R4003<br />
4.02K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
105 38<br />
105 38<br />
105 38<br />
105 38<br />
SOC_MIPI1C_REXT<br />
104 80 37<br />
104 80 37<br />
1<br />
C4007<br />
0.1UF<br />
10%<br />
2<br />
6.3V<br />
CERM-X5R<br />
0201<br />
BI<br />
OUT<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
MIPIC_DATA_P<br />
MIPIC_DATA_N<br />
MIPIC_CLK_P<br />
MIPIC_CLK_N<br />
I2C_CAM_SDA<br />
I2C_CAM_SCL<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
M3<br />
M2<br />
L1<br />
L2<br />
K1<br />
B2<br />
A2<br />
D12<br />
C12<br />
A12<br />
A11<br />
B11<br />
F10<br />
B12<br />
E11<br />
C10<br />
C11<br />
B14<br />
E13<br />
A14<br />
C13<br />
F12<br />
B13<br />
A13<br />
E12<br />
B1<br />
F5<br />
C1<br />
H6<br />
F2<br />
G24<br />
G23<br />
V23<br />
U23<br />
F24<br />
F3<br />
VDD18_EFUSE1<br />
VDD18_EFUSE2<br />
VDD18_EFUSE3<br />
VDD18_EFUSE4<br />
VDD18_EFUSE5<br />
VDD18_EFUSE6<br />
MIPI1C_DPDATA0<br />
MIPI1C_DNDATA0<br />
MIPI1C_DPCLK<br />
MIPI1C_DNCLK<br />
MIPI1C_REXT<br />
ISP0_SDA<br />
ISP0_SCL<br />
ENET_MDC<br />
ENET_MDIO<br />
RMII_CLK<br />
RMII_CRSDV<br />
RMII_RXD_0<br />
RMII_RXD_1<br />
RMII_RXER<br />
RMII_TXD_0<br />
RMII_TXD_1<br />
RMII_TXEN<br />
SD_CLKOUT<br />
SD_CMD_IO<br />
SD_DATA_IO_0<br />
SD_DATA_IO_1<br />
SD_DATA_IO_2<br />
SD_DATA_IO_3<br />
SDIO_IRQ<br />
WL_HOST_WAKE<br />
SWD_TMS2<br />
SWD_TMS3<br />
ANALOGMUX_OUT<br />
BB_HSIC_DATA<br />
BB_HSIC_STROBE<br />
G3<br />
VDD12_HSIC<br />
G5<br />
VDD_FIXED_HSIC<br />
L4<br />
M4<br />
VDD18_MIPI<br />
U3900<br />
M8-LPDDR4-H-A-FUSE<br />
UFBGA<br />
(4 OF 7)<br />
OMIT_TABLE<br />
K4<br />
N4<br />
VDD_FIXED_MIPI<br />
G4<br />
VDD18_AMUX<br />
PP0V8_SLEEP1_SW1 41<br />
1<br />
C4008<br />
0.1UF<br />
10%<br />
2<br />
6.3V<br />
CERM-X5R<br />
0201<br />
PP1V8_AWAKE_SW3C 37 38 39 41<br />
MIPI0D_DPDATA0<br />
MIPI0D_DNDATA0<br />
MIPI0D_DPCLK<br />
MIPI0D_DNCLK<br />
MIPI0D_REXT<br />
DISP_VSYNC<br />
DISP_TE<br />
NAND_CEN_0<br />
NAND_CEN_1<br />
NAND_ALE<br />
NAND_CLE<br />
NAND_REN<br />
NAND_WEN<br />
NAND_IO_0<br />
NAND_IO_1<br />
NAND_IO_2<br />
NAND_IO_3<br />
NAND_IO_4<br />
NAND_IO_5<br />
NAND_IO_6<br />
NAND_IO_7<br />
MON_0<br />
MON_1<br />
MON_2<br />
MON_3<br />
MON_4<br />
MON_5<br />
MON_6<br />
MON_7<br />
SEP_GPIO0<br />
SEP_GPIO1<br />
SEP_SPI0_MISO<br />
SEP_SPI0_MOSI<br />
SEP_SPI0_SCLK<br />
SEP_I2C_SCL<br />
SEP_I2C_SDA<br />
H1<br />
H2<br />
J2<br />
J1<br />
K2<br />
C2<br />
D2<br />
D17<br />
B20<br />
D15<br />
C16<br />
A20<br />
A18<br />
E16<br />
A19<br />
B18<br />
D16<br />
C17<br />
A21<br />
B19<br />
E17<br />
N3<br />
P6<br />
P4<br />
P3<br />
N2<br />
P5<br />
R4<br />
P2<br />
D24<br />
E21<br />
D22<br />
F22<br />
E24<br />
E22<br />
D23<br />
MIPID_DATA_P<br />
MIPID_DATA_N<br />
MIPID_CLK_P<br />
MIPID_CLK_N<br />
SOC_MIPI0D_REXT<br />
DFR_DISP_VSYNC<br />
DFR_DISP_TE<br />
SOC_NAND_CEN_0<br />
NC<br />
DFR_TOUCH_PANEL_DETECT<br />
DFR_TOUCH_GPIO2<br />
DFR_TOUCH_ROM_WC<br />
SOC_PANIC_L<br />
S2R_ACK_L<br />
SOC_PCH_DBELL_L<br />
SEP_I2C_SCL<br />
SEP_I2C_SDA<br />
PP1V8_AWAKE_SW3C<br />
1<br />
R4036<br />
10K<br />
2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
38<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
OUT<br />
BI<br />
SOC_REQUEST_DFU1<br />
IN<br />
IN<br />
105 38<br />
37<br />
37<br />
105 38<br />
42<br />
42<br />
BI<br />
OUT<br />
OUT<br />
38<br />
105<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
BI<br />
IN<br />
104<br />
104<br />
42<br />
42<br />
13<br />
42<br />
42<br />
13<br />
42<br />
42<br />
42<br />
104<br />
19<br />
19<br />
104<br />
PP1V8_AWAKE_SW3C<br />
1<br />
R4024<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
38<br />
MIPIC_DATA_P<br />
MIPIC_DATA_N<br />
MIPIC_CLK_P<br />
37<br />
38<br />
40<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
41<br />
GND_VOID=TRUE<br />
PP1V8_AWAKE_SW3C<br />
1<br />
R4037<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
SOC_REQUEST_DFU2<br />
MIPIC FILTERING<br />
L4002<br />
3.25-OHM-0.1A-2.4GHZ<br />
TAM0605-4SM<br />
1<br />
37<br />
38<br />
R4004<br />
4.02K<br />
1 2<br />
40<br />
SYM_VER-1<br />
1%<br />
1/20W<br />
MF<br />
201<br />
41<br />
2 3<br />
L4003<br />
4<br />
PLACE_NEAR=U3900.K2:2mm<br />
PLACE_NEAR=J8500:2.54mm<br />
GND_VOID=TRUE<br />
MIPI_DATA_CONN_P<br />
GND_VOID=TRUE<br />
MIPI_DATA_CONN_N<br />
3.25-OHM-0.1A-2.4GHZ PLACE_NEAR=J8500:2.54mm<br />
TAM0605-4SM<br />
SYM_VER-1<br />
GND_VOID=TRUE<br />
1<br />
4<br />
38<br />
37<br />
38<br />
40<br />
41<br />
MIPI_CLK_CONN_P<br />
BI<br />
BI<br />
OUT<br />
80<br />
80<br />
104<br />
105<br />
104<br />
105<br />
D<br />
C<br />
B<br />
A<br />
1<br />
2<br />
C4041<br />
12PF<br />
5%<br />
50V<br />
C0G-CERM<br />
0201<br />
R4010<br />
499K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
Y4000<br />
1.60X1.20MM-SM<br />
24.000MHZ-30PPM-9.5PF-60OHM<br />
1 3<br />
SOC_XTAL_24M_O_R<br />
2 4<br />
SOC_XTAL_24M_O<br />
1<br />
R4020<br />
0.00<br />
1%<br />
1/20W<br />
MF<br />
2<br />
0201<br />
1<br />
12PF<br />
38 19 13<br />
C4040<br />
5%<br />
2<br />
50V<br />
C0G-CERM<br />
0201<br />
BI<br />
PCH<br />
T208 SOC_S2R_ACK_L bi-directional Isolation<br />
SOC_S2R_ACK_L<br />
101<br />
42<br />
PP3V3_S0<br />
NOSTUFF<br />
1<br />
2<br />
R4080<br />
200K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
SYM_VER_1<br />
1<br />
G<br />
S<br />
PP1V8_AWAKE_SW3C<br />
D<br />
3<br />
S2R_ACK_L<br />
Q4000<br />
DMN32D2LFB4<br />
DFN1006H4-3<br />
1<br />
R4082<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
T208<br />
PP1V8_S0<br />
Q4000 to act as bi-directional islation for SOC_S2R_ACK_L<br />
When in system S0 and M8 AWAKE, FET will be on & line will be pulled high<br />
Below S0, SOC_S2R_ACK_L will be low and FET will be open (isolated from M8 power rails)<br />
When M8 enters S2R, FET will be on, PP1V8_AWAKE_SW3C will turn off and SOC_S2R_ACK_L will be low<br />
38<br />
100<br />
42<br />
38<br />
1<br />
2<br />
37<br />
C4080<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
38<br />
T208<br />
NOSTUFF<br />
S2R_ACK_L<br />
T208 SOC_S2R_ACK_L Isolation (NOSTUFF)<br />
2<br />
1<br />
B<br />
A<br />
NC<br />
NOSTUFF<br />
6 74LVC1G08FW5<br />
DFN1010<br />
4 SOC_S2R_ACK_L<br />
U4080 Y<br />
NC<br />
5<br />
3<br />
PCH<br />
13<br />
19<br />
38<br />
PCH<br />
14<br />
100 42 38 37 PP1V8_S0<br />
SOC_BOOT:DFU<br />
SOC_BOOT:DFU 1<br />
C4070<br />
1 0.1UF<br />
R4070<br />
10%<br />
47K<br />
2<br />
6.3V<br />
5%<br />
CERM-X5R<br />
1/20W<br />
0201<br />
MF<br />
2<br />
201<br />
PCH_SOC_FORCE_DFU<br />
T208 FORCE_DFU Isolation<br />
2<br />
1<br />
U4070<br />
NC<br />
5<br />
R4071<br />
6<br />
3<br />
0<br />
1 2<br />
SOC_FORCE_DFU should be pulled up to S4<br />
In the SOC_BOOT:DFU option<br />
U4070 prevents it from leaking into PCH<br />
5%<br />
201 1/20W SOC_BOOT:SPI<br />
MF<br />
SOC_BOOT:DFU<br />
74LVC1G08FW5<br />
DFN1010<br />
4 SOC_FORCE_DFU<br />
T208<br />
38<br />
105 38<br />
106 101<br />
BOM_COST_GROUP=T151<br />
MIPIC_CLK_N<br />
PP5V_S0<br />
GND_VOID=TRUE<br />
2 3<br />
L4004<br />
FERR-120-OHM-1.5A<br />
1 2<br />
0402A<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
GND_VOID=TRUE<br />
MIPI_CLK_CONN_N<br />
PP5V_S0_ALSCAM_F<br />
VOLTAGE=5V<br />
Camera/DFR 2<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
OUT<br />
IN<br />
B<br />
A<br />
NC<br />
Y<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
BRANCH<br />
1<br />
2<br />
REVISION<br />
C4062<br />
0.1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
DRAWING NUMBER<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
OUT<br />
dvt-fab09-0<br />
40 OF 145<br />
38 OF 119<br />
80<br />
104<br />
SIZE<br />
D<br />
106<br />
A
TABLE_BOMGROUP_HEAD<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
SYNC_MASTER=J79_ANDREW<br />
SYNC_DATE=04/25/2016<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
T4<br />
U4<br />
V5<br />
U5<br />
D<br />
C<br />
B<br />
A<br />
41<br />
1<br />
2<br />
41 PP1V1_SLEEP3_BUCK2<br />
1<br />
2<br />
C4106<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
41<br />
41<br />
39<br />
37<br />
38<br />
37<br />
41 PP1V1_SLEEP1_SW2<br />
C4116<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
41<br />
39 PP0V8_SLEEP1_SW1<br />
1<br />
2<br />
1<br />
2<br />
C4121<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
1<br />
2<br />
1<br />
0.1UF<br />
1<br />
C4119<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
41<br />
PP1V8_SLEEP3_BUCK3<br />
1<br />
2<br />
C4100<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
PP1V8_SLEEP2_SW3A<br />
C4112<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
PP1V8_AWAKE_SW3C<br />
C4114<br />
1.0UF<br />
20%<br />
10%<br />
2<br />
6.3V<br />
X5R<br />
2<br />
6.3V<br />
CERM-X5R<br />
0201-1<br />
0201<br />
1<br />
1<br />
2<br />
PP0V8_SLEEP2_BUCK1<br />
1<br />
2<br />
2<br />
2<br />
4<br />
4<br />
4<br />
3<br />
3<br />
C4141<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
C4107<br />
4.3UF<br />
20%<br />
4V<br />
CER-X5R<br />
0402<br />
C4117<br />
4.3UF<br />
20%<br />
4V<br />
CER-X5R<br />
0402<br />
3<br />
1<br />
2<br />
1<br />
C4122<br />
4.3UF<br />
20%<br />
4V<br />
CER-X5R<br />
0402<br />
10%<br />
6.3V<br />
X5R<br />
0201<br />
0.1UF<br />
1<br />
2<br />
C4113<br />
0.1UF<br />
C4115<br />
1<br />
2<br />
1<br />
1<br />
1<br />
2<br />
2<br />
2<br />
4<br />
4<br />
4<br />
3<br />
3<br />
C4142<br />
2.2UF<br />
20%<br />
6.3V<br />
X5R-CERM<br />
0201<br />
C4101<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
C4108<br />
4.3UF<br />
20%<br />
4V<br />
CER-X5R<br />
0402<br />
C4118<br />
4.3UF<br />
20%<br />
4V<br />
CER-X5R<br />
0402<br />
3<br />
C4123<br />
4.3UF<br />
20%<br />
4V<br />
CER-X5R<br />
0402<br />
A24<br />
AC24<br />
AC28<br />
C27<br />
K28<br />
N1<br />
R28<br />
A27<br />
AC25<br />
AC27<br />
B24<br />
J28<br />
K27<br />
M1<br />
M28<br />
P28<br />
T28<br />
AB23<br />
W12<br />
W16<br />
W18<br />
Y13<br />
Y15<br />
Y19<br />
Y22<br />
Y9<br />
E5<br />
F19<br />
F21<br />
F7<br />
F9<br />
G10<br />
G12<br />
G14<br />
G16<br />
R5<br />
H23<br />
AB25<br />
AB26<br />
B25<br />
B26<br />
D28<br />
F28<br />
H28<br />
J23<br />
K23<br />
L23<br />
M23<br />
N23<br />
P23<br />
R23<br />
R27<br />
T23<br />
U27<br />
U28<br />
Y28<br />
W10<br />
W15<br />
W19<br />
Y21<br />
L17<br />
M14<br />
M18<br />
M20<br />
M22<br />
M8<br />
N11<br />
N5<br />
P12<br />
P14<br />
P18<br />
P20<br />
P22<br />
P8<br />
T12<br />
T14<br />
T18<br />
T20<br />
T22<br />
V13<br />
V21<br />
W13<br />
W9<br />
Y23<br />
VDD1<br />
VDD2<br />
VDDIO18_AOP<br />
VDDIO18_GRP0<br />
VDDIO18_GRP1<br />
VDD18_FMON<br />
VDDIO11_DDR<br />
VDD_SRAM_AON<br />
VDD_SRAM<br />
U3900<br />
M8-LPDDR4-H-A-FUSE<br />
UFBGA<br />
(5 OF 7)<br />
OMIT_TABLE<br />
VDD_SOC<br />
VDD_SOC_AON<br />
VDD_SRAM<br />
E4<br />
F11<br />
F15<br />
G17<br />
G19<br />
G22<br />
G6<br />
G8<br />
H14<br />
H16<br />
H18<br />
H8<br />
J15<br />
J19<br />
J21<br />
J9<br />
K10<br />
K12<br />
K16<br />
K18<br />
L13<br />
L15<br />
L19<br />
L21<br />
L5<br />
L7<br />
L9<br />
M10<br />
M12<br />
M16<br />
N13<br />
N15<br />
N17<br />
N19<br />
N21<br />
N6<br />
N9<br />
P10<br />
P16<br />
R11<br />
R13<br />
R15<br />
R17<br />
R19<br />
R21<br />
R9<br />
T10<br />
T16<br />
U11<br />
U13<br />
U15<br />
U17<br />
U19<br />
U9<br />
V10<br />
V12<br />
V22<br />
W11<br />
W23<br />
V14<br />
V16<br />
V18<br />
V20<br />
W17<br />
W21<br />
Y11<br />
F13<br />
F17<br />
F23<br />
F6<br />
F8<br />
G11<br />
G13<br />
G15<br />
G18<br />
G21<br />
G9<br />
H17<br />
H20<br />
H22<br />
J11<br />
J13<br />
J17<br />
J7<br />
K14<br />
K20<br />
K22<br />
K5<br />
K8<br />
L11<br />
1<br />
2<br />
1<br />
2<br />
C4102<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
C4109<br />
2.2UF<br />
20%<br />
6.3V<br />
X5R-CERM<br />
0201<br />
PP0V6_SLEEP2_LDO0 41<br />
PP0V8_SLEEP1_SW1<br />
1<br />
1<br />
2<br />
2<br />
4<br />
4<br />
3<br />
3<br />
C4103<br />
4.3UF<br />
20%<br />
4V<br />
CER-X5R<br />
0402<br />
C4110<br />
4.3UF<br />
20%<br />
4V<br />
CER-X5R<br />
0402<br />
PP0V6_SLEEP1_BUCK0<br />
1<br />
2<br />
1<br />
1<br />
2<br />
C4120<br />
0.1UF<br />
2<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
BOM GROUP<br />
4<br />
4<br />
T208_PROG:REV0<br />
T208_PROG:REV1<br />
T208_PROG:REV2<br />
T208_PROG:REV3<br />
T208_PROG:REV4<br />
T208_PROG:REV5<br />
3<br />
20%<br />
4V<br />
CER-X5R<br />
0402<br />
3<br />
C4104<br />
4.3UF<br />
C4111<br />
4.3UF<br />
20%<br />
4V<br />
CER-X5R<br />
0402<br />
1<br />
2<br />
C4105<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
C4124<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
A1<br />
A25<br />
A26<br />
A28<br />
AA1<br />
AA26<br />
AA27<br />
AA28<br />
AA4<br />
AB27<br />
AB28<br />
AC20<br />
AC26<br />
AC9<br />
AD14<br />
AD28<br />
AD5<br />
AE1<br />
AE28<br />
B27<br />
B28<br />
C18<br />
C20<br />
C26<br />
C28<br />
D11<br />
D14<br />
D26<br />
D27<br />
D4<br />
D9<br />
E1<br />
E23<br />
E25<br />
E28<br />
F1<br />
F16<br />
F25<br />
G20<br />
G25<br />
G28<br />
G7<br />
H11<br />
H13<br />
H15<br />
H19<br />
H21<br />
H24<br />
H25<br />
H5<br />
H7<br />
H9<br />
J10<br />
J14<br />
J16<br />
J18<br />
J20<br />
J24<br />
J25<br />
J27<br />
J4<br />
J8<br />
K11<br />
K13<br />
K15<br />
K17<br />
K19<br />
K21<br />
K24<br />
K3<br />
K7<br />
K9<br />
L10<br />
L12<br />
L14<br />
L16<br />
L18<br />
L20<br />
VSS<br />
M8-LPDDR4-H-A-FUSE<br />
T208_CONFIG2_H,T208_CONFIG1_H,T208_CONFIG0_H<br />
T208_CONFIG2_H,T208_CONFIG1_H<br />
T208_CONFIG2_H,T208_CONFIG0_H<br />
T208_CONFIG2_H<br />
T208_CONFIG1_H, T208_CONFIG0_H<br />
T208_CONFIG1_H<br />
U3900<br />
UFBGA<br />
(6 OF 7)<br />
OMIT_TABLE<br />
VSS<br />
L22<br />
L28<br />
L3<br />
L6<br />
L8<br />
M11<br />
M13<br />
M15<br />
M17<br />
M19<br />
M21<br />
M5<br />
M9<br />
N10<br />
N12<br />
N14<br />
N16<br />
N18<br />
N20<br />
N22<br />
N28<br />
N8<br />
P11<br />
P13<br />
P15<br />
P17<br />
P19<br />
P21<br />
P27<br />
P9<br />
R10<br />
R12<br />
R14<br />
R16<br />
R18<br />
R20<br />
R22<br />
R24<br />
R25<br />
R8<br />
T11<br />
T13<br />
T15<br />
T17<br />
T19<br />
T21<br />
T24<br />
T25<br />
T7<br />
T9<br />
U10<br />
U12<br />
U14<br />
U16<br />
U18<br />
U20<br />
U22<br />
U24<br />
U25<br />
U6<br />
U8<br />
V11<br />
V15<br />
V17<br />
V19<br />
V24<br />
V25<br />
V28<br />
V7<br />
V9<br />
W14<br />
W20<br />
W22<br />
W28<br />
W6<br />
W8<br />
Y17<br />
Y27<br />
BOM OPTIONS<br />
38<br />
38<br />
38<br />
38<br />
PP1V8_AWAKE_SW3C<br />
SOC_BOARD_REV_2<br />
SOC_BOARD_REV_1<br />
SOC_BOARD_REV_0<br />
1 2<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
BOARD REV[3:0] MODE<br />
1111 T208_Rev0 (X362 P0)<br />
1110 T208_Rev1 (X363 P0)<br />
1101 T208_Rev2 (X362 P1)<br />
1100 T208_Rev3 (X362 P2)<br />
1011 T208_Rev4 (X363 P2/X362 localEVT)<br />
1010 T208_Rev5 (X363 EVT/X362 EVT1)<br />
AC8<br />
T2<br />
T1<br />
R1<br />
R2<br />
V1<br />
V2<br />
W1<br />
W2<br />
U1<br />
U2<br />
Y1<br />
Y2<br />
T3<br />
T5<br />
M7<br />
N7<br />
R6<br />
R7<br />
U7<br />
V4<br />
V6<br />
AA3<br />
M6<br />
P7<br />
T8<br />
V8<br />
W5<br />
W7<br />
Y4<br />
Y5<br />
Y6<br />
Y7<br />
CFSB_MAR<br />
MAX_RX_IP<br />
MAX_RX_IM<br />
MAX_RX_QP<br />
MAX_RX_QM<br />
MAX_TX_IP<br />
MAX_TX_IM<br />
MAX_TX_QP<br />
MAX_TX_QM<br />
MAX_TX_BTAP<br />
MAX_TX_BTAM<br />
MAX_TX_WLETP<br />
MAX_TX_WLETM<br />
MAX_FREF<br />
MAX_TEST_OUT<br />
T208_CONFIG2_H<br />
R4100<br />
2.2K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
VDD_SOC_MAR<br />
VDD_SRAM_MAR<br />
VDDIO18_MAR<br />
1 2<br />
BOM_COST_GROUP=T151<br />
OMIT_TABLE<br />
U3900<br />
M8-LPDDR4-H-A-FUSE<br />
UFBGA<br />
(7 OF 7)<br />
U3<br />
V3<br />
W3<br />
W4<br />
Y3<br />
T208 BOARD REV/BOARD ID<br />
S/W READ FLOW<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
1. SET GPIO AS INPUT<br />
2. DISABLE PU AND ENABLE PD<br />
3. READ<br />
4. DISABLE PD AND ENABLE PU<br />
PP1V8_AWAKE_SW3C 37 38 39 41<br />
PP1V8_AWAKE_SW3C<br />
T208_CONFIG1_H<br />
R4101<br />
2.2K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
VDD12_MAR_PLL<br />
VDD12_MAR_LV<br />
VDD12_MAR_HV<br />
VDD12_MAR_BG<br />
1 2<br />
VSS_MXL<br />
T208_CONFIG0_H<br />
R4102<br />
2.2K<br />
PAGE TITLE<br />
41<br />
39<br />
38<br />
5%<br />
1/20W<br />
MF<br />
201<br />
ID_3 reserved for DEV<br />
SOC_BOARD_ID_3<br />
R<br />
37<br />
38<br />
42 38<br />
42 38<br />
42 38<br />
AC6<br />
AD2<br />
AB1<br />
AC1<br />
AC2<br />
AB2<br />
AB3<br />
AD1<br />
AD8<br />
AE7<br />
AE9<br />
AA7<br />
AC7<br />
AD7<br />
AD6<br />
AE8<br />
AD3<br />
AA5<br />
AA2<br />
AB4<br />
AC3<br />
AD4<br />
AE2<br />
AC4<br />
AB5<br />
AE3<br />
AE4<br />
AE5<br />
AA6<br />
AC5<br />
AB6<br />
AB7<br />
AE6<br />
SOC_ROM_SPI_MISO<br />
SOC_ROM_SPI_MOSI<br />
SOC_ROM_SPI_CLK<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
1 2<br />
NOSTUFF<br />
R4103<br />
2.2K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
1 2<br />
BOARD ID[3:0] MODE<br />
1XXX<br />
0010<br />
T202 DEV<br />
T208<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
Camera/DFR 3<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
IV ALL RIGHTS RESERVED<br />
MAR_SYSALIVE<br />
MAR_TX_THROTTLE_N<br />
MAR_BT_RFIC_IRQ<br />
MAR_WL_RFIC_IRQ<br />
MAR_RFIC_PDET_0<br />
MAR_RFIC_PDET_1<br />
MAR_VDD1V2_PWR_REQ<br />
MAR_VDD1V2_FORCE_PWM<br />
MAR_RF_SWITCH_CTRL_0<br />
MAR_RF_SWITCH_CTRL_1<br />
MAR_RF_SWITCH_CTRL_2<br />
MAR_RFIC_EN<br />
MAR_PA_EN<br />
MAR_PA_CTRL<br />
MAR_ETIC_GPIO_0<br />
MAR_ETIC_GPIO_1<br />
MAR_RFFE_SCLK<br />
MAR_RFFE_SDATA<br />
MAR_SPARE_0<br />
MAR_SPARE_1<br />
MAR_SPARE_2<br />
MAR_SPI_CLK<br />
MAR_SPI_CS<br />
MAR_SPI_DATA_0<br />
MAR_SPI_DATA_1<br />
MAR_SPI_DATA_2<br />
MAR_SPI_DATA_3<br />
MAR_SPI_DATA_4<br />
MAR_SPI_DATA_5<br />
MAR_SPI_DATA_6<br />
MAR_SPI_DATA_7<br />
MAR_COEX_UART_RXD<br />
MAR_COEX_UART_TXD<br />
Apple Inc.<br />
NOSTUFF<br />
R4104<br />
2.2K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
REVISION<br />
BRANCH<br />
1 2<br />
DRAWING NUMBER<br />
PAGE<br />
SHEET<br />
R4105<br />
2.2K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
1 2<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
41 OF 145<br />
39 OF 119<br />
NOSTUFF<br />
R4106 2.2K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
SIZE<br />
D<br />
D<br />
C<br />
B<br />
A<br />
8 7 6<br />
5 4 3<br />
2 1
SYNC_MASTER=J79_ANDREW<br />
SYNC_DATE=03/14/2016<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
PP0V8_SLEEP2_BUCK1<br />
40<br />
41<br />
Berkelium<br />
FB for Bucks<br />
D<br />
C<br />
B<br />
41 40<br />
40<br />
SW1_EXT_ON<br />
PP0V8_SLEEP1_SW1<br />
3<br />
G<br />
1 2 5 6 8<br />
D<br />
S<br />
4 7<br />
VOLTAGE=1.8V<br />
PP1V8_ALWAYS_LDO9<br />
1<br />
2<br />
Q4201<br />
CSD58892Q2<br />
SON2X2<br />
C4227<br />
0.22UF<br />
20%<br />
10V<br />
CERM-X5R<br />
0201<br />
PLACE_NEAR=U4200.A7:2mm<br />
101<br />
41<br />
40<br />
101<br />
41<br />
PLACE_NEAR=U4200.M4:2mm<br />
VOLTAGE=0.6V<br />
40<br />
C4220 1<br />
2.2UF<br />
20%<br />
6.3V<br />
2<br />
1<br />
2<br />
X5R-CERM<br />
0201<br />
C4226<br />
0.022UF<br />
10%<br />
6.3V<br />
X5R-CERM<br />
0201<br />
101<br />
41<br />
PP3V3_S4_SOC_PMU<br />
40<br />
PP3V3_S4_SOC_PMU<br />
1<br />
C4228<br />
2.2UF<br />
20%<br />
2<br />
6.3V<br />
X5R-CERM<br />
0201<br />
1<br />
PP3V3_S4_SOC_PMU<br />
CRITICAL<br />
C4204<br />
15UF<br />
20%<br />
2<br />
6.3V<br />
CERM<br />
0402<br />
20%<br />
PLACE_NEAR=U4200.E1:3mm 2<br />
6.3V<br />
CERM<br />
0402<br />
1<br />
2<br />
C4219<br />
2.2UF<br />
20%<br />
6.3V<br />
X5R-CERM<br />
0201<br />
2.2UF<br />
20%<br />
6.3V<br />
X5R-CERM<br />
0201<br />
PLACE_NEAR=U4200.L8:2mm<br />
41<br />
41<br />
1<br />
2<br />
PP3V0_AWAKE_LDO7<br />
101<br />
41<br />
40<br />
PP0V6_SLEEP2_LDO0<br />
1<br />
C4218<br />
CRITICAL<br />
C4207<br />
15UF<br />
101<br />
PP3V3_S4_SOC_PMU<br />
41 40<br />
41 40<br />
41 40<br />
41<br />
41 40<br />
41 37<br />
41 38 37<br />
41<br />
101<br />
40<br />
41<br />
PP3V3_S4_SOC_PMU<br />
40<br />
PP0V8_SLEEP2_BUCK1<br />
PP0V8_SLEEP1_SW1<br />
PP1V1_SLEEP3_BUCK2<br />
PP1V1_SLEEP1_SW2<br />
PP1V8_SLEEP3_BUCK3<br />
PP1V8_SLEEP2_SW3A<br />
1<br />
2<br />
1<br />
15UF<br />
20%<br />
6.3V<br />
CERM<br />
0402<br />
PP1V8_AWAKE_SW3C<br />
CRITICAL<br />
C4203<br />
15UF<br />
20%<br />
2<br />
6.3V<br />
CERM<br />
0402<br />
PLACE_NEAR=U4200.K11:2mm<br />
CRITICAL<br />
C4205<br />
NC<br />
SW1_EXT_ON<br />
PP3V3_S4_SOC_PMU<br />
PLACE_NEAR=U4200.F12:2mm<br />
PLACE_NEAR=U4200.A2:2mm<br />
40<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
C6<br />
D7<br />
E1<br />
G1<br />
J3<br />
H1<br />
M4<br />
N2<br />
L8<br />
L3<br />
M5<br />
N4<br />
M1<br />
N3<br />
N5<br />
M2<br />
M10<br />
M6<br />
M9<br />
N7<br />
N10<br />
N9<br />
N6<br />
M8<br />
N8<br />
B10<br />
A11<br />
C10<br />
B1<br />
C1<br />
B12<br />
B11<br />
C11<br />
C12<br />
K1<br />
1<br />
2<br />
CRITICAL<br />
C4206<br />
15UF<br />
20%<br />
6.3V<br />
CERM<br />
0402<br />
SW0_EXT<br />
SW1_EXT<br />
BB_LX1<br />
BB_LX2<br />
BB_FB<br />
BB_OUT<br />
VDD_HVLDO_237<br />
VDD_HVLDO_45<br />
VDD_HVLDO_RTC<br />
VDD_HVLDO_SW6<br />
LDO2_OUT<br />
LDO3_OUT<br />
LDO4_OUT<br />
LDO5_OUT<br />
LDO7_OUT<br />
SW4_OUT<br />
A7<br />
A8<br />
A2<br />
F12<br />
G12<br />
VDD_MAIN_BUCK0<br />
VDD_MAIN_BUCK1<br />
VDD_MAIN_BUCK2<br />
VDD_MAIN_BUCK3<br />
VDD_MAIN_BUCK4<br />
VDD_MAIN_LDO_16<br />
VDD_MAIN_LDO_8<br />
VDD_MAIN_LDO_9<br />
VDD_MAIN_LDO_AUX<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
LDO1_OUT<br />
LDO6_OUT<br />
LDO8_OUT<br />
LDO9_OUT<br />
AUX_PWR_OUT<br />
SW1_IN<br />
SW1_OUT<br />
LDO0_OUT<br />
SW2_IN<br />
SW2_OUT<br />
SW3_IN<br />
SW3A_OUT<br />
SW3B_OUT<br />
SW3C_OUT<br />
SW5_IN<br />
D1<br />
VDD_MAIN_BB<br />
K11<br />
L11<br />
M11<br />
VDD_MAIN_CHG<br />
VDD_MAIN_CHG<br />
VDD_MAIN_CHG<br />
U4200<br />
D2346A1-OTP-CE<br />
WLCSP<br />
J1<br />
VDD_MAIN_BBCORE<br />
SYM 1 OF 2<br />
K3<br />
NC<br />
ACT_DIODE*<br />
L2<br />
VDD_MAIN_SW4<br />
NC<br />
NC<br />
K12<br />
L12<br />
M12<br />
NC<br />
VBAT<br />
VBAT<br />
VBAT<br />
K10<br />
NC<br />
VBAT_S<br />
BUCK0_LX<br />
BUCK0_FB<br />
BUCK1_LX<br />
BUCK1_FB<br />
BUCK2_LX<br />
BUCK2_FB<br />
BUCK3_LX<br />
BUCK3_FB<br />
BUCK4_LX<br />
BUCK4_FB<br />
VSS_BB<br />
VSS_BUCK0<br />
VSS_BUCK1<br />
VSS_BUCK2<br />
VSS_BUCK3<br />
VSS_BUCK4<br />
A6<br />
C9<br />
A9<br />
D9<br />
A3<br />
C2<br />
E12<br />
D10<br />
H12<br />
J10<br />
F1<br />
A5<br />
A10<br />
A4<br />
D12<br />
J12<br />
SOC_PMU_BUCK0_LX<br />
SOC_PMU_BUCK0_FB<br />
SOC_PMU_BUCK1_LX<br />
SOC_PMU_BUCK1_FB<br />
SOC_PMU_BUCK2_LX<br />
SOC_PMU_BUCK2_FB<br />
SOC_PMU_BUCK3_LX<br />
SOC_PMU_BUCK3_FB<br />
CRITICAL<br />
Place same side as PMU<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
CRITICAL<br />
Place same side as PMU<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
CRITICAL<br />
Place same side as PMU<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
CRITICAL<br />
Place same side as PMU<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
Not using Buck4<br />
NC<br />
NC<br />
PP3V3_S4_SOC_PMU 40 41 101<br />
L4202<br />
1.0UH-1.82A-0.203OHM<br />
40<br />
1 2<br />
MCFK2012-SM<br />
L4203<br />
1.0UH-1.3A-0.326OHM<br />
40<br />
1 2<br />
MCFK1608T1R0M NA<br />
L4204<br />
1.0UH-1.3A-0.326OHM<br />
40<br />
1 2<br />
MCFK1608T1R0M NA<br />
L4205<br />
1.0UH-1.3A-0.326OHM<br />
40<br />
1 2<br />
MCFK1608T1R0M NA<br />
1<br />
2<br />
1<br />
2<br />
PLACE_NEAR=U4200.D1:2mm<br />
CRITICAL<br />
C4202<br />
15UF<br />
20%<br />
6.3V<br />
CERM<br />
0402<br />
CRITICAL<br />
1<br />
2<br />
1<br />
C4208<br />
15UF<br />
20%<br />
6.3V<br />
CERM<br />
0402<br />
CRITICAL<br />
C4211<br />
4.2UF<br />
10%<br />
2<br />
16V<br />
X5R-CERM<br />
0402-1<br />
1<br />
2<br />
CRITICAL<br />
C4234<br />
4.7UF<br />
20%<br />
6.3V<br />
CER-X5R<br />
0402<br />
CRITICAL<br />
C4238<br />
10UF<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402<br />
1<br />
2<br />
CRITICAL<br />
1<br />
2<br />
1<br />
2<br />
C4209<br />
15UF<br />
20%<br />
6.3V<br />
CERM<br />
0402<br />
CRITICAL<br />
C4231<br />
4.2UF<br />
10%<br />
16V<br />
X5R-CERM<br />
0402-1<br />
CRITICAL<br />
1<br />
CRITICAL<br />
C4235<br />
4.7UF<br />
20%<br />
6.3V<br />
CER-X5R<br />
0402<br />
C4239<br />
10UF<br />
20%<br />
2<br />
6.3V<br />
CERM-X5R<br />
0402<br />
1<br />
2<br />
C4210<br />
2.2UF<br />
20%<br />
6.3V<br />
X5R-CERM<br />
0201<br />
Mirror Capacitors in Layout<br />
1<br />
2<br />
1<br />
2<br />
CRITICAL<br />
C4236<br />
4.7UF<br />
20%<br />
6.3V<br />
CER-X5R<br />
0402<br />
1<br />
CRITICAL<br />
C4240<br />
4.7UF<br />
20%<br />
6.3V<br />
CER-X5R<br />
0402<br />
C4233<br />
4.7UF<br />
SOC_PMU_BUCK0_FB<br />
SOC_PMU_BUCK1_FB<br />
SOC_PMU_BUCK2_FB<br />
SOC_PMU_BUCK3_FB<br />
PP0V6_SLEEP1_BUCK0<br />
1<br />
Mirror Capacitors in Layout<br />
PP0V8_SLEEP2_BUCK1<br />
PP1V1_SLEEP3_BUCK2<br />
1<br />
CRITICAL<br />
Mirror Capacitors in Layout<br />
PP1V8_SLEEP3_BUCK3<br />
CRITICAL<br />
1<br />
2<br />
40<br />
40<br />
2<br />
2<br />
C4237<br />
4.7UF<br />
20%<br />
6.3V<br />
CER-X5R<br />
0402<br />
C4230<br />
2.2UF<br />
20%<br />
6.3V<br />
X5R-CERM<br />
0201<br />
1<br />
C4241<br />
4.7UF<br />
20%<br />
6.3V<br />
CER-X5R<br />
0402<br />
C4232<br />
4.7UF<br />
20%<br />
20%<br />
6.3V<br />
2<br />
6.3V<br />
2<br />
CER-X5R<br />
CER-X5R<br />
0402<br />
0402<br />
CRITICAL<br />
CRITICAL<br />
Mirror Capacitors in Layout<br />
40<br />
41<br />
40<br />
41<br />
R4200<br />
0<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
R4201<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
R4202<br />
0<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
R4203<br />
0<br />
0<br />
1 2<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
VDD_SOC<br />
501MA MAX<br />
VDD_SRAM_AON<br />
VDD_SRAM<br />
VDD_SOC_AON<br />
VDD_FIXED_MIPI<br />
VDD_FIXED_USB<br />
300MA MAX<br />
VDD2<br />
VDDQ<br />
VDD11_XTAL<br />
460MA MAX<br />
VDD1<br />
VDD18_USB<br />
VDDIO18_GRP0<br />
100MA MAX<br />
PP0V6_SLEEP1_BUCK0<br />
PP0V8_SLEEP1_SW1<br />
PP1V1_SLEEP3_BUCK2<br />
40 40 41<br />
40<br />
40<br />
40<br />
41<br />
41<br />
PP1V8_SLEEP3_BUCK3<br />
40<br />
40<br />
40<br />
41<br />
41<br />
41<br />
D<br />
C<br />
B<br />
A<br />
NC<br />
NC<br />
L1<br />
K2<br />
SW5_OUT<br />
SW6_OUT<br />
VSS1<br />
VSS2<br />
VSS3<br />
VSS3<br />
VSS4<br />
VSS4<br />
VSS4<br />
VSS4<br />
VSS4<br />
VSS4<br />
VSS4<br />
VSS4<br />
VSS6<br />
VSS7<br />
VSS8<br />
VSS8<br />
VSS8<br />
VSS8<br />
VSS8<br />
VSS8<br />
VSS8<br />
VSS9<br />
VSS9<br />
VSS9<br />
VSS9<br />
B2<br />
B9<br />
C4<br />
C5<br />
E5<br />
E6<br />
H5<br />
H6<br />
F5<br />
F6<br />
G5<br />
G6<br />
M3<br />
M7<br />
G8<br />
H7<br />
H8<br />
E7<br />
F7<br />
F8<br />
G7<br />
A1<br />
A12<br />
N1<br />
N12<br />
BOM_COST_GROUP=T151<br />
PAGE TITLE<br />
R<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
Berkelium - 1<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
IV ALL RIGHTS RESERVED<br />
Apple Inc.<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
42 OF 145<br />
40 OF 119<br />
SIZE<br />
D<br />
A<br />
8 7 6<br />
5 4 3<br />
2 1
SYNC_MASTER=J79_ANDREW<br />
SYNC_DATE=02/01/2016<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
Berkelium - 2<br />
D<br />
C<br />
PP1V8_SLEEP2_SW3A 41<br />
1<br />
R4305<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
37 19<br />
PMU_TO_SOC_SYS_ALIVE<br />
IN<br />
NC<br />
SOC_PMU_CLK_32K<br />
37<br />
41<br />
F4<br />
F3<br />
CLK_32K_ALT<br />
CLK_32K_IN<br />
U4200<br />
D2346A1-OTP-CE<br />
WLCSP<br />
SYM 2 OF 2<br />
I2C1_SCL<br />
I2C1_SDA<br />
I2C2_SCL<br />
I2C2_SDA<br />
BB_FORCE_PWM<br />
VBUS_DET*<br />
SHDN<br />
RESET_IN1<br />
RESET_IN2<br />
INCKT_OTP<br />
IRQ*<br />
RESET*<br />
VDD_OK<br />
SYS_ALIVE<br />
ACTIVE_REQUEST<br />
ACTIVE_PWRGOOD<br />
SLEEP1_REQUEST<br />
SLEEP1_PWRGOOD<br />
SOC_VDD_CORE_HI_LO<br />
UWAKE*<br />
E3<br />
E4<br />
G3<br />
G4<br />
B4<br />
K9<br />
G2<br />
H2<br />
H3<br />
B3<br />
E11<br />
B7<br />
B8<br />
D11<br />
D6<br />
E9<br />
D5<br />
E10<br />
F2<br />
H4<br />
SOC_PMU_I2C_SCL<br />
SOC_PMU_I2C_SDA<br />
SMBUS_SOC_PMU_BR_SCL<br />
SMBUS_SOC_PMU_BR_SDA<br />
BB_FORCE_PWM<br />
PMU_SOC_VBUS_DET_L<br />
SMC_SOCPMU_RESET<br />
SOC_PMU_INCKT_OTP<br />
PMU_TO_SOC_IRQ_L<br />
PMU_TO_SOC_RESET_L<br />
PMU_TO_SOC_VDD_OK<br />
PMU_TO_SOC_SYS_ALIVE<br />
SOC_AWAKE_REQ<br />
PMU_TO_SOC_AWAKE_PWRGD<br />
SOC_SLEEP1_REQ<br />
PMU_TO_SOC_SLEEP1_PWRGD<br />
SOC_VDD_HI_LO<br />
PMU_SOC_UWAKE_L<br />
NC<br />
NC<br />
41<br />
41<br />
41<br />
IN<br />
IN<br />
41<br />
37<br />
37<br />
BI<br />
38<br />
1 2<br />
1 2<br />
R4321<br />
41<br />
OUT<br />
OUT<br />
OUT<br />
37<br />
37<br />
37<br />
38<br />
OUT<br />
IN<br />
OUT<br />
IN 37<br />
38<br />
37<br />
37<br />
5%<br />
R4320<br />
SMBUS_SMC_2_S4_SCL<br />
SMBUS_SMC_2_S4_SDA<br />
5% 1/20W 201<br />
37<br />
38<br />
OUT<br />
41<br />
37<br />
MF<br />
1/20W 201 0<br />
0<br />
MF<br />
To T208, Device ID=0x3C, READ=0x79, WRITE-0x78<br />
To SMC, Device ID=0x3C, READ=0x79, WRITE-0x78<br />
PP3V3_S4_SOC_PMU 40 101<br />
R4302<br />
100K<br />
1 2<br />
PMU_SOC_VBUS_DET_L<br />
IN<br />
BI<br />
5%<br />
1/20W<br />
MF<br />
201<br />
51<br />
51<br />
PMU_SOC_UWAKE_L<br />
41<br />
41<br />
BUCK0<br />
BUCK1<br />
LDO0<br />
SW1<br />
BUCK2<br />
SW2<br />
39<br />
39<br />
39<br />
39<br />
PP0V6_SLEEP1_BUCK0<br />
PP0V8_SLEEP2_BUCK1<br />
PP0V6_SLEEP2_LDO0<br />
PP0V8_SLEEP1_SW1<br />
37 PP1V1_SLEEP3_BUCK2<br />
39<br />
PP1V1_SLEEP1_SW2<br />
T208 POWER ALIASES<br />
PP0V6_SLEEP1_BUCK0<br />
VOLTAGE=0.6V<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
MAKE_BASE=TRUE<br />
PP0V8_SLEEP2_BUCK1<br />
VOLTAGE=0.8V<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
MAKE_BASE=TRUE<br />
PP0V6_SLEEP2_LDO0<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
MAKE_BASE=TRUE<br />
VOLTAGE=0.6V<br />
PP0V8_SLEEP1_SW1<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
MAKE_BASE=TRUE<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
MAKE_BASE=TRUE VOLTAGE=1.1V<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
MAKE_BASE=TRUE VOLTAGE=1.1V<br />
VOLTAGE=0.8V<br />
PP0V8_SLEEP1_SW1 38<br />
PP0V8_SLEEP1_SW1 38<br />
PP0V8_SLEEP1_SW1<br />
PP1V1_SLEEP3_BUCK2<br />
PP1V1_SLEEP3_BUCK2 39<br />
PP1V1_SLEEP1_SW2<br />
40<br />
40<br />
40<br />
40<br />
PP1V1_SLEEP1_SW2 37<br />
40<br />
40<br />
D<br />
C<br />
B<br />
1<br />
2<br />
NOSTUFF<br />
C4300<br />
100PF<br />
5%<br />
25V<br />
C0G<br />
0201<br />
PMU_TCAL_GND<br />
1<br />
2<br />
1 2<br />
NOSTUFF<br />
3.92K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
PMU_VREF<br />
C4301<br />
0.1UF<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
R4307<br />
OMIT<br />
XW4300<br />
SHORT-8L-0.1MM-SM<br />
1 2<br />
R4308<br />
PMU_TCAL_PWR<br />
200K<br />
1 2<br />
PMU_IREF<br />
0.1%<br />
1/20W<br />
TF<br />
0201<br />
1<br />
2<br />
C4302<br />
0.1UF<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
PMU_VDD_RTC<br />
PMU_VPUMP<br />
1<br />
2<br />
C4303<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
L9<br />
L6<br />
N11<br />
J5<br />
L7<br />
D2<br />
TCAL<br />
VREF<br />
IREF<br />
VDD_RTC_DIG<br />
VDD_RTC<br />
VPUMP<br />
VSS8<br />
VSS8<br />
VSS8<br />
VSS8<br />
VSS8<br />
E8<br />
J7<br />
J8<br />
K8<br />
K7<br />
BUTTON1<br />
BUTTON2<br />
BUTTON3<br />
DBLCLICK_DET<br />
GPIO1<br />
GPIO2<br />
GPI3<br />
GPIO4<br />
GPIO5<br />
GPIO6<br />
GPIO7<br />
GPIO8<br />
GPIO9<br />
GPIO10<br />
GPIO11<br />
GPIO12<br />
GPIO13<br />
GPIO14<br />
GPIO15<br />
AMUX_IN1<br />
AMUX_IN2<br />
AMUX_IN3<br />
AMUX_IN4<br />
AMUX_OUT<br />
NTC1<br />
NTC2<br />
NTC3<br />
NTC4<br />
TBAT<br />
E2<br />
D3<br />
D4<br />
C3<br />
C7<br />
B5<br />
B6<br />
C8<br />
D8<br />
F9<br />
F10<br />
F11<br />
G9<br />
G10<br />
G11<br />
H9<br />
H10<br />
H11<br />
J11<br />
K6<br />
L4<br />
J6<br />
K5<br />
L5<br />
J9<br />
J2<br />
K4<br />
J4<br />
L10<br />
PMU_TO_SOC_CLK_32K<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
OUT<br />
37<br />
R4301<br />
100K<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
1 2<br />
R4303<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
BB_FORCE_PWM<br />
SOC_PMU_INCKT_OTP<br />
R4315<br />
5%<br />
1/20W<br />
MF<br />
201<br />
We can remove R4304 this once we verify grounding is ok<br />
1 2<br />
0<br />
41<br />
41<br />
BUCK3<br />
SW3A<br />
SW3C<br />
LDO7<br />
38<br />
39<br />
38<br />
39<br />
37<br />
PP1V8_SLEEP3_BUCK3<br />
PP1V8_SLEEP2_SW3A<br />
PP1V8_AWAKE_SW3C<br />
PP3V0_AWAKE_LDO7<br />
PP1V1_SLEEP1_SW2 38<br />
PP1V1_SLEEP1_SW2 38<br />
PP1V1_SLEEP1_SW2 38<br />
PP1V1_SLEEP1_SW2 37<br />
PP1V8_SLEEP3_BUCK3<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
MAKE_BASE=TRUE<br />
VOLTAGE=1.8V<br />
PP1V8_SLEEP2_SW3A<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
MAKE_BASE=TRUE VOLTAGE=1.8V<br />
PP1V8_SLEEP2_SW3A 37<br />
PP1V8_SLEEP2_SW3A 41<br />
PP1V8_AWAKE_SW3C<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
MAKE_BASE=TRUE VOLTAGE=1.8V<br />
PP1V8_AWAKE_SW3C 38<br />
PP1V8_AWAKE_SW3C 37 38 39<br />
PP3V0_AWAKE_LDO7<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
MAKE_BASE=TRUE<br />
VOLTAGE=3.0V<br />
40<br />
40<br />
37 40<br />
37 38 40<br />
B<br />
Signal Aliases<br />
A<br />
48<br />
SMC_SOCPMU_RESET<br />
SMC_SOCPMU_RESET<br />
41<br />
MAKE_BASE=TRUE<br />
BOM_COST_GROUP=T151<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
Berkelium - 2<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
43 OF 145<br />
41 OF 119<br />
SIZE<br />
D<br />
A
SYNC_MASTER=J79_ANDREW<br />
SYNC_DATE=07/01/2016<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
T208 Support<br />
PP1V8_S0SW_DFR<br />
37<br />
42<br />
104<br />
106<br />
D<br />
C<br />
38<br />
38 37<br />
104<br />
38 37<br />
104<br />
104 37<br />
1<br />
R4491<br />
24K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
BI<br />
IN<br />
104 42<br />
IN<br />
BI<br />
IN<br />
5%<br />
1/20W<br />
MF<br />
201<br />
D<br />
3<br />
Q4400<br />
DMN32D2LFB4<br />
DFN1006H4-3<br />
104<br />
R4481<br />
1<br />
4.7K<br />
DFR_TOUCH_LID<br />
DFR_TOUCH_GPIO2<br />
SMC_LID<br />
DFR_TOUCH_SPI_CS_L<br />
DFR_TOUCH_SPI_MOSI_R<br />
DFR_TOUCH_ROM_I2C_SCL<br />
DFR_TOUCH_ROM_I2C_SDA<br />
DFR_TOUCH_RESET_L<br />
104 42 37 PP1V8_S0SW_DFR<br />
106<br />
104 101 PP5V_S0_T139<br />
2<br />
SYM_VER_2<br />
1<br />
S G<br />
2<br />
PP1V8_S0SW_DFR<br />
37<br />
42<br />
104<br />
1<br />
2<br />
106<br />
C4490<br />
100PF<br />
5%<br />
25V<br />
C0G<br />
0201<br />
DFR Touch Conn<br />
J4402<br />
AA07-S022VA1<br />
2<br />
4<br />
6<br />
8<br />
10<br />
12<br />
14<br />
16<br />
18<br />
20<br />
22<br />
43<br />
49<br />
50<br />
F-ST-SM<br />
104<br />
24<br />
23<br />
1<br />
3<br />
5<br />
7<br />
9<br />
11<br />
13<br />
15<br />
17<br />
19<br />
21<br />
25<br />
26<br />
106 104 42 37<br />
DFR_TOUCH_PANEL_DETECT<br />
DFR_DISP_VSYNC<br />
DFR_TOUCH_SPI_MISO_R<br />
DFR_TOUCH_SPI_CLK_R<br />
DFR_TOUCH_INT_L<br />
DFR_CLKIN_RESET_L<br />
DFR_TOUCH_ROM_WC<br />
PP1V8_S0SW_DFR<br />
PP1V8_S0SW_DFR<br />
106 104 42 37<br />
104 42<br />
106<br />
R4480<br />
1<br />
PP1V8_S0SW_DFR<br />
42<br />
42<br />
BI<br />
OUT<br />
104<br />
104<br />
IN<br />
IN<br />
NOSTUFF<br />
10K<br />
1/20W<br />
5%<br />
201 MF<br />
2<br />
80 42<br />
38<br />
38<br />
38<br />
104<br />
38<br />
IN<br />
104<br />
42<br />
104<br />
104<br />
1<br />
2<br />
NOSTUFF<br />
1<br />
R4485<br />
4.7K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
OUT<br />
P3V3S0SW_RAMP<br />
C4410<br />
2200PF<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
38<br />
80<br />
38<br />
DFR_DISP_PWR_EN<br />
104<br />
R4492<br />
1<br />
100K<br />
IN<br />
IN<br />
1/20W<br />
5%<br />
MF<br />
201<br />
DFR_DISP_RST_L<br />
DFR Connectors<br />
2<br />
DFR_DISP_SMC_RST_L<br />
100<br />
38 37<br />
42<br />
3.3V DFR Switch<br />
1<br />
VDD<br />
U4405<br />
SLG5AP1443V<br />
TDFN<br />
PP1V8_S0<br />
7 CAP<br />
D 3<br />
2 ON<br />
S 5<br />
GND<br />
8<br />
1<br />
2<br />
C4403<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
PP3V3_S5_T139 42<br />
101<br />
1<br />
2<br />
2<br />
1<br />
B<br />
A<br />
EDP: 182mA<br />
Part<br />
Type<br />
1<br />
0<br />
2<br />
NOSTUFF<br />
5%<br />
1/20W<br />
MF<br />
201<br />
NC<br />
C4400<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
U4406<br />
NC<br />
5<br />
R4490<br />
6<br />
3<br />
104<br />
74LVC1G08FW5<br />
DFN1010<br />
4<br />
Y<br />
R4400<br />
1<br />
100K<br />
1/20W<br />
5%<br />
MF<br />
201<br />
PP3V3_S0SW_DFR<br />
2<br />
SLG5AP1443V<br />
Load Switch<br />
42 38<br />
104<br />
104 38<br />
104 38<br />
OUT<br />
OUT<br />
OUT<br />
VOLTAGE=3.3V<br />
MIN_NECK_WIDTH=0.0520<br />
MIN_LINE_WIDTH=0.0900<br />
DFR_DISP_VSYNC<br />
DFR_DISP_TE<br />
DFR_DISP_INT<br />
DFR_DISP_RESET_L<br />
104<br />
C4470 1<br />
0.1UF<br />
2<br />
10%<br />
6.3V<br />
X5R<br />
0201<br />
U4405<br />
DFR Disp Conn<br />
J4401<br />
DF40PG(1.5)-26DS-04V(51)<br />
F-ST-SM<br />
28<br />
2<br />
4<br />
6<br />
8<br />
10<br />
12<br />
14<br />
16<br />
18<br />
20<br />
22<br />
24<br />
26<br />
30<br />
GND<br />
GND<br />
GND<br />
GND<br />
27<br />
1<br />
3<br />
5<br />
7<br />
9<br />
11<br />
13<br />
15<br />
17<br />
19<br />
21<br />
23<br />
25<br />
29<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
MIN_NECK_WIDTH=0.0520<br />
DFRDRV_I2C_SCL<br />
DFRDRV_I2C_SDA<br />
105 104<br />
105 104<br />
105 104<br />
105 104<br />
VOLTAGE=1.8V<br />
MIN_LINE_WIDTH=0.0900<br />
IN<br />
BI<br />
37<br />
37<br />
MIPID_CLK_CONN_P<br />
MIPID_CLK_CONN_N<br />
MIPID_DATA_CONN_P<br />
MIPID_DATA_CONN_N<br />
PP1V8_S0SW_DFR<br />
38<br />
38<br />
104<br />
104<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
VOLTAGE=1.8V<br />
MIN_NECK_WIDTH=0.0520<br />
MIN_LINE_WIDTH=0.0900<br />
1<br />
EDP: 32.6mA<br />
1<br />
1<br />
2<br />
PLACE_NEAR=J4401:5mm<br />
C4471<br />
1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0402<br />
2<br />
MIPID FILTERING<br />
3.25-OHM-0.1A-2.4GHZ<br />
TAM0605-4SM<br />
L4400<br />
MIPID_CLK_P<br />
MIPID_CLK_N<br />
3.25-OHM-0.1A-2.4GHZ<br />
TAM0605-4SM<br />
PLACE_NEAR=J4401:2.54mm<br />
SYM_VER-1<br />
GND_VOID=TRUE<br />
4<br />
1<br />
3<br />
C4401<br />
1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0402<br />
4<br />
3<br />
L4401<br />
OUT<br />
SYM_VER-1<br />
2<br />
1<br />
2<br />
PLACE_NEAR=J4401:2.54mm<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
MIPID_DATA_P<br />
GND_VOID=TRUE<br />
U4404<br />
NCP160AMX180<br />
XDFN-COMBO<br />
EPAD<br />
5<br />
GND<br />
2<br />
MIPID_DATA_N<br />
IN<br />
EN<br />
4<br />
3<br />
IN 38<br />
IN 38<br />
IN 38<br />
IN 38<br />
DFR_DISP_PWR_EN<br />
PP3V3_S5_T139 42 101<br />
IN 42 80<br />
1<br />
2<br />
C4402<br />
1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0402<br />
D<br />
C<br />
R(on)<br />
@ 3.3V<br />
Current<br />
17 mOhm Typ<br />
19 mOhm Max<br />
2.5A Max<br />
SWD DEBUG MUX<br />
T208 I2C Mapping<br />
SPI TERM<br />
B<br />
14<br />
IN<br />
101<br />
42<br />
37<br />
37<br />
38<br />
OUT<br />
BI<br />
PP3V3_S4_SOC_PMU<br />
SOC<br />
SOC_SWCLK<br />
SOC_SWDIO<br />
INT PU SOC 50k<br />
PCH_SWD_MUX_SEL<br />
1<br />
2<br />
10<br />
Y+<br />
Y-<br />
SEL<br />
9<br />
VCC<br />
U4408<br />
PI3USB102EZLE<br />
TQFN<br />
GND<br />
3<br />
M+<br />
M-<br />
D+<br />
D-<br />
OE*<br />
5<br />
4<br />
7<br />
6<br />
8<br />
1<br />
PLACE_NEAR=U4408:2mm<br />
C4444<br />
0.1UF<br />
10%<br />
2<br />
6.3V<br />
CERM-X5R<br />
0201<br />
SOC_XB_DBG1_1V8<br />
SOC_XB_DBG2_1V8<br />
SOC_SWD_CLK<br />
PCH_SWD_IO<br />
37 42<br />
ACE<br />
(Default)<br />
42<br />
IN<br />
BI<br />
14<br />
14<br />
PCH<br />
(When SEL driven high)<br />
19<br />
Bus<br />
AP0<br />
AP1<br />
AP2_0<br />
AOP0<br />
AOP1<br />
SEP<br />
Device<br />
PMU<br />
Touch EEPROM<br />
Tesla<br />
Mesa EEPROM<br />
ALS<br />
M34128 EEPROM<br />
7-bit Address<br />
8-bit Address<br />
Read<br />
Write<br />
0011110 (0x3C)<br />
0x79 0x78<br />
1010000 (0x50)<br />
0xA1 0xA0<br />
1010100 (0x4C)<br />
0x99 0x98<br />
101000x (0x50/0x51)<br />
0xA1/A3 0xA0/A2<br />
0111001 (0x39)<br />
0x73 0x72<br />
1010001 (0x51)<br />
0xA3 0xA2<br />
T208 LEVEL SHIFTING<br />
37<br />
37<br />
OUT<br />
37<br />
DFR_TOUCH_SPI_MISO<br />
PLACE_NEAR=U3900.Y20:5mm<br />
DFR_TOUCH_SPI_MOSI<br />
IN<br />
PLACE_NEAR=U3900.AB21:5mm<br />
DFR_TOUCH_SPI_CLK<br />
IN<br />
38 IN<br />
38 IN<br />
PLACE_NEAR=U3900.C9:5mm<br />
MESA_SPI_MOSI<br />
PLACE_NEAR=U3900.B9:5mm<br />
MESA_SPI_CLK<br />
R4453<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R4455<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R4456<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
PLACE_NEAR=J4402.7:5mm<br />
DFR_TOUCH_SPI_MISO_R<br />
R4454<br />
0<br />
1 2<br />
DFR_TOUCH_SPI_MOSI_R<br />
5%<br />
1/20W<br />
MF<br />
201<br />
DFR_TOUCH_SPI_CLK_R<br />
MESA_SPI_MOSI_R<br />
R4457<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
MESA_SPI_CLK_R<br />
42<br />
104<br />
OUT<br />
42<br />
104<br />
47<br />
39 38<br />
42<br />
39 38<br />
OUT<br />
104<br />
47<br />
OUT<br />
39 38<br />
SOC_ROM_SPI_MISO<br />
PLACE_NEAR=U3900.D10:5mm<br />
PLACE_NEAR=U3900.B10:5mm<br />
IN<br />
IN<br />
SOC_ROM_SPI_MOSI<br />
SOC_ROM_SPI_CLK<br />
R4450<br />
100<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R4452<br />
0<br />
SOC_BOOT:SPI<br />
PLACE_NEAR=U3906.2:5mm<br />
SOC_ROM_SPI_MISO_R<br />
R4451<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
SOC_BOOT:SPI<br />
SOC_ROM_SPI_MOSI_R<br />
1 2 SOC_ROM_SPI_CLK_R<br />
5% SOC_BOOT:SPI<br />
1/20W<br />
MF<br />
201<br />
IN<br />
37<br />
OUT<br />
37<br />
OUT<br />
37<br />
B<br />
A<br />
T208<br />
37<br />
37<br />
100<br />
BI<br />
IN<br />
37<br />
PP1V8_S0<br />
1<br />
2<br />
C4450<br />
0.1UF<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
ALS_SCL_I2C_1V8<br />
ALS_SDA_I2C_1V8<br />
SOC_ALS_LS_EN<br />
1 2<br />
R4470<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
3<br />
5<br />
ALS I2C<br />
1<br />
IO/VL1<br />
IO/VL2<br />
EN<br />
VL<br />
U4403<br />
NLSX4402<br />
UDFN<br />
4<br />
8<br />
GND<br />
VCC<br />
101 PP3V3_S0<br />
IO/VCC1<br />
IO/VCC2<br />
7<br />
6<br />
1<br />
2<br />
C4451<br />
0.1UF<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
I2C_ALS_SCL_R<br />
I2C_ALS_SDA_R<br />
1<br />
1<br />
R4420<br />
100<br />
1/20W<br />
201<br />
MF 5%<br />
R4421<br />
100<br />
1/20W<br />
201<br />
MF 5%<br />
2<br />
2<br />
1 2<br />
I2C_ALS_SCL<br />
I2C_ALS_SDA<br />
R4471<br />
1K 5%<br />
1/20W<br />
MF<br />
201<br />
ALS<br />
OUT<br />
1 2<br />
80<br />
104<br />
100<br />
1/20W<br />
MF<br />
201<br />
42<br />
R4472<br />
1K 5%<br />
BI<br />
80<br />
38<br />
38<br />
104<br />
IN<br />
37 PP1V8_S0<br />
1 2<br />
R4443<br />
47K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
38<br />
OUT<br />
1 2<br />
38<br />
T208<br />
R4442<br />
47K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
IN<br />
1 2<br />
38<br />
R4441<br />
47K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
OUT<br />
1 2<br />
R4440<br />
47K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
C4440<br />
0.1UF<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
SOC_UART_LS_EN<br />
PCH_TO_SOC_UART_TXD<br />
SOC_TO_PCH_UART_TXD<br />
PCH_ALS_TO_SOC_UART_TXD<br />
SOC_TO_PCH_ALS_UART_TXD<br />
1<br />
2<br />
1 2<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
ALS/DEBUG UART<br />
R4444<br />
12<br />
2<br />
3<br />
4<br />
5<br />
EN<br />
1<br />
VL<br />
U4401<br />
NLSX5014MU_G<br />
UQFN<br />
IOLV[1]<br />
IOLV[2]<br />
IOLV[3]<br />
IOLV[4]<br />
6<br />
GND<br />
11<br />
VCC<br />
IOVCC[1]<br />
IOVCC[2]<br />
IOVCC[3]<br />
IOVCC[4]<br />
PP3V3_S0<br />
10<br />
9<br />
8<br />
7<br />
1<br />
2<br />
C4441<br />
0.1UF<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
38 101<br />
SOC_DBG_UART_R2D<br />
SOC_DBG_UART_D2R<br />
ALS_SOC_UART_R2D<br />
ALS_SOC_UART_D2R<br />
IN<br />
OUT<br />
PCH<br />
IN<br />
OUT<br />
19<br />
19<br />
19<br />
19<br />
100<br />
38<br />
T208 SWD MUX<br />
42<br />
42<br />
PP1V8_S4<br />
1<br />
2<br />
C4460<br />
0.1UF<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
SOC_XB_DBG1_1V8<br />
SOC_XB_DBG2_1V8<br />
SOC_SWD_LS_EN<br />
1 2<br />
ACE SWD DBG<br />
R4460<br />
5% 100K<br />
1/20W<br />
MF<br />
201<br />
2<br />
3<br />
5<br />
1<br />
IO/VL1<br />
IO/VL2<br />
EN<br />
VL<br />
U4402<br />
NLSX4402<br />
UDFN<br />
4<br />
8<br />
GND<br />
VCC<br />
BOM_COST_GROUP=T151<br />
PP3V3_S4_SOC_PMU 38 42 101<br />
IO/VCC1<br />
IO/VCC2<br />
7<br />
6<br />
1<br />
C4461<br />
0.1UF<br />
10%<br />
2<br />
16V<br />
X5R-CERM<br />
0201<br />
MAKE_BASE=TRUE<br />
SOC_SWCLK_DBG<br />
SOC_SWDIO_DBG<br />
PAGE TITLE<br />
ACE DBG<br />
R<br />
MAKE_BASE=TRUE<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
T208 Support<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
IV ALL RIGHTS RESERVED<br />
Apple Inc.<br />
SOC_SWCLK_DBG 30<br />
SOC_SWDIO_DBG 30<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
44 OF 145<br />
42 OF 119<br />
SIZE<br />
D<br />
A<br />
8 7 6<br />
5 4 3<br />
2 1
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
104<br />
104<br />
104 43<br />
104 43<br />
104 58<br />
104 58<br />
101<br />
100<br />
104<br />
43<br />
104 43<br />
104 43<br />
104 43<br />
104 43<br />
GND_FAN<br />
PP5V_S0_FAN_CONN<br />
FAN_LT_TACH<br />
FAN_LT_PWM<br />
PP5V_S0_KBD<br />
50 PP3V3_G3H<br />
KBD_BLC_GSSOUT<br />
KBD_BLC_GSLAT<br />
101 PP3V3_S4<br />
KBD_BLC_GSSIN<br />
KBD_BLC_XBLANK<br />
KBD CONNECTOR<br />
J4500<br />
DF40PC-40DS-0.4V-51<br />
F-ST-SM<br />
1 2<br />
3 4<br />
5 6<br />
7 8<br />
9 10<br />
11 12<br />
13 14<br />
15 16<br />
17 18<br />
19 20<br />
21 22<br />
23 24<br />
25 26<br />
27 28<br />
29 30<br />
31 32<br />
33 34<br />
35 36<br />
37 38<br />
39 40<br />
104 43<br />
GND_FAN<br />
VOLTAGE=0V<br />
PP5V_S0_FAN_CONN<br />
VOLTAGE=5V<br />
FAN_RT_TACH<br />
FAN_RT_PWM<br />
PP5V_S0_KBD 43 101 104<br />
KBD_I2C_SDA<br />
KBD_INT_L<br />
KBD_I2C_SCL<br />
SMC_LSOC_RST_L<br />
KBD_BLC_GSSCK<br />
XW4500<br />
SM<br />
1 2<br />
58<br />
58<br />
43<br />
43<br />
43<br />
50<br />
43<br />
104<br />
104<br />
104<br />
104<br />
104<br />
104<br />
104<br />
XW4502<br />
SM<br />
1 2<br />
PP5V_S0 58 101<br />
1<br />
2<br />
C4501<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
C4501 FOR DESENSE<br />
TPAD CONNECTOR<br />
104 51 SMBUS_SMC_3_SCL<br />
2<br />
1<br />
SMC_LID<br />
42 49<br />
104 51 SMBUS_SMC_3_SDA<br />
4<br />
3<br />
SMC_PME_S4_WAKE_L 50 104<br />
104 43 KBD_INT_L<br />
6<br />
5<br />
SMC_ACTUATOR_DISABLE_L 50 104<br />
KBD_I2C_SDA<br />
8<br />
7<br />
TPAD_SPI_INT_CONN_L<br />
104 43<br />
104 43<br />
104 43<br />
104 43<br />
104 43<br />
104 43<br />
104 43<br />
104 43<br />
KBD_I2C_SCL<br />
KBD_BLC_XBLANK<br />
KBD_BLC_GSSIN<br />
KBD_BLC_GSSOUT<br />
KBD_BLC_GSSCK<br />
KBD_BLC_GSLAT<br />
ACT_GND<br />
J4501<br />
DF40C-50DS-0.4V-51<br />
F-ST-SM<br />
10<br />
12<br />
14<br />
16<br />
18<br />
20<br />
22<br />
24<br />
26<br />
28<br />
30<br />
32<br />
34<br />
36<br />
38<br />
40<br />
42<br />
44<br />
9<br />
11<br />
13<br />
15<br />
17<br />
19<br />
21<br />
23<br />
25<br />
27<br />
29<br />
31<br />
33<br />
35<br />
37<br />
39<br />
41<br />
43<br />
104<br />
104<br />
104<br />
104<br />
104<br />
TPAD_SPI_MOSI_R<br />
TPAD_SPI_CS_CONN_R_L<br />
TPAD_SPI_MISO_R<br />
TPAD_SPI_IF_EN_CONN<br />
TPAD_SPI_CLK_R<br />
PP5V_S4_TPAD_CONN<br />
VOLTAGE=5V<br />
PP3V3_S4_TPAD 43 101<br />
104<br />
PP3V3_S0 43 101<br />
SMC_VIBE_L 50<br />
104 43<br />
ACT_GND<br />
XW4501<br />
SM<br />
1 2<br />
43<br />
OUT<br />
104<br />
50<br />
43<br />
104<br />
104<br />
C4500 1<br />
0.1UF<br />
10%<br />
25V<br />
2<br />
X5R<br />
402<br />
R4512<br />
33<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
1<br />
2<br />
R4513<br />
33<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R4511<br />
33<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
NOSTUFF<br />
C4511<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
0402A<br />
TPAD_SPI_MOSI<br />
TPAD_SPI_CS_CONN_L<br />
R4510<br />
33<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
L4500<br />
FERR-120-OHM-1.5A<br />
1 2<br />
TPAD_SPI_MISO<br />
TPAD_SPI_CLK<br />
16<br />
43<br />
16<br />
16<br />
PP5V_S4 101<br />
D<br />
46<br />
45<br />
C<br />
516S00177 (RCPT, 0.3A per pin)<br />
MATE WITH PLUG 516S00054<br />
100<br />
PPBUS_S4_HS_TPAD<br />
F4500<br />
2.5A-16V-0.1OHM<br />
1 2<br />
104<br />
PPVIN_S4_TPAD_FUSE<br />
48<br />
50<br />
47<br />
49<br />
C<br />
1812<br />
VOLTAGE=12.6V<br />
516S00187, MATE WITH 516S00188<br />
TRACKPAD ISOLATION<br />
101<br />
PP3V3_SUS<br />
B<br />
104 77 74 48 19 14<br />
104<br />
16<br />
101<br />
IN<br />
IN<br />
43<br />
PP3V3_S4_TPAD<br />
TPAD_SPI_IF_EN<br />
PM_SLP_S4_L<br />
C4530 1<br />
0.1UF<br />
10%<br />
10V<br />
2<br />
X5R-CERM<br />
0201<br />
NOSTUFF<br />
R4535<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
1<br />
2<br />
B<br />
A<br />
5<br />
3<br />
CRITICAL<br />
U4530<br />
74LVC1G08GW<br />
SOT353<br />
4<br />
Y<br />
TPAD_SPI_IF_EN_CONN<br />
43<br />
104<br />
101 43<br />
16<br />
IN<br />
IN<br />
PP3V3_S0<br />
TPAD_SPI_CS_L<br />
104 101 43<br />
S G 1<br />
PP3V3_S4_TPAD<br />
Q4530<br />
2<br />
3<br />
DMN32D2LFB4<br />
DFN1006H4-3<br />
SYM_VER_3<br />
D<br />
SIGNAL_MODEL=TPAD_FET<br />
1<br />
R4530<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
NOSTUFF<br />
R4536<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
TPAD_SPI_CS_CONN_L<br />
43<br />
16<br />
IN<br />
C4531 1<br />
0.1UF<br />
10%<br />
10V<br />
2<br />
X5R-CERM<br />
0201<br />
TPAD_SPI_INT_L<br />
CRITICAL<br />
U4531<br />
74LVC1G08GW<br />
SOT353<br />
4<br />
Y<br />
5<br />
3<br />
1<br />
B<br />
2<br />
A<br />
NOSTUFF<br />
R4537<br />
0<br />
1 2<br />
PP3V3_S4_TPAD 43 101 104<br />
1<br />
R4531<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
TPAD_SPI_INT_CONN_L<br />
43<br />
104<br />
B<br />
5%<br />
1/20W<br />
MF<br />
201<br />
A<br />
BOM_COST_GROUP=KEYBOARD<br />
SYNC_MASTER=J79_GAREN<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
Connectors&ESD<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
SYNC_DATE=11/21/2015<br />
9.0.0<br />
dvt-fab09-0<br />
45 OF 145<br />
43 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
D<br />
C<br />
C<br />
B<br />
B<br />
A<br />
SYNC_MASTER=J79_DAYU<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
Empty<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
SYNC_DATE=05/26/2015<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
46 OF 145<br />
44 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
D<br />
C<br />
C<br />
B<br />
B<br />
A<br />
SYNC_MASTER=J79_DAYU<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
Empty<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
SYNC_DATE=05/26/2015<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
47 OF 145<br />
45 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
D<br />
C<br />
C<br />
B<br />
B<br />
A<br />
SYNC_MASTER=J79_DAYU<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
Empty<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
REVISION<br />
BRANCH<br />
SYNC_DATE=05/12/2015<br />
DRAWING NUMBER<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
48 OF 145<br />
46 OF 119<br />
SIZE<br />
D<br />
A
SYNC_DATE=01/06/2016<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
MOJAVE 16V BOOST<br />
ISOLATE FROM OTHER COMPONENTS/NETS AS MUCH AS POSSIBLE<br />
D<br />
C<br />
101 47<br />
101 47<br />
47<br />
PP3V3_S4_MESA<br />
1<br />
2<br />
C4910<br />
10UF<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402-9<br />
PP3V3_S4_MESA<br />
MESA_BOOST_EN<br />
3.0V MESA<br />
L4901<br />
1.0UH-0.4A-0.636OHM<br />
R4915<br />
0<br />
NOSTUFF<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
R4916<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
Option to feed LDO from 5V in case of dropout issue<br />
0<br />
1 2<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
PP3V3_S4_MESA_SW<br />
1 2<br />
0402<br />
DIDT=TRUE<br />
VOLTAGE=3.3V<br />
MOJAVE_EN_M<br />
B1<br />
A2<br />
B2<br />
A3<br />
C2<br />
SW<br />
VIN<br />
EN_M<br />
EN_S<br />
LDOIN<br />
A1<br />
U4900<br />
LM3638<br />
BGA<br />
PGND<br />
AGND<br />
B3<br />
XW4900<br />
SHORT-0201<br />
1 2<br />
VOUT C3<br />
VOLTAGE=17V<br />
PMID C1 PP17V0_MOJAVE_LDOIN<br />
P16V0_AGND<br />
PP16V0_MESA<br />
1<br />
2<br />
VOLTAGE=0V<br />
C4923<br />
2.2UF<br />
20%<br />
25V<br />
X5R<br />
0402-3<br />
1<br />
2<br />
C4924<br />
2.2UF<br />
20%<br />
25V<br />
X5R<br />
0402-3<br />
1<br />
2<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=16V<br />
C4925<br />
2.2UF<br />
20%<br />
25V<br />
X5R<br />
0402-3<br />
1<br />
2<br />
PP16V0_MESA<br />
C4926<br />
56PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
47<br />
104<br />
EDP:12.5mA<br />
FL4900<br />
80-OHM-25%-500MA<br />
1 2<br />
PP16V0_MESA_CONN<br />
MESA_SPI_MOSI_R<br />
MESA_SPI_CLK_R<br />
MESA_SPI_MISO<br />
104 47 47<br />
0201<br />
1<br />
2<br />
42<br />
42<br />
38<br />
100PF<br />
5%<br />
25V<br />
C0G<br />
0201<br />
IN<br />
IN<br />
OUT<br />
C4927<br />
VOLTAGE=16V<br />
MIN_NECK_WIDTH=0.0520<br />
MIN_LINE_WIDTH=0.0900<br />
R4950<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
R4951<br />
0<br />
56<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R4912<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
PLACE_NEAR=J4900:3MM<br />
MESA_SPI_MOSI_CONN<br />
1<br />
2<br />
MESA_SPI_CLK_CONN<br />
1<br />
MESA_SPI_MISO_CONN<br />
1<br />
C4950<br />
56PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
C4951<br />
56PF<br />
5%<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
C4952<br />
56PF<br />
5%<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
104<br />
ESD_GND<br />
47<br />
104<br />
OUT<br />
OUT<br />
47<br />
MIN_LINE_WIDTH=0.0900<br />
MESA_SNSR_INT<br />
MESA_BOOST_EN<br />
104<br />
SMC_ONOFF_L<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
MESA FLEX CONNECTOR<br />
R4954<br />
680<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R4911<br />
Proto1 Connector for X434/X435 Support<br />
PLUG (516S00115) - X434/ X435 Jumper<br />
Recptacle (516S00203) - X362/X363 MLB<br />
PP<br />
PP<br />
R4953<br />
680<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
PP4900<br />
PP4901<br />
MESA_SNSR_INT_CONN<br />
1<br />
2<br />
MESA_BOOST_EN_CONN<br />
1<br />
2<br />
MENU_KEY_L<br />
1<br />
2<br />
C4953<br />
100PF<br />
5%<br />
25V<br />
C0G<br />
0201<br />
C4954<br />
100PF<br />
5%<br />
25V<br />
C0G<br />
0201<br />
C4955<br />
100PF<br />
5%<br />
25V<br />
C0G<br />
0201<br />
47<br />
104<br />
47<br />
47<br />
104<br />
104<br />
D<br />
C<br />
101<br />
47<br />
PP3V3_S4_MESA<br />
1<br />
2<br />
C4911<br />
1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0402<br />
104 47<br />
PP1V8_MESA<br />
4<br />
3<br />
IN<br />
EN<br />
U4910<br />
NCP160AMX300<br />
XDFN-COMBO<br />
GND<br />
2<br />
5<br />
EPAD<br />
OUT<br />
1<br />
PP3V0_MESA<br />
1<br />
C4916<br />
1UF<br />
10%<br />
2<br />
10V<br />
X5R-CERM<br />
0402<br />
104 47<br />
EDP:100mA<br />
104 VOLTAGE=3.0V<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
47<br />
PP3V0_MESA<br />
1<br />
2<br />
C4920<br />
2.2UF<br />
20%<br />
6.3V<br />
X5R-CERM<br />
0201<br />
1<br />
C4921<br />
2.2UF<br />
C4922<br />
2.2UF<br />
20%<br />
20%<br />
2<br />
6.3V<br />
X5R-CERM 2<br />
6.3V<br />
X5R-CERM<br />
0201<br />
0201<br />
1<br />
FL4910<br />
80-OHM-25%-500MA<br />
1 2<br />
0201<br />
C4928 1<br />
0.1UF<br />
2<br />
10%<br />
10V<br />
X6S-CERM<br />
0201<br />
PP3V0_MESA_CONN<br />
C4929 1<br />
100PF<br />
2<br />
5%<br />
25V<br />
C0G<br />
0201<br />
47<br />
VOLTAGE=3.0V<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
104 47<br />
104 47<br />
104 47<br />
MESA_SPI_MISO_CONN<br />
MESA_SNSR_INT_CONN<br />
MESA_BOOST_EN_CONN<br />
104 47 37 MESA_I2C_SDA<br />
MESA_I2C_SCL<br />
104 47 37<br />
PP3V0_MESA_CONN<br />
J4900<br />
505066-1220<br />
F-ST-SM<br />
Mesa Power Sequencing Requirements<br />
47<br />
14<br />
2<br />
4<br />
6<br />
8<br />
10<br />
12<br />
16<br />
13<br />
1<br />
3<br />
5<br />
7<br />
9<br />
11<br />
15<br />
PP1V8_MESA_CONN<br />
MESA_SPI_MOSI_CONN<br />
MENU_KEY_L<br />
MESA_SPI_CLK_CONN<br />
PP16V0_MESA_CONN<br />
47<br />
47<br />
104<br />
47 104<br />
47<br />
47<br />
104<br />
B<br />
1.8V MESA<br />
Power On: 1V8 -> 3V3 -> 16V0<br />
B<br />
PP1V8_MESA_CONN<br />
47<br />
101<br />
PP3V3_S4_MESA<br />
47<br />
1<br />
2<br />
C4912<br />
1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0402<br />
37<br />
IN<br />
MESA_PWR_EN<br />
U4920<br />
LP5907SNX-1.825<br />
4 VIN<br />
X2SON<br />
VOUT 1<br />
VOLTAGE=1.8V<br />
3 EN<br />
MIN_NECK_WIDTH=0.0520<br />
MIN_LINE_WIDTH=0.0900<br />
GND EPAD<br />
2<br />
5<br />
PP1V8_MESA<br />
1<br />
2<br />
C4914<br />
1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0402<br />
EDP:1.5mA<br />
104 47 37<br />
IN<br />
MESA_I2C_SCL<br />
1<br />
R4920<br />
2.2K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
1<br />
R4921<br />
2.2K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
I2C pullups on same rail as EEPROM VCC<br />
A<br />
PP1V8_MESA<br />
1<br />
C4918<br />
2.2UF<br />
20%<br />
2<br />
6.3V<br />
X5R-CERM<br />
0201<br />
FL4920<br />
80-OHM-25%-500MA<br />
1 2<br />
0201<br />
PP1V8_MESA_CONN<br />
104 47 47<br />
1<br />
2<br />
C4917<br />
100PF<br />
5%<br />
25V<br />
C0G<br />
0201<br />
VOLTAGE=1.8V<br />
MIN_NECK_WIDTH=0.0520<br />
MIN_LINE_WIDTH=0.0900<br />
104 47 37<br />
MESA_I2C_SDA<br />
BOM_COST_GROUP=T151<br />
SYNC_MASTER=J79_ANDREW<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
MESA<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
BI<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
49 OF 145<br />
47 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
D<br />
C<br />
B<br />
13<br />
13<br />
13<br />
13<br />
105 13<br />
13<br />
19<br />
13<br />
13<br />
13<br />
15<br />
14<br />
51<br />
51<br />
51<br />
51<br />
50<br />
50<br />
51<br />
51<br />
50<br />
50<br />
51<br />
51<br />
58<br />
58<br />
58<br />
58<br />
49<br />
50<br />
50<br />
50<br />
50<br />
50<br />
18<br />
50<br />
49<br />
105 49<br />
50<br />
50<br />
50 49<br />
50 49 28<br />
74 49<br />
50 49<br />
50<br />
50<br />
50<br />
94 51 28<br />
50 49<br />
104 74 19 14<br />
92 80 77 74 73 26 19 14<br />
104<br />
104 77 74 43 19 14<br />
104 77 19 14<br />
104 50 49 47<br />
50<br />
50<br />
50<br />
50 36 35<br />
BI<br />
BI<br />
BI<br />
BI<br />
IN<br />
IN<br />
IN<br />
BI<br />
OUT<br />
IN<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
OUT<br />
IN<br />
OUT<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
BI<br />
OUT<br />
BI<br />
OUT<br />
OUT<br />
BI<br />
OUT<br />
IN<br />
IN<br />
IN<br />
IN<br />
BI<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
OUT<br />
IN<br />
OUT<br />
LPC_AD<br />
LPC_AD<br />
LPC_AD<br />
LPC_AD<br />
LPC_CLK24M_SMC<br />
LPC_FRAME_L<br />
SMC_LRESET_L<br />
LPC_SERIRQ<br />
LPC_CLKRUN_L<br />
LPC_PWRDWN_L<br />
SMC_RUNTIME_SCI_L<br />
SMC_WAKE_SCI_L<br />
SMBUS_SMC_0_S0_SCL<br />
SMBUS_SMC_0_S0_SDA<br />
SMBUS_SMC_1_S0_SCL<br />
SMBUS_SMC_1_S0_SDA<br />
SMBUS_SMC_2_S4_SCL<br />
SMBUS_SMC_2_S4_SDA<br />
SMBUS_SMC_3_SCL<br />
SMBUS_SMC_3_SDA<br />
SMBUS_SMC_4_G3H_SCL<br />
SMBUS_SMC_4_G3H_SDA<br />
SMBUS_SMC_5_G3_SCL<br />
SMBUS_SMC_5_G3_SDA<br />
SMC_FAN_0_CTL<br />
SMC_FAN_0_TACH<br />
SMC_FAN_1_CTL<br />
SMC_FAN_1_TACH<br />
SMC_TOPBLK_SWP_L<br />
SMC_SENSOR_PWR_EN<br />
SMC_DEV_SUPPLY_L<br />
SMC_ACTUATOR_DISABLE_L<br />
NC_SMC_GFX_SELF_THROTTLE<br />
NC_SYS_ONEWIRE<br />
SMC_CLK12M_EN<br />
SMC_PCH_SUSACK_L<br />
CPU_PECI_R<br />
SMC_PECI_L<br />
SMC_CHGR_INT_L<br />
NC_SMC_DP_HPD_L<br />
SMC_PME_S4_WAKE_L<br />
SMC_PME_S4_DARK_L<br />
SMC_PMIC_INT_L<br />
SMC_SENSOR_ALERT_L<br />
SMC_VIBE_L<br />
SMC_LID_LEFT<br />
SMC_PCH_SUSWARN_L<br />
SMC_USBC_INT_L<br />
SMC_AUX_OK<br />
PM_SLP_S0_L<br />
PM_SLP_S3_L<br />
PM_SLP_S4_L<br />
PM_SLP_S5_L<br />
SMC_ONOFF_L<br />
WLAN_UART_TX<br />
WLAN_UART_RX<br />
SMC_LID_RIGHT<br />
SMC_WIFI_PWR_EN<br />
(OD)<br />
(OD)<br />
(OD)<br />
(OD)<br />
(OD)<br />
(OD)<br />
(OD)<br />
(OD)<br />
(OD)<br />
(OD)<br />
(OD)<br />
(OD)<br />
(OD)<br />
(OD)<br />
(IPU)<br />
(OD)<br />
(IPD)<br />
(OD)<br />
(OD)<br />
(IPD when sampling)<br />
D10<br />
B13<br />
C11<br />
A13<br />
H10<br />
C12<br />
C13<br />
G10<br />
G11<br />
F10<br />
G12<br />
B11<br />
D13<br />
D12<br />
N4<br />
L5<br />
N10<br />
K8<br />
N9<br />
M9<br />
L9<br />
L8<br />
N5<br />
M5<br />
H13<br />
H11<br />
A12<br />
B12<br />
K4<br />
A9<br />
L12<br />
M12<br />
N13<br />
L11<br />
K3<br />
K2<br />
C6<br />
C7<br />
J10<br />
H12<br />
K6<br />
J11<br />
J12<br />
K7<br />
A7<br />
L6<br />
D2<br />
D1<br />
F1<br />
M6<br />
N6<br />
L7<br />
M7<br />
N7<br />
L3<br />
K5<br />
E13<br />
E12<br />
PL3<br />
PL2<br />
PL1<br />
PL0<br />
PM5<br />
PL4<br />
PL5<br />
PM4<br />
PM2<br />
PM0<br />
PM1<br />
PK5<br />
PB2/I2C0SCL<br />
PB3/I2C0SDA<br />
PA6<br />
PA7<br />
PF6<br />
PF7<br />
PG0<br />
PG1<br />
PG2<br />
PG3<br />
PG6<br />
PG7<br />
PM6<br />
PM7<br />
PK6<br />
PK7<br />
PN2<br />
PN3<br />
PN4<br />
PN5<br />
PN6<br />
PN7<br />
PH2<br />
PH3<br />
PJ7<br />
PJ6<br />
PP0<br />
PP1<br />
PP2<br />
PP3<br />
PP4<br />
PP5<br />
PP6<br />
PP7<br />
PQ0<br />
PQ1<br />
PQ2<br />
PQ3<br />
PQ4<br />
PQ5<br />
PQ6<br />
PQ7<br />
PA0/U0RX<br />
PA1/U0TX<br />
PL7<br />
PL6<br />
U5000<br />
TM4EA231H6ZXRI<br />
BGA<br />
SYM 1 OF 2<br />
OMIT_TABLE<br />
PE3<br />
PE2<br />
PE1<br />
PE0<br />
PD7<br />
PD6<br />
PD5<br />
PD4<br />
PE5<br />
PE4<br />
PB4<br />
PB5<br />
PD3<br />
PD2<br />
PD1<br />
PD0<br />
PK0<br />
PK1<br />
PK2<br />
PK3<br />
PE7<br />
PE6<br />
PN1<br />
PN0<br />
PC7<br />
PC6<br />
PC4<br />
PC5<br />
PJ5<br />
PJ4<br />
PA2/SSI0CLK<br />
PA3/SSI0FSS<br />
PA4/SSI0RX<br />
PA5/SSI0TX<br />
PB0<br />
PB1<br />
PB6<br />
PB7<br />
PF0<br />
PF1<br />
PF2<br />
PF3<br />
PF4<br />
PF5<br />
PG4<br />
PG5<br />
PH0<br />
PH1<br />
PH4<br />
PH5<br />
PH6<br />
PH7<br />
PJ0<br />
PJ1<br />
PJ2<br />
PJ3<br />
PM3<br />
G4<br />
G3<br />
G2<br />
G1<br />
C2<br />
C3<br />
A1<br />
A2<br />
A3<br />
B3<br />
A4<br />
B4<br />
D4<br />
D3<br />
C1<br />
B1<br />
H4<br />
H3<br />
H1<br />
H2<br />
C4<br />
C5<br />
B5<br />
A5<br />
M1<br />
N1<br />
M3<br />
M2<br />
B6<br />
A6<br />
N2<br />
N3<br />
L4<br />
M4<br />
E11<br />
D11<br />
E3<br />
E4<br />
L10<br />
N11<br />
N12<br />
M11<br />
K10<br />
M10<br />
M8<br />
N8<br />
L2<br />
L1<br />
K1<br />
J3<br />
J2<br />
J4<br />
D8<br />
A8<br />
B8<br />
C8<br />
G13<br />
SMC_CPU_HI_ISENSE<br />
SMC_PBUS_VSENSE<br />
SMC_BMON_ISENSE<br />
SMC_DCIN_ISENSE<br />
SMC_DCIN_VSENSE<br />
SMC_CPUGT_ISENSE<br />
SMC_CPU_ISENSE<br />
SMC_OTHER5V_HI_ISENSE<br />
SMC_OTHER3V3_HI_ISENSE<br />
SMC_DDR1V2_ISENSE<br />
SMC_CPUEDRAM_ISENSE<br />
SMC_PCH_ISENSE<br />
SMC_TPAD_ISENSE<br />
SMC_PICCOLO_ISENSE<br />
SMC_SSDNAND_ISENSE<br />
SMC_PCHPRIMCORE_ISENSE<br />
SMC_DDR1V8_ISENSE<br />
SMC_CPUSA_ISENSE<br />
SMC_CPUDDR_ISENSE<br />
SMC_CPUSA_VSENSE<br />
SMC_CPU_VSENSE<br />
SMC_CPUGT_VSENSE<br />
SMC_CPU_IMON_ISENSE<br />
SMC_CPUGT_IMON_ISENSE<br />
CPU_PROCHOT_L<br />
SMC_VCCIO_CPU_DIV2<br />
PM_THRMTRIP_L<br />
SPI_DESCRIPTOR_OVERRIDE_L<br />
CPU_CATERR_L<br />
SMC_BT_PWR_EN<br />
SMC_PM_G2_EN<br />
PM_DSW_PWRGD<br />
SMC_DELAYED_PWRGD<br />
SMC_PROCHOT<br />
SMC_DEBUGPRT_RX_L<br />
SMC_DEBUGPRT_TX_L<br />
PM_RSMRST_L<br />
NC_SMC_GFX_THROTTLE_L<br />
NC_SPI_SMC_MISO<br />
NC_SPI_SMC_MOSI<br />
NC_SPI_SMC_CLK<br />
NC_SPI_SMC_CS_L<br />
S5_PWRGD<br />
PM_PCH_SYS_PWROK<br />
SMC_CBC_ON<br />
NC_SMC_GFX_OVERTEMP<br />
ALL_SYS_PWRGD<br />
SMC_THRMTRIP<br />
PM_PWRBTN_L<br />
PM_SYSRST_L<br />
BKLT_PWM_TCON2MLB<br />
SMC_ADAPTER_EN<br />
SMC_OOB1_D2R_L<br />
SMC_OOB1_R2D_L<br />
SMC_SOCPMU_RESET<br />
NC_SMC_DEBUGPRT_EN_L<br />
PM_BATLOW_L<br />
(IPU)<br />
(IPD)<br />
(OD)<br />
(OD)<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
OUT<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
OUT<br />
IN<br />
BI<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
50<br />
50<br />
50<br />
50<br />
50<br />
50<br />
50<br />
50<br />
50<br />
50<br />
50<br />
50<br />
50<br />
50<br />
50<br />
50<br />
50<br />
50<br />
50<br />
50<br />
50<br />
50<br />
50<br />
50<br />
6<br />
49<br />
6<br />
18<br />
6<br />
35<br />
49<br />
14<br />
49<br />
49<br />
28<br />
28<br />
50<br />
50<br />
77<br />
14<br />
66<br />
50<br />
73<br />
49<br />
17<br />
14<br />
80<br />
49<br />
50<br />
50<br />
41<br />
50<br />
14<br />
49<br />
49<br />
19<br />
74<br />
49<br />
49<br />
73<br />
74<br />
50<br />
17<br />
104<br />
28<br />
67<br />
77<br />
104<br />
104<br />
104<br />
77<br />
94<br />
PP3V3_G3H_SMC_ISNS 49 57 100<br />
BYPASS=U5000.E6::5MM<br />
BYPASS=U5000.F8::5MM<br />
BYPASS=U5000.E6::5MM<br />
BYPASS=U5000.F6::5MM<br />
BYPASS=U5000.G6::5MM<br />
1<br />
2<br />
C5002<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
1<br />
BYPASS=U5000.H6::5MM<br />
BYPASS=U5000.G8::5MM<br />
1<br />
2<br />
C5003<br />
0.1UF<br />
10%<br />
2<br />
10V<br />
X5R-CERM<br />
0201<br />
C5007<br />
0.1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
1<br />
C5004<br />
0.1UF<br />
10%<br />
2<br />
10V<br />
X5R-CERM<br />
0201<br />
1<br />
C5008<br />
0.1UF<br />
BYPASS=U5000.H7::5MM<br />
C5009<br />
0.1UF<br />
10%<br />
10%<br />
2<br />
10V<br />
X5R-CERM 2<br />
10V<br />
X5R-CERM<br />
0201<br />
0201<br />
1<br />
2<br />
1<br />
C5005<br />
0.1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
1<br />
2<br />
C5006<br />
0.1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
80<br />
49<br />
49<br />
18<br />
BUF_SMC_RESET_L<br />
SMC_WIFI_EVENT_L<br />
SMC_WAKE_L<br />
NC_SMC_HIB_L<br />
NO_TEST=1<br />
SMC_CLK32K<br />
NC_SMC_XOSC1<br />
NO_TEST=1<br />
SYSCLK_CLK12M_SMC<br />
NC_SMC_OSC1<br />
NO_TEST=1<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.2V<br />
(OD)<br />
F11<br />
A11<br />
M13<br />
L13<br />
K11<br />
K12<br />
F13<br />
F12<br />
K13<br />
E6<br />
E7<br />
F6<br />
F7<br />
F8<br />
G6<br />
G7<br />
G8<br />
H6<br />
H7<br />
D7<br />
H9<br />
J1<br />
J9<br />
J13<br />
U5000<br />
TM4EA231H6ZXRI<br />
BGA<br />
OMIT_TABLE<br />
PP3V3_G3H_SMC_VDDA<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
B9<br />
C9<br />
C10<br />
B10<br />
B7<br />
F3<br />
E1<br />
E2<br />
F2<br />
F4<br />
A10<br />
D5<br />
D6<br />
D9<br />
E5<br />
E8<br />
E9<br />
E10<br />
F5<br />
F9<br />
G5<br />
G9<br />
H5<br />
H8<br />
J5<br />
J6<br />
J7<br />
J8<br />
K9<br />
SMC_TCK<br />
SMC_TMS<br />
SMC_TDO<br />
SMC_TDI<br />
PP3V0_G3H_AVREF_SMC<br />
GND_SMC_AVSS<br />
BYPASS=U5000.H9::5MM<br />
BYPASS=U5000.H9::5MM<br />
BYPASS=U5000.J1::5MM<br />
BYPASS=U5000.J13::5MM<br />
BYPASS=U5000.D7::5MM<br />
BYPASS=U5000.D7::5MM<br />
BYPASS=U5000.J9::5MM<br />
BYPASS=U5000.J9::5MM<br />
1<br />
IN<br />
BI<br />
IN<br />
IN<br />
C5010<br />
1.0UF<br />
20%<br />
2<br />
6.3V<br />
X5R<br />
0201-1<br />
1<br />
R5002<br />
1M 5%<br />
1/20W<br />
MF<br />
2 201<br />
1<br />
2<br />
C5017<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
1<br />
2<br />
C5015<br />
0.1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
L5001<br />
30-OHM-1.7A<br />
1 2<br />
1<br />
0402<br />
C5016<br />
0.1UF<br />
10%<br />
2<br />
10V<br />
X5R-CERM<br />
0201<br />
SYM 2 OF 2<br />
1<br />
VREFA+<br />
VREFA-<br />
GNDA<br />
GNDA<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
C5014<br />
1.0UF<br />
20%<br />
2<br />
6.3V<br />
X5R<br />
0201-1<br />
NC<br />
1<br />
2<br />
49<br />
55<br />
54<br />
53<br />
52<br />
50<br />
49<br />
C5012<br />
0.1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
1<br />
2<br />
C5013<br />
0.1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
49<br />
49<br />
49<br />
49<br />
59<br />
59<br />
1<br />
2<br />
1<br />
C5011<br />
0.1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
1<br />
2<br />
C5020<br />
0.01UF<br />
C5001<br />
0.1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
XW5000<br />
2<br />
SM<br />
PLACE_NEAR=U5000.A10:4MM<br />
10%<br />
20%<br />
14 17 77<br />
VDDS<br />
GND<br />
2<br />
10V<br />
6.3V<br />
X5R-CERM<br />
2 X5R<br />
50<br />
VDDS<br />
GND<br />
0201<br />
0201-1<br />
VDDS<br />
GND<br />
50<br />
BYPASS=U5000.E1:F2:1MM<br />
GND<br />
BYPASS=U5000.E1:F2:1MM<br />
50<br />
PP1V2_G3H_SMC_VDDC<br />
GND<br />
RST*<br />
PK4<br />
WAKE*<br />
HIB*<br />
XOSC0<br />
XOSC1<br />
OSC0<br />
OSC1<br />
VBAT<br />
VDDS<br />
VDDS<br />
VDDS<br />
VDDS<br />
VDDS<br />
VDDS<br />
VDDS<br />
VDDC<br />
VDDC<br />
VDDC<br />
VDDC<br />
VDDC<br />
PC0/SWCLK/TCK<br />
PC1/SWDIO/TMS<br />
PC3/SWO/TDO<br />
PC2/TDI<br />
NC<br />
VDDA<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
1<br />
1<br />
C5021<br />
1.0UF<br />
C<br />
B<br />
A<br />
NOTE:<br />
SMS Interrupt can be active high or low, rename net accordingly.<br />
If SMS interrupt is not used, pull up to SMC rail.<br />
NOTE:<br />
Unused pins have "SMC_Pxx" names. Unused<br />
pins designed as outputs can be left floating,<br />
those designated as inputs require pull-ups.<br />
SYNC_MASTER=J79_JACK<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
SMC<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
50 OF 145<br />
48 OF 119<br />
SYNC_DATE=04/11/2016<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
100<br />
PP3V3_G3H<br />
C5165<br />
1.0UF<br />
1 2<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
SMC AVREF Supply<br />
5<br />
IN<br />
U5165<br />
REF3330-COMBO<br />
QFN<br />
CRITICAL<br />
GND<br />
4<br />
OUT<br />
NC0<br />
NC1<br />
NC2<br />
NC3<br />
NC4<br />
8<br />
1<br />
2<br />
3<br />
6<br />
7<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
C5166 1<br />
10UF<br />
2<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402-1<br />
PP3V0_G3H_AVREF_SMC<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.0V<br />
1<br />
2<br />
C5167<br />
0.1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
GND_SMC_AVSS<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=0V<br />
48<br />
50<br />
52<br />
48<br />
53<br />
54<br />
55<br />
67 48 6<br />
48 6<br />
BI<br />
OUT<br />
CPU_PROCHOT_L<br />
PM_THRMTRIP_L<br />
PROCHOT/THRMTRIP Support<br />
R5158<br />
100<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
PLACE_NEAR=Q5159.6:5MM<br />
R5159<br />
100<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
PLACE_NEAR=Q5159.3:5MM<br />
SMC_PROCHOT_L<br />
SMC_THRMTRIP_L<br />
6<br />
1<br />
3<br />
D<br />
S<br />
D<br />
Q5159<br />
DMN5L06VK-7<br />
SOT563<br />
VER 3<br />
G<br />
2<br />
SMC_PROCHOT<br />
Q5159<br />
DMN5L06VK-7<br />
SOT563<br />
VER 3<br />
IN<br />
48<br />
105 48<br />
IN<br />
From SMC<br />
PECI Support<br />
SMC_PECI_L<br />
CRITICAL<br />
DMN32D2LFB4<br />
DFN1006H4-3<br />
CPU_PECI_R<br />
To SMC<br />
NOSTUFF<br />
C5134 1<br />
47PF<br />
5%<br />
25V<br />
2<br />
C0G<br />
0201<br />
PLACE_NEAR=Q5150.2:5MM<br />
Q5150 D 3<br />
SYM_VER_2<br />
1<br />
G<br />
S<br />
PP1V0_S3 49 101<br />
2<br />
R5134<br />
43<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
CPU_PECI<br />
48 OUT<br />
BI 6<br />
1<br />
R5151<br />
330<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
From/To CPU/PCH<br />
D<br />
4<br />
S<br />
G<br />
5<br />
SMC_THRMTRIP<br />
IN<br />
48<br />
49<br />
C<br />
C<br />
B<br />
48<br />
IN<br />
SMC_TOPBLK_SWP_L<br />
Top-Block Swap<br />
R5182 1<br />
1K<br />
5%<br />
1/20W<br />
201<br />
MF<br />
2<br />
PP3V3_S0 101<br />
R5183<br />
1K<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
PCH_STRP_TOPBLK_SWP_L<br />
OUT<br />
13<br />
15<br />
IN<br />
50<br />
SMC_AUX_OK<br />
PM_CLK32K_SUSCLK_R<br />
R5112<br />
22<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
Place near CPU<br />
SMC_AUX_OK 48 49 50<br />
MAKE_BASE=TRUE<br />
SMC_CLK32K<br />
OUT 48<br />
50 48<br />
50 48 28<br />
48<br />
74 48<br />
104 50 48 47<br />
50 48<br />
104 50 43 42<br />
101<br />
49<br />
48<br />
PP1V0_S3<br />
SMC_VCCIO_CPU_DIV2<br />
SMC_PME_S4_WAKE_L<br />
SMC_PME_S4_DARK_L<br />
SMC_WIFI_EVENT_L<br />
SMC_PMIC_INT_L<br />
SMC_ONOFF_L<br />
SMC_SENSOR_ALERT_L<br />
SMC_LID<br />
1<br />
R5197<br />
100K<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
1<br />
R5196<br />
100K<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
100 57 48 PP3V3_G3H_SMC_ISNS<br />
101 50 PP3V3_S4<br />
101 PP3V3_S0<br />
R5166 100K 1 2<br />
R5167 100K 1 2<br />
R5168 100K 1 2<br />
R5169 100K 1 2<br />
R5170 10K 1 2<br />
R5172 10K 1 2<br />
330K<br />
R5171 1 2<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
B<br />
104 48 28<br />
104 48 28<br />
59 48<br />
48<br />
48<br />
59 48<br />
50 49 48<br />
48<br />
49 48<br />
48<br />
77 74 48<br />
SMC_DEBUGPRT_TX_L<br />
SMC_DEBUGPRT_RX_L<br />
SMC_TMS NOSTUFF<br />
SMC_TDO NOSTUFF<br />
SMC_TDI NOSTUFF<br />
SMC_TCK NOSTUFF<br />
SMC_AUX_OK NOSTUFF<br />
SMC_ADAPTER_EN<br />
SMC_THRMTRIP<br />
SMC_DELAYED_PWRGD<br />
SMC_PM_G2_EN<br />
R5175 1 2<br />
20K<br />
R5176 20K 1 2<br />
R5177 10K 1 2<br />
R5178 10K 1 2<br />
R5179 10K 1 2<br />
R5180 10K 1 2<br />
R5187 100K 1 2<br />
R5185 100K 1 2<br />
R5186 10K 1 2<br />
R5191 100K 1 2<br />
R5192 100K 1 2<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
5% 1/20W MF 201<br />
A<br />
BOM_COST_GROUP=SMC<br />
SYNC_MASTER=J79_JACK<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
SMC Shared Support<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
SYNC_DATE=04/14/2016<br />
dvt-fab09-0<br />
51 OF 145<br />
49 OF 119<br />
SIZE<br />
D<br />
A
TABLE_BOMGROUP_HEAD<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_HEAD<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
TABLE_BOMGROUP_ITEM<br />
D<br />
C<br />
B<br />
A<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
50<br />
50<br />
49<br />
SMC12 ADC Assignments<br />
SMC12 Pin Assignments<br />
NC_SMC_DEBUGPRT_EN_L<br />
48<br />
48<br />
48<br />
SMC_CPU_HI_ISENSE<br />
SMC_PBUS_VSENSE<br />
SMC_BMON_ISENSE<br />
SMC_DCIN_ISENSE<br />
SMC_DCIN_VSENSE<br />
SMC_CPUGT_ISENSE<br />
SMC_CPU_ISENSE<br />
SMC_OTHER5V_HI_ISENSE<br />
SMC_OTHER3V3_HI_ISENSE<br />
SMC_DDR1V2_ISENSE<br />
SMC_CPUEDRAM_ISENSE<br />
SMC_PCH_ISENSE<br />
SMC_TPAD_ISENSE<br />
SMC_PICCOLO_ISENSE<br />
SMC_SSDNAND_ISENSE<br />
SMC_PCHPRIMCORE_ISENSE<br />
SMC_DDR1V8_ISENSE<br />
SMC_CPUSA_ISENSE<br />
SMC_CPUGT_VSENSE<br />
SMC_CPU_IMON_ISENSE<br />
NC_SMC_GFX_THROTTLE_L<br />
NC_SMC_GFX_OVERTEMP<br />
48 NC_SMC_GFX_SELF_THROTTLE<br />
48<br />
SMC_CPUDDR_ISENSE<br />
SMC_CPUSA_VSENSE<br />
SMC_CPU_VSENSE<br />
SMC_CPUGT_IMON_ISENSE<br />
NC_SMC_DP_HPD_L<br />
NC_SYS_ONEWIRE<br />
SMC_LID_RIGHT<br />
NC_SPI_SMC_MISO<br />
NC_SPI_SMC_MOSI<br />
NC_SPI_SMC_CLK<br />
NC_SPI_SMC_CS_L<br />
SMC_VIBE_L<br />
MAKE_BASE=TRUE<br />
SMC_PCH_SUSWARN_L<br />
MAKE_BASE=TRUE<br />
SMC_PCH_SUSACK_L<br />
MAKE_BASE=TRUE<br />
SMC_SENSOR_PWR_EN<br />
MAKE_BASE=TRUE<br />
WLAN_UART_RX<br />
WLAN_UART_TX<br />
SMC_AUX_OK<br />
MAKE_BASE=TRUE<br />
PM_PWRBTN_L<br />
MAKE_BASE=TRUE<br />
SMC_AUX_OK<br />
MAKE_BASE=TRUE<br />
SMBUS_SMC_4_G3H_SCL<br />
MAKE_BASE=TRUE<br />
SMBUS_SMC_4_G3H_SDA<br />
MAKE_BASE=TRUE<br />
SMBUS_SMC_2_S4_SCL<br />
MAKE_BASE=TRUE<br />
SMBUS_SMC_2_S4_SDA<br />
MAKE_BASE=TRUE<br />
SMC_OOB1_D2R_L<br />
MAKE_BASE=TRUE<br />
SMC_OOB1_R2D_L<br />
MAKE_BASE=TRUE<br />
SMC_ACTUATOR_DISABLE_L<br />
MAKE_BASE=TRUE<br />
SMC_CHGR_INT_L<br />
MAKE_BASE=TRUE<br />
SMC_CPU_HI_ISENSE<br />
MAKE_BASE=TRUE<br />
SMC_PBUS_VSENSE<br />
MAKE_BASE=TRUE<br />
SMC_BMON_ISENSE<br />
MAKE_BASE=TRUE<br />
SMC_DCIN_ISENSE<br />
MAKE_BASE=TRUE<br />
SMC_DCIN_VSENSE<br />
MAKE_BASE=TRUE<br />
SMC_CPUGT_ISENSE<br />
MAKE_BASE=TRUE<br />
SMC_CPU_ISENSE<br />
MAKE_BASE=TRUE<br />
SMC_OTHER5V_HI_ISENSE<br />
MAKE_BASE=TRUE<br />
SMC_OTHER3V3_HI_ISENSE<br />
MAKE_BASE=TRUE<br />
SMC_DDR1V2_ISENSE<br />
MAKE_BASE=TRUE<br />
SMC_CPUEDRAM_ISENSE<br />
MAKE_BASE=TRUE<br />
SMC_PCH_ISENSE<br />
MAKE_BASE=TRUE<br />
SMC_TPAD_ISENSE<br />
MAKE_BASE=TRUE<br />
SMC_PICCOLO_ISENSE<br />
MAKE_BASE=TRUE<br />
SMC_SSDNAND_ISENSE<br />
MAKE_BASE=TRUE<br />
SMC_PCHPRIMCORE_ISENSE<br />
MAKE_BASE=TRUE<br />
SMC_DDR1V8_ISENSE<br />
MAKE_BASE=TRUE<br />
SMC_CPUSA_ISENSE<br />
MAKE_BASE=TRUE<br />
SMC_CPUDDR_ISENSE<br />
MAKE_BASE=TRUE<br />
SMC_CPUSA_VSENSE<br />
MAKE_BASE=TRUE<br />
SMC_CPU_VSENSE<br />
MAKE_BASE=TRUE<br />
SMC_CPUGT_VSENSE<br />
MAKE_BASE=TRUE<br />
SMC_CPU_IMON_ISENSE<br />
MAKE_BASE=TRUE<br />
SMC_CPUGT_IMON_ISENSE<br />
MAKE_BASE=TRUE<br />
NC_SMC_GFX_THROTTLE_L<br />
MAKE_BASE=TRUE<br />
NC_SMC_GFX_OVERTEMP<br />
MAKE_BASE=TRUE<br />
NC_SMC_DP_HPD_L<br />
MAKE_BASE=TRUE<br />
SMC_LID_RIGHT<br />
MAKE_BASE=TRUE<br />
NC_SPI_SMC_CLK<br />
NC_SPI_SMC_CS_L<br />
NO_TEST=1<br />
SMC_VIBE_L 43<br />
SMC_PCH_SUSWARN_L<br />
SMC_PCH_SUSACK_L<br />
NO_TEST=1<br />
NO_TEST=1<br />
NC_SMC_GFX_SELF_THROTTLE<br />
MAKE_BASE=TRUE<br />
NC_SYS_ONEWIRE<br />
MAKE_BASE=TRUE<br />
NC_SMC_DEBUGPRT_EN_L<br />
MAKE_BASE=TRUE<br />
NC_SPI_SMC_MISO<br />
NC_SPI_SMC_MOSI<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
48 OUT<br />
IN 14<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
48<br />
8<br />
50 48<br />
66<br />
48 17<br />
48<br />
48<br />
51<br />
51<br />
51<br />
51<br />
48<br />
48<br />
7<br />
SMC_SENSOR_PWR_EN 78<br />
SMC_SENSOR_PWR_EN 52<br />
WLAN_UART_RX<br />
MAKE_BASE=TRUE<br />
WLAN_UART_TX<br />
MAKE_BASE=TRUE<br />
OUT<br />
SMC_AUX_OK 49<br />
PM_PWRBTN_L 14<br />
SMC_AUX_OK 52<br />
SMBUS_SMC_4_G3H_SCL 48<br />
SMBUS_SMC_4_G3H_SDA 48<br />
SMBUS_SMC_2_S4_SCL 48<br />
SMBUS_SMC_2_S4_SDA 48<br />
SMC_OOB1_D2R_L 88<br />
SMC_OOB1_R2D_L 88<br />
SMC_ACTUATOR_DISABLE_L 43 104<br />
SMC_CHGR_INT_L 66<br />
14<br />
50<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
104 43<br />
104 50 49 48 47<br />
35<br />
35<br />
52<br />
52<br />
52<br />
52<br />
52<br />
55<br />
53<br />
52<br />
52<br />
53<br />
55<br />
53<br />
52<br />
55<br />
55<br />
55<br />
55<br />
55<br />
53<br />
55<br />
54<br />
54<br />
54<br />
54<br />
50<br />
50<br />
IN<br />
IN<br />
104 43<br />
Debug Power "Buttons"<br />
53<br />
56<br />
56<br />
56<br />
56<br />
56<br />
IN<br />
35<br />
Thermal Alerts<br />
SMC_ONOFF_L<br />
HALL_SENSOR_LEFT<br />
PLACE_SIDE=TOP<br />
SILK_PART=PWR_BTN<br />
CRITICAL<br />
SMC_CPUHI_COMP_ALERT_L<br />
CPUTHMSNS_THM_L<br />
CPUTHMSNS_ALERT_L<br />
TBTTHMSNS_THM_L<br />
HALL_SENSOR_RIGHT<br />
TBTTHMSNS_ALERT_L<br />
TBTTHMSNS_THM_T_L<br />
TBTTHMSNS_ALERT_T_L<br />
SMC_LSOC_RST_L<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
6<br />
DEBUG_BUTTON<br />
R5226<br />
SOX-152HNT<br />
SM<br />
1 2<br />
PLACE_SIDE=BOTTOM<br />
SILK_PART=PWR_BTN<br />
CRITICAL<br />
R5225<br />
SOX-152HNT<br />
SM<br />
1 2<br />
DEBUG_BUTTON<br />
1<br />
R5258<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
S4 SMC Wake Sources<br />
SMC_PME_S4_WAKE_L<br />
SMC_PME_S4_DARK_L<br />
48<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
SMC_ONOFF_L<br />
1<br />
2<br />
R5251<br />
1 2<br />
R5261<br />
1 2<br />
02<br />
100<br />
50<br />
SMC_DEV_SUPPLY_L<br />
5<br />
3<br />
R5216<br />
100<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R5220<br />
100<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R5221<br />
100<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
C5256 1<br />
0.1UF<br />
2<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
R5210<br />
100<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
PP3V3_G3H<br />
SMC_SENSOR_ALERT_L<br />
PP3V3_G3H 43 100 104<br />
BYPASS=U5256.5::5MM<br />
SN74LVC1G02<br />
SOT553-5<br />
4 SMC_4FINGERS_RST<br />
U5256<br />
CRITICAL<br />
<br />
OUT<br />
47<br />
NOSTUFF<br />
R5217<br />
100<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R5211<br />
100<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
48<br />
R5214<br />
100<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
49<br />
R5259<br />
0<br />
50<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
5<br />
104<br />
BYPASS=U5255.6::5MM<br />
C5255 1<br />
0.1UF<br />
2<br />
CPUTHRM_THRM:SMC<br />
CPUTHRM_ALRT:SMC<br />
TBTTHRM_THRM:SMC<br />
TBTTHRM_ALRT:SMC<br />
TBTTHRM_THRM:SMC<br />
TBTTHRM_ALRT:SMC<br />
SMC_LID_LEFT_R<br />
2<br />
1<br />
NC<br />
5<br />
NC<br />
6<br />
3<br />
OUT<br />
Debug RESET "Buttons"<br />
66<br />
U5255<br />
74LVC1G32<br />
SOT891<br />
4 SMC_LID_R<br />
CRITICAL<br />
TP_SMC_DEV_SUPPLY_L<br />
DEBUG_BUTTON<br />
PLACE_SIDE=BOTTOM<br />
SILK_PART=RESET_BTN<br />
CRITICAL<br />
SW5227<br />
SOX-152HNT<br />
SM<br />
1 2<br />
R5256<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
48<br />
49<br />
R5255<br />
10K<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
SMC_RESET_L<br />
Specify one of these BOM GROUPs.<br />
Specify one of these BOM GROUPs.<br />
Hall Effect Pads - Left<br />
Hall Effect Pads - Right<br />
Requires EMC1412-1 or EMC1412-2 instead of EMC1412-A, new APN needs to be created.<br />
SMC_PME_S4_WAKE_L<br />
MAKE_BASE=TRUE<br />
SMC_PME_S4_DARK_L<br />
MAKE_BASE=TRUE<br />
SMC_LID_LEFT<br />
NOSTUFF<br />
1<br />
R5257<br />
2<br />
0<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
SMC_LID<br />
SMC_LID_RIGHT<br />
104<br />
50<br />
CPUTHRM:BOTH<br />
CPUTHRM:THRM<br />
CPUTHRM:ALRT<br />
CPUTHRM:NONE<br />
TBTTHRM:BOTH<br />
TBTTHRM:THRM<br />
TBTTHRM:ALRT<br />
TBTTHRM:NONE<br />
50<br />
48<br />
42<br />
59<br />
43<br />
66<br />
49<br />
80<br />
104<br />
104<br />
48<br />
28<br />
49<br />
48<br />
49<br />
SMC_WIFI_PWR_EN<br />
SMC_SENSOR_PWR_EN<br />
SMC_RESET_L<br />
GND_SMC_AVSS<br />
AMR-MLB-X502<br />
8<br />
7<br />
6<br />
5<br />
OMIT_TABLE<br />
J5260<br />
AMR-MLB-X502<br />
8<br />
7<br />
6<br />
5<br />
J5250<br />
SM<br />
SM<br />
OMIT_TABLE<br />
50<br />
50<br />
1<br />
2<br />
3<br />
4<br />
1<br />
2<br />
3<br />
4<br />
48<br />
48<br />
HALL_SENSOR_LEFT<br />
PP3V3_G3H 50 100<br />
HALL_SENSOR_RIGHT<br />
PP3V3_G3H 50 100<br />
677-04255 2 SUBASSY (T&R) PCBA,HES INTERPOSER,X502<br />
J5250, J5260 CRITICAL<br />
NOSTUFF<br />
C5270 1<br />
1000PF<br />
10%<br />
16V<br />
2<br />
X7R-CERM<br />
0201<br />
48 36 35<br />
50 48<br />
CPUTHRM_THRM:SMC,CPUTHRM_ALRT:SMC<br />
CPUTHRM_THRM:SMC,CPUTHRM_ALRT:PU<br />
CPUTHRM_ALRT:SMC<br />
CPUTHRM_ALRT:PU<br />
TBTTHRM_THRM:SMC,TBTTHRM_ALRT:SMC<br />
TBTTHRM_THRM:SMC,TBTTHRM_ALRT:PU<br />
TBTTHRM_THRM:PU,TBTTHRM_ALRT:SMC<br />
TBTTHRM_THRM:PU,TBTTHRM_ALRT:PU<br />
50<br />
48<br />
59<br />
49<br />
66<br />
52<br />
80<br />
53<br />
WLAN_UART_RX<br />
WLAN_UART_TX<br />
104<br />
54<br />
55<br />
BOM_COST_GROUP=SMC<br />
2 1<br />
1<br />
2<br />
1<br />
SYNC_MASTER=J79_JACK<br />
1000PF<br />
10%<br />
16V<br />
X7R-1<br />
0201<br />
101<br />
NOSTUFF<br />
C5260<br />
1000PF<br />
10%<br />
2<br />
16V<br />
X7R-1<br />
0201<br />
10K<br />
100K<br />
NOSTUFF<br />
C5250<br />
49<br />
R5273<br />
1 2<br />
1 2<br />
R5274<br />
R5295 10K 1 2<br />
R5294 10K 1 2<br />
50<br />
50<br />
PP3V3_S4<br />
5%<br />
1/20W<br />
MF<br />
5% 1/20W MF<br />
5% 1/20W<br />
201<br />
201<br />
MF 201<br />
5% 1/20W MF 201<br />
PAGE_TITLE=SMC Project Support<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
OUT<br />
4<br />
OUT<br />
BOM GROUP<br />
BOM GROUP<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
3<br />
PART NUMBER QTY DESCRIPTION<br />
REFERENCE DES CRITICAL BOM OPTION<br />
BOM OPTIONS<br />
BOM OPTIONS<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
52 OF 145<br />
50 OF 119<br />
SYNC_DATE=04/11/2016<br />
SIZE<br />
D<br />
D<br />
C<br />
B<br />
A
SYNC_MASTER=J79_JACK<br />
SYNC_DATE=03/31/2016<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
LYNX POINT LP S0 "SMBus 0" Connections<br />
SMC SMBus "0" S0 Connections<br />
SMC SMBus "5" G3H Connections<br />
101<br />
51<br />
PP3V3_S0<br />
101 PP3V3_S0<br />
100 PP3V3_G3H<br />
D<br />
13<br />
13<br />
LYNX POINT LP<br />
U0500<br />
(MASTER)<br />
SMBUS_PCH_CLK<br />
MAKE_BASE=TRUE<br />
SMBUS_PCH_DATA<br />
MAKE_BASE=TRUE<br />
R5300 1<br />
1K 5%<br />
1/20W<br />
MF<br />
201 2<br />
1<br />
R5301<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
48<br />
48<br />
SMC<br />
U5000<br />
(MASTER)<br />
SMBUS_SMC_0_S0_SCL<br />
MAKE_BASE=TRUE<br />
SMBUS_SMC_0_S0_SDA<br />
MAKE_BASE=TRUE<br />
R5350 1<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
201 2<br />
1<br />
R5351<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
Internal DP<br />
J8500<br />
(0x10-0x1F)<br />
SMBUS_SMC_0_S0_SCL 80 104<br />
SMBUS_SMC_0_S0_SDA 80 104<br />
48<br />
48<br />
SMC<br />
U5000<br />
(MASTER)<br />
SMBUS_SMC_5_G3_SCL<br />
MAKE_BASE=TRUE<br />
SMBUS_SMC_5_G3_SDA<br />
MAKE_BASE=TRUE<br />
R5380 1<br />
2.0K<br />
5%<br />
1/20W<br />
MF<br />
201 2<br />
1<br />
R5381<br />
2.0K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
Battery Charger<br />
ISL6259 - U7000<br />
(Write: 0x12 Read: 0x13)<br />
SMBUS_SMC_5_G3_SCL 66<br />
SMBUS_SMC_5_G3_SDA 66<br />
D<br />
ACE I2C Interrupt<br />
SMC SMBus "2" S4 Connections<br />
74<br />
Banjo<br />
U7800<br />
(Write: 0x68 Read: 0x69)<br />
SMBUS_SMC_5_G3_SCL<br />
SMBUS_SMC_5_G3_SDA<br />
Battery<br />
J6951<br />
(Write: 0x16 Read:0x17)<br />
SMBUS_SMC_5_G3_SCL 65 104<br />
SMBUS_SMC_5_G3_SDA 65 104<br />
C<br />
101<br />
51<br />
PP3V3_S4<br />
SMC<br />
(MASTER)<br />
SMBUS_SMC_2_S4_SCL<br />
SMBUS_SMC_2_S4_SDA<br />
101<br />
51<br />
PP3V3_S4<br />
Berkelium<br />
U4200<br />
1K<br />
1K<br />
U5000 5%<br />
5%<br />
1/20W<br />
1/20W<br />
(Write: 0x78 Read: 0x79)<br />
SMBUS_SMC_2_S4_SCL<br />
SMBUS_SMC_2_S4_SDA<br />
LOADISNS<br />
1<br />
C5372<br />
R5372 1 0.1UF<br />
10%<br />
100K<br />
2<br />
6.3V<br />
5%<br />
CERM-X5R<br />
1/20W<br />
0201<br />
MF<br />
LOADISNS<br />
201 2<br />
BYPASS=U5372.1::5MM<br />
SMBUS_2_OE<br />
51 50<br />
51 50<br />
51 50<br />
51 50<br />
5<br />
2<br />
3<br />
1<br />
OE<br />
A1<br />
A2<br />
VCCA<br />
NO_XNET_CONNECTION=1<br />
R5370 1 R5371 1<br />
MF<br />
MF<br />
201 2<br />
201 2<br />
NO_XNET_CONNECTION=1<br />
U5372<br />
TXS0102DQE<br />
X2SON-COMBO<br />
CRITICAL<br />
LOADISNS<br />
GND<br />
8<br />
VCCB<br />
B1<br />
B2<br />
PP5V_S4SW_ISNS 55 101<br />
1<br />
2<br />
7<br />
6<br />
C5373<br />
0.1UF<br />
10%<br />
10V<br />
X5R-CERM LOADISNS<br />
0201 BYPASS=U5372.8::3MM<br />
SMBUS_2_SCL_Q<br />
MAKE_BASE=TRUE<br />
CKPLUS_WAIVE=I2C_PULLUP<br />
SMBUS_SMC_2_S4_SCL 41<br />
SMBUS_SMC_2_S4_SDA 41<br />
EADC1<br />
U5700<br />
(Write: 0x10 Read: 0x11)<br />
SMBUS_2_SCL_Q 55<br />
SMBUS_2_SDA_Q 55<br />
EADC2<br />
U5710<br />
(Write: 0x12 Read: 0x13)<br />
SMC<br />
U5000<br />
(MASTER)<br />
Trackpad<br />
J4501<br />
(Write: 0x98 Read: 0x99)<br />
104<br />
48<br />
48<br />
43<br />
SMBUS_SMC_3_SCL<br />
MAKE_BASE=TRUE<br />
SMBUS_SMC_3_SDA<br />
MAKE_BASE=TRUE<br />
SMBUS_SMC_3_SCL<br />
SMBUS_SMC_3_SDA<br />
SMC SMBus "3" S0 Connections<br />
101 PP3V3_S0<br />
R5390 1<br />
2.0K 5%<br />
1/20W<br />
MF<br />
201 2<br />
1<br />
R5391<br />
2.0K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
X100 Temp<br />
HPA00330AI: U5<strong>820</strong><br />
(Write: 0x92 Read: 0x93)<br />
SMBUS_SMC_3_SCL 56<br />
SMBUS_SMC_3_SDA 56<br />
TBT & Airflow Left<br />
TMP461: U5850<br />
(Write: 0x90 Read: 0x91)<br />
SMBUS_SMC_3_SCL 56<br />
SMBUS_SMC_3_SDA 56<br />
C<br />
4<br />
SMBUS_2_SDA_Q<br />
MAKE_BASE=TRUE<br />
CKPLUS_WAIVE=I2C_PULLUP<br />
SMBUS_2_SCL_Q 55<br />
SMBUS_2_SDA_Q 55<br />
TBT & Airflow Right<br />
TMP461: U5860<br />
(Write: 0x96 Read: 0x97)<br />
SMBUS_SMC_3_SCL 56<br />
SMBUS_SMC_3_SDA 56<br />
B<br />
LYNX POINT LP S0 "SMLink 0" Connections<br />
100 PP3V3_G3H<br />
SMC SMBUS "4" G3H CONNECTIONS<br />
B<br />
13<br />
13<br />
LYNX POINT LP<br />
U0500<br />
(MASTER)<br />
SML_PCH_0_CLK<br />
MAKE_BASE=TRUE<br />
SML_PCH_0_DATA<br />
MAKE_BASE=TRUE<br />
101<br />
51<br />
PP3V3_S0<br />
R5310 1<br />
8.2K<br />
5%<br />
1/20W<br />
201<br />
MF<br />
2<br />
1<br />
R5311<br />
8.2K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
LYNX POINT LP S0 "SMLink 1" Connections<br />
48<br />
48<br />
SMC<br />
U5000<br />
(MASTER)<br />
SMBUS_SMC_1_S0_SCL<br />
MAKE_BASE=TRUE<br />
SMBUS_SMC_1_S0_SDA<br />
MAKE_BASE=TRUE<br />
SMC SMBus "1" S0 Connections<br />
101 PP3V3_S0<br />
R5360 1<br />
2.0K<br />
5%<br />
1/20W<br />
MF<br />
201 2<br />
1<br />
R5361<br />
2.0K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
CPU, Mem,<br />
Finstack Left, Right<br />
TMP513A: U5870<br />
(Write: 0xB8 Read: 0xB9)<br />
SMBUS_SMC_1_S0_SCL 56<br />
SMBUS_SMC_1_S0_SDA 56<br />
50<br />
50<br />
28<br />
94 48<br />
SMC<br />
U5000<br />
(MASTER)<br />
Pri ACE<br />
UC400 - ADDR: 0X20<br />
(Write: 0x40 Read: 0x41)<br />
SMBUS_SMC_4_G3H_SCL<br />
94<br />
94<br />
SMBUS_SMC_4_G3H_SCL<br />
MAKE_BASE=TRUE<br />
SMBUS_SMC_4_G3H_SDA<br />
MAKE_BASE=TRUE<br />
SMC_USBC_INT_L<br />
MAKE_BASE=TRUE<br />
SMBUS_SMC_4_G3H_SDA<br />
1<br />
R5322<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
1<br />
R5320<br />
2.0K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
1<br />
R5321<br />
2.0K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
USB-C PORT CONTROLLER XA<br />
U3100 - ADDR: 0X38<br />
(WRITE: 0X70 READ: 0X71)<br />
SMBUS_SMC_4_G3H_SCL 28<br />
SMBUS_SMC_4_G3H_SDA 28<br />
SMC_USBC_INT_L 29<br />
USB-C PORT CONTROLLER XB<br />
U3200 - ADDR: 0X3F<br />
(WRITE: 0X7E READ: 0X7F)<br />
SMBUS_SMC_4_G3H_SCL 28<br />
SMBUS_SMC_4_G3H_SDA 28<br />
95<br />
SMC_USBC_INT_L<br />
SMC_USBC_INT_L 30<br />
A<br />
LYNX POINT LP<br />
U0500<br />
(Write: 0x88 Read: 0x89)<br />
13<br />
13<br />
SMBUS_SMC_1_S0_SCL<br />
SMBUS_SMC_1_S0_SDA<br />
SMLink 1 is slave port to<br />
access PCH.<br />
Sec ACE<br />
UC500 - ADDR: 0X27<br />
(Write: 0x4E Read: 0x4F)<br />
94<br />
94<br />
96<br />
SMBUS_SMC_4_G3H_SCL<br />
SMBUS_SMC_4_G3H_SDA<br />
SMC_USBC_INT_L<br />
BOM_COST_GROUP=SMC<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
SMBus Connections<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
53 OF 145<br />
51 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
C<br />
B<br />
100<br />
100<br />
100<br />
100<br />
100<br />
100<br />
79<br />
79<br />
CPU High Side Current Sense (IC0R)<br />
Gain: 100x, EDP: 10.5 A<br />
Rsense: 0.003 (R5400)<br />
Vsense: 31.5 mV, Range: 10 A<br />
SMC ADC: 00<br />
PPBUS_HS_CPU<br />
PPBUS_G3H<br />
OTHER 5V High Side Current Sense (IO5R)<br />
Gain: 200x, EDP: 1.22 A<br />
Rsense: 0.01 (R5410) or Rsense SHORT<br />
Vsense: 12.2 mV, Range: 1.5 A<br />
SMC ADC:<br />
PPBUS_G3H<br />
PPBUS_HS_OTH5V<br />
Gain: 200x, EDP: 4.31 A<br />
Rsense: 0.003 (R5440) or Rsense SHORT<br />
Vsense: 12.93 mV, Range: 5 A<br />
SMC ADC:<br />
LCD Backlight Current Sense (IBLR)<br />
Gain: 100x. EDP: 1 A<br />
Rsense: 0.025 (R8400)<br />
Vsense: 25 mV, Range: 2.4 A<br />
EADC1: CH0<br />
PP3V3_S0<br />
100x<br />
PP3V3_S4SW_SNS<br />
100x<br />
200x<br />
OTHER 3.3V High Side Current Sense (IO3R)<br />
PPBUS_G3H<br />
PPBUS_HS_OTH3V3<br />
IN<br />
IN<br />
ISNS_LCDBKLT_P<br />
ISNS_LCDBKLT_N<br />
101<br />
CRITICAL<br />
0612<br />
2 4<br />
CYN<br />
1W<br />
1%<br />
0.003<br />
R5400 1 3<br />
NO_XNET_CONNECTION=1<br />
OMIT<br />
R5410 1<br />
0.005<br />
1%<br />
1/3W<br />
MF<br />
0306-SHORT<br />
2<br />
OMIT<br />
R5440 1<br />
0.005<br />
1%<br />
1/3W<br />
MF<br />
0306-SHORT<br />
2<br />
PLACE_NEAR=R8400.4:5MM<br />
PLACE_NEAR=R8400.3:5MM<br />
200x<br />
Trackpad Actuator X239 Current Sense (ITAR)<br />
101<br />
101<br />
101<br />
53<br />
52<br />
52<br />
ISNS_HS_OTHER3V3_N<br />
PP3V3_S0<br />
PLACE_NEAR=U5400.5:10MM<br />
ISNS_HS_COMPUTING_N<br />
ISNS_HS_COMPUTING_P<br />
PLACE_NEAR=U5400.4:10MM<br />
PLACE_NEAR=U5410.2:3:10MM<br />
ISNS_HS_OTHER5V_P<br />
3<br />
4<br />
ISNS_HS_OTHER5V_N<br />
PP3V3_S4SW_SNS<br />
PLACE_NEAR=U5440.2:3:10MM<br />
ISNS_HS_OTHER3V3_P<br />
3<br />
4<br />
54<br />
54<br />
PLACE_NEAR=U5410.4:5:10MM<br />
PLACE_NEAR=U5440.4:5:10MM<br />
2<br />
3<br />
4<br />
5<br />
IN+<br />
IN+<br />
6<br />
V+<br />
U5450<br />
INA214A<br />
UQFN<br />
CRITICAL<br />
LOADISNS<br />
9<br />
GND<br />
OUT<br />
REF<br />
NC<br />
NC<br />
10<br />
8<br />
1<br />
7<br />
1<br />
2<br />
NC<br />
NC<br />
5<br />
4<br />
2<br />
3<br />
4<br />
5<br />
2<br />
3<br />
4<br />
5<br />
LOADISNS<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
IN-<br />
IN+<br />
C5450<br />
3<br />
U5400<br />
INA214<br />
SC70<br />
CRITICAL<br />
2<br />
6<br />
U5410<br />
INA210A<br />
UQFN<br />
CRITICAL<br />
LOADISNS<br />
9<br />
6<br />
U5440<br />
INA210A<br />
UQFN<br />
CRITICAL<br />
LOADISNS<br />
9<br />
BYPASS=U5450.6::5MM<br />
ISNS_LCDBKLT_IOUT<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
LOADISNS<br />
IN+<br />
IN+<br />
IN-<br />
IN-<br />
IN-<br />
IN-<br />
IN+<br />
IN+<br />
IN-<br />
IN-<br />
1<br />
R5455<br />
6.04K<br />
GND<br />
V+<br />
V+<br />
V+<br />
GND<br />
GND<br />
OUT<br />
REF<br />
OUT<br />
REF<br />
NC<br />
NC<br />
OUT<br />
REF<br />
NC<br />
NC<br />
6<br />
1<br />
10<br />
8<br />
1<br />
7<br />
10<br />
8<br />
1<br />
7<br />
LOADISNS<br />
PLACE_NEAR=U5450.10:5MM<br />
1<br />
2<br />
CPUHI_IOUT<br />
1<br />
2<br />
R5459<br />
453K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
LOADISNS<br />
BYPASS=U5410.6::5MM<br />
C5411<br />
1<br />
0.1UF<br />
10%<br />
2<br />
6.3V<br />
CERM-X5R<br />
0201<br />
NC<br />
NC<br />
NC<br />
NC<br />
BYPASS=U5400.3::5MM<br />
C5401<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
1<br />
R5405<br />
15K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
PLACE_NEAR=U5400.6:5MM<br />
HS_OTHER5V_IOUT<br />
1<br />
R5415<br />
LOADISNS<br />
BYPASS=U5440.6::5MM<br />
C5441<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
HS_OTHER3V3_IOUT<br />
1<br />
R5445<br />
15K<br />
2<br />
15K<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
LOADISNS<br />
PLACE_NEAR=U5410.10:5MM<br />
1%<br />
1/20W<br />
MF<br />
201<br />
LOADISNS<br />
PLACE_NEAR=U5440.10:5MM<br />
PLACE_NEAR=U5700.22:5MM<br />
1<br />
2<br />
EADC1_LCDBKLT_ISENSE<br />
C5459<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
LOADISNS<br />
PLACE_NEAR=U5700.22:5MM<br />
GND_EADC1_COM<br />
1/20W 1%<br />
MF<br />
201<br />
(to CPU High Side Threshold<br />
Alert circuit)<br />
PLACE_NEAR=U5000.E2:5MM<br />
R5409<br />
4.53K<br />
1 2<br />
SMC_CPU_HI_ISENSE<br />
GND_SMC_AVSS<br />
SMC_OTHER5V_HI_ISENSE<br />
GND_SMC_AVSS<br />
LOADISNS<br />
PLACE_NEAR=U5000.B5:5MM<br />
R5449<br />
4.53K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
1<br />
2<br />
SMC_OTHER3V3_HI_ISENSE<br />
1<br />
2<br />
C5409<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
LOADISNS<br />
PLACE_NEAR=U5000.A4:5MM<br />
R5419<br />
4.53K<br />
1 2<br />
53<br />
1%<br />
1/20W<br />
MF<br />
201<br />
54<br />
55<br />
1<br />
2<br />
PLACE_NEAR=U5000.E2:5MM<br />
C5419<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
C5449<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
LOADRC:YES<br />
PLACE_NEAR=U5000.B5:5MM<br />
GND_SMC_AVSS<br />
55<br />
LOADRC:YES<br />
PLACE_NEAR=U5000.A4:5MM<br />
OUT<br />
OUT<br />
OUT<br />
53<br />
48<br />
48<br />
50<br />
48<br />
49<br />
49<br />
50<br />
OUT<br />
49<br />
50<br />
OUT<br />
50<br />
52<br />
52<br />
50<br />
52<br />
53<br />
53<br />
50<br />
53<br />
54<br />
54<br />
54<br />
55<br />
55<br />
55<br />
100<br />
PPBUS_G3H<br />
50<br />
100<br />
50<br />
PBUS Voltage Sense & Enable (VP0R)<br />
Gain: 0.167x<br />
Vnominal: 12.6 V, Range: 17.97 V<br />
SMC ADC: 01<br />
XW5480<br />
SM<br />
Enables PBUS VSense<br />
divider when in S0.<br />
DC In Voltage Sense & Enable (VD0R)<br />
Gain: 0.13x<br />
Vnominal: 16.5 V, Range: 22.96 V<br />
SMC ADC: 04<br />
SMC_AUX_OK<br />
PPDCIN_G3H<br />
SMC_SENSOR_PWR_EN<br />
1 2 PBUS_S0_VSENSE_IN<br />
PLACE_NEAR=R5400.1:10 MM<br />
Enables DC-In VSense<br />
divider when AC present.<br />
Charger (BMON) Current Sense (IPBR)<br />
Charger Gain: 20x, EDP: 7.2 A<br />
Rsense: 0.005 (R7060) PLACE_NEAR=U5000.F2:5MM<br />
SMC ADC: 02<br />
R5429<br />
CHGR_BMON<br />
300K<br />
1 2 SMC_BMON_ISENSE<br />
66<br />
IN<br />
IN<br />
IN<br />
PBUSVSENS_EN_L_DIV<br />
PDCINVSENS_EN_L_DIV<br />
3300PF<br />
10%<br />
10V<br />
X7R-CERM PLACE_NEAR=U5000.F2:5MM<br />
0201<br />
GND_SMC_AVSS<br />
117S0008 2 RES,MTL FLIM,100K,1/16W,0201,SMD,LF C5419,C5449<br />
LOADRC:NO<br />
117S0008 1 RES,MTL FLIM,100K,1/16W,0201,SMD,LF C5469<br />
LOADRC:NO<br />
1%<br />
1/20W<br />
MF<br />
201<br />
R5481 1<br />
100K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
R54911 69.8K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
C5429<br />
2<br />
1<br />
5<br />
4<br />
2<br />
1<br />
5<br />
4<br />
CRITICAL<br />
Q5480<br />
NTUD3169CZ<br />
SOT-963<br />
N-CHANNEL<br />
CRITICAL<br />
Q5490<br />
DMC31D5UDJ<br />
SOT963<br />
N-CHANNEL<br />
PART NUMBER QTY DESCRIPTION<br />
REFERENCE DES CRITICAL BOM OPTION<br />
1<br />
2<br />
G<br />
G<br />
G<br />
G<br />
50<br />
48<br />
49<br />
D<br />
S<br />
S<br />
P-CHANNEL<br />
D<br />
S<br />
S<br />
D<br />
P-CHANNEL<br />
OUT<br />
D<br />
50<br />
52<br />
53<br />
6<br />
3<br />
54<br />
6<br />
3<br />
55<br />
PBUSVSENS_EN_L<br />
PBUS_S0_VSENSE<br />
DCINVSENS_EN_L<br />
DCIN_S5_VSENSE<br />
66<br />
Rthevenin = 4573 Ohms<br />
SMC_PBUS_VSENSE<br />
PLACE_NEAR=U5000.E1:5MM<br />
GND_SMC_AVSS<br />
Rthevenin = 4129 Ohms<br />
DC-IN (AMON) Current Sense (ID0R)<br />
Charger Gain: 20x, EDP: 4.6 A<br />
PLACE_NEAR=U5000.B3:5MM<br />
Rsense: 0.010 (R7020)<br />
SMC ADC: 03 PLACE_NEAR=U5000.F1:5MM<br />
IN<br />
CHGR_AMON<br />
R5482 1<br />
100K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
R5492 1<br />
200K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
R54881 27.4K<br />
1%<br />
1/20W<br />
201<br />
MF<br />
2<br />
R54891 5.49K<br />
1%<br />
1/20W<br />
201<br />
MF<br />
2<br />
R54981 31.6K<br />
1/20W<br />
201<br />
MF<br />
2<br />
R5439<br />
453K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
1<br />
2<br />
SMC_DCIN_ISENSE<br />
1<br />
C5439<br />
2200PF<br />
10%<br />
10V PLACE_NEAR=U5000.F1:5MM<br />
X7R-CERM<br />
0201<br />
GND_SMC_AVSS<br />
2<br />
C5489<br />
0.22UF<br />
20%<br />
6.3V PLACE_NEAR=U5000.E1:5MM<br />
X5R<br />
0201<br />
1%<br />
PLACE_NEAR=U5000.B3:5MM<br />
SMC_DCIN_VSENSE<br />
OUT 50<br />
PLACE_NEAR=U5000.B3:5MM<br />
R5499 1 1 C5499<br />
1<br />
4.75K<br />
C5497<br />
1%<br />
0.22UF 0.022UF<br />
1/20W<br />
20%<br />
10%<br />
MF 2<br />
6.3V<br />
6.3V<br />
X5R<br />
2<br />
201<br />
X6S<br />
2 0201<br />
0201-1<br />
GND_SMC_AVSS 48 49 50 52 53<br />
PLACE_NEAR=U5000.B3:5MM<br />
OUT<br />
OUT<br />
50<br />
48<br />
50<br />
48<br />
49<br />
49<br />
50<br />
50<br />
52<br />
52<br />
53<br />
53<br />
54<br />
54<br />
54<br />
55<br />
55<br />
55<br />
D<br />
C<br />
B<br />
A<br />
Gain: 24.9x, EDP: 2.61 A (Transient)<br />
Rsense: 0.02 (R5460)<br />
Vsense: 52.2 mV, Range: 6 A<br />
SMC ADC: 12<br />
PPBUS_G3H<br />
101<br />
100<br />
57<br />
55<br />
IN<br />
54<br />
53<br />
52<br />
PP3V3_S4SW_SNS<br />
BYPASS=U5460.5::5MM<br />
PLACE_NEAR=U5460.3:3MM<br />
LOADISNS<br />
C5460 1<br />
0.1UF<br />
2<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
ISNS_TPAD_P<br />
5<br />
V+<br />
OMIT<br />
R5460<br />
0.005<br />
1%<br />
1/3W<br />
MF<br />
0306-SHORT<br />
1 2 PPBUS_S4_HS_TPAD<br />
3 4 PLACE_NEAR=U5460.4:3MM<br />
3 4<br />
VIN+ VIN-<br />
U5460<br />
INA139<br />
SOT23-5<br />
LOADISNS<br />
CRITICAL<br />
GND<br />
2<br />
ISNS_TPAD_N<br />
OUT<br />
1<br />
ISNS_X239_IOUT_BUF<br />
1<br />
R5461<br />
24.9K<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
57 55 54 53 52<br />
101<br />
OUT<br />
LOADISNS<br />
PLACE_NEAR=U5460.1:5MM<br />
Gain: 1000uA/V * 24.9KOhm = 24.9<br />
100<br />
PP3V3_S4SW_SNS<br />
C5462 1<br />
0.1UF<br />
2<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
ISNS_X239_IOUT<br />
3<br />
2<br />
V+<br />
V-<br />
8<br />
4<br />
LOADISNS<br />
CRITICAL<br />
U5462<br />
OPA2340<br />
MSOP<br />
LOADISNS<br />
BYPASS=U5462.8::5MM<br />
1<br />
101<br />
LOADISNS<br />
57<br />
10K<br />
55<br />
R5465<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
54<br />
53<br />
52<br />
PP3V3_S4SW_SNS<br />
ISNS_X239_INT_NI<br />
LOADISNS<br />
R5468<br />
10K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
5<br />
6<br />
V+<br />
V-<br />
LOADISNS<br />
8<br />
4<br />
10K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
LOADISNS<br />
CRITICAL<br />
U5462<br />
OPA2340<br />
MSOP<br />
7<br />
R5467<br />
1 2<br />
ISNS_X239_INT_I<br />
ISNS_X239_IOUT_INT<br />
PLACE_NEAR=U5000.C1:5MM<br />
LOADISNS<br />
R5469<br />
4.53K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
SMC_TPAD_ISENSE<br />
1<br />
C5469<br />
0.22UF<br />
20%<br />
2<br />
6.3V<br />
X5R LOADRC:YES<br />
0201<br />
PLACE_NEAR=U5000.C1:5MM<br />
GND_SMC_AVSS<br />
48<br />
49<br />
50<br />
OUT<br />
52<br />
53<br />
50<br />
54<br />
55<br />
BOM_COST_GROUP=SENSORS<br />
SYNC_MASTER=J79_JACK<br />
PAGE TITLE<br />
Power Sensors: High Side<br />
R<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
IV ALL RIGHTS RESERVED<br />
Apple Inc.<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
54 OF 145<br />
52 OF 119<br />
SYNC_DATE=12/07/2015<br />
SIZE<br />
D<br />
A<br />
8 7 6<br />
5 4 3<br />
2 1
D<br />
C<br />
B<br />
A<br />
PCH 1.0V Current Sense (IS1C)<br />
Gain: 200x, EDP: 3.29 A<br />
Rsense: 0.003 (R8004) or Rsense SHORT<br />
Vsense: 9.87 mV, Range: 5 A<br />
SMC ADC: 11<br />
DDR 1.2V S3 (CPU & Memory) Current Sense (IM0C)<br />
Gain: 100x, EDP: 8.21 A<br />
Rsense: 0.003 (R7918) or XWTBD<br />
Vsense: 24.63 mV, Range: 10 A<br />
SMC ADC: 09<br />
CPU DDR 1.2V S3 (CPU Only) Current Sense (IMCC)<br />
Gain: 200x, EDP: 2 A<br />
Rsense: 0.005 (R5510) or Rsense SHORT<br />
Vsense: 10 mV, Range: 3 A<br />
SMC ADC: 18<br />
100<br />
100<br />
PP1V2_S3<br />
PP1V2_S3_CPUDDR<br />
T139 Current Sense (IF3C)<br />
Gain: 200x, EDP: 0.06 A<br />
Rsense: 0.05 (R5520) or Rsense SHORT<br />
Vsense: 3 mV, Range: 0.25 A<br />
EADC1: CH3<br />
101<br />
101<br />
36 35<br />
106<br />
PP3V3_S5<br />
PP3V3_S5_T139<br />
WLAN Current Sense (IAPC)<br />
Gain: 163.3x, EDP: 1.67 A<br />
Rsense: 0.015 (R5530) or Rsense SHORT<br />
Vsense: 25.05 mV, Range: 1.67 A<br />
EADC1: CH4<br />
36<br />
8<br />
76<br />
76<br />
101<br />
101<br />
101<br />
57<br />
57<br />
57<br />
101<br />
55<br />
55<br />
55<br />
57<br />
54<br />
54<br />
54<br />
55<br />
53<br />
53<br />
53<br />
54<br />
52<br />
PLACE_NEAR=R8004.3:5MM<br />
ISNS_1V0_P<br />
ISNS_1V0_N<br />
PLACE_NEAR=R8004.4:5MM<br />
52<br />
PLACE_NEAR=R7918.3:5MM<br />
ISNS_CPUDDR_P<br />
ISNS_CPUDDR_N<br />
PLACE_NEAR=R7918.4:5MM<br />
52<br />
53<br />
PP3V3_S4SW_SNS<br />
PP3V3_S4SW_SNS<br />
PP3V3_S4SW_SNS<br />
PLACE_NEAR=U5510.2:3:10MM<br />
ISNS_CPUVDDQ_P<br />
ISNS_CPUVDDQ_N<br />
52<br />
ISNS_PP3V3S0_N<br />
101<br />
PP3V3_S4SW_SNS<br />
PLACE_NEAR=U5520.2:3:10MM<br />
ISNS_PP3V3S0_P<br />
PP3V3_S4_WLAN_SW PLACE_NEAR=U5530.3:10MM<br />
ISNS_PP3V3S4_WLAN_P<br />
OMIT<br />
0306-SHORT 2 4<br />
MF<br />
1/3W<br />
1%<br />
0.005<br />
R5530 1 3<br />
PP3V3_S4_WLAN_SW_R<br />
ISNS_PP3V3S4_WLAN_N<br />
NO_XNET_CONNECTION=1 PLACE_NEAR=U5530.4:10MM<br />
75<br />
75<br />
OMIT<br />
R5510 1 0.005<br />
1%<br />
1/3W<br />
MF<br />
0306-SHORT<br />
2<br />
IN<br />
IN<br />
IN<br />
IN<br />
3<br />
4<br />
OMIT<br />
R5520 1<br />
0.005<br />
1%<br />
1/3W<br />
MF<br />
0306-SHORT<br />
2<br />
3<br />
4<br />
7<br />
PLACE_NEAR=U5510.4:5:10MM<br />
PLACE_NEAR=U5520.4:5:10MM<br />
2<br />
3<br />
4<br />
5<br />
2<br />
3<br />
4<br />
5<br />
2<br />
3<br />
4<br />
5<br />
2<br />
3<br />
4<br />
5<br />
IN+<br />
IN+<br />
IN+<br />
IN+<br />
IN-<br />
IN-<br />
IN-<br />
IN-<br />
IN-<br />
IN-<br />
IN+<br />
IN+<br />
IN-<br />
IN-<br />
IN+<br />
IN+<br />
IN-<br />
IN-<br />
PP5V_S4SW_ISNS<br />
6<br />
U5560<br />
INA210A<br />
UQFN<br />
CRITICAL<br />
LOADISNS<br />
200x<br />
9<br />
6<br />
INA214A<br />
CRITICAL<br />
LOADISNS<br />
U5570<br />
UQFN<br />
100x<br />
9<br />
6<br />
U5510<br />
INA210A<br />
UQFN<br />
CRITICAL<br />
LOADISNS<br />
LOADISNS<br />
200x<br />
9<br />
6<br />
U5520<br />
INA210A<br />
UQFN<br />
CRITICAL<br />
200x<br />
9<br />
ISNS_PP3V3S4_WLAN_R_P<br />
R5531<br />
LOADISNS<br />
10<br />
1<br />
7<br />
10<br />
1<br />
7<br />
10<br />
1<br />
7<br />
ISNS_PP3V3S4_WLAN_R_N<br />
R5532<br />
LOADISNS<br />
120<br />
1 2<br />
0.1%<br />
1/20W<br />
MF<br />
0201<br />
120<br />
1 2<br />
0.1%<br />
1/20W<br />
MF<br />
0201<br />
V+<br />
GND<br />
V+<br />
GND<br />
V+<br />
GND<br />
V+<br />
GND<br />
OUT<br />
REF<br />
NC<br />
NC<br />
OUT<br />
REF<br />
NC<br />
NC<br />
OUT<br />
REF<br />
NC<br />
NC<br />
OUT<br />
REF<br />
NC<br />
NC<br />
8<br />
10<br />
8<br />
1<br />
7<br />
8<br />
8<br />
ISNS_WLAN_OP<br />
P1V0S0_IOUT<br />
ISNS_DDR_IOUT<br />
ISNS_CPUDDR_IOUT<br />
ISNS_PP3V3S0_IOUT<br />
LOADISNS<br />
D5530<br />
SM-0201<br />
A K<br />
DSF01S30SCAP<br />
CKPLUS_WAIVE=PDIFPR_BADTERM<br />
CKPLUS_WAIVE=NDIFPR_BADTERM<br />
1<br />
2<br />
NC<br />
NC<br />
1<br />
2<br />
NC<br />
NC<br />
1<br />
2<br />
NC<br />
NC<br />
1<br />
2<br />
NC<br />
NC<br />
LOADISNS<br />
BYPASS=U5560.6::5MM<br />
C5560<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
1<br />
R5565<br />
20K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
LOADISNS<br />
BYPASS=U5570.6::5MM<br />
C5570<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
1<br />
R5575<br />
20K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
NOSTUFF<br />
LOADISNS<br />
BYPASS=U5510.3::5MM<br />
C5510<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
1<br />
R5515<br />
20K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
NOSTUFF<br />
PLACE_NEAR=U5510.10:5MM<br />
LOADISNS<br />
BYPASS=U5520.6::5MM<br />
C5520<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
1<br />
R5525<br />
20K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
4<br />
CRITICAL<br />
LOADISNS<br />
3<br />
5<br />
2<br />
6<br />
NOSTUFF<br />
PLACE_NEAR=U5560.10:5MM<br />
PLACE_NEAR=U5570.10:5MM<br />
NOSTUFF<br />
PLACE_NEAR=U5520.10:5MM<br />
LOADISNS<br />
PLACE_NEAR=U5000.H2:5MM<br />
R5569<br />
4.53K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=5V<br />
PP5V_S4_WLAN_ISNS_D<br />
NO_XNET_CONNECTION=1<br />
Q5530<br />
DMP31D0UFB4<br />
DFN1006H4-3<br />
LOADISNS<br />
U5530<br />
LTC2050HVCS5<br />
TSOT23-5<br />
1<br />
1<br />
1<br />
R5533<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
LOADISNS<br />
LOADISNS<br />
GAIN:163.3x<br />
SMC_PCH_ISENSE<br />
1<br />
2<br />
C5569<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
PLACE_NEAR=U5000.H2:5MM<br />
LOADRC:YES<br />
GND_SMC_AVSS<br />
PLACE_NEAR=U5000.A5:5MM<br />
R5579<br />
4.53K<br />
1 2<br />
1/20W 1%<br />
MF<br />
201<br />
SMC_DDR1V2_ISENSE<br />
GND_SMC_AVSS<br />
LOADISNS<br />
PLACE_NEAR=U5000.H1:5MM<br />
R5519<br />
4.53K<br />
1 2<br />
1/20W 1%<br />
MF<br />
201<br />
SMC_CPUDDR_ISENSE<br />
GND_SMC_AVSS<br />
117S0008 2<br />
EADC1_PP3V3S0_T139_ISENSE<br />
GND_EADC1_COM<br />
RES,MTL FLIM,100K,1/16W,0201,SMD,LF<br />
ISNS_PP3V3S4_WLAN_IOUT<br />
50<br />
68<br />
68<br />
68<br />
68<br />
CPU Fixed Current Sense (ICAC)<br />
Gain: 275.74x, EDP: 29 A<br />
Rsense: 2x of 0.00075 (R7310, R7320), Rsum: 0.000375<br />
Vsense: 10.875 mV, Range: 29.01 A<br />
SMC ADC: 06<br />
R5545<br />
CPUCORE_ISNS1_P<br />
4.42K<br />
1 2<br />
BT Current Sense (IBTC)<br />
Gain: 200x, EDP: 0.06 A<br />
Rsense: 0.05 (R5580)<br />
Vsense: 3 mV, Range: 0.25 A<br />
EADC1: CH5<br />
106<br />
106<br />
101<br />
101<br />
CPUCORE_ISNS2_P<br />
CPUCORE_ISNS1_N<br />
CPUCORE_ISNS2_N<br />
PP3V3_S4<br />
PP3V3_S4_BT<br />
CPU High Side Current (IC0R) Threshold Alert<br />
Gain: 100x<br />
Rsense: 0.003 (R5400)<br />
PP3V3_S0<br />
101<br />
Trip Target on CPU High current: 2.5 A<br />
Hysteresis Circuit:<br />
Vref = 0.737 V<br />
Vth = 0.616 V -> 2.054 A on CPU High current<br />
Vtl = 0.771 V -> 2.571 A on CPU High current<br />
Hysteresis Margin = 0.518 A<br />
C5569,C5519<br />
1.8V Current Sense (I18C)<br />
Gain: 200x, EDP: 0.7 A<br />
Rsense: 0.025 (R8024) or Rsense SHORT<br />
Vsense: 17.5 mV, Range: 0.6 A<br />
SMC ADC: 16<br />
52<br />
GND_EADC1_COM<br />
101<br />
EADC1_PP3V3S4_WLAN_ISENSE<br />
CPUVR_ISNS_P<br />
CPUVR_ISNS_N<br />
57<br />
55<br />
54<br />
101<br />
53<br />
57<br />
52<br />
55<br />
PLACE_NEAR=U5580.2:3:10MM<br />
ISNS_BT_P<br />
ISNS_BT_N<br />
117S0008 2<br />
RES,MTL FLIM,100K,1/16W,0201,SMD,LF<br />
C5549,C5579 LOADRC:NO<br />
LOADISNS<br />
PLACE_NEAR=U5700.1:5MM<br />
R5529<br />
453K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
G<br />
1<br />
2<br />
1<br />
2<br />
1<br />
2<br />
2<br />
3<br />
C5579<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
LOADRC:YES<br />
C5519<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
LOADRC:YES<br />
C5529<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
PLACE_NEAR=U5700.1:5MM<br />
LOADISNS<br />
1<br />
2<br />
C5530<br />
0.1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
LOADISNS<br />
BYPASS=U5530.5::5MM<br />
LOADISNS<br />
1<br />
R5534<br />
19.6K<br />
0.1%<br />
1/20W<br />
MF<br />
2<br />
0201<br />
5<br />
PLACE_NEAR=U5000.A5:5MM<br />
PLACE_NEAR=U5000.H1:5MM<br />
48<br />
50<br />
48<br />
48<br />
52<br />
49<br />
49<br />
50<br />
49<br />
53<br />
50<br />
50<br />
50<br />
54<br />
52<br />
52<br />
52<br />
55<br />
53<br />
53<br />
53<br />
54<br />
54<br />
54<br />
55<br />
55<br />
55<br />
55<br />
LOADISNS<br />
PLACE_NEAR=R7210:5MM<br />
LOADISNS<br />
PLACE_NEAR=R7220:5MM<br />
LOADISNS<br />
PLACE_NEAR=R7210:5MM<br />
PLACE_NEAR=R7220:5MM<br />
0.1%<br />
1/20W<br />
MF<br />
0201<br />
R5546<br />
4.42K<br />
1 2<br />
0.1%<br />
1/20W<br />
MF<br />
0201<br />
R5547<br />
4.42K<br />
1 2<br />
0.1%<br />
1/20W<br />
MF<br />
0201<br />
R5548<br />
4.42K<br />
1 2<br />
0.1%<br />
LOADISNS 1/20W<br />
MF<br />
0201<br />
NO_XNET_CONNECTION=1<br />
1%<br />
1/3W<br />
MF<br />
0306-SHORT<br />
OMIT<br />
R5580 1<br />
0.005<br />
2<br />
76<br />
76<br />
3<br />
4<br />
54<br />
53<br />
ISNS_1V8_SUS_P<br />
ISNS_1V8_SUS_N<br />
52<br />
LOADRC:NO<br />
PLACE_NEAR=R8024.3:5MM<br />
PLACE_NEAR=R8024.4:5MM<br />
LOADISNS<br />
R5542<br />
383<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
R5543<br />
383<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
LOADISNS<br />
PLACE_NEAR=U5580.4:5:10MM<br />
PART NUMBER QTY DESCRIPTION<br />
REFERENCE DES CRITICAL BOM OPTION<br />
S<br />
D<br />
<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
IN<br />
IN<br />
LOADISNS<br />
PLACE_NEAR=U5700.2:5MM<br />
R5539<br />
453K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
1<br />
2<br />
C5539<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
PLACE_NEAR=U5700.2:5MM<br />
LOADISNS<br />
52<br />
53<br />
54<br />
55<br />
PP3V3_S4SW_SNS<br />
55<br />
PP3V3_S4SW_SNS<br />
2<br />
3<br />
4<br />
5<br />
2<br />
3<br />
4<br />
5<br />
CPUHYS<br />
294K<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
200x<br />
LOADISNS<br />
101<br />
200x<br />
PP3V3_S0<br />
CPUVR_ISNS_R_P<br />
CPUVR_ISNS_R_N<br />
1<br />
R5544<br />
0.1%<br />
1/20W<br />
MF<br />
2<br />
0201<br />
LOADISNS<br />
6<br />
U5590<br />
INA210A<br />
UQFN<br />
CRITICAL<br />
9<br />
715K<br />
1<br />
R5554<br />
CPUHYS<br />
1<br />
R5555<br />
84.5K<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
NOSTUFF<br />
SM-201<br />
RB521ZS-30<br />
NO_XNET_CONNECTION=1<br />
6<br />
U5580<br />
INA210A<br />
UQFN<br />
CRITICAL<br />
LOADISNS<br />
D5557 A K<br />
9<br />
CPUHI_COMP_VREF<br />
0<br />
NOSTUFF<br />
1<br />
R5557<br />
5%<br />
1/20W<br />
MF<br />
2 0201<br />
BMON_IOUT_D<br />
10<br />
8<br />
1<br />
7<br />
1<br />
2<br />
10<br />
8<br />
1<br />
7<br />
LOADISNS<br />
0.1UF<br />
1<br />
3<br />
P1V8SUS_IOUT<br />
2 5<br />
ISNS_S4_BT_IOUT<br />
CPUHI_IOUT_R<br />
CPUHI_IOUT<br />
BYPASS=U5590.6::5MM<br />
C5590<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
20K<br />
5%<br />
NOSTUFF<br />
1<br />
2<br />
1<br />
R5595<br />
1/20W<br />
MF<br />
2 201<br />
R5541<br />
715K<br />
1 2<br />
LOADISNS<br />
0.1UF<br />
BOM_COST_GROUP=SENSORS<br />
LOADISNS<br />
CRITICAL<br />
U5540<br />
ISL28133<br />
SC70-5<br />
4<br />
CPUVR_ISUM_IOUT<br />
0.1%<br />
1/20W<br />
MF LOADISNS<br />
0201 NO_XNET_CONNECTION=1<br />
BYPASS=U5580.6::5MM<br />
C5580<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
1<br />
R5585<br />
20K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
1<br />
2<br />
0<br />
BYPASS=U5551.5::5MM<br />
CPUHYS<br />
CPUHYS<br />
C5551<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
R5556<br />
12K<br />
1 2<br />
CPUHYS<br />
5%<br />
1/20W<br />
MF<br />
2 0201<br />
1%<br />
1/20W<br />
MF<br />
201<br />
1<br />
R5552<br />
PLACE_NEAR=U5590.10:5MM<br />
1<br />
2<br />
3<br />
4<br />
LOADISNS<br />
1<br />
R5540<br />
20K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
NOSTUFF<br />
PLACE_NEAR=U5580.10:5MM<br />
NOSTUFF<br />
C5552<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
453K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
SYNC_MASTER=J79_JACK<br />
5<br />
2<br />
1<br />
2<br />
LOADISNS<br />
BYPASS=U5540.5::5MM<br />
C5540<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
R5549<br />
4.53K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
NOSTUFF<br />
PLACE_NEAR=U5540.4:5MM<br />
EADC1_BT_ISENSE<br />
EADC1_P1V8SUS_ISENSE<br />
GND_EADC1_COM<br />
GND_EADC1_COM<br />
CPUHI_COMP_FB<br />
CPUHYS<br />
52<br />
U5551<br />
LOADISNS<br />
PLACE_NEAR=U5000.B4:5MM<br />
SMC_CPU_ISENSE<br />
1<br />
2<br />
C5549<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
LOADRC:YES<br />
PLACE_NEAR=U5000.B4:5MM<br />
GND_SMC_AVSS<br />
MAX9119EXK-T<br />
SC70-5<br />
CPUHYS<br />
1 CPUHI_COMP_OUT<br />
CRITICAL<br />
PLACE_NEAR=U5700.23:5MM<br />
R5599<br />
1 2<br />
2 1<br />
LOADISNS<br />
R5589<br />
453K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
1<br />
2<br />
C5599<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
PLACE_NEAR=U5700.23:5MM<br />
LOADISNS<br />
PLACE_NEAR=U5700.6:5MM<br />
1<br />
2<br />
CPUHYS<br />
LOADISNS<br />
C5589<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
PLACE_NEAR=U5700.6:5MM<br />
DMN32D2LFB4<br />
DFN1006H4-3<br />
NOSTUFF<br />
C5553<br />
0.22UF<br />
1 2<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
R5553<br />
255K<br />
1 2<br />
1/20W<br />
MF<br />
201<br />
SMC_CPUHI_COMP_ALERT_L<br />
U5552 D 3<br />
1<br />
2<br />
Power Sensors: Load Side<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
4<br />
IN<br />
IN<br />
OUT<br />
IN+<br />
IN+<br />
3<br />
IN+<br />
IN+<br />
IN-<br />
IN-<br />
V+<br />
GND<br />
V+<br />
OUT<br />
GND<br />
REF<br />
NC<br />
NC<br />
OUT<br />
REF<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
V+<br />
V-<br />
IN<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
SYM_VER_2<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
G<br />
S<br />
1%<br />
OUT<br />
52<br />
55<br />
53<br />
OUT<br />
54<br />
55<br />
55<br />
52<br />
53<br />
54<br />
BRANCH<br />
55<br />
REVISION<br />
50<br />
48<br />
49<br />
DRAWING NUMBER<br />
PAGE<br />
OUT<br />
SHEET<br />
50<br />
OUT<br />
52<br />
53<br />
50<br />
051-00777<br />
9.0.0<br />
54<br />
dvt-fab09-0<br />
55 OF 145<br />
53 OF 119<br />
55<br />
SYNC_DATE=04/03/2016<br />
SIZE<br />
D<br />
D<br />
C<br />
B<br />
A
SYNC_MASTER=J79_JACK<br />
SYNC_DATE=01/08/2016<br />
D<br />
C<br />
B<br />
A<br />
106<br />
T139 5V Current Sense (IF5C)<br />
Gain: 200x, EDP: 0.004 A<br />
Rsense: 0.05 (R5630) or Rsense SHORT<br />
Vsense: 0.2 mV, Range: 0.25 A<br />
EADC1: CH6<br />
Thunderbolt TBT Current Left (IULC)<br />
Gain: 200x. EDP: 0.5 A<br />
Rsense: 0.025 (R5640) or Rsense SHORT<br />
Vsense: 12.5 mV, Range: 0.5 A<br />
101<br />
EADC1: CH7<br />
101<br />
101<br />
101<br />
101<br />
LCD Panel Current Sense (ILDC)<br />
Gain: 200x. EDP: 1 A<br />
RSENSE: 0.01 (R8520) or Rsense SHORT<br />
Vsense: 5 mV, Range: 1.25 A<br />
EADC2: CH0<br />
Trackpad 3V Current Sense (IT3C)<br />
Gain: 200x, EDP: 0.2 A<br />
Rsense: 0.05 (R5650) or Rsense SHORT<br />
Vsense: 10 mV, Range: 0.25 A<br />
EADC2: CH1<br />
101<br />
101<br />
PP3V3_S4<br />
PP3V3_S4_TPAD<br />
Camera Current Sense (ICMC)<br />
Gain: 200x. EDP: 0.82 A<br />
Rsense: 0.015 (R5610) or XW5610<br />
Vsense: 12.3 mV, Range: 0.83 A<br />
EADC2: CH2<br />
101<br />
101<br />
PP5V_S0<br />
PP5V_S0_T139<br />
PP3V3_S0<br />
8<br />
PP3V3_TBT_X_S0<br />
NO_XNET_CONNECTION=1<br />
PP3V3_S4<br />
PP3V3_S4_SOC_PMU<br />
NO_XNET_CONNECTION=1<br />
OMIT<br />
R5630<br />
1<br />
0.005<br />
1%<br />
1/3W<br />
MF<br />
0306-SHORT<br />
OMIT<br />
R5640<br />
1<br />
0.005<br />
1%<br />
1/3W<br />
MF<br />
0306-SHORT<br />
2<br />
R5650 1<br />
0.005<br />
2<br />
1%<br />
1/3W<br />
MF<br />
0306-SHORT<br />
OMIT<br />
0.005<br />
1%<br />
1/3W<br />
MF<br />
0306-SHORT<br />
2<br />
OMIT<br />
R5610<br />
1<br />
2<br />
101<br />
57<br />
101<br />
101<br />
57<br />
55<br />
57<br />
57<br />
55<br />
54<br />
55<br />
55<br />
54<br />
53<br />
54<br />
54<br />
53<br />
52<br />
53<br />
ISNS_TBT_P<br />
ISNS_TBT_N<br />
53<br />
52<br />
52<br />
ISNS_PP5V_T139_N<br />
PP3V3_S4SW_SNS<br />
PLACE_NEAR=U5630.2:3:10MM<br />
ISNS_PP5V_T139_P<br />
PP3V3_S4SW_SNS<br />
52<br />
101<br />
ISNS_LCDPANEL_P<br />
ISNS_LCDPANEL_N<br />
PP3V3_S0<br />
PP3V3_S4SW_SNS<br />
PLACE_NEAR=U5650.2:3:10MM<br />
ISNS_PP3V3_TPAD_P<br />
3<br />
4<br />
3<br />
4<br />
PLACE_NEAR=U5630.4:5:10MM<br />
PLACE_NEAR=U5640.2:3:10MM<br />
3<br />
4<br />
PLACE_NEAR=U5640.4:5:10MM<br />
ISNS_PP3V3_TPAD_N<br />
ISNS_CAMERA_N<br />
PP3V3_S4SW_SNS<br />
PLACE_NEAR=U5610.2:3:10MM<br />
3 ISNS_CAMERA_P<br />
4<br />
80<br />
80<br />
PLACE_NEAR=R8520.3:5MM<br />
IN<br />
IN<br />
PLACE_NEAR=R8520.4:5MM<br />
PLACE_NEAR=U5610.4:5:10MM<br />
7<br />
2<br />
3<br />
4<br />
5<br />
PLACE_NEAR=U5650.4:5:10MM<br />
2<br />
3<br />
4<br />
5<br />
2<br />
3<br />
4<br />
5<br />
IN+<br />
IN+<br />
2<br />
3<br />
4<br />
5<br />
IN+<br />
IN+<br />
IN+<br />
IN+<br />
IN-<br />
IN-<br />
IN-<br />
IN-<br />
IN-<br />
IN-<br />
200x<br />
INA210A<br />
UQFN<br />
CRITICAL<br />
LOADISNS<br />
IN+<br />
IN+<br />
6<br />
U5640<br />
200x<br />
9<br />
200x<br />
INA210A<br />
UQFN<br />
CRITICAL<br />
LOADISNS<br />
INA210A<br />
CRITICAL<br />
LOADISNS<br />
V+<br />
GND<br />
2<br />
3<br />
4<br />
5<br />
INA210A<br />
UQFN<br />
CRITICAL<br />
LOADISNS<br />
6<br />
U5610<br />
200x<br />
9<br />
U5630<br />
U5650<br />
V+<br />
6<br />
UQFN<br />
9<br />
6<br />
9<br />
GND<br />
V+<br />
GND<br />
IN+<br />
IN+<br />
IN-<br />
IN-<br />
IN-<br />
IN-<br />
IN-<br />
IN-<br />
V+<br />
GND<br />
OUT<br />
REF<br />
NC<br />
NC<br />
6<br />
INA210A<br />
CRITICAL<br />
LOADISNS<br />
U5620<br />
UQFN<br />
200x<br />
9<br />
OUT<br />
REF<br />
OUT<br />
10<br />
8<br />
1<br />
7<br />
NC<br />
NC<br />
REF<br />
V+<br />
NC<br />
NC<br />
GND<br />
OUT<br />
REF<br />
NC<br />
NC<br />
10<br />
8<br />
1<br />
7<br />
10<br />
8<br />
1<br />
7<br />
1<br />
7<br />
1<br />
2<br />
NC<br />
NC<br />
10<br />
8<br />
ISNS_PP5V_T139_IOUT<br />
LOADISNS<br />
BYPASS=U5640.6::5MM<br />
ISNS_TBT_IOUT<br />
ISNS_LCDPANEL_IOUT<br />
ISNS_PP3V3_TPAD_IOUT<br />
1<br />
1<br />
C5640<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
1<br />
LOADISNS<br />
BYPASS=U5630.6::5MM<br />
C5630<br />
LOADISNS<br />
BYPASS=U5650.6::5MM<br />
C5650<br />
LOADISNS<br />
0.1UF<br />
10%<br />
2<br />
6.3V<br />
CERM-X5R<br />
0201<br />
10<br />
8<br />
1<br />
7<br />
0.1UF<br />
10%<br />
2<br />
6.3V<br />
CERM-X5R<br />
0201<br />
BYPASS=U5610.6::5MM<br />
C5610<br />
0.1UF<br />
10%<br />
2<br />
6.3V<br />
CERM-X5R<br />
0201<br />
NC<br />
NC<br />
NC<br />
NC<br />
OUT<br />
1<br />
R5635<br />
20K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
NOSTUFF<br />
1<br />
2<br />
LOADISNS<br />
0.1UF<br />
1<br />
R5655<br />
20K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
ISNS_CAMERA_IOUT<br />
LOADISNS<br />
BYPASS=U5620.6::5MM<br />
C5620<br />
PLACE_NEAR=U5700.5:5MM<br />
R5649<br />
453K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
LOADISNS<br />
PLACE_NEAR=U5630.10:5MM<br />
1<br />
R5645<br />
20K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
NOSTUFF<br />
PLACE_NEAR=U5640.10:5MM<br />
REF<br />
NC<br />
NC<br />
NC<br />
NC<br />
NOSTUFF<br />
PLACE_NEAR=U5650.10:5MM<br />
20K<br />
NC<br />
NC<br />
1<br />
R5615<br />
51K<br />
6<br />
1<br />
R5625<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
NOSTUFF<br />
PLACE_NEAR=U5620.10:5MM<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
NOSTUFF<br />
PLACE_NEAR=U5610.10:5MM<br />
LOADISNS<br />
PLACE_NEAR=U5700.4:5MM<br />
R5639<br />
LOADISNS<br />
453K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
EADC1_PP5V_T139_ISENSE<br />
GND_EADC1_COM<br />
EADC1_TBT_ISENSE<br />
1<br />
2<br />
C5649<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
LOADISNS<br />
PLACE_NEAR=U5700.5:5MM<br />
GND_EADC1_COM<br />
LOADISNS<br />
PLACE_NEAR=U5710.22:5MM<br />
R5629<br />
453K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
GND_EADC2_COM<br />
PLACE_NEAR=U5710.23:5MM<br />
R5659<br />
453K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
1<br />
2<br />
EADC2_PP3V3_TPAD_ISENSE<br />
1<br />
2<br />
C5639<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
PLACE_NEAR=U5700.4:5MM<br />
LOADISNS<br />
C5659<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
PLACE_NEAR=U5710.24:5MM<br />
R5619<br />
453K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
GND_EADC2_COM<br />
EADC2_CAMERA_ISENSE<br />
1<br />
2<br />
GND_EADC2_COM<br />
EADC2_LCDPANEL_ISENSE<br />
0201<br />
PLACE_NEAR=U5710.23:5MM<br />
LOADISNS<br />
C5619<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
LOADISNS<br />
1<br />
C5629<br />
0.22UF<br />
20%<br />
2<br />
6.3V<br />
X5R<br />
0201<br />
LOADISNS<br />
55<br />
PLACE_NEAR=U5710.22:5MM<br />
PLACE_NEAR=U5710.24:5MM<br />
<br />
OUT<br />
52<br />
53<br />
54<br />
5<br />
54<br />
55<br />
52<br />
54<br />
OUT<br />
55<br />
53<br />
55<br />
OUT<br />
55<br />
54<br />
54<br />
OUT<br />
55<br />
55<br />
OUT<br />
55<br />
55<br />
54 52<br />
54 52<br />
55<br />
IN<br />
IN<br />
106<br />
101<br />
101<br />
101<br />
56<br />
Battery Discrete Current Sense (IB0L)<br />
Gain: 2940x. EDP: 8 A<br />
Rsense: 0.003 (R501//R502)<br />
Vsense: 24 mV, Range: 0.28 A<br />
EADC2: CH5<br />
Thunderbolt TBT Current Right (IURC)<br />
Gain: 200x. EDP: 0.5 A<br />
Rsense: 0.025 (R5670) or Rsense SHORT<br />
Vsense: 12.5 mV, Range: 0.5 A<br />
EADC1: CH2<br />
101<br />
PP3V3_S0<br />
CPU GT Voltage Sense (VCGC)<br />
SMC ADC: 21<br />
100<br />
8<br />
CPU Core Voltage Sense (VCAC)<br />
SMC ADC: 20<br />
PP3V3_S0<br />
CKPLUS_WAIVE=NdifPr_badTerm<br />
CKPLUS_WAIVE=NdifPr_badTerm<br />
ISNS_HS_COMPUTING_P<br />
ISNS_HS_COMPUTING_N<br />
PP3V3_TBT_T_S0<br />
117S0008<br />
PPVCCGT_S0_CPU<br />
104<br />
100<br />
PLACE_NEAR=R5400.3:10MM<br />
PLACE_NEAR=R5400.4:10MM<br />
CKPLUS_WAIVE=NdifPr_badTerm<br />
CKPLUS_WAIVE=NdifPr_badTerm<br />
8<br />
PPVCC_S0_CPU<br />
Gain: 1 A / 34.223 mV, Range: 29 A.<br />
SMC ADC: 22<br />
With R7150 (Ri) set to 226 Ohm,<br />
R7210 (Rsen) set to 0.75 mOhm,<br />
R7160 set to 82.5 kOhm,<br />
Num Phases (N) is 2, and Io (ICCmax) is 29A,<br />
then 1A of Io gives 34.223mV at the Vimon.<br />
2<br />
OMIT<br />
R5670 1 0.005<br />
1%<br />
1/3W<br />
MF<br />
0306-SHORT<br />
2<br />
XW5600<br />
SM<br />
1 2<br />
CPU High Side (IC0R) Peak Detection Support<br />
LOADISNS<br />
200x<br />
PP3V3_S4SW_SNS<br />
CPU Core IMON Current Sense (ICAM)<br />
2<br />
3<br />
4<br />
5<br />
R5660<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
57<br />
55<br />
INA210A<br />
CRITICAL<br />
LOADISNS<br />
U5660<br />
54<br />
6<br />
UQFN<br />
9<br />
53<br />
PLACE_NEAR=U5670.2:3:10MM<br />
3<br />
CPUGTVSENSE_IN<br />
52<br />
ISNS_TBT_T_P<br />
ISNS_TBT_T_N<br />
4<br />
PLACE_NEAR=U5670.4:5:10MM<br />
RES,MTL FLIM,100K,1/16W,0201,SMD,LF<br />
R5609<br />
4.53K<br />
1 2<br />
PLACE_NEAR=R7410.2:5 MM<br />
1/20W 1%<br />
MF<br />
201<br />
PLACE_NEAR=U5000.A7:5MM<br />
XW5680<br />
SM<br />
1 2<br />
10<br />
8<br />
1<br />
7<br />
CPUVSENSE_IN<br />
IMON_B_CPUCORE<br />
PP3V3_S0_CPUTHMSNS_R<br />
ISNS_CPUHIGAIN_OUT<br />
2<br />
3<br />
4<br />
5<br />
6<br />
U5670<br />
INA210A<br />
UQFN<br />
CRITICAL<br />
LOADISNS<br />
200x<br />
9<br />
C5608, C5699<br />
SMC_CPUGT_VSENSE<br />
1<br />
1<br />
15K<br />
C5660<br />
0.1UF<br />
10%<br />
2<br />
6.3V<br />
CERM-X5R<br />
0201<br />
BYPASS=U5660.6::5MM<br />
LOADISNS<br />
1<br />
R5664<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
LOADISNS<br />
PLACE_NEAR=U5660.10:5MM<br />
C5609<br />
0.22UF<br />
20%<br />
2<br />
6.3V<br />
X5R<br />
0201<br />
PLACE_NEAR=R7210.2:5 MM<br />
1%<br />
1/20W<br />
MF<br />
201<br />
PLACE_NEAR=U5000.B7:5MM<br />
67<br />
GND_SMC_AVSS<br />
R5689<br />
4.53K<br />
1 2<br />
LOADISNS<br />
R5699<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
PLACE_NEAR=U5000.B8:5MM<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
10<br />
1<br />
7<br />
SMC_CPU_VSENSE<br />
GND_SMC_AVSS<br />
SMC_CPU_IMON_ISENSE<br />
8<br />
1<br />
2<br />
NO_XNET_CONNECTION=1<br />
XW5660<br />
ISNS_CPUHIGAIN_OUT_R<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
ISNS_TBT_T_IOUT<br />
GND_SMC_AVSS 48 49 50 52 53 54 55<br />
BOM_COST_GROUP=SENSORS<br />
2<br />
SM<br />
LOADISNS<br />
BYPASS=U5670.6::5MM<br />
C5670<br />
0.1UF<br />
PLACE_NEAR=U5000.A7:5MM<br />
1<br />
2<br />
1<br />
2<br />
C5689<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
LOADISNS<br />
C5699<br />
0.22UF<br />
R5665<br />
0<br />
1 2<br />
48<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
49<br />
50<br />
1<br />
R5676<br />
20K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
50<br />
NOSTUFF<br />
C5665<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
NOSTUFF<br />
PLACE_NEAR=U5670.10:5MM<br />
1<br />
BMON_IOUT<br />
PART NUMBER QTY DESCRIPTION<br />
REFERENCE DES CRITICAL BOM OPTION<br />
LOADRC:NO<br />
ISNS_CPUHIGAIN_R_P<br />
1 2 ISNS_CPUHIGAIN_P<br />
OUT 56<br />
PLACE_NEAR=U5660.10:10MM<br />
5%<br />
1/20W<br />
1<br />
R5662<br />
MF<br />
R5667<br />
1K<br />
0201<br />
0<br />
1%<br />
54 52 ISNS_HS_COMPUTING_P 1 2<br />
IN<br />
1/20W<br />
PLACE_NEAR=U5660.10:10MM<br />
MF<br />
NO_XNET_CONNECTION=1 5%<br />
NOSTUFF<br />
1/20W<br />
2 201<br />
MF<br />
LOADISNS<br />
R5668<br />
0201<br />
0<br />
ISNS_CPUHIGAIN_R_N<br />
1 2 ISNS_CPUHIGAIN_N<br />
OUT 56<br />
PLACE_NEAR=U5660.10:10MM<br />
5%<br />
1/20W<br />
1<br />
R5661<br />
MF<br />
0201 R5669<br />
16K<br />
0<br />
1%<br />
54 52 ISNS_HS_COMPUTING_N 1 2<br />
IN<br />
1/20W<br />
PLACE_NEAR=U5660.10:10MM<br />
MF<br />
NO_XNET_CONNECTION=1 5%<br />
201<br />
1/20W<br />
2<br />
LOADISNS<br />
MF<br />
NO_XNET_CONNECTION=1<br />
0201<br />
In battery discharge scenario negative voltage will be<br />
present on IN+/- pins with INA output voltage decreasing<br />
from 3.3V with increasing discharge current.<br />
SENSE+ pins of EMC1704 sink 10-20uA current.<br />
This deviation has been designed in our Peak Detection circuit.<br />
With 10uA sink: 0.125A - 2.1A -> 13mV - 83 mV<br />
With 20uA sink: 0.125A - 2.1A -> 23mV - 92 mV<br />
LOADISNS<br />
1<br />
R5675<br />
20K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
LOADISNS<br />
PLACE_NEAR=U5700.24:5MM<br />
R56A9<br />
453K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
LOADISNS<br />
PLACE_NEAR=U5710.6:5MM<br />
R5679<br />
453K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
CPU GT IMON Current Sense (ICGM)<br />
Gain: 1 A / 17.963 mV, Range: 64 A.<br />
SMC ADC: 23<br />
LOADISNS<br />
50<br />
PLACE_NEAR=U5000.B7:5MM<br />
20%<br />
6.3V<br />
X5R LOADRC:YES<br />
0201 PLACE_NEAR=U5000.B8:5MM<br />
52<br />
53<br />
1<br />
2<br />
54<br />
48<br />
104 65<br />
55<br />
49<br />
50<br />
52<br />
53<br />
54<br />
50<br />
55<br />
67<br />
2 1<br />
IMON_A_CPUGT<br />
EADC2_BMON_DISCRETE_ISENSE<br />
EADC1_TBT_T_ISENSE<br />
1<br />
2<br />
C56A9<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
LOADISNS<br />
PLACE_NEAR=U5700.24:5MM<br />
GND_EADC1_COM<br />
R5608<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
PLACE_NEAR=U5000.A8:5MM<br />
GND_EADC2_COM<br />
SMC_CPUGT_IMON_ISENSE<br />
GND_SMC_AVSS<br />
With R7154 (Ri) set to 294 Ohm,<br />
R7410 (Rsen) set to 0.75 mOhm,<br />
R7194 set to 84.5 kOhm,<br />
Num Phases (N) is 3, and Io (ICCmax) is 64A,<br />
then 1A of Io gives 17.963mV at the Vimon.<br />
1<br />
0<br />
1 2<br />
C5679<br />
0.22UF<br />
20%<br />
2<br />
6.3V<br />
X5R<br />
0201<br />
PLACE_NEAR=U5710.6:5MM<br />
LOADISNS<br />
NOSTUFF<br />
1<br />
R5666<br />
0<br />
C5608<br />
0.22UF<br />
20%<br />
2<br />
6.3V<br />
X5R<br />
0201<br />
Power Sensors: Extended<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
4<br />
IN+<br />
IN+<br />
IN-<br />
IN-<br />
V+<br />
GND<br />
OUT<br />
REF<br />
NC<br />
NC<br />
NC<br />
NC<br />
IN+<br />
IN+<br />
3<br />
V+<br />
GND<br />
OUT<br />
REF<br />
NC<br />
NC<br />
NC<br />
NC<br />
OUT<br />
OUT<br />
OUT<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
OUT<br />
52<br />
55<br />
53<br />
54<br />
55<br />
54<br />
55<br />
LOADRC:YES<br />
PLACE_NEAR=U5000.A8:5MM<br />
48<br />
49<br />
50<br />
BRANCH<br />
52<br />
REVISION<br />
53<br />
55<br />
54<br />
DRAWING NUMBER<br />
PAGE<br />
SHEET<br />
OUT<br />
OUT<br />
50<br />
55<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
56 OF 145<br />
54 OF 119<br />
SIZE<br />
D<br />
D<br />
C<br />
B<br />
A
SYNC_MASTER=J79_JACK<br />
SYNC_DATE=05/10/2016<br />
D<br />
C<br />
B<br />
A<br />
101<br />
Gain: 200x, EDP: 2.574 A<br />
Rsense: 0.005 (R8054)<br />
Vsense: 12.87 mV, Range: 3 A<br />
SMC ADC: 15<br />
KB backlite Current Sense (IKBC)<br />
Gain: 200x, EDP: 300m A<br />
Rsense: 0.035 (R5730)<br />
Vsense: 10.5 mV, Range: 0.36 A<br />
EADC2: CH3<br />
NAND Current Sense (IHNC)<br />
PCH PrimeCore Current Sense (ISCC)<br />
55<br />
51<br />
PLACE_NEAR=R8054.4:5MM<br />
ISNS_PCHPRIMCORE_P<br />
101<br />
101<br />
117S0008<br />
117S0008<br />
117S0008<br />
117S0008<br />
PP5V_S4SW_ISNS<br />
52<br />
53<br />
54<br />
53<br />
53<br />
53<br />
54<br />
54<br />
54 53 52<br />
76<br />
76<br />
IN<br />
IN<br />
8<br />
ISNS_SSDNAND_IOUT<br />
ISNS_PCHPRIMCORE_N<br />
PP5V_S0<br />
PP5V_S0_KBD<br />
2<br />
100<br />
EADC1_LCDBKLT_ISENSE<br />
EADC1_P1V8SUS_ISENSE<br />
EADC1_TBT_T_ISENSE<br />
EADC1_PP3V3S0_T139_ISENSE<br />
EADC1_PP3V3S4_WLAN_ISENSE<br />
EADC1_BT_ISENSE<br />
EADC1_PP5V_T139_ISENSE<br />
EADC1_TBT_ISENSE<br />
GND_EADC1_COM<br />
12<br />
101<br />
57<br />
55<br />
101<br />
57<br />
55<br />
200x<br />
200x<br />
PCH PrimeCore Voltage Sense (VSCC)<br />
EADC2: CH7<br />
8 PPVCCPRIMCORE_SUS_PCH<br />
2<br />
PLACE_NEAR=U0500.V21:5MM<br />
54<br />
53<br />
52<br />
54<br />
PP3V3_S4SW_SNS<br />
53<br />
52<br />
EADC1<br />
PP5V_EADC1_AVDD<br />
SMC_SSDNAND_ISENSE<br />
57 OUT 50<br />
57<br />
PLACE_NEAR=R8054.3:5MM<br />
GND_SMC_AVSS<br />
PP3V3_S4SW_SNS<br />
PLACE_NEAR=U5730.2:3:10MM<br />
ISNS_KBBLT_P<br />
ISNS_KBBLT_N<br />
VSNS_PCHPRIMCORE<br />
(Write: 0x10 Read: 0x11)<br />
PICCOLO Current Sense (IHCC)<br />
SMBUS_2_SDA_Q 51<br />
SMBUS_2_SCL_Q 51<br />
PP2V5_ADC1_VREF<br />
ADC1_REFCOMP<br />
ISNS_PICCOLO_IOUT<br />
ISNS_PCHCORE_IOUT<br />
ISNS_KBBLT_IOUT<br />
2 RES,MTL FLIM,100K,1/16W,0201,SMD,LF<br />
C5749,C5779<br />
LOADRC:NO<br />
2<br />
RES,MTL FLIM,100K,1/16W,0201,SMD,LF<br />
RES,MTL FLIM,100K,1/16W,0201,SMD,LF<br />
C5769,C5778<br />
C5729,C5799<br />
LOADRC:NO<br />
LOADRC:NO<br />
2 RES,MTL FLIM,100K,1/16W,0201,SMD,LF<br />
C5709,C5789<br />
LOADRC:NO<br />
LOADISNS<br />
R5700<br />
10<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
BYPASS=U5700.12::5MM<br />
1<br />
2<br />
LOADISNS<br />
PLACE_NEAR=U5000.B1:5MM<br />
R5789<br />
C5702<br />
4.7UF<br />
20%<br />
10V<br />
X5R<br />
0402<br />
4.53K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
OMIT<br />
R5730<br />
1<br />
0.005<br />
1%<br />
1/3W<br />
MF<br />
0306-SHORT<br />
2<br />
LOADISNS<br />
BYPASS=U5700.12::5MM<br />
XW5700<br />
2<br />
SM<br />
22<br />
23<br />
24<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
1<br />
2<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
PLACE_NEAR=U5000.B1:5MM<br />
LOADRC:YES<br />
C5701<br />
0.1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
PLACE_NEAR=U5700.6:1MM<br />
PLACE_NEAR=U5700.25:1MM<br />
1<br />
3<br />
4<br />
1<br />
2<br />
C5789<br />
LOADISNS<br />
XW5764<br />
SM<br />
BYPASS=U5700.12::3MM<br />
12<br />
13<br />
U5700<br />
LTC2309<br />
QFN<br />
CRITICAL<br />
LOADISNS<br />
9<br />
10<br />
11<br />
18<br />
19<br />
20<br />
21<br />
2<br />
3<br />
4<br />
5<br />
PLACE_NEAR=U5730.4:5:10MM<br />
25<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
INA210A<br />
UQFN<br />
CRITICAL<br />
LOADISNS<br />
U5760<br />
9<br />
BYPASS=U5700.8::3MM<br />
PLACE_NEAR=U5710.5:5MM<br />
1<br />
2<br />
14<br />
15<br />
17<br />
16<br />
7<br />
8<br />
C5703<br />
0.1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
LOADISNS<br />
BYPASS=U5700.21::3MM<br />
1<br />
2<br />
6<br />
INA210A<br />
LOADISNS<br />
U5730<br />
UQFN<br />
CRITICAL<br />
9<br />
C5705<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
LOADISNS<br />
10<br />
8<br />
1<br />
7<br />
1<br />
2<br />
LOADISNS<br />
BYPASS=U5760.6::5MM<br />
1<br />
2<br />
C5760<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
10<br />
8<br />
1<br />
7<br />
1<br />
R5765<br />
20K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
NOSTUFF<br />
PLACE_NEAR=U5760.10:5MM<br />
10UF<br />
LOADISNS<br />
C5706<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-10<br />
LOADISNS<br />
LOADISNS<br />
BYPASS=U5730.6::5MM<br />
C5730<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
1<br />
R5735<br />
20K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
PART NUMBER QTY DESCRIPTION<br />
REFERENCE DES CRITICAL BOM OPTION<br />
CH0<br />
CH1<br />
CH2<br />
CH3<br />
CH4<br />
CH5<br />
CH6<br />
CH7<br />
COM<br />
7<br />
AVDD<br />
GND<br />
DVDD<br />
1<br />
2<br />
0.1UF<br />
NOSTUFF<br />
PLACE_NEAR=U5730.10:5MM<br />
R5764<br />
453K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
1<br />
2<br />
101<br />
55<br />
GND_EADC2_COM<br />
51<br />
T151 Current Sense (IIDC)<br />
EADC2: CH4<br />
PP5V_S4SW_ISNS<br />
453K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
ISNS_T151_IOUT<br />
EADC2_PCHPRIMCORE_VSENSE<br />
PLACE_NEAR=U5710.5:5MM<br />
1<br />
2<br />
2.2UF<br />
20%<br />
6.3V<br />
X5R-CERM<br />
0201<br />
LOADISNS<br />
C5764<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
LOADISNS<br />
C5700<br />
BYPASS=U5700.8::5MM<br />
BYPASS=U5700.7::5MM<br />
LOADISNS<br />
PLACE_NEAR=U5000.C2:5MM<br />
R5709<br />
4.53K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
SMC_PICCOLO_ISENSE<br />
GND_SMC_AVSS<br />
SMC_PCHPRIMCORE_ISENSE<br />
GND_SMC_AVSS<br />
LOADISNS<br />
PLACE_NEAR=U5710.1:5MM<br />
R5739<br />
1 2<br />
C5709<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
PLACE_NEAR=U5000.C2:5MM<br />
LOADRC:YES<br />
48 49 50 52 53 54 55<br />
48 49 50 52 53 54 55<br />
IN+<br />
IN+<br />
THRM<br />
PAD<br />
AD0<br />
AD1<br />
SDA<br />
SCL<br />
VREF<br />
REFCOMP<br />
V+<br />
GND<br />
IN+<br />
IN+<br />
OUT<br />
REF<br />
V+<br />
NC<br />
NC<br />
GND<br />
NC<br />
NC<br />
OUT<br />
REF<br />
NC<br />
NC<br />
NC<br />
NC<br />
6<br />
57<br />
54<br />
54<br />
54<br />
55<br />
55<br />
54<br />
55<br />
55 54<br />
1<br />
2<br />
LOADISNS<br />
PLACE_NEAR=U5000.A5:5MM<br />
R5769<br />
4.53K<br />
1 2 50<br />
1%<br />
1/20W<br />
MF<br />
201<br />
54<br />
55<br />
EADC2_KBBLT_ISENSE<br />
1<br />
2<br />
C5739<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
PLACE_NEAR=U5710.1:5MM<br />
LOADISNS<br />
GND_EADC2_COM<br />
BYPASS=U5710.12::=5MM<br />
1<br />
<br />
C5769<br />
LOADISNS<br />
0.22UF<br />
20%<br />
2<br />
6.3V<br />
X5R<br />
0201<br />
PLACE_NEAR=U5000.A5:5MM<br />
LOADRC:YES<br />
10<br />
5%<br />
1/20W<br />
MF<br />
201<br />
LOADISNS<br />
PLACE_NEAR=U5710.2:5MM<br />
R5759<br />
453K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
20%<br />
10V<br />
X5R<br />
0402<br />
BYPASS=U5710.12::5MM<br />
C5712<br />
4.7UF<br />
EADC2_LCDPANEL_ISENSE<br />
EADC2_PP3V3_TPAD_ISENSE<br />
EADC2_CAMERA_ISENSE<br />
EADC2_KBBLT_ISENSE<br />
EADC2_T151_ISENSE<br />
EADC2_BMON_DISCRETE_ISENSE<br />
EADC2_PCHPRIMCORE_VSENSE<br />
GND_EADC2_COM<br />
55<br />
R5710<br />
1 2<br />
1<br />
2<br />
5<br />
EADC2_T151_ISENSE<br />
1<br />
2<br />
C5759<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
PLACE_NEAR=U5710.2:5MM<br />
LOADISNS<br />
GND_EADC2_COM<br />
LOADISNS<br />
50<br />
XW5710<br />
2<br />
54<br />
OUT<br />
48<br />
55<br />
SM<br />
PP5V_EADC2_AVDD<br />
1<br />
2<br />
C5711<br />
0.1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
LOADISNS<br />
70<br />
70<br />
70<br />
70<br />
70<br />
CPU SA Current Sense (ICSC)<br />
Gain: 200x, EDP: 5.1 A<br />
Rsense: 0.002 (R7270)<br />
Vsense: 10.2 mV, Range: 7.5 A<br />
SMC ADC: 19<br />
Gain: 200x, EDP: 0.555 A<br />
Rsense: 0.025 (R5720) or Rsense SHORT<br />
Vsense: 13.875 mV, Range: 0.6 A<br />
SMC ADC: 16<br />
EADC2<br />
12<br />
13<br />
BYPASS=U5710.12::3MM<br />
AVDD<br />
22<br />
23<br />
24<br />
1<br />
2<br />
3<br />
4<br />
5<br />
PLACE_NEAR=U5710.6:1MM<br />
PLACE_NEAR=U5710.25:1MM<br />
49<br />
55<br />
1<br />
50<br />
52<br />
NC<br />
53<br />
54<br />
6<br />
55<br />
OUT<br />
CH0<br />
CH1<br />
CH2<br />
CH3<br />
CH4<br />
CH5<br />
CH6<br />
CH7<br />
COM<br />
54<br />
55<br />
70<br />
CPU GT+GTX Current Sense (ICGC)<br />
Gain: 188.49x, EDP: 64 A<br />
Rsense: 3x of 0.00075 (R7410, R7420, R7430), Rsum: 0.00025<br />
Vsense: 16 mV, Range: 63.66 A<br />
SMC ADC: 5<br />
R5745<br />
CPUGT_ISNS1_P<br />
4.42K<br />
1 2<br />
CPUGT_ISNS2_P<br />
CPUGT_ISNS3_P<br />
CPUGT_ISNS1_N<br />
CPUGT_ISNS2_N<br />
CPUGT_ISNS3_N<br />
PLACE_NEAR=R7270.3:5MM<br />
LPDDR 1.8V Current Sense (IM1C)<br />
55<br />
U5710<br />
LTC2309<br />
QFN<br />
CRITICAL<br />
LOADISNS<br />
GND<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
68<br />
68<br />
9<br />
10<br />
11<br />
18<br />
19<br />
20<br />
PLACE_NEAR=R7410.4:5MM<br />
PLACE_NEAR=R7420.4:5MM<br />
PLACE_NEAR=R7430.4:5MM<br />
PLACE_NEAR=R7410.3:5MM<br />
PLACE_NEAR=R7420.3:5MM<br />
PLACE_NEAR=R7430.3:5MM<br />
IN<br />
IN<br />
21<br />
100<br />
100<br />
DVDD<br />
CPUSA_ISNS_P<br />
CPUSA_ISNS_N<br />
PLACE_NEAR=R7270.4:5MM<br />
THRM<br />
PAD<br />
25<br />
AD0<br />
AD1<br />
SDA<br />
SCL<br />
VREF<br />
REFCOMP<br />
PP1V8_S3<br />
PP1V8_S3_MEM<br />
1<br />
2<br />
14<br />
15<br />
17<br />
16<br />
C5713<br />
0.1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
BYPASS=U5710.10::3MM<br />
7<br />
8<br />
EADC2_AD0<br />
R5712<br />
100K<br />
1 2<br />
5%<br />
1/20W NOSTUFF<br />
MF<br />
201<br />
PP5V_S4SW_ISNS 51 55 101<br />
SMBUS_2_SDA_Q 51<br />
SMBUS_2_SCL_Q 51<br />
PP2V5_ADC2_VREF<br />
ADC2_REFCOMP<br />
1<br />
4<br />
LOADISNS<br />
LOADISNS<br />
LOADISNS<br />
LOADISNS<br />
LOADISNS<br />
LOADISNS<br />
LOADISNS<br />
CPUGT_ISNS_R_P<br />
CPUGT_ISNS_R_N<br />
R5760<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
LOADISNS<br />
BYPASS=U5710.21::3MM<br />
C5715<br />
0.1UF<br />
10%<br />
2<br />
6.3V<br />
CERM-X5R<br />
0201<br />
LOADISNS<br />
0.1%<br />
1/20W<br />
MF<br />
0201<br />
R5746<br />
4.42K<br />
1 2<br />
0.1%<br />
1/20W<br />
MF<br />
0201<br />
R5747<br />
4.42K<br />
1 2<br />
0.1%<br />
1/20W<br />
MF<br />
0201<br />
R5748<br />
4.42K<br />
1 2<br />
0.1%<br />
1/20W<br />
MF<br />
0201<br />
R5757<br />
4.42K<br />
1 2<br />
0.1%<br />
1/20W<br />
MF<br />
0201<br />
R5758<br />
4.42K<br />
1 2<br />
0.1%<br />
1/20W<br />
MF<br />
0201<br />
1<br />
C5716<br />
10UF<br />
20%<br />
2<br />
10V<br />
X5R-CERM<br />
0402-10<br />
LOADISNS<br />
1<br />
2<br />
LOADISNS<br />
OMIT<br />
R5720 1<br />
0.005<br />
1%<br />
1/3W<br />
0306-SHORT<br />
MF<br />
2<br />
0<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
101<br />
R5761<br />
1 2<br />
C5710<br />
2.2UF<br />
20%<br />
6.3V<br />
X5R-CERM<br />
0201<br />
LOADISNS<br />
101<br />
(Write: 0x12 Read: 0x13)<br />
57<br />
57<br />
55<br />
55<br />
54<br />
54<br />
53<br />
53<br />
101<br />
52<br />
CPUSA_ISNS_R_P<br />
CPUSA_ISNS_R_N<br />
52<br />
ISNS_LPDDR_N<br />
57<br />
CPU SA Voltage Sense (VCSC)<br />
SMC ADC: 17<br />
100<br />
PP3V3_S4SW_SNS<br />
PP3V3_S4SW_SNS<br />
PLACE_NEAR=U5720.2:3:10MM<br />
ISNS_LPDDR_P<br />
BYPASS=U5710.7::5MM<br />
BYPASS=U5710.10::5MM<br />
3<br />
4<br />
LOADISNS<br />
R5742<br />
2.32K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
R5743<br />
2.32K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
LOADISNS<br />
PLACE_NEAR=R5760.2:5MM<br />
PLACE_NEAR=R5761.2:5MM<br />
PLACE_NEAR=U5720.4:5:10MM<br />
73<br />
73<br />
55<br />
54<br />
53<br />
52<br />
8<br />
101<br />
CPUGT_ISNS_P<br />
CPUGT_ISNS_N<br />
1<br />
R5744<br />
715K<br />
PLACE_NEAR=R7718.3:5MM<br />
IN<br />
IN<br />
3<br />
ISNS_CPUEDRAM_P<br />
ISNS_CPUEDRAM_N<br />
PLACE_NEAR=R7718.4:5MM<br />
PP3V3_S0<br />
0.1%<br />
1/20W<br />
MF<br />
2<br />
0201<br />
LOADISNS<br />
NO_XNET_CONNECTION=1<br />
PPVCCSA_S0_CPU<br />
2<br />
3<br />
4<br />
5<br />
2<br />
3<br />
4<br />
5<br />
IN+<br />
IN+<br />
IN+<br />
IN+<br />
IN-<br />
IN-<br />
IN-<br />
IN-<br />
IN-<br />
IN-<br />
IN-<br />
IN-<br />
IN-<br />
IN-<br />
6<br />
INA210A<br />
UQFN<br />
CRITICAL<br />
LOADISNS<br />
U5770<br />
PP3V3_S4SW_SNS<br />
200x<br />
9<br />
6<br />
INA210A<br />
UQFN<br />
CRITICAL<br />
LOADISNS<br />
U5720<br />
200x<br />
9<br />
2<br />
3<br />
4<br />
5<br />
V+<br />
GND<br />
V+<br />
GND<br />
IN+<br />
IN+<br />
200x<br />
BOM_COST_GROUP=SENSORS<br />
1<br />
3<br />
2 5<br />
XW5778<br />
SM<br />
1 2<br />
LOADISNS<br />
CRITICAL<br />
U5740<br />
ISL28133<br />
SC70-5<br />
4<br />
ISNS_LPDDR_IOUT<br />
CPUGT_ISUM_IOUT<br />
CPUSAVSENSE_IN<br />
ISNS_CPUSA_IOUT<br />
1<br />
R5740<br />
20K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
SMC_CPUSA_VSENSE<br />
GND_SMC_AVSS<br />
SMC_CPUSA_ISENSE<br />
SMC_DDR1V8_ISENSE<br />
CPU EDRAM Current Sense (ICEC)<br />
ISNS_CPUEDRAM_IOUT<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
R5749<br />
4.53K<br />
1 2<br />
1/20W 1%<br />
MF<br />
201<br />
NOSTUFF<br />
PLACE_NEAR=U5740.4:5MM<br />
LOADISNS<br />
0.1UF<br />
R5778<br />
4.53K<br />
1 2<br />
PLACE_NEAR=R7410.2:5 MM<br />
1%<br />
1/20W<br />
MF<br />
201<br />
PLACE_NEAR=U5000.A7:5MM<br />
OUT<br />
REF<br />
NC<br />
NC<br />
OUT<br />
REF<br />
NC<br />
NC<br />
6<br />
INA210A<br />
UQFN<br />
CRITICAL<br />
LOADISNS<br />
V+<br />
U5790<br />
9<br />
10<br />
8<br />
1<br />
7<br />
10<br />
8<br />
1<br />
7<br />
GND<br />
R5741<br />
715K<br />
1 2<br />
0.1%<br />
1/20W<br />
MF LOADISNS<br />
0201 NO_XNET_CONNECTION=1<br />
1<br />
2<br />
NC<br />
NC<br />
1<br />
2<br />
NC<br />
NC<br />
V+<br />
V-<br />
LOADISNS<br />
BYPASS=U5770.6::5MM<br />
C5770<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
OUT<br />
1<br />
R5775<br />
20K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
LOADISNS<br />
BYPASS=U5720.6::5MM<br />
C5720<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
REF<br />
NC<br />
NC<br />
1<br />
R5725<br />
20K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
NOSTUFF<br />
BYPASS=U5790.6::5MM<br />
10<br />
8<br />
1<br />
7<br />
1<br />
2<br />
LOADISNS<br />
C5790<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
1<br />
2<br />
BYPASS=U5740.5::5MM<br />
LOADISNS<br />
NOSTUFF<br />
PLACE_NEAR=U5770.10:5MM<br />
C5740<br />
LOADISNS<br />
PLACE_NEAR=U5720.10:5MM<br />
NC<br />
NC<br />
2 1<br />
1<br />
R5795<br />
20K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
NOSTUFF<br />
LOADISNS<br />
4.53K<br />
1<br />
2<br />
LOADISNS<br />
PLACE_NEAR=U5000.B4:5MM<br />
SMC_CPUGT_ISENSE<br />
1<br />
C5749<br />
0.22UF<br />
6.3V<br />
20%<br />
2 X5R<br />
0201<br />
LOADRC:YES<br />
PLACE_NEAR=U5000.B4:5MM<br />
GND_SMC_AVSS<br />
LOADRC:YES<br />
C5778<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201 PLACE_NEAR=U5000.A7:5MM<br />
GND_SMC_AVSS<br />
PLACE_NEAR=U5000.H1:5MM<br />
R5729<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
PLACE_NEAR=U5790.10:5MM<br />
PAGE TITLE<br />
PLACE_NEAR=U5000.A5:5MM<br />
R5779<br />
4.53K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
1<br />
2<br />
1<br />
2<br />
C5729<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
PLACE_NEAR=U5000.H1:5MM<br />
LOADRC:YES<br />
GND_SMC_AVSS<br />
Gain: 200x, EDP: 4.5 A<br />
Rsense: 0.003 (R7718)<br />
Vsense: 13.5 mV, Range: 5 A<br />
SMC ADC: 10<br />
LOADISNS<br />
C5779<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
PLACE_NEAR=U5000.A5:5MM<br />
LOADRC:YES<br />
PLACE_NEAR=U5000.A5:5MM<br />
R5799<br />
4.53K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
SMC_CPUEDRAM_ISENSE<br />
C5799<br />
0.22UF<br />
20%<br />
6.3V<br />
X5R<br />
0201<br />
PLACE_NEAR=U5000.A5:5MM<br />
LOADRC:YES<br />
GND_SMC_AVSS<br />
Power Sensors: Extended 2<br />
R<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
IV ALL RIGHTS RESERVED<br />
Apple Inc.<br />
1<br />
2<br />
48<br />
48<br />
48<br />
48<br />
49<br />
49<br />
49<br />
49<br />
OUT<br />
50<br />
50<br />
50<br />
50<br />
50<br />
BRANCH<br />
52<br />
52<br />
52<br />
52<br />
REVISION<br />
53<br />
53<br />
53<br />
53<br />
48<br />
54<br />
54<br />
54<br />
50<br />
54<br />
50<br />
49<br />
DRAWING NUMBER<br />
PAGE<br />
SHEET<br />
OUT<br />
OUT<br />
OUT<br />
55<br />
55<br />
50<br />
55<br />
55<br />
50<br />
52<br />
9.0.0<br />
53<br />
051-00777<br />
OUT<br />
54<br />
dvt-fab09-0<br />
57 OF 145<br />
55 OF 119<br />
50<br />
55<br />
SIZE<br />
D<br />
D<br />
C<br />
B<br />
A<br />
8 7 6<br />
5 4 3<br />
2 1
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
Thermal Sensor A:<br />
Thunderbolt Die, Airflow Left<br />
I2C Write: 0xD8, I2C Read: 0xD9<br />
Thermal Diode: TBT Die (TBT1)<br />
Placement Note:<br />
The P leg connects to THERMDA pin of the TBT<br />
chip, the N leg connect to pin AC22.<br />
26<br />
27<br />
BI<br />
BI<br />
101<br />
56<br />
PP3V3_S0<br />
TBTTHMSNS_D1_P<br />
TBTTHMSNS_D1_N<br />
TBTTHMSNS_D1_P<br />
MAKE_BASE=TRUE<br />
TBTTHMSNS_D1_N<br />
MAKE_BASE=TRUE<br />
Note: Use GND pin AC22 on U2800 for N leg.<br />
R5850<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
NO_XNET_CONNECTION=1<br />
PLACE_NEAR=U5850.2:5MM<br />
C5851 1<br />
2200PF<br />
2<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
TBTTHRM_SNS<br />
PLACE_NEAR=U5850.3:5MM<br />
PP3V3_S0_TBTTHMSNS_R<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
2<br />
3<br />
5<br />
10<br />
D+<br />
D-<br />
A0<br />
A1<br />
1<br />
U5850<br />
TMP461<br />
6<br />
V+<br />
CRITICAL<br />
QFN<br />
SCL<br />
SDA<br />
ALERT*/THERM2*<br />
THERM*<br />
GND<br />
9<br />
8<br />
7<br />
4<br />
TBTTHRM_SNS<br />
1<br />
2<br />
BYPASS=U5850.1::5MM<br />
C5850<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
TBTTHRM_SNS<br />
TBTTHRM_THRM:PU<br />
SMBUS_SMC_3_SCL<br />
SMBUS_SMC_3_SDA<br />
TBTTHMSNS_ALERT_L<br />
TBTTHMSNS_THM_L<br />
1<br />
R5851<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
1<br />
R5852<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
TBTTHRM_ALRT:PU<br />
BI 51<br />
BI 51<br />
OUT 50<br />
OUT 50<br />
U5850 I2C Address:<br />
TMP461 is 0x90/0x91.<br />
D<br />
C<br />
B<br />
A<br />
Thermal Sensor C:<br />
Thunderbolt Die, Air Flow Right<br />
I2C Write: 0xB8, I2C Read: 0xB9<br />
Thermal Diode: TBT Die (TBT2)<br />
Placement Note:<br />
The P leg connects to THERMDA pin of the TBT<br />
chip, the N leg connect to pin AC22.<br />
Note: Use GND pin AC22 on UB000 for N leg.<br />
Thermal Sensor B & CPU High Peak Detection:<br />
CPU Proximity, Memory Proximity, Fin Stack Left, Fin Stack Right<br />
I2C Write: 0xB8, I2C Read: 0xB9<br />
Thermal Diode: Fin Stack Left (Th2H)<br />
Placement Note:<br />
Place Q5871, Airflow thermal indicator, above<br />
the X100, on the TOP side.<br />
Thermal Diode: CPU Proximity (TC0P)<br />
Placement Note:<br />
Place Q5873 under the CPU,<br />
on the BOTTOM side.<br />
Thermal Diode: Memory Proximity (TM0P)<br />
Placement Note:<br />
Place Q5872 between two rows of Memory devices,<br />
between channel A and B, on the BOTTOM side.<br />
106<br />
101<br />
92<br />
93<br />
54<br />
BI<br />
BI<br />
101<br />
PP3V3_S0<br />
56<br />
PP3V3_S0<br />
RIO_TBTTHMSNS_D1_P<br />
RIO_TBTTHMSNS_D1_N<br />
Q5871 1<br />
BC846BLP<br />
DFN1006H4-3<br />
2 CRITICAL<br />
Q5873 1<br />
BC846BLP<br />
DFN1006H4-3<br />
BC846BLP<br />
3<br />
3<br />
2<br />
DFN1006H4-3<br />
2<br />
CPUTHMSNS_D1_P<br />
CPUTHMSNS_D1_N<br />
CPUTHMSNS_D2_P<br />
CRITICAL<br />
Q5872<br />
1<br />
3<br />
CPUTHMSNS_D2_N<br />
CPUTHMSNS_D3_P<br />
CRITICAL<br />
CPUTHMSNS_D3_N<br />
RIO_TBTTHMSNS_D1_P<br />
MAKE_BASE=TRUE<br />
RIO_TBTTHMSNS_D1_N<br />
MAKE_BASE=TRUE<br />
NO_XNET_CONNECTION=1<br />
54<br />
54<br />
PLACE_NEAR=U5870.8:5MM<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
PLACE_NEAR=U5870.9:5MM<br />
U5860 I2C Address:<br />
R5870<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
NO_XNET_CONNECTION=1<br />
PLACE_NEAR=U5870.6:5MM<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
PLACE_NEAR=U5870.7:5MM<br />
C5872 1<br />
2200PF<br />
2<br />
NO_XNET_CONNECTION=1<br />
PLACE_NEAR=U5870.10:5MM<br />
C5873 1<br />
2200PF<br />
2<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
PLACE_NEAR=U5870.11:5MM<br />
IN<br />
IN<br />
C5871 1<br />
2200PF<br />
2<br />
ISNS_CPUHIGAIN_P<br />
ISNS_CPUHIGAIN_N<br />
R5860<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
NO_XNET_CONNECTION=1<br />
PLACE_NEAR=U5860.2:5MM<br />
C5861 1<br />
2200PF<br />
2<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
TBTTHRM_SNS<br />
PLACE_NEAR=U5860.3:5MM<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
PP3V3_S0_TBTTHMSNS_T_R<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
TMP461 is 0x96/0x97.<br />
PP3V3_S0_CPUTHMSNS_TI_R<br />
6<br />
7<br />
8<br />
9<br />
10<br />
11<br />
1<br />
2<br />
1<br />
U5860<br />
TMP461<br />
CRITICAL<br />
2 D+<br />
QFN<br />
SCL<br />
3 D-<br />
SDA<br />
5 A0<br />
ALERT*/THERM2*<br />
NC<br />
10 A1 THERM*<br />
6<br />
TBTTHRM_SNS<br />
Placement Note:<br />
Place U5860 on the BOTTOM side, on the right portion<br />
of the board, 1" to the left of USB connector.<br />
U5870<br />
TMP513AISAR<br />
14<br />
16<br />
QFN<br />
CRITICAL<br />
17<br />
15<br />
5<br />
13<br />
3<br />
4<br />
12<br />
SMBUS_SMC_1_S0_SDA<br />
SMBUS_SMC_1_S0_SCL<br />
CPUTHMSNS_THM_L<br />
Thermal Sensor: Fin Stack Right (Th1H)<br />
Placement Note:<br />
Place U5870 at corner near right Fan,<br />
on the TOP side.<br />
1<br />
2<br />
9<br />
8<br />
7<br />
4<br />
Placement Note:<br />
Place U5850 on the BOTTOM side, on the left portion<br />
of the board, 1" to the right of USB connector.<br />
TBTTHRM_THRM:PU<br />
SMBUS_SMC_3_SCL<br />
SMBUS_SMC_3_SDA<br />
TBTTHMSNS_ALERT_T_L<br />
TBTTHMSNS_THM_T_L<br />
BYPASS=U5870.16::5MM<br />
C5870<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
CPUTHMSNS_FILTER<br />
CPUTHMSNS_ADDR_SEL<br />
CPUTHMSNS_ALERT_L<br />
1<br />
2<br />
BYPASS=U5860.1::5MM<br />
C5860<br />
0.1UF<br />
TBTTHRM_SNS<br />
1<br />
R5873<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
100K<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
51<br />
51<br />
1<br />
R5871<br />
1R5861<br />
1<br />
R5872<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
50<br />
50<br />
1<br />
R5862<br />
101<br />
SMBUS_SMC_3_SDA<br />
SMBUS_SMC_3_SCL<br />
CPUTHRM_ALRT:PU<br />
51<br />
51<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
TBTTHRM_ALRT:PU<br />
50<br />
50<br />
51<br />
51<br />
1<br />
0.47UF<br />
PP3V3_S0<br />
PLACE_NEAR=U5870.15:2.54MM<br />
C5874<br />
10%<br />
2<br />
6.3V<br />
CERM-X5R<br />
0201<br />
BOM_COST_GROUP=SENSORS<br />
X100 PROXIMITY<br />
AP_TEMP<br />
PLACE_NEAR=U3730::10MM<br />
6<br />
1<br />
HPA00330AI<br />
SOT563<br />
CRITICAL<br />
Placement note:<br />
PLACE U5<strong>820</strong> ON BOTTOM NEAR X100<br />
SYNC_MASTER=J79_JACK<br />
5<br />
V+<br />
U5<strong>820</strong><br />
2<br />
4<br />
3<br />
1<br />
2<br />
AP_TEMP<br />
C5<strong>820</strong><br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
WIFI_THMSNS_A0<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
AP_TEMP<br />
1<br />
R5<strong>820</strong><br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
WRITE ADDRESS: 0X92<br />
READ ADDRESS: 0X93<br />
Thermal Sensors<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
DXP1<br />
DXN1<br />
DXP2<br />
DXN2<br />
DXP3<br />
DXN3<br />
VIN+<br />
VIN-<br />
GND<br />
V+<br />
V+<br />
GND<br />
FILTER C<br />
THRM<br />
PAD<br />
A0<br />
ALERT<br />
SDA<br />
SCL<br />
GPIO<br />
BI<br />
BI<br />
OUT<br />
BI<br />
BI<br />
OUT<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
SDA<br />
SCL<br />
GND<br />
PAGE TITLE<br />
ADD0<br />
ALERT<br />
IV ALL RIGHTS RESERVED<br />
R<br />
NC<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
58 OF 145<br />
56 OF 119<br />
SYNC_DATE=09/24/2015<br />
SIZE<br />
D<br />
C<br />
B<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
EADC Current Sense (IADC)<br />
Gain: 200x, EDP: 200m A<br />
Rsense: 0.050 (R5950) or Rsense SHORT<br />
Vsense: 10 mV, Range: 0.25 A<br />
EADC2: CH7<br />
D<br />
101<br />
101<br />
PP5V_S4SW<br />
NO_XNET_CONNECTION=1<br />
PP5V_S4SW_ISNS<br />
1%<br />
1/3W<br />
MF<br />
0306-SHORT<br />
OMIT<br />
R5950 1<br />
0.005<br />
2<br />
3<br />
4<br />
TP_ISNS_EADCP<br />
TP_ISNS_EADCN<br />
D<br />
89<br />
89<br />
NAND Current Sense (IHNC)<br />
Gain: 200x, EDP: 4.25 A<br />
Rsense: 0.002 (R9430)<br />
Vsense: 8.5 mV, Range: 7.5 A<br />
SMC ADC: 14<br />
ISNS_SSDNAND_N<br />
ISNS_SSDNAND_P<br />
101<br />
ISNS_SSDNAND_N<br />
MAKE_BASE=TRUE<br />
ISNS_SSDNAND_P<br />
MAKE_BASE=TRUE<br />
PLACE_NEAR=R9430.3:5MM<br />
78<br />
57<br />
PLACE_NEAR=R9430.4:5MM<br />
PP3V3_S5<br />
5<br />
4<br />
IN-<br />
IN+<br />
3<br />
U5910<br />
INA210<br />
SC70<br />
CRITICAL<br />
LOADISNS<br />
200x<br />
GND<br />
2<br />
V+<br />
OUT<br />
REF<br />
6<br />
1<br />
1<br />
2<br />
BYPASS=U5910.3::5MM<br />
LOADISNS<br />
C5910<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
1<br />
R5915<br />
20K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
ISNS_SSDNAND_IOUT<br />
OUT<br />
55<br />
C<br />
NOSTUFF<br />
PLACE_NEAR=U5910.6:5MM<br />
C<br />
101<br />
101<br />
Piccolo Current Sense (IHCC)<br />
Gain: 200x, EDP: 4.06 A<br />
Rsense: 0.003 (R5520)<br />
Vsense: 12.18 mV, Range: 5 A<br />
SMC ADC: 13<br />
PP3V3_S5_SSD<br />
NO_XNET_CONNECTION=1<br />
OMIT<br />
0306-SHORT<br />
MF<br />
1/3W<br />
1%<br />
PP3V3_S5_SSD_LB<br />
2<br />
0.005<br />
R5920 1<br />
101<br />
PLACE_NEAR=U5920.4:10MM<br />
4 ISNS_PICCOLO_N<br />
3<br />
ISNS_PICCOLO_P<br />
PLACE_NEAR=U5920.5:10MM<br />
78<br />
57<br />
PP3V3_S5<br />
5<br />
4<br />
IN-<br />
IN+<br />
3<br />
U5920<br />
INA210<br />
SC70<br />
CRITICAL<br />
LOADISNS<br />
200x<br />
GND<br />
2<br />
V+<br />
OUT<br />
REF<br />
6<br />
1<br />
1<br />
2<br />
LOADISNS<br />
BYPASS=U5920.3::5MM<br />
C5920<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
1<br />
R5925<br />
20K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
NOSTUFF<br />
PLACE_NEAR=U5920.6:5MM<br />
ISNS_PICCOLO_IOUT<br />
OUT<br />
55<br />
B<br />
SMC Current Sense (ISMC)<br />
Gain: 391.67x, EDP: 0.2 A<br />
Rsense: 0.05 (R5940) or Rsense SHORT<br />
Vsense: 10 mV, Range: 0.21A<br />
EADC2: CH6<br />
101<br />
101<br />
T151 Current Sense (IIDC)<br />
Gain: 200x, EDP: 163.8m A<br />
Rsense: 0.050 (R5530) or Rsense SHORT<br />
Vsense: 819 mV, Range: 0.25 A<br />
EADC2: CH4<br />
PP3V3_S4<br />
NO_XNET_CONNECTION=1<br />
PP3V3_S4_MESA<br />
1%<br />
1/3W<br />
MF<br />
0306-SHORT<br />
OMIT<br />
R5930 1<br />
0.005<br />
2<br />
101<br />
PLACE_NEAR=U5930.2:3:10MM<br />
ISNS_T151_P<br />
3<br />
4<br />
55<br />
ISNS_T151_N<br />
PLACE_NEAR=U5930.4:5:10MM<br />
54<br />
53<br />
52<br />
PP3V3_S4SW_SNS<br />
2<br />
3<br />
4<br />
5<br />
IN+<br />
IN+<br />
IN-<br />
IN-<br />
6<br />
INA210A<br />
UQFN<br />
CRITICAL<br />
LOADISNS<br />
V+<br />
U5930<br />
200x<br />
9<br />
GND<br />
OUT<br />
REF<br />
NC<br />
NC<br />
10<br />
8<br />
1<br />
7<br />
1<br />
2<br />
NC<br />
NC<br />
LOADISNS<br />
BYPASS=U5930.6::5MM<br />
C5930<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
1<br />
R5935<br />
51K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
NOSTUFF<br />
PLACE_NEAR=U5930.10:5MM<br />
ISNS_T151_IOUT<br />
OUT<br />
55<br />
B<br />
A<br />
100<br />
49<br />
100<br />
48<br />
80<br />
PP3V3_G3H_SMC_ISNS<br />
PP3V3_G3H<br />
NO_XNET_CONNECTION=1<br />
0306-SHORT 2<br />
MF<br />
1/3W<br />
1%<br />
0.005<br />
R5940 1<br />
OMIT<br />
4<br />
3<br />
TP_ISNS_PP3V3G3H_SMCN<br />
TP_ISNS_PP3V3G3H_SMCP<br />
BOM_COST_GROUP=SENSORS<br />
SYNC_MASTER=J79_JACK<br />
Power Sensors:Extended 3<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
59 OF 145<br />
57 OF 119<br />
SYNC_DATE=04/14/2016<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
D<br />
FAN CONTROL<br />
PP3V3_S0 58 101<br />
PP3V3_S0 58 101<br />
C<br />
C<br />
R6000 1 2<br />
48<br />
OUT<br />
SMC_FAN_0_TACH<br />
R6005<br />
47K<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
47K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
FAN_LT_TACH<br />
43<br />
104<br />
48<br />
OUT<br />
SMC_FAN_1_TACH<br />
R6055<br />
47K<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R6050 1<br />
47K<br />
2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
FAN_RT_TACH<br />
43<br />
104<br />
R6001 1<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
1<br />
G<br />
Q6000<br />
DMN32D2LFB4<br />
DFN1006H4-3<br />
SYM_VER_3<br />
R6051 1<br />
100K<br />
5%<br />
1/20W<br />
201<br />
MF<br />
2<br />
1<br />
G<br />
Q6050<br />
DMN32D2LFB4<br />
DFN1006H4-3<br />
SYM_VER_3<br />
48<br />
IN<br />
SMC_FAN_0_CTL<br />
S<br />
2<br />
D<br />
3<br />
FAN_LT_PWM<br />
48 IN<br />
SMC_FAN_1_CTL<br />
S<br />
D<br />
2<br />
3<br />
FAN_RT_PWM<br />
43 104<br />
43 104<br />
B<br />
B<br />
FOR DEBUG FAN POWER<br />
PP5V_S0 43 101<br />
NOSTUFF<br />
J6000<br />
TH<br />
1 2<br />
A<br />
998-0470<br />
BOM_COST_GROUP=FAN<br />
SYNC_MASTER=J79_JACK<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
Fans<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
SYNC_DATE=08/21/2015<br />
dvt-fab09-0<br />
60 OF 145<br />
58 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
SPI ROM<br />
Quad-IO Mode (Mode 0 & 3) supported.<br />
SPI Frequency: 50MHz for CPU, 20MHz for SMC.<br />
SPI+SWD SAM Connector<br />
D<br />
59<br />
59 16<br />
101<br />
SPI_MLB_CS_L<br />
SPIROM_USE_MLB<br />
PP3V3_SUS<br />
2 A<br />
3 B<br />
5 C<br />
6 D<br />
8<br />
VCC<br />
U6101<br />
74LVC1G99<br />
SOT833<br />
CRITICAL<br />
GND<br />
4<br />
Y<br />
OE*<br />
7<br />
1<br />
1<br />
2<br />
BYPASS=U6101::3mm<br />
BYPASS=U6100::3mm<br />
C6101<br />
0.1UF<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
100<br />
0201<br />
2<br />
1<br />
64MBIT<br />
IO0<br />
SPI_MLB_CLK<br />
6<br />
WSON<br />
5 SPI_MLB_IO0_MOSI<br />
SPI_ALT_IO0_MOSI<br />
4<br />
3<br />
59 CLK<br />
DI(IO0)<br />
59<br />
59<br />
SPI_ALT_CLK<br />
59<br />
SPI_ALT_IO1_MISO<br />
6<br />
5<br />
59<br />
SPI_ALT_CS_L<br />
59<br />
OMIT_TABLE<br />
SPI_ALT_IO2_WP_L<br />
8<br />
7<br />
59<br />
SPIROM_USE_MLB<br />
1<br />
BI<br />
CS*<br />
IO1<br />
2 SPI_MLB_IO1_MISO<br />
SPI_ALT_IO3_HOLD_L<br />
10<br />
9<br />
SMC_TMS (SWDIO)<br />
SPI_MLB_IO2_WP_L<br />
3<br />
DO(IO1)<br />
59<br />
59<br />
BI<br />
59<br />
IO2<br />
104 80 66 50 SMC_RESET_L<br />
12<br />
11<br />
SMC_TCK (SWCLK)<br />
59 SPI_MLB_IO3_HOLD_L<br />
7<br />
OUT<br />
OUT<br />
IO3<br />
SPI_MLBROM_CS_L<br />
PLACE_NEAR=U6100.1:12MM<br />
C6100 1<br />
0.1UF<br />
2<br />
10%<br />
16V<br />
X5R-CERM<br />
U6100<br />
CRITICAL<br />
W25Q64FVZPIG<br />
WP*(IO2)<br />
HOLD*(IO3)<br />
GND<br />
8<br />
VCC<br />
THRM_PAD<br />
1<br />
2<br />
BYPASS=U6100::3mm<br />
CRITICAL<br />
C6102<br />
1UF<br />
20%<br />
10V<br />
X5R<br />
0201<br />
PP3V3_G3H<br />
SAMCONN<br />
CRITICAL<br />
J6100<br />
DF40PC-12DP-0.4V-51<br />
14<br />
16<br />
M-ST-SM<br />
13<br />
15<br />
16 59<br />
48 49<br />
48 49<br />
D<br />
4<br />
9<br />
NOTE: If HOLD* is asserted<br />
ROM will ignore SPI cycles<br />
in normal and Dual-IO modes.<br />
Quad SPI and QPI instructions require the non-volatile Quad Enable bit (QE)<br />
in Status Register-2 to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.<br />
C<br />
SPI Bus Series Termination (Modified per PDG)<br />
C<br />
PLACE_NEAR=J6100.10:5MM<br />
PLACE_NEAR=J6100.8:5MM<br />
PLACE_NEAR=J6100.6:5MM<br />
PLACE_NEAR=J6100.4:5MM<br />
PLACE_NEAR=J6100.3:5MM<br />
PLACE_NEAR=J6100.5:5MM<br />
SAMCONN SAMCONN SAMCONN SAMCONN SAMCONN SAMCONN<br />
1<br />
R6133<br />
0<br />
5%<br />
1/20W<br />
MF<br />
2 0201<br />
1<br />
R6132<br />
0<br />
5%<br />
1/20W<br />
MF<br />
2 0201<br />
1<br />
R6128<br />
0<br />
5%<br />
1/20W<br />
MF<br />
2 0201<br />
1<br />
R6127<br />
0<br />
5%<br />
1/20W<br />
MF<br />
2 0201<br />
1<br />
R6126<br />
0<br />
5%<br />
1/20W<br />
MF<br />
2 0201<br />
1<br />
R6125<br />
0 5%<br />
MF<br />
1/20W<br />
2 0201<br />
SPI_ALT_IO3_HOLD_L<br />
SPI_ALT_IO2_WP_L<br />
SPI_ALT_IO1_MISO<br />
SPI_ALT_IO0_MOSI<br />
SPI_ALT_CLK<br />
SPI_ALT_CS_L<br />
59<br />
59<br />
59<br />
59<br />
59<br />
59<br />
Sam Card ROM Slave<br />
B<br />
CPU Master<br />
13<br />
13<br />
13<br />
13<br />
17 13<br />
13<br />
IN<br />
IN<br />
BI<br />
BI<br />
BI<br />
BI<br />
SPI_CS0_R_L<br />
SPI_CLK_R<br />
SPI_MOSI_R<br />
(SPI_IO)<br />
SPI_MISO<br />
(SPI_IO)<br />
SPI_IO<br />
SPI_IO<br />
PLACE_NEAR=U0500.AV2:50MM<br />
PLACE_NEAR=U0500.AW3:50MM<br />
PLACE_NEAR=U0500.AW2:50MM<br />
PLACE_NEAR=U0500.AU4:50MM<br />
PLACE_NEAR=U0500.AU3:50MM<br />
R6118<br />
22<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R6111<br />
22<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
PLACE_NEAR=U0500.AV3:50MM<br />
R6113<br />
22<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R6119<br />
22<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R6110<br />
22<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R6112<br />
22<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
SPI_CS0_L<br />
SPI_CLK<br />
SPI_MOSI<br />
SPI_MISO_R<br />
SPI_IO2_R<br />
SPI_IO3_R<br />
R6121<br />
22<br />
1 2<br />
1/20W 5%<br />
MF<br />
201<br />
R6123<br />
22<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R6131<br />
22<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R6120<br />
22<br />
1 2<br />
PLACE_NEAR=U6100.1:12MM<br />
5%<br />
1/20W<br />
MF<br />
201<br />
PLACE_NEAR=U6100.6:12MM<br />
R6122<br />
22<br />
1 2<br />
PLACE_NEAR=U6100.5:12MM<br />
5%<br />
1/20W<br />
MF<br />
201<br />
PLACE_NEAR=U6100.2:12MM<br />
R6130<br />
22<br />
1 2<br />
PLACE_NEAR=U6100.3:12MM<br />
5%<br />
1/20W<br />
MF<br />
201<br />
PLACE_NEAR=U6100.7:12MM<br />
SPI_MLB_CS_L<br />
SPI_MLB_CLK<br />
SPI_MLB_IO0_MOSI<br />
SPI_MLB_IO1_MISO<br />
SPI_MLB_IO2_WP_L<br />
SPI_MLB_IO3_HOLD_L<br />
59<br />
59<br />
59<br />
59<br />
59<br />
59<br />
SPI ROM Slave<br />
B<br />
A<br />
BOM_COST_GROUP=CPU & CHIPSET<br />
SYNC_MASTER=J52_MLB<br />
SPI Debug Connector<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
REVISION<br />
BRANCH<br />
SYNC_DATE=05/12/2015<br />
DRAWING NUMBER<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
61 OF 145<br />
59 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
PLACE_NEAR=U6200:5MM<br />
R6280<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
PLACE_NEAR=U6200:5MM<br />
R6282<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
PLACE_NEAR=U6200:5MM<br />
R6281<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
1<br />
2<br />
C6281<br />
27PF<br />
5%<br />
6.3V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
NOSTUFF<br />
C6282<br />
47PF<br />
5%<br />
25V<br />
C0G<br />
0201<br />
8409_ASP2_SCLK_RC<br />
8409_ASP2_LRCLK_RC<br />
8409_ASP2_SDOUT_RC<br />
1<br />
2<br />
NOSTUFF<br />
C6283<br />
47PF<br />
5%<br />
25V<br />
C0G<br />
0201<br />
R6210<br />
33<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R6213<br />
33<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R6211<br />
33<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
PLACE_NEAR=U6200:5MM<br />
AUD_ASP2_SCLK<br />
PLACE_NEAR=U6200:5MM<br />
AUD_ASP2_LRCLK<br />
AUD_ASP2_SDIN<br />
PLACE_NEAR=U6200:5MM<br />
AUD_ASP2_SDOUT<br />
OUT<br />
OUT<br />
IN<br />
OUT<br />
61<br />
61<br />
61<br />
61<br />
AUDIO JACK CODEC<br />
D<br />
C<br />
PCH AUDIO<br />
104<br />
100<br />
63 62 60<br />
13<br />
13<br />
13<br />
105 13<br />
13<br />
PP1V8_S0<br />
IN<br />
IN<br />
IN<br />
OUT<br />
IN<br />
HDA_BIT_CLK<br />
HDA_SYNC<br />
HDA_SDOUT<br />
HDA_SDIN0<br />
HDA_RST_L<br />
1<br />
2<br />
U6200.B2:A1:3 MM<br />
C6203<br />
0.22UF<br />
10%<br />
10V<br />
CERM<br />
402<br />
R6203<br />
33<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
1<br />
U6200.E2:C3:3 MM<br />
C6204<br />
0.1UF<br />
10%<br />
10%<br />
2<br />
25V<br />
X5R<br />
2<br />
25V<br />
X5R<br />
0201<br />
0201<br />
PLACE_NEAR=U6200:5MM<br />
8409_HDA_SDIN0_R<br />
1<br />
U6200.C4:C3:3 MM<br />
C6201<br />
0.1UF<br />
B1<br />
B3<br />
A2<br />
C1<br />
A3<br />
1<br />
2<br />
C6205<br />
2.9PF<br />
+/-0.05PF<br />
25V<br />
C0G-CERM<br />
0201<br />
BCLK<br />
SYNC<br />
SDO<br />
SDI<br />
RST*<br />
E2<br />
VL_DM<br />
A6<br />
VA_PLL<br />
8409_VA_PLL<br />
B2<br />
VL_HD<br />
C4<br />
U6200<br />
CS8409<br />
WLCSP<br />
VL_SP<br />
1<br />
2<br />
ASP2_MCLK<br />
ASP2_SCLK<br />
ASP2_LRCK/FSYNC<br />
ASP2_SDIN<br />
ASP2_SDOUT<br />
U6200.A6:A5:3 MM<br />
C6200<br />
1UF<br />
10%<br />
25V<br />
X5R<br />
603-1<br />
F3<br />
F2<br />
E4<br />
E3<br />
F4<br />
NC<br />
8409_ASP2_SCLK_R<br />
8409_ASP2_LRCLK_R<br />
8409_ASP2_SDOUT_R<br />
PLACE_NEAR=U6200:5MM<br />
R6284<br />
R6283<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
0<br />
MF<br />
1 2 201<br />
5%<br />
1/20W R6285<br />
MF 0<br />
201 1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
PLACE_NEAR=U6200:5MM<br />
PLACE_NEAR=U6200:5MM<br />
1<br />
2<br />
C6285<br />
47PF<br />
5%<br />
25V<br />
C0G<br />
0201<br />
1<br />
2<br />
8409_ASP1_SCLK_RC<br />
8409_ASP1_LRCLK_RC<br />
8409_ASP1_SDOUT_RC<br />
NOSTUFF<br />
C6286<br />
47PF<br />
5%<br />
25V<br />
C0G<br />
0201<br />
1<br />
NOSTUFF<br />
C6287<br />
47PF<br />
5%<br />
2<br />
25V<br />
C0G<br />
0201<br />
R6219<br />
33<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R6221<br />
33<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R6223<br />
33<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R6220<br />
33<br />
AUD_ASP1B_SCLK<br />
PLACE_NEAR=U6200:5MM<br />
AUD_ASP1B_LRCLK<br />
1 2<br />
OUT 63<br />
5% PLACE_NEAR=U6200:5MM<br />
1/20W<br />
MF<br />
201 AUD_ASP1B_SDOUT<br />
OUT 63<br />
R6222<br />
33<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R6225<br />
33<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
PLACE_NEAR=U6200:5MM<br />
PLACE_NEAR=U6200:5MM<br />
AUD_ASP1A_SCLK<br />
PLACE_NEAR=U6200:5MM<br />
AUD_ASP1A_LRCLK<br />
PLACE_NEAR=U6200:5MM<br />
AUD_ASP1A_SDOUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
63<br />
62<br />
62<br />
62<br />
RIGHT SPEAKER AMPS<br />
LEFT SPEAKER AMPS<br />
C<br />
B<br />
3-MIC CONNECTOR<br />
APN: 518S0818<br />
J6200<br />
FF14A-6C-R11DL-B-3H<br />
F-RT-SM<br />
7<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
8<br />
DMIC1_DATA<br />
DMIC1_CLK<br />
PP1V8_S0 60 62 63 100 104<br />
104<br />
104<br />
104<br />
104<br />
DMIC2_DATA<br />
DMIC2_CLK<br />
R6206<br />
33<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R6208<br />
33<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R6205<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R6207<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
PLACE_NEAR=U6200:5MM<br />
8409_DMIC1_DATA<br />
PLACE_NEAR=U6200:5MM<br />
8409_DMIC1_CLK_R<br />
PLACE_NEAR=U6200:5MM<br />
8409_DMIC2_DATA<br />
PLACE_NEAR=U6200:5MM<br />
8409_DMIC2_CLK_R<br />
D2<br />
E1<br />
C2<br />
D1<br />
DMIC1_DATA<br />
DMIC1_CLK<br />
DMIC2_DATA<br />
DMIC2_CLK<br />
GNDL<br />
C3<br />
GND_PLL<br />
A5<br />
GNDD<br />
A1<br />
ASP1_MCLK<br />
ASP1_SCLK<br />
ASP1_LRCK/FSYNC<br />
ASP1_SDIN<br />
ASP1_SDOUT<br />
SPI_SCLK<br />
MOSI<br />
GPIO0/MISO1<br />
GPIO1/CS1*<br />
GPIO2/CS2*<br />
GPIO6/SCL<br />
GPIO7/SDA<br />
GPIO3/MISO2<br />
GPIO4<br />
GPIO5<br />
B6<br />
C5<br />
D6<br />
B5<br />
C6<br />
E6<br />
B4<br />
E5<br />
D5<br />
F5<br />
D4<br />
D3<br />
F6<br />
F1<br />
A4<br />
NC<br />
8409_ASP1_SCLK_R<br />
8409_ASP1_LRCLK_R<br />
NC<br />
8409_ASP1_SDOUT_R<br />
NC<br />
NC<br />
8409_SPKR_ID0<br />
8409_I2C_SCL<br />
8409_I2C_SDA<br />
NC<br />
NC<br />
NC<br />
1<br />
R6227<br />
47K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
IN<br />
62<br />
104<br />
1<br />
R6229<br />
<strong>820</strong><br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
1<br />
C6288<br />
100PF<br />
5%<br />
2<br />
25V<br />
C0G<br />
0201<br />
ESD<br />
1<br />
2<br />
<strong>820</strong><br />
5%<br />
25V<br />
C0G<br />
0201<br />
ESD<br />
PP1V8_S0 60 62 63 100 104<br />
1<br />
R6228<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
C6289<br />
100PF<br />
R6230<br />
33<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R6231<br />
33<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R6232<br />
33<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R6233<br />
33<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
PLACE_NEAR=U6200:5MM<br />
AMP_LT_I2C_SCL<br />
PLACE_NEAR=U6200:5MM<br />
AMP_CODEC_RT_I2C_SCL<br />
PLACE_NEAR=U6200:5MM<br />
AMP_LT_I2C_SDA<br />
PLACE_NEAR=U6200:5MM<br />
AMP_CODEC_RT_I2C_SDA<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
62<br />
61<br />
62<br />
61<br />
63<br />
63<br />
B<br />
PP1V8_S0 60 62 63 100 104<br />
A<br />
R6290 1<br />
47K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
CODEC_INT_L<br />
CODEC_RESET_L<br />
61<br />
61<br />
BOM_COST_GROUP=AUDIO<br />
DESIGN: X502/DEV_MLB_U<br />
LAST CHANGE: Wed Feb 18 17:12:24 2015<br />
SYNC_MASTER=J79_JCURCIO<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
HDA Bridge<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
IN<br />
OUT<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
SYNC_DATE=03/24/2016<br />
dvt-fab09-0<br />
62 OF 145<br />
60 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
AUDIO JACK CODEC I2C ADDRESS<br />
AD1<br />
AD0<br />
ADDRESS<br />
GND GND<br />
0x90
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
2X MONO SPEAKER AMPLIFIERS<br />
APN: 353S4074<br />
GAIN = TBD<br />
PLACE_NEAR=U6400.C4:3MM<br />
PLACE_NEAR=U6400.C4:3MM<br />
PLACE_NEAR=U6400.C4:3MM<br />
PPBUS_G3H 62 63 100<br />
D<br />
BYPASS=U6400.A1:A2:3 MM 1<br />
SPRAMP_5V_TL<br />
C6402<br />
2.2UF<br />
20%<br />
2<br />
10V<br />
X5R-CERM<br />
402<br />
1<br />
2<br />
C6403<br />
0.1UF<br />
10%<br />
16V<br />
X7R-CERM<br />
0402<br />
1<br />
2<br />
C6404<br />
1UF<br />
10%<br />
25V<br />
X5R<br />
603-1<br />
1<br />
2<br />
C6405<br />
22UF<br />
20%<br />
25V<br />
X5R-CERM<br />
0805<br />
D<br />
C<br />
TDM SLOT 1<br />
62 60<br />
62 60<br />
62 60<br />
IN<br />
IN<br />
IN<br />
104<br />
100<br />
63<br />
62<br />
60<br />
AUD_ASP1A_SCLK<br />
AUD_ASP1A_LRCLK<br />
AUD_ASP1A_SDOUT<br />
PP1V8_S0<br />
PLACE_NEAR=U6400.D1:3MM<br />
PLACE_NEAR=U6400:5MM<br />
PLACE_NEAR=U6400:5MM<br />
PLACE_NEAR=U6400:5MM<br />
62 60<br />
62 60<br />
C6400 1<br />
1UF<br />
2<br />
IN<br />
BI<br />
0<br />
0<br />
20%<br />
10V<br />
X5R<br />
0201<br />
R6400<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R6402<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
AMP_LT_I2C_SCL<br />
AMP_LT_I2C_SDA<br />
R6401<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
PLACE_NEAR=U6400.D1:3MM<br />
1<br />
2<br />
C6401<br />
0.1UF<br />
10%<br />
16V<br />
X7R-CERM<br />
0402<br />
AMP_TL_SCLK<br />
AMP_TL_LRCLK<br />
AMP_TL_SDOUT<br />
C1<br />
B1<br />
C2<br />
E2<br />
D2<br />
E1<br />
SCL<br />
SDA<br />
REG_EN<br />
BCLK<br />
FSYNC<br />
SDATA<br />
D1<br />
A1<br />
VREG18/DVDD<br />
VREG50/AVDD<br />
U6400<br />
SSM3515B<br />
WLCSP<br />
PGND<br />
PGND<br />
A3<br />
E3<br />
C3<br />
C4<br />
PVDD<br />
PVDD<br />
AGND<br />
A2<br />
BST+<br />
OUT+<br />
OUT+<br />
OUT-<br />
OUT-<br />
BST-<br />
ADDR<br />
E4<br />
D3<br />
D4<br />
B3<br />
B4<br />
A4<br />
B2<br />
SPKRAMP_BSTP_1<br />
SPKRAMP_TL_OUT_P<br />
MIN_LINE_WIDTH=0.4000<br />
MIN_NECK_WIDTH=0.1000<br />
SPKRAMP_TL_OUT_N<br />
MIN_LINE_WIDTH=0.4000<br />
MIN_NECK_WIDTH=0.1000<br />
SPKRAMP_BSTP_2<br />
SPKRAMP_LT_I2C_ADDR<br />
NO STUFF<br />
1<br />
R6408<br />
0<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
I2C ADDR<br />
0x2A / 0X15<br />
C6406<br />
0.22UF<br />
1 2<br />
20%<br />
25V<br />
X5R<br />
603<br />
C6407<br />
0.22UF<br />
1 2<br />
20%<br />
25V<br />
X5R<br />
603<br />
L6400<br />
180OHM-3.4A<br />
0806<br />
1 2<br />
1 2<br />
L6401<br />
180OHM-3.4A<br />
0806<br />
Speaker ID Uses 2 Center Connector Pins<br />
Confirm at Speaker Connector<br />
1<br />
2<br />
104<br />
104<br />
SPKRCONN_TL_OUT_P<br />
SPKRCONN_TL_OUT_N<br />
C6408<br />
220PF<br />
5%<br />
25V<br />
C0G-CERM<br />
0402<br />
1<br />
2<br />
C6409<br />
220PF<br />
5%<br />
25V<br />
C0G-CERM<br />
0402<br />
104 60<br />
OUT<br />
8409_SPKR_ID0<br />
10 PIN APN: 998-5655<br />
J6410<br />
FF14A-10C-R11DL-B-3H<br />
F-RT-SM1<br />
11<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10<br />
12<br />
LEFT TWEETER SPEAKER CONNECTOR<br />
C<br />
BYPASS=U6420.A1:A2:3 MM 1<br />
2<br />
SPRAMP_5V_WL<br />
C6422<br />
2.2UF<br />
20%<br />
10V<br />
X5R-CERM<br />
402<br />
PLACE_NEAR=U6400.C4:3MM<br />
PLACE_NEAR=U6400.C4:3MM<br />
1<br />
2<br />
C6423<br />
0.1UF<br />
10%<br />
16V<br />
X7R-CERM<br />
0402<br />
1<br />
2<br />
C6424<br />
1UF<br />
10%<br />
25V<br />
X5R<br />
603-1<br />
1<br />
2<br />
22UF<br />
PPBUS_G3H 62 63 100<br />
C6425<br />
20%<br />
25V<br />
X5R-CERM<br />
0805<br />
B<br />
TDM SLOT 2<br />
62 60<br />
62 60<br />
62 60<br />
IN<br />
IN<br />
IN<br />
104<br />
100<br />
63<br />
62<br />
60<br />
PLACE_NEAR=U6420:5MM<br />
AUD_ASP1A_SCLK<br />
PLACE_NEAR=U6420:5MM<br />
AUD_ASP1A_LRCLK<br />
PLACE_NEAR=U6420:5MM<br />
AUD_ASP1A_SDOUT<br />
PP1V8_S0<br />
62 60<br />
62 60<br />
C6420 1<br />
1UF<br />
20%<br />
2<br />
IN<br />
BI<br />
R6420<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R6422<br />
0<br />
10V<br />
X5R<br />
0201<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
AMP_LT_I2C_SCL<br />
AMP_LT_I2C_SDA<br />
R6421<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
1<br />
2<br />
C6421<br />
0.1UF<br />
10%<br />
16V<br />
X7R-CERM<br />
0402<br />
AMP_WL_SCLK<br />
AMP_WL_LRCLK<br />
AMP_WL_SDOUT<br />
C1<br />
B1<br />
C2<br />
E2<br />
D2<br />
E1<br />
SCL<br />
SDA<br />
REG_EN<br />
BCLK<br />
FSYNC<br />
SDATA<br />
D1<br />
A1<br />
VREG18/DVDD<br />
VREG50/AVDD<br />
U6420<br />
SSM3515B<br />
WLCSP<br />
PGND<br />
PGND<br />
A3<br />
E3<br />
C3<br />
C4<br />
PVDD<br />
PVDD<br />
AGND<br />
A2<br />
BST+<br />
OUT+<br />
OUT+<br />
OUT-<br />
OUT-<br />
BST-<br />
ADDR<br />
E4<br />
D3<br />
D4<br />
B3<br />
B4<br />
A4<br />
B2<br />
SPKRAMP_BSTP_3<br />
SPKRAMP_WL_OUT_P<br />
SPKRAMP_WL_OUT_N<br />
SPKRAMP_BSTP_4<br />
SPKRAMP_I2C_ADDR<br />
1<br />
R6423<br />
47K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
I2C ADDR<br />
0x28 / 0X14<br />
C6426<br />
0.22UF<br />
1 2<br />
20%<br />
25V<br />
X5R<br />
603<br />
C6427<br />
0.22UF<br />
1 2<br />
20%<br />
25V<br />
X5R<br />
603<br />
L6420<br />
180OHM-3.4A<br />
0806<br />
1 2<br />
1 2<br />
L6421<br />
180OHM-3.4A<br />
0806<br />
104<br />
104<br />
1<br />
2<br />
SPKRCONN_WL_OUT_P<br />
SPKRCONN_WL_OUT_N<br />
C6428<br />
220PF<br />
5%<br />
25V<br />
C0G-CERM<br />
0402<br />
1<br />
2<br />
C6429<br />
220PF<br />
5%<br />
25V<br />
C0G-CERM<br />
0402<br />
10 PIN APN: 998-5655<br />
J6430<br />
FF14A-10C-R11DL-B-3H<br />
F-RT-SM1<br />
11<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10<br />
12<br />
LEFT WOOFER SPEAKER CONNECTOR<br />
B<br />
A<br />
100<br />
63<br />
62<br />
PPBUS_G3H<br />
1<br />
2<br />
C6480<br />
33UF<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
1<br />
C6481<br />
33UF<br />
20%<br />
2 16V<br />
TANT-POLY<br />
CASE-B3<br />
1<br />
2<br />
C6482<br />
33UF<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
1<br />
2<br />
C6483<br />
33UF<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
C6484<br />
1<br />
33UF<br />
20%<br />
2 16V<br />
TANT-POLY<br />
CASE-B3<br />
1<br />
2<br />
C6485<br />
33UF<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
BOM_COST_GROUP=AUDIO<br />
DESIGN: X502/DEV_MLB_U<br />
LAST CHANGE: Wed Feb 18 17:12:24 2015<br />
SYNC_MASTER=J79_JCURCIO<br />
Left Speaker Amps & Conn<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
64 OF 145<br />
62 OF 119<br />
SYNC_DATE=11/18/2015<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
2X MONO SPEAKER AMPLIFIERS<br />
APN: 353S4073<br />
GAIN = TBD<br />
D<br />
BYPASS=U6500.A1:A2:3 MM<br />
SPKRAMP_5V_TR<br />
1<br />
2<br />
CRITICAL<br />
C6502<br />
2.2UF<br />
20%<br />
10V<br />
X5R-CERM<br />
402<br />
PLACE_NEAR=U6500.C4:3mm<br />
PLACE_NEAR=U6500.C4:3mm<br />
PLACE_NEAR=U6500.C4:3mm<br />
1<br />
2<br />
CRITICAL<br />
C6503<br />
0.1UF<br />
10%<br />
16V<br />
X7R-CERM<br />
0402<br />
1<br />
2<br />
CRITICAL<br />
C6504<br />
1UF<br />
10%<br />
25V<br />
X5R<br />
603-1<br />
1<br />
2<br />
CRITICAL<br />
C6505<br />
22UF<br />
20%<br />
25V<br />
X5R-CERM<br />
0805<br />
PPBUS_G3H 62 63 100<br />
D<br />
C<br />
TDM SLOT 3<br />
104<br />
100<br />
63 61 60<br />
63 61 60<br />
63<br />
62<br />
60<br />
PLACE_NEAR=U6500:5mm<br />
PLACE_NEAR=U6500:5mm<br />
PLACE_NEAR=U6500:5mm<br />
PP1V8_S0<br />
PLACE_NEAR=U6500.D1:3mm<br />
CRITICAL<br />
IN<br />
BI<br />
C6500 1<br />
1UF<br />
2<br />
AMP_CODEC_RT_I2C_SCL<br />
AMP_CODEC_RT_I2C_SDA<br />
0<br />
5%<br />
1/20W<br />
MF<br />
201<br />
5%<br />
1/20W<br />
MF<br />
201<br />
20%<br />
10V<br />
X5R<br />
0201<br />
R6500<br />
1 2<br />
R6502<br />
0<br />
1 2<br />
R6501<br />
0<br />
AMP_TR_SCLK<br />
1 2AMP_TR_LRCLK<br />
5%<br />
1/20W<br />
MF<br />
201<br />
PLACE_NEAR=U6500.D1:3mm<br />
CRITICAL<br />
1<br />
2<br />
C6501<br />
0.1UF<br />
10%<br />
16V<br />
X7R-CERM<br />
0402<br />
AMP_TR_SDOUT<br />
C1<br />
B1<br />
C2<br />
E2<br />
D2<br />
E1<br />
SCL<br />
SDA<br />
REG_EN<br />
BCLK<br />
FSYNC<br />
SDATA<br />
D1<br />
A1<br />
VREG18/DVDD<br />
VREG50/AVDD<br />
U6500<br />
SSM3515B<br />
WLCSP<br />
PGND<br />
PGND<br />
A3<br />
E3<br />
C3<br />
C4<br />
PVDD<br />
PVDD<br />
AGND<br />
A2<br />
BST+<br />
OUT+<br />
OUT+<br />
OUT-<br />
OUT-<br />
BST-<br />
ADDR<br />
E4<br />
D3<br />
D4<br />
B3<br />
B4<br />
A4<br />
B2<br />
RIO_SPKRAMP_BSTP_1<br />
SPKRAMP_TR_OUT_P<br />
MIN_LINE_WIDTH=0.4000<br />
MIN_NECK_WIDTH=0.1000<br />
SPKRAMP_TR_OUT_N<br />
MIN_LINE_WIDTH=0.4000<br />
MIN_NECK_WIDTH=0.1000<br />
RIO_SPKRAMP_BSTP_2<br />
U6400_B2<br />
1<br />
R6503<br />
47K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
I2C ADDRESS<br />
0x2C / 0X16<br />
C6506<br />
0.22UF<br />
1 2<br />
20%<br />
25V<br />
X5R<br />
603<br />
C6507<br />
0.22UF<br />
1 2<br />
20%<br />
25V<br />
X5R<br />
603<br />
BYPASS=U6500.E4:D4:3 MM<br />
PLACE_NEAR=U6500.D4:5mm<br />
FL6500<br />
180OHM-3.4A<br />
1 2<br />
0806<br />
0806<br />
1 2<br />
FL6501<br />
180OHM-3.4A<br />
PLACE_NEAR=U6500.B4:5mm<br />
BYPASS=U6500.A4:B4:3 MM<br />
CRITICAL<br />
CRITICAL<br />
C6508 1<br />
220PF<br />
2<br />
5%<br />
25V<br />
C0G-CERM<br />
0402<br />
CRITICAL<br />
1<br />
2<br />
104<br />
104<br />
SPKRCONN_TR_OUT_P<br />
MIN_LINE_WIDTH=0.4000<br />
MIN_NECK_WIDTH=0.1000<br />
DIFFERENTIAL_PAIR=DP_RIO_SPKRAMP_BSTP_<br />
SPKRCONN_TR_OUT_N<br />
MIN_LINE_WIDTH=0.4000<br />
MIN_NECK_WIDTH=0.1000<br />
DIFFERENTIAL_PAIR=DP_RIO_SPKRAMP_BSTP_<br />
C6509<br />
220PF<br />
5%<br />
25V<br />
C0G-CERM<br />
0402<br />
CRITICAL<br />
10-PIN APN: 998-5655<br />
J6500<br />
FF14A-10C-R11DL-B-3H<br />
1<br />
2<br />
3<br />
4<br />
5<br />
NC<br />
6<br />
NC<br />
7<br />
8<br />
9<br />
10<br />
12<br />
F-RT-SM1<br />
11<br />
RIGHT TWEETER SPEAKER CONNECTOR<br />
C<br />
PP1V8_S0 60 62 63 100 104<br />
60<br />
IN<br />
AUD_ASP1B_SCLK<br />
BYPASS=U6550.A1:A2:3 MM<br />
SPKRAMP_5V_WR<br />
1<br />
2<br />
CRITICAL<br />
C6552<br />
2.2UF<br />
20%<br />
10V<br />
X5R-CERM<br />
402<br />
PLACE_NEAR=U6550.C4:3mm<br />
PLACE_NEAR=U6550.C4:3mm<br />
PLACE_NEAR=U6550.C4:3mm<br />
1<br />
2<br />
CRITICAL<br />
C6553<br />
0.1UF<br />
10%<br />
16V<br />
X7R-CERM<br />
0402<br />
CRITICAL<br />
1<br />
C6554<br />
1UF<br />
10%<br />
2<br />
25V<br />
X5R<br />
603-1<br />
1<br />
2<br />
CRITICAL<br />
C6555<br />
22UF<br />
20%<br />
25V<br />
X5R-CERM<br />
0805<br />
PPBUS_G3H 62 63 100<br />
B<br />
60<br />
60<br />
IN<br />
IN<br />
AUD_ASP1B_LRCLK<br />
AUD_ASP1B_SDOUT<br />
TDM SLOT 4<br />
104<br />
100<br />
63 61 60<br />
63 61 60<br />
63<br />
62<br />
60<br />
PLACE_NEAR=U6550:5mm<br />
PLACE_NEAR=U6550:5mm<br />
PLACE_NEAR=U6550:5mm<br />
PP1V8_S0<br />
PLACE_NEAR=U6550.D1:3mm<br />
CRITICAL<br />
IN<br />
BI<br />
C6550 1<br />
1UF<br />
2<br />
AMP_CODEC_RT_I2C_SCL<br />
AMP_CODEC_RT_I2C_SDA<br />
R6550<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R6552<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
20%<br />
10V<br />
X5R<br />
0201<br />
R6551<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
PLACE_NEAR=U6550.D1:3mm<br />
CRITICAL<br />
1<br />
2<br />
C6551<br />
0.1UF<br />
10%<br />
16V<br />
X7R-CERM<br />
0402<br />
AMP_WR_SCLK<br />
AMP_WR_LRCLK<br />
AMP_WR_SDOUT<br />
C1<br />
B1<br />
C2<br />
E2<br />
D2<br />
E1<br />
SCL<br />
SDA<br />
REG_EN<br />
BCLK<br />
FSYNC<br />
SDATA<br />
D1<br />
A1<br />
VREG18/DVDD<br />
VREG50/AVDD<br />
U6550<br />
SSM3515B<br />
WLCSP<br />
PGND<br />
PGND<br />
A3<br />
E3<br />
C3<br />
C4<br />
PVDD<br />
PVDD<br />
AGND<br />
A2<br />
BST+<br />
OUT+<br />
OUT+<br />
OUT-<br />
OUT-<br />
BST-<br />
ADDR<br />
E4<br />
D3<br />
D4<br />
B3<br />
B4<br />
A4<br />
B2<br />
RIO_SPKRAMP_BSTP_3<br />
SPKRAMP_WR_OUT_P<br />
MIN_LINE_WIDTH=0.4000<br />
MIN_NECK_WIDTH=0.1000<br />
SPKRAMP_WR_OUT_N<br />
MIN_LINE_WIDTH=0.4000<br />
MIN_NECK_WIDTH=0.1000<br />
RIO_SPKRAMP_BSTP_4<br />
I2C ADDRESS<br />
0x2E / 0X17<br />
C6556<br />
0.22UF<br />
1 2<br />
20%<br />
25V<br />
X5R<br />
603<br />
C6557<br />
0.22UF<br />
1 2<br />
20%<br />
25V<br />
X5R<br />
603<br />
PP1V8_S0 60 62 63 100 104<br />
BYPASS=U6550.E4:D4:3 MM<br />
PLACE_NEAR=U6550.D4:5mm<br />
FL6502<br />
180OHM-3.4A<br />
1 2<br />
0806<br />
0806<br />
1 2<br />
FL6503<br />
180OHM-3.4A<br />
PLACE_NEAR=U6550.B4:5mm<br />
BYPASS=U6550.A4:B4:3 MM<br />
CRITICAL<br />
CRITICAL<br />
C6558 1<br />
220PF<br />
2<br />
5%<br />
25V<br />
C0G-CERM<br />
0402<br />
CRITICAL<br />
104<br />
104<br />
SPKRCONN_WR_OUT_P<br />
MIN_LINE_WIDTH=0.4000<br />
MIN_NECK_WIDTH=0.1000<br />
DIFFERENTIAL_PAIR=DP1_RIO_SPKRAMP_BSTP_<br />
SPKRCONN_WR_OUT_N<br />
MIN_LINE_WIDTH=0.4000<br />
MIN_NECK_WIDTH=0.1000<br />
DIFFERENTIAL_PAIR=DP1_RIO_SPKRAMP_BSTP_<br />
1<br />
2<br />
C6559<br />
220PF<br />
5%<br />
25V<br />
C0G-CERM<br />
0402<br />
CRITICAL<br />
10-PIN APN: 998-5655<br />
J6550<br />
FF14A-10C-R11DL-B-3H<br />
F-RT-SM1<br />
11<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10<br />
12<br />
RIGHT WOOFER SPEAKER CONNECTOR<br />
B<br />
A<br />
100<br />
63<br />
62<br />
PPBUS_G3H<br />
1<br />
CRITICAL<br />
C6580<br />
33UF<br />
20%<br />
2 16V<br />
TANT-POLY<br />
CASE-B3<br />
1<br />
2<br />
CRITICAL<br />
C6581<br />
33UF<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
1<br />
2<br />
CRITICAL<br />
C6582<br />
33UF<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
1<br />
2<br />
CRITICAL<br />
C6583<br />
33UF<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
1<br />
2<br />
CRITICAL<br />
C6584<br />
33UF<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
1<br />
2<br />
CRITICAL<br />
C6585<br />
33UF<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
BOM_COST_GROUP=AUDIO<br />
DESIGN: X502/DEV_MLB_U<br />
LAST CHANGE: Wed Feb 18 17:12:24 2015<br />
SYNC_MASTER=J79_JCURCIO<br />
Right Speaker Amps & Conn<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
65 OF 145<br />
63 OF 119<br />
SYNC_DATE=12/03/2015<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
CODEC OUTPUT SIGNAL PATHS<br />
xxxxxxxxxxxxxxxxxxx<br />
SUB<br />
FUNCTION<br />
HP/HS OUT<br />
TWEETERS<br />
SPDIF OUT<br />
VOLUME<br />
0X02 (2)<br />
0X03 (3)<br />
0X04 (4)<br />
N/A<br />
CONVERTER<br />
0X03 (3)<br />
0X04 (4)<br />
0X0E (14)<br />
PIN COMPLEX<br />
0X02 (2) 0X10 (16)<br />
0X12 (18)<br />
0X13 (19)<br />
0X21 (33)<br />
MUTE CONTROL<br />
N/A<br />
CODEC GPIO0<br />
CODEC GPIO0<br />
N/A<br />
LEFT SPEAKER ID<br />
RIGHT SPEAKER ID<br />
DFET CONTROL<br />
OTHER CODEC GPIO LINES<br />
GPIO2<br />
GPIO3<br />
GPIO4<br />
INPUT<br />
INPUT<br />
OUTPUT<br />
HIGH = FG, LOW = MERRY<br />
HIGH = FG, LOW = MERRY<br />
HIGH = DFETs OPEN<br />
D<br />
FUNCTION<br />
DMIC 1<br />
DMIC 2<br />
CONVERTER<br />
0X09 (9)<br />
0X09 (9)<br />
PIN COMPLEX<br />
0X1C (28)<br />
VREF<br />
3.3V<br />
3.3V<br />
xxxxxxxxxx<br />
CODEC INPUT SIGNAL PATHS<br />
0X1C (28)<br />
D<br />
HEADSET MIC<br />
0X07 (7)<br />
0X18 (24)<br />
2.7V<br />
C<br />
61<br />
61<br />
61<br />
61<br />
61<br />
61<br />
61<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
AUD_HP_PORT_L<br />
AUD_HP_PORT_R<br />
AUD_HP_PORT_US_GND<br />
AUD_HP_PORT_CH_GND<br />
AUD_HP_SENSE_L<br />
AUD_HP_SENSE_R<br />
AUD_TIP_SENSE<br />
CRITICAL<br />
FL6601<br />
120-OHM-25%-1.3A<br />
1 2<br />
0402<br />
CRITICAL<br />
FL6600<br />
120-OHM-25%-1.3A<br />
1 2<br />
0402<br />
CRITICAL<br />
FL6603<br />
120-OHM-25%-1.3A<br />
1 2<br />
0402<br />
CRITICAL<br />
FL6605<br />
120-OHM-25%-1.3A<br />
1 2<br />
0402<br />
CRITICAL<br />
FL6606<br />
120-OHM-25%-1.3A<br />
1 2<br />
0402<br />
CRITICAL<br />
FL6607<br />
120-OHM-25%-1.3A<br />
1 2<br />
0402<br />
CRITICAL<br />
L6605<br />
FERR-470-OHM<br />
1 2<br />
0201<br />
104 64<br />
104 64<br />
104 64<br />
104 64<br />
104<br />
104<br />
104<br />
AUD_CONN_HP_LEFT<br />
MIN_LINE_WIDTH=0.0730<br />
MIN_NECK_WIDTH=0.0850<br />
AUD_CONN_HP_RIGHT<br />
MIN_LINE_WIDTH=0.0730<br />
MIN_NECK_WIDTH=0.0850<br />
AUD_CONN_RING2<br />
MIN_LINE_WIDTH=0.0730<br />
MIN_NECK_WIDTH=0.0850<br />
AUD_CONN_SLEEVE<br />
MIN_LINE_WIDTH=0.0730<br />
MIN_NECK_WIDTH=0.0850<br />
AUD_CONN_HP_SENSE_L<br />
AUD_CONN_HP_SENSE_R<br />
AUD_CONN_TIP_SENSE<br />
Audio Jack Flex Connector<br />
APN: 516S00055<br />
(Matching plug APN: 516S1055)<br />
NC<br />
J6600<br />
503304-2040<br />
22<br />
21<br />
F-ST-SM<br />
1 2<br />
3 4<br />
5 6<br />
7 8<br />
9 10<br />
11 12<br />
13 14<br />
15 16<br />
17 18<br />
19 20<br />
23<br />
24<br />
AUD_CONN_HP_LEFT<br />
AUD_CONN_HP_RIGHT<br />
AUD_CONN_RING2<br />
AUD_CONN_SLEEVE<br />
64<br />
64<br />
64<br />
64<br />
104<br />
104<br />
104<br />
104<br />
C<br />
B<br />
61<br />
61<br />
OUT<br />
OUT<br />
AUD_HS_MIC_P<br />
AUD_HS_MIC_N<br />
CRITICAL<br />
FL6602<br />
120-OHM-25%-1.3A<br />
1 2<br />
0402<br />
CRITICAL<br />
FL6604<br />
120-OHM-25%-1.3A<br />
1 2<br />
0402<br />
104<br />
104<br />
AUD_CONN_SLEEVE_XW<br />
MIN_LINE_WIDTH=0.0920<br />
MIN_NECK_WIDTH=0.0920<br />
AUD_CONN_RING2_XW<br />
MIN_LINE_WIDTH=0.0920<br />
MIN_NECK_WIDTH=0.0920<br />
B<br />
A<br />
BOM_COST_GROUP=AUDIO<br />
DESIGN: X502/DEV_MLB_U<br />
LAST CHANGE: Wed Feb 18 17:12:24 2015<br />
SYNC_MASTER=J79_JCURCIO<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
AUDIO JACK CONNECTOR<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
66 OF 145<br />
64 OF 119<br />
SYNC_DATE=12/18/2015<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
J79 Battery Hotbar Flex Pads<br />
D<br />
J6950<br />
PWR-MLB-X362<br />
HB-SM<br />
11<br />
10<br />
J6951<br />
FF14A-6C-R11DL-B-3H<br />
F-RT-SM<br />
7<br />
D<br />
13<br />
14<br />
1<br />
2<br />
12<br />
9<br />
8<br />
7<br />
3<br />
6<br />
4 5<br />
C6950 1<br />
0.1UF<br />
10%<br />
25V<br />
2<br />
X5R<br />
402<br />
PPVBAT_G3H_CONN<br />
C6960 1<br />
1UF<br />
2<br />
10%<br />
25V<br />
X5R<br />
603-1<br />
66<br />
104<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
8<br />
NC<br />
104<br />
SYS_DETECT_L<br />
1<br />
R6950<br />
10K<br />
5%<br />
1/16W<br />
MF-LF<br />
2 402<br />
SMBUS_SMC_5_G3_SCL<br />
SMBUS_SMC_5_G3_SDA<br />
BMON_IOUT<br />
D6950<br />
RCLAMP3552T<br />
SLP1006N3T<br />
CRITICAL<br />
1<br />
3<br />
2<br />
BI<br />
BI<br />
OUT<br />
51 104<br />
51 104<br />
54 104<br />
C<br />
BMU POWER FLEX HOTBAR'd TO THE MLB:<br />
PART NUMBER QTY DESCRIPTION<br />
REFERENCE DES CRITICAL BOM OPTION<br />
632-00566 1 PCBA,FLEX,BMU PWR,X362<br />
J6950<br />
CRITICAL<br />
C<br />
B<br />
100<br />
104 66<br />
FROM PBUS<br />
PPBUS_G3H<br />
PPDCIN_G3H_CHGR<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=20V<br />
FROM DCIN<br />
R6902<br />
0<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
R6907<br />
2.2<br />
1 2<br />
5%<br />
1/8W<br />
MF-LF<br />
805<br />
PPBUS_G3H_R<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=8.6V<br />
PPDCIN_G3H_CHGR_R<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=20V<br />
D6902<br />
BAT30CWFILM<br />
SOT-323<br />
1<br />
3<br />
2<br />
66<br />
PPVIN_G3H_P3V3G3H<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=8.6V<br />
66<br />
1<br />
2<br />
C6905<br />
2.2UF<br />
20%<br />
35V<br />
X5R-CERM<br />
0402<br />
PM_EN_P3V3_G3H<br />
1<br />
2<br />
C6906<br />
2.2UF<br />
20%<br />
35V<br />
X5R-CERM<br />
0402<br />
NC<br />
2<br />
7<br />
10<br />
6<br />
SUP<br />
MODE<br />
EN<br />
RESET*<br />
U6903<br />
MAX77596<br />
TDFN<br />
CRITICAL<br />
AGND<br />
PGND<br />
5<br />
4<br />
XW6900<br />
SM<br />
1 2<br />
EPAD<br />
11<br />
BST<br />
LX<br />
OUT/FB<br />
BIAS<br />
1<br />
3<br />
9<br />
8<br />
P3V3G3H_VBST<br />
P3V3G3H_LX<br />
P3V3G3H_FB<br />
R69081 0<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
2<br />
P3V3G3H_BIAS<br />
1<br />
2<br />
C6910<br />
0.33UF<br />
10%<br />
16V<br />
CERM-X7R<br />
603<br />
P3V3G3H_VBST_R<br />
1<br />
2<br />
C6907<br />
0.1UF<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
L6900<br />
10UH-20%-1.4A-0.399OHM<br />
1 2<br />
PIYA25201B-SM<br />
1<br />
R6911<br />
47K<br />
0.1%<br />
1/20W<br />
MF<br />
2<br />
0201<br />
R6910<br />
115K<br />
1 2<br />
0.1%<br />
1/20W<br />
MF<br />
0201<br />
P3V3G3H_FB_RC<br />
C6911<br />
5.6PF<br />
2<br />
1<br />
+/-0.1PF<br />
25V<br />
C0G<br />
0201<br />
1<br />
R6912<br />
10<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
P3V3G3H_FB_R<br />
1<br />
2<br />
C6912<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
R6915<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
1<br />
2<br />
0<br />
1 2<br />
C6913<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
2.4G DESENSE<br />
5G DESENSE<br />
PP3V3_G3H 100 104<br />
1<br />
2<br />
1<br />
2<br />
CRITICAL<br />
C6920<br />
C6914<br />
10UF<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
1<br />
2<br />
1<br />
2<br />
CRITICAL<br />
C6921<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
PP3V3_G3H_REG_R<br />
VOLTAGE=3.3V<br />
C6915<br />
10UF<br />
3.0PF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
1<br />
2<br />
C6916<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
1<br />
2<br />
C6917<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
B<br />
P3V3G3H_AGND<br />
1<br />
R6913<br />
1.47K<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
A<br />
BOM_COST_GROUP=PLATFORM POWER<br />
SYNC_MASTER=J79_JSHAO<br />
DC-In & Battery Connectors<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
69 OF 145<br />
65 OF 119<br />
SYNC_DATE=12/03/2015<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
1<br />
2<br />
CRITICAL<br />
C7000<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7001<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7002<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
CRITICAL<br />
C7003<br />
3.0PF<br />
CRITICAL<br />
C7006<br />
12PF<br />
+/-0.1PF<br />
5%<br />
2<br />
25V<br />
NP0-C0G<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
0201<br />
1<br />
1<br />
CRITICAL<br />
C7008<br />
12PF<br />
CRITICAL<br />
C7009<br />
3.0PF<br />
5%<br />
+/-0.1PF<br />
2<br />
25V<br />
NP0-C0G<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
0201<br />
1<br />
1<br />
2<br />
CRITICAL<br />
C7090<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7091<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7092<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7093<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7094<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7095<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7096<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7097<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7098<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7099<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
D<br />
2.4G DESENSE<br />
5G DESENSE 2.4G DESENSE 5G DESENSE<br />
2.4G DESENSE 2.4G DESENSE 5G DESENSE<br />
1<br />
2<br />
CRITICAL<br />
C7024<br />
6.8UF<br />
20%<br />
35V-0.09OHM<br />
POLY-TANT<br />
CASE-B1-2-SM<br />
1<br />
2<br />
CRITICAL<br />
C7025<br />
6.8UF<br />
20%<br />
35V-0.09OHM<br />
POLY-TANT<br />
CASE-B1-2-SM<br />
1<br />
CRITICAL<br />
C7026<br />
6.8UF<br />
20%<br />
2 35V-0.09OHM<br />
POLY-TANT<br />
CASE-B1-2-SM<br />
1<br />
CRITICAL<br />
C7027<br />
6.8UF<br />
20%<br />
2 35V-0.09OHM<br />
POLY-TANT<br />
CASE-B1-2-SM<br />
1<br />
CRITICAL<br />
C7028<br />
6.8UF<br />
35V-0.09OHM<br />
20%<br />
2<br />
POLY-TANT<br />
CASE-B1-2-SM<br />
1<br />
2<br />
CRITICAL<br />
C7029<br />
6.8UF<br />
20%<br />
35V-0.09OHM<br />
POLY-TANT<br />
CASE-B1-2-SM<br />
104 65<br />
PPDCIN_G3H_CHGR<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
1<br />
1<br />
2<br />
C7032<br />
2.2UF<br />
20%<br />
35V<br />
X5R-CERM<br />
0402<br />
2<br />
C7033<br />
2.2UF<br />
20%<br />
35V<br />
X5R-CERM<br />
0402<br />
VOLTAGE=20V<br />
1<br />
2<br />
2.4G DESENSE 5G DESENSE 2.4G DESENSE 5G DESENSE 2.4G DESENSE 5G DESENSE 2.4G DESENSE 5G DESENSE 2.4G DESENSE 5G DESENSE<br />
C7034<br />
2.2UF<br />
20%<br />
35V<br />
X5R-CERM<br />
0402<br />
1<br />
2<br />
C7035<br />
2.2UF<br />
20%<br />
35V<br />
X5R-CERM<br />
0402<br />
1<br />
CRITICAL<br />
C7050<br />
68UF<br />
20%<br />
2 16V<br />
POLY-TANT<br />
CASE-D2E-SM<br />
1<br />
CRITICAL<br />
C7051<br />
68UF<br />
20%<br />
2 16V<br />
POLY-TANT<br />
CASE-D2E-SM<br />
1<br />
2<br />
C7053<br />
2.2UF<br />
20%<br />
25V<br />
X5R<br />
0402-1<br />
1<br />
2<br />
C7055<br />
2.2UF<br />
20%<br />
25V<br />
X5R<br />
0402-1<br />
1<br />
C7054<br />
1000PF<br />
10%<br />
2<br />
25V<br />
X7R<br />
0201<br />
D<br />
PLACE_NEAR=Q7030.2:1MM<br />
PLACE_NEAR=Q7030.1:3mm<br />
C<br />
B<br />
A<br />
PP7011<br />
PP7012<br />
PP7013<br />
PP7014<br />
PP7015<br />
PP7016<br />
66<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
66 65<br />
PP<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
50<br />
PP<br />
PP<br />
PP<br />
PP<br />
PP<br />
66<br />
66<br />
FROM USB-C SOURCE<br />
TBA_GATE_Q1<br />
TBA_GATE_Q2<br />
TBA_GATE_Q3<br />
TBA_GATE_Q4<br />
TBA_LX1<br />
TBA_LX2<br />
PM_EN_P3V3_G3H<br />
SMC_CHGR_INT_L<br />
PPDCIN_G3H<br />
100<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
PP3V3_G3H<br />
PP7001<br />
PP7002<br />
PP7003<br />
PP7004<br />
PP7005<br />
PP7006<br />
PP7007<br />
PP7008<br />
PPVIN_G3H_P3V3G3H<br />
PLACE_NEAR=U7000.A5:2MM<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
C7080 1<br />
1UF<br />
20%<br />
10V<br />
2<br />
X5R<br />
0201<br />
C7081 1<br />
2.2UF<br />
2<br />
20%<br />
35V<br />
X5R-CERM<br />
0402<br />
R70081 10K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
NO STUFF<br />
C7016 1<br />
0.01UF<br />
10%<br />
25V<br />
2<br />
X5R-CERM<br />
0201<br />
R7009 1<br />
100K<br />
1/20W<br />
5%<br />
MF<br />
201<br />
2<br />
(AMON)<br />
TBA_CSI_R_P<br />
1<br />
R7015<br />
750K<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
51<br />
51<br />
50<br />
TBA_AUX_DET<br />
1<br />
R7016<br />
255K<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
TBA_MPM_DET<br />
CRITICAL<br />
R7020<br />
0.01<br />
0.5%<br />
0.5W<br />
MF<br />
0306<br />
1 2<br />
3 4<br />
C7023<br />
0.47UF<br />
2<br />
20%<br />
4V<br />
CERM-X5R-1<br />
201<br />
TBA_CSI_R_N<br />
SMBUS_SMC_5_G3_SDA<br />
SMBUS_SMC_5_G3_SCL<br />
SMC_4FINGERS_RST<br />
HPWR_EN_L<br />
C7070 1<br />
0.12UF<br />
10%<br />
10.0V<br />
2<br />
CERM-X5R<br />
402<br />
1<br />
TBA_CSI_N<br />
PLACE_NEAR=U7000.C5:1MM<br />
PPVIN_G3H_P3V3G3H<br />
1<br />
2<br />
TBA_COMP<br />
C7071<br />
0.12UF<br />
10%<br />
10.0V<br />
CERM-X5R<br />
402<br />
NO STUFF<br />
B5<br />
C5<br />
D5<br />
A5<br />
D3<br />
B2<br />
C2<br />
E4<br />
F5<br />
G5<br />
H5<br />
G2<br />
G3<br />
E5<br />
G4<br />
TBA_GATE_Q1<br />
TBA_VDDA<br />
1<br />
2<br />
C7075<br />
2.2UF<br />
20% 25V<br />
X6S-CERM<br />
0402<br />
A2<br />
OMIT_TABLE<br />
U7000<br />
ISL9239<br />
WCSP-1<br />
E3<br />
D2<br />
E2<br />
TBA_LX1<br />
1<br />
2<br />
0.1UF<br />
2.7UH-0.0196OHM-13.5A<br />
TBA_PHASE1 1 2 TBA_PHASE2<br />
C7030<br />
10%<br />
25V<br />
X7R-CERM-1<br />
0402<br />
TBA_BOOT1<br />
TBA_GATE_Q2<br />
TBA_BOOT1_RC<br />
1<br />
R7030<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
2 402<br />
R7075<br />
4.7<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
TBA_VDDP<br />
C7077 1<br />
10UF<br />
20%<br />
25V<br />
2<br />
X5R-CERM<br />
0603<br />
H1<br />
F1<br />
G1<br />
E1<br />
D1<br />
B1<br />
C1<br />
A1<br />
A3<br />
A4<br />
B4<br />
B3<br />
C3<br />
F2<br />
H4<br />
H3<br />
H2<br />
F4<br />
F3<br />
D4<br />
C4<br />
152S00198<br />
OMIT_TABLE<br />
L7030<br />
IHLP4040BD-PIMA102D-COMBO<br />
104 100 104<br />
66 65<br />
PP<br />
PP<br />
PP<br />
PP<br />
PP<br />
PP<br />
PP<br />
PP<br />
R7021 1<br />
1.00<br />
1%<br />
1/20W<br />
MF-LF<br />
0201 2<br />
TBA_CSI_P<br />
C7021 1 2<br />
0.047UF<br />
10%<br />
50V<br />
CER-X7R<br />
0402<br />
BI<br />
IN<br />
IN<br />
104<br />
65<br />
66<br />
1<br />
R7022<br />
1.00<br />
1%<br />
1/20W<br />
MF-LF<br />
2 0201<br />
1<br />
2<br />
C7022<br />
0.047UF<br />
10%<br />
50V<br />
CER-X7R<br />
0402<br />
Q7030<br />
FDMD8800<br />
DFN<br />
1<br />
2<br />
3<br />
13<br />
D1<br />
SGATE<br />
AGATE<br />
MPM_DET<br />
CELL<br />
G1<br />
12<br />
P_IN<br />
CSIN<br />
CSIP<br />
MPM_PBUS<br />
AUX_DET<br />
VR1_3P3<br />
SDA<br />
SCL<br />
SMC_RST_IN<br />
HPWR_EN*<br />
COMP<br />
7<br />
8<br />
9<br />
10<br />
S1/D2<br />
G1R<br />
11<br />
VDDA<br />
AGND<br />
VDDP<br />
PGND<br />
G2<br />
4<br />
5<br />
6<br />
14<br />
S2<br />
GATE_Q1<br />
BOOT1<br />
LX1<br />
GATE_Q2<br />
GATE_Q3<br />
LX2<br />
BOOT2<br />
GATE_Q4<br />
PBUS<br />
CSOP<br />
CSON<br />
BGATE<br />
VBAT<br />
EN_VR1<br />
SMC_RST*<br />
IRQ*<br />
CBC_ON<br />
MPM_OK<br />
AUX_OK<br />
AMON<br />
BMON<br />
NC<br />
1<br />
14<br />
6<br />
5<br />
TBA_GATE_Q3<br />
4<br />
10%<br />
25V<br />
X7R-CERM-1<br />
0402<br />
PM_EN_P3V3_G3H<br />
SMC_RST_L<br />
SMC_CHGR_INT_L<br />
SMC_CBC_ON<br />
TBA_LX2<br />
C7040 1<br />
0.1UF<br />
2<br />
TBA_BOOT2_RC<br />
R7040 1<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402 2<br />
TBA_BOOT2<br />
SMC_AUX_OK<br />
CHGR_AMON<br />
CHGR_BMON<br />
10<br />
9<br />
8<br />
7<br />
11<br />
TBA_GATE_Q4<br />
(PBUS)<br />
IND,MLD,2.7UH,19.6MO,12.5A,10.9X10X2.4MM<br />
65<br />
50<br />
48<br />
50<br />
52<br />
52<br />
12<br />
13<br />
3<br />
2<br />
1<br />
66<br />
66<br />
DFN<br />
FDMD8800<br />
Q7040<br />
(BMON)<br />
TBA_CSO_R_P<br />
R7061 1<br />
1.00<br />
1/20W<br />
1%<br />
MF-LF<br />
0201 2<br />
TBA_CSO_P<br />
C7061 1 2<br />
0.047UF<br />
10%<br />
50V<br />
CER-X7R<br />
0402<br />
R7090<br />
100K<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
L7030<br />
PPVBAT_G3H_CHGR_REG<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=13.1V<br />
CRITICAL<br />
R7060<br />
0.005<br />
1%<br />
1W<br />
MF<br />
0612-5<br />
1 2<br />
3 4<br />
C7020<br />
0.47UF<br />
2<br />
1<br />
20%<br />
4V<br />
CERM-X5R-1<br />
201<br />
SMC_RESET_L<br />
PPVBAT_G3H_CHGR_R<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=13.1V<br />
TBA_CSO_R_N<br />
1<br />
R7062<br />
1.00<br />
1%<br />
1/20W<br />
MF-LF<br />
2 0201<br />
TBA_CSO_N<br />
1<br />
2<br />
C7066 1<br />
2.2UF<br />
20%<br />
25V<br />
2<br />
X5R<br />
0402-1<br />
C7062<br />
0.047UF<br />
10%<br />
50V<br />
CER-X7R<br />
0402<br />
PLACE_NEAR=U7000.A4:1MM<br />
50<br />
59<br />
CRITICAL<br />
80<br />
104<br />
C7069 1<br />
2.2UF<br />
2<br />
20%<br />
25V<br />
X5R<br />
0402-1<br />
PART NUMBER QTY DESCRIPTION<br />
REFERENCE DES CRITICAL BOM OPTION<br />
C7064<br />
1000PF<br />
1 2<br />
10%<br />
25V<br />
X7R<br />
0201<br />
BOM_COST_GROUP=PLATFORM POWER<br />
3<br />
2<br />
1<br />
C7067 1<br />
0.1UF<br />
10%<br />
25V<br />
2<br />
X5R<br />
0201<br />
CRITICAL<br />
Q7065<br />
SI7137DP<br />
SO-8<br />
4<br />
TBA_BGATE<br />
1<br />
2<br />
CRITICAL<br />
F7000<br />
12AMP-32V<br />
1 2<br />
C7063<br />
4700PF<br />
10%<br />
25V<br />
CER-X5R<br />
0201<br />
TO/FROM BATTERY<br />
PPVBAT_G3H_CONN<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=13.1V<br />
PLACE_NEAR=Q7065.5:2MM<br />
1<br />
DESIGN: X502/MLB<br />
LAST CHANGE: Thu Mar 5 18:14:03 2015<br />
SYNC_MASTER=J79_JSHAO<br />
1206<br />
5<br />
C7068 1<br />
0.01UF<br />
2<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
2<br />
C7060<br />
0.1UF<br />
10%<br />
25V<br />
X5R<br />
0201<br />
65<br />
TO SYSTEM<br />
PPBUS_G3H 100<br />
PBUS Supply & Battery Charger<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
S2<br />
G2<br />
S1/D2<br />
G1R<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
G1<br />
D1<br />
OUT<br />
S<br />
G<br />
SYM-VER-2<br />
D<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
104<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
70 OF 145<br />
66 OF 119<br />
SYNC_DATE=12/03/2015<br />
SIZE<br />
D<br />
C<br />
B<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
C<br />
B<br />
A<br />
8<br />
8<br />
IN<br />
IN<br />
68 67<br />
68<br />
68 67<br />
68 67<br />
68 67<br />
8<br />
8<br />
68<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
CPU_VCCSENSE_P<br />
CPU_VCCSENSE_N<br />
IN<br />
IN<br />
CPUCORE_ISUMP<br />
CPUCORE_ISUMN<br />
CPUCORE_ISEN1<br />
CPUCORE_ISEN2<br />
R7160<br />
2<br />
93.1K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
CPUSA_ISUMP<br />
CPUSA_ISUMN<br />
CPU_VCCSASENSE_P<br />
CPU_VCCSASENSE_N<br />
1<br />
C7154 1 0.01UF<br />
2<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
IMON_B_CPUCORE<br />
C7160<br />
150PF<br />
2<br />
1<br />
10%<br />
25V<br />
X7R-CERM<br />
0201<br />
C7181 1<br />
220PF<br />
2<br />
10%<br />
25V<br />
X7R-CERM<br />
201<br />
C7182 1<br />
0.01UF<br />
2<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
R7190<br />
2<br />
147K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
1<br />
C7190<br />
68PF<br />
2<br />
5%<br />
25V<br />
C0G<br />
0201<br />
1<br />
C7141 1 330PF<br />
2<br />
C7151 1<br />
220PF<br />
2<br />
10%<br />
25V<br />
X7R-CERM<br />
201<br />
C7153 1<br />
0.01UF<br />
2<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
R7181<br />
1K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
10%<br />
16V<br />
X7R<br />
0201<br />
C7152 1<br />
0.01UF<br />
2<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
R7180<br />
2<br />
422<br />
1%<br />
1/20W<br />
MF<br />
201<br />
R7142<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
1<br />
SA_ISUMN_R<br />
IMON_C_CPUSA<br />
10%<br />
16V<br />
X7R<br />
0201<br />
54<br />
1<br />
C7171 1<br />
330PF<br />
2<br />
67<br />
FB_CORE_R<br />
XW7140<br />
330PF<br />
SM<br />
1 2<br />
C7142<br />
10%<br />
2<br />
16V<br />
X7R<br />
0201<br />
R7151<br />
1K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
C7180<br />
3300PF<br />
1 2<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
C7144<br />
3300PF<br />
2 1FB_B_CORE_R<br />
249<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
R7150<br />
2<br />
R7172<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
1<br />
2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
1<br />
CORE_ISUMN_R<br />
C7161<br />
6800PF<br />
2<br />
1<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
67<br />
10%<br />
16V<br />
X7R<br />
0201<br />
RTN_B_CPUCORE<br />
COMP_B_CPUCORE_L<br />
FB_SA_R<br />
C7174<br />
3300PF<br />
2<br />
XW7170<br />
330PF<br />
SM<br />
1 2<br />
C7172<br />
1<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
R7143<br />
2<br />
1.58K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
1<br />
C7150<br />
3300PF<br />
1 2<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
C7162<br />
CPUSA_ISUMN_R<br />
C7191<br />
6800PF<br />
2<br />
68PF<br />
2<br />
5%<br />
25V<br />
C0G<br />
0201<br />
1<br />
1<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
R7173<br />
2<br />
2.15K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
FB_C_SA_R<br />
100<br />
CPU VCC Core<br />
COMP_B_CPUCORE<br />
COMP_C_CPUSA_L<br />
1<br />
RTN_C_CPUSA<br />
R7144<br />
2<br />
1K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
1<br />
FB_B_CPUCORE<br />
R7145<br />
560<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
PPBUS_HS_CPU<br />
CPUCORE_ISUMN_R<br />
R7161<br />
2<br />
4.99K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
1<br />
CPU VCC SA<br />
C7192<br />
150PF<br />
2<br />
R7174<br />
2<br />
67<br />
67<br />
2.15K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
1<br />
10%<br />
25V<br />
X7R-CERM<br />
0201<br />
67<br />
1<br />
R7191<br />
2<br />
4.99K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
FB_C_CPUSA<br />
R7175<br />
560<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
FB_B_CORE_RC<br />
C7143 1<br />
1000PF<br />
2<br />
67<br />
1<br />
67<br />
68<br />
68 67<br />
68<br />
68 67<br />
68 67<br />
68 67<br />
68<br />
68 67<br />
68 67<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
IN<br />
67<br />
67<br />
67<br />
67 54<br />
OUT<br />
OUT<br />
IN<br />
67<br />
67<br />
67<br />
67<br />
10%<br />
25V<br />
X7R<br />
0201<br />
COMP_C_CPUSA<br />
FB_C_SA_RC<br />
C7173 1<br />
<strong>820</strong>PF<br />
10%<br />
25V<br />
2<br />
X7R-CERM<br />
0201<br />
R7101<br />
10<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
CPUCORE_FCCM<br />
CPUCORE_PWM1<br />
CPUCORE_PWM2<br />
CPUCORE_ISUMP<br />
CPUCORE_ISUMN_R<br />
CPUCORE_ISEN1<br />
CPUCORE_ISEN2<br />
COMP_B_CPUCORE<br />
FB_B_CPUCORE<br />
RTN_B_CPUCORE<br />
IMON_B_CPUCORE<br />
NTC_B_CPUCORE<br />
CPUSA_FCCM<br />
CPUSA_PWM<br />
CPUSA_ISUMP<br />
CPUSA_ISUMN_R<br />
COMP_C_CPUSA<br />
FB_C_CPUSA<br />
RTN_C_CPUSA<br />
IMON_C_CPUSA<br />
PROG1_CPUCOREVR<br />
PROG2_CPUCOREVR<br />
PROG3_CPUCOREVR<br />
PROG4_CPUCOREVR<br />
PROG5_CPUCOREVR<br />
78.7K<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
1<br />
2<br />
1<br />
R7111<br />
CPUCORE_PWM1<br />
CPUSA_PWM<br />
PPVIN_S0_CPUVR_VIN<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=13.1V<br />
C7101<br />
0.22UF<br />
10%<br />
25V<br />
X7R<br />
0402<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
PP7100<br />
PP7202<br />
PP5V_COREVR_VCC<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=5V<br />
CPUGT_PWM1<br />
CPUGT_PWM2<br />
CPUGT_FCCM<br />
CPUGT_PWM1<br />
CPUGT_PWM2<br />
CPUGT_PWM3<br />
CPUGT_ISUMP<br />
CPUGT_ISUMN_R<br />
CPUGT_ISEN1<br />
CPUGT_ISEN2<br />
CPUGT_ISEN3<br />
COMP_A_CPUGT<br />
FB_A_CPUGT<br />
RTN_A_CPUGT<br />
IMON_A_CPUGT<br />
NTC_A_CPUGT<br />
CPU_PROCHOT_L_R<br />
CPUVR_PGOOD<br />
CPU_VR_EN_R<br />
CPUVR_VIDSOUT_R<br />
CPUVR_VIDALERT_L_R<br />
CPUVR_VIDSCLK_R<br />
CPUCORE_PSYS<br />
PROG1_CPUCOREVR<br />
67<br />
PROG2_CPUCOREVR<br />
67<br />
PROG3_CPUCOREVR<br />
67<br />
PROG4_CPUCOREVR<br />
67<br />
PROG5_CPUCOREVR<br />
1<br />
R7112<br />
63.4K<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
11<br />
12<br />
13<br />
7<br />
8<br />
9<br />
10<br />
4<br />
5<br />
6<br />
2<br />
3<br />
34<br />
32<br />
33<br />
29<br />
30<br />
28<br />
40<br />
39<br />
38<br />
37<br />
36<br />
1<br />
R7113<br />
1.87K<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
41<br />
U7100<br />
ISL95828HRTZ<br />
LLP<br />
1<br />
R7114<br />
182K<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
1<br />
R7115<br />
100K<br />
0.1%<br />
1/20W<br />
MF<br />
2<br />
0201-1<br />
1<br />
2<br />
R7100<br />
1UF<br />
1<br />
1 2<br />
C7100<br />
10%<br />
10V<br />
CER-X6S<br />
0402<br />
67 67<br />
67<br />
67<br />
67<br />
67<br />
67<br />
67<br />
67<br />
67<br />
67<br />
67<br />
68 67<br />
68 67<br />
35<br />
FCCM_B<br />
PWM1_B<br />
PWM2_B<br />
ISUMP_B<br />
ISUMN_B<br />
ISEN1_B<br />
ISEN2_B<br />
COMP_B<br />
FB_B<br />
RTN_B<br />
IMON_B<br />
NTC_B<br />
FCCM_C<br />
PWM_C<br />
ISUMP_C<br />
ISUMN_C<br />
COMP_C<br />
FB_C<br />
24<br />
25<br />
26<br />
27<br />
19<br />
20<br />
21<br />
22<br />
23<br />
31 RTN_C<br />
SCLK 45<br />
IMON_C<br />
PROG1<br />
PROG2<br />
PROG3<br />
PROG4<br />
PROG5<br />
VIN<br />
THRM_PAD<br />
49<br />
42<br />
VCC<br />
PP<br />
PP<br />
FCCM_A<br />
PWM1_A<br />
PWM2_A<br />
PWM3_A<br />
ISUMP_A<br />
ISUMN_A<br />
ISEN1_A<br />
ISEN2_A<br />
ISEN3_A<br />
COMP_A<br />
FB_A<br />
RTN_A<br />
IMON_A<br />
NTC_A<br />
VR_HOT*<br />
VR_READY<br />
VR_ENABLE<br />
SDA<br />
ALERT*<br />
PSYS<br />
16<br />
17<br />
18<br />
14<br />
15<br />
46<br />
47<br />
48<br />
43<br />
44<br />
1<br />
70 67<br />
70 67<br />
1<br />
C7108<br />
4700PF<br />
10%<br />
2<br />
10V<br />
X7R<br />
201<br />
5%<br />
1/20W<br />
MF<br />
201<br />
67<br />
12.1K<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
PP7103<br />
PP7104<br />
PP5V_S4 101<br />
67<br />
67<br />
67<br />
67<br />
54<br />
1%<br />
1/20W<br />
MF<br />
201<br />
70<br />
67<br />
67<br />
70<br />
67<br />
67<br />
67<br />
67<br />
R7106<br />
49.9<br />
1 2<br />
70<br />
70<br />
70<br />
70<br />
70<br />
70<br />
45.3<br />
PP5V_S0 68 101<br />
NOSTUFF<br />
1<br />
R7107<br />
1<br />
R7108<br />
12.1K<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
67<br />
74<br />
77<br />
R7103<br />
0<br />
1 2<br />
67<br />
5%<br />
1/20W<br />
MF<br />
201<br />
FB_A_CPUGT<br />
CPU VCC GT + GTx Merged<br />
1<br />
R7110<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
R7105<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
67<br />
R7102<br />
100<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
NTC_B_CPUCORE<br />
67<br />
C7148 1<br />
680PF<br />
2<br />
10%<br />
25V<br />
X7R-CERM<br />
0201<br />
FB_A_GT_RC<br />
CPUGT_ISUMN_R<br />
CPU_PROCHOT_L<br />
ALL_SYS_PWRGD<br />
PP1V0_S3 101<br />
R7104<br />
10<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
NTC_A_CPUGT<br />
1<br />
R7109<br />
100<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
R7120<br />
13.3K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
67<br />
CPU_VIDSOUT<br />
CPU_VIDALERT_L<br />
CPU_VIDSCLK<br />
R7121<br />
13.3K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
R7149<br />
2<br />
453<br />
1%<br />
1/20W<br />
MF<br />
201<br />
C7155<br />
3300PF<br />
2 1 GT_ISUMN_R<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
NTC_A_CPUGT_R<br />
NTC_B_CPUCORE_R<br />
1<br />
6<br />
77<br />
R7148<br />
1K<br />
1 2<br />
67<br />
8<br />
8<br />
1%<br />
1/20W<br />
MF<br />
201<br />
FB_A_GT_R<br />
RTN_A_CPUGT<br />
R7154<br />
332<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
BOM_COST_GROUP=CPU & CHIPSET<br />
48<br />
8<br />
49<br />
1<br />
2<br />
R7147<br />
2.67K<br />
1 2<br />
1<br />
2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
R7155<br />
2<br />
1K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
67<br />
R7123<br />
220KOHM-3%<br />
0201<br />
1<br />
FB_GT_R<br />
C7147<br />
1500PF<br />
1 2<br />
10%<br />
10V<br />
X7R<br />
0201<br />
XW7141<br />
2<br />
1<br />
SM<br />
COMP_A_CPUGT<br />
R7124<br />
220KOHM-3%<br />
0201<br />
SYNC_MASTER=J79_JSHAO<br />
1<br />
2<br />
1<br />
R7146<br />
2<br />
10%<br />
16V<br />
X7R<br />
0201<br />
0<br />
5%<br />
1/20W<br />
MF<br />
201<br />
C7146 1<br />
330PF<br />
2<br />
C7156<br />
220PF<br />
10%<br />
25V<br />
X7R-CERM<br />
201<br />
1<br />
0.01UF<br />
C7157<br />
0.01UF<br />
10%<br />
2<br />
10V<br />
X7R-CERM<br />
0201<br />
C7149<br />
10%<br />
2<br />
10V<br />
X7R-CERM<br />
0201<br />
67 54<br />
1<br />
1<br />
2<br />
R7193<br />
2.49K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
IMON_A_CPUGT<br />
1<br />
2<br />
C7145<br />
330PF<br />
10%<br />
16V<br />
X7R<br />
0201<br />
C7158<br />
0.01UF<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
C7193<br />
68PF<br />
1 2<br />
5%<br />
25V<br />
C0G<br />
0201<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
CPU_VCCGTSENSE_P<br />
CPU_VCCGTSENSE_N<br />
COMP_A_CPUGT_L<br />
C7195<br />
150PF<br />
10%<br />
25V<br />
X7R-CERM<br />
0201<br />
CPUGT_ISUMP<br />
CPUGT_ISUMN<br />
CPUGT_ISEN1<br />
CPUGT_ISEN2<br />
CPUGT_ISEN3<br />
CORE & SA IMVP IC<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
IN<br />
IN<br />
PP<br />
PP<br />
OUT<br />
IN<br />
BI<br />
IN<br />
IN<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
1<br />
2<br />
C7159<br />
0.01UF<br />
10%<br />
2<br />
10V<br />
X7R-CERM<br />
0201<br />
1<br />
C7194<br />
6800PF<br />
1 2<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
R7194<br />
95.3K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
9.0.0<br />
67<br />
70<br />
67<br />
67<br />
67<br />
051-00777<br />
dvt-fab09-0<br />
71 OF 145<br />
67 OF 119<br />
8<br />
8<br />
70<br />
70<br />
70<br />
70<br />
SYNC_DATE=03/02/2016<br />
SIZE<br />
D<br />
D<br />
C<br />
B<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
100<br />
68<br />
PPBUS_HS_CPU<br />
D<br />
C<br />
B<br />
101 68<br />
100<br />
101 68<br />
67<br />
68<br />
67<br />
PP5V_S0<br />
CPU VCC Phase 1<br />
PPBUS_HS_CPU<br />
PP5V_S0<br />
68<br />
68<br />
PVCCCORE_PH1_AGND<br />
68 67<br />
PVCCCORE_PH2_AGND<br />
CPU VCC Phase 2<br />
67<br />
68 67<br />
67<br />
R7215<br />
1<br />
1 2<br />
IN<br />
IN<br />
R7225<br />
1<br />
1 2<br />
IN<br />
IN<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
C7217 1<br />
2.2UF<br />
20%<br />
25V<br />
X6S-CERM 2<br />
0402<br />
CPUCORE_FCCM<br />
CPUCORE_PWM1<br />
68<br />
CPUCORE_FCCM<br />
CPUCORE_PWM2<br />
PVCCCORE_PH1_AGND<br />
C7227 1<br />
2.2UF<br />
20%<br />
2<br />
25V<br />
X6S-CERM<br />
0402<br />
68<br />
VOLTAGE=5V<br />
PP5V_S0_VCORE1<br />
NC<br />
NC<br />
8<br />
9<br />
VOLTAGE=5V<br />
PVCCCORE_PH2_AGND<br />
2<br />
1<br />
30<br />
31<br />
PP5V_S0_VCORE2<br />
NC<br />
NC<br />
8<br />
9<br />
2<br />
1<br />
30<br />
31<br />
3<br />
FDMF5808A<br />
VIN<br />
BOOT<br />
VIN PQFN-COMBO-THICKSTNCL<br />
PHASE<br />
OMIT_TABLE<br />
FCCM<br />
SW<br />
PWM<br />
SW<br />
NC<br />
NC<br />
4<br />
32<br />
3<br />
U7220<br />
FDMF5808A<br />
VIN<br />
BOOT<br />
VIN PQFN-COMBO-THICKSTNCL<br />
PHASE<br />
OMIT_TABLE<br />
FCCM<br />
SW<br />
PWM<br />
SW<br />
NC<br />
NC<br />
VCC<br />
AGND<br />
AGND<br />
4<br />
32<br />
29<br />
U7210<br />
CRITICAL<br />
12<br />
28<br />
29<br />
CRITICAL<br />
12<br />
28<br />
XW7220<br />
2<br />
SM<br />
5<br />
7<br />
16<br />
24<br />
27<br />
33<br />
PLACE_NEAR=U7210.32:2MM<br />
VCC<br />
AGND<br />
AGND<br />
XW7210<br />
2<br />
PVCC<br />
PGND<br />
PGND<br />
PVCC<br />
PGND<br />
PGND<br />
SM<br />
1<br />
1<br />
GL0<br />
GL1<br />
GH<br />
GL0<br />
GL1<br />
GH<br />
6<br />
5<br />
7<br />
16<br />
24<br />
27<br />
33<br />
6<br />
NC<br />
NC<br />
1<br />
2<br />
1<br />
2<br />
C7216<br />
2.2UF<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
CPUCORE1_GL0<br />
CPUCORE1_DRVH<br />
C7226<br />
2.2UF<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
CPUCORE_BOOT1<br />
MIN_LINE_WIDTH=0.2500<br />
MIN_NECK_WIDTH=0.2000<br />
DIDT=TRUE<br />
MIN_LINE_WIDTH=0.2500<br />
MIN_NECK_WIDTH=0.2000<br />
DIDT=TRUE<br />
MIN_LINE_WIDTH=0.2500<br />
MIN_NECK_WIDTH=0.2000<br />
DIDT=TRUE<br />
CPUCORE2_GL0<br />
MIN_LINE_WIDTH=0.2500<br />
MIN_NECK_WIDTH=0.2000<br />
DIDT=TRUE<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
CPUCORE2_DRVH<br />
CPUCORE_SW1<br />
CPUCORE_BP1<br />
68<br />
CPUCORE_PHASE1<br />
CPUCORE_SW2<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
CPUCORE_BOOT2<br />
CPUCORE_BP2<br />
MIN_LINE_WIDTH=0.2500<br />
MIN_NECK_WIDTH=0.2000<br />
DIDT=TRUE<br />
68<br />
68<br />
MIN_LINE_WIDTH=0.2500<br />
MIN_NECK_WIDTH=0.2000<br />
DIDT=TRUE<br />
CPUCORE_PHASE2<br />
68<br />
R7219 1<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
C7219 1<br />
0.22UF<br />
2<br />
10%<br />
25V<br />
X7R<br />
0402<br />
R7229 1<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
C7229 1<br />
0.22UF<br />
2<br />
10%<br />
25V<br />
X7R<br />
0402<br />
L7210<br />
0.22UH-35A-0.00255OHM<br />
1 2<br />
PILS062D-IHLP2525BD-SM-COMBO<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.5V<br />
1<br />
R7218<br />
2.2<br />
5%<br />
1/10W<br />
MF-LF<br />
2<br />
603<br />
NOSTUFF<br />
CPUCORE_SW1_SNUB<br />
1<br />
2<br />
DIDT=TRUE<br />
L7220<br />
0.22UH-35A-0.00255OHM<br />
1 2 PPVCC_CPU_PH2<br />
PILS062D-IHLP2525BD-SM-COMBO MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.5V<br />
1<br />
R7228<br />
2.2<br />
5%<br />
1/10W<br />
MF-LF<br />
2<br />
603<br />
NOSTUFF<br />
CPUCORE_SW2_SNUB<br />
1<br />
2<br />
C7218<br />
0.001UF<br />
10%<br />
50V<br />
X7R-CERM<br />
0402<br />
NOSTUFF<br />
DIDT=TRUE<br />
C7228<br />
0.001UF<br />
10%<br />
50V<br />
X7R-CERM<br />
0402<br />
NOSTUFF<br />
PPVCC_CPU_PH1<br />
NO_XNET_CONNECTION=1<br />
R7212 1<br />
1K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
NO_XNET_CONNECTION=1<br />
R7222 1<br />
1K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
CRITICAL<br />
R7210<br />
0.00075<br />
1%<br />
1W<br />
MF<br />
0612-1<br />
2 1<br />
4 3<br />
CRITICAL<br />
R7220<br />
0.00075<br />
1%<br />
1W<br />
MF<br />
0612-1<br />
2 1<br />
4 3<br />
2.2<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
2.2<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
NO_XNET_CONNECTION=1<br />
1<br />
R7223<br />
200K<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
1<br />
C7210<br />
33UF<br />
20%<br />
20%<br />
20%<br />
2 16V<br />
2 16V<br />
2 16V<br />
TANT-POLY<br />
TANT-POLY<br />
TANT-POLY<br />
CASE-B3<br />
CASE-B3<br />
CASE-B3<br />
NO_XNET_CONNECTION=1<br />
1<br />
R7211<br />
NO_XNET_CONNECTION=1<br />
1<br />
R7213<br />
200K<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
1<br />
R7221<br />
CPUCORE_ISNS1_P<br />
CPUCORE_ISNS1_N<br />
NO_XNET_CONNECTION=1<br />
1<br />
2<br />
C7220<br />
33UF<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
NO_XNET_CONNECTION=1<br />
CPUCORE_ISNS2_P<br />
CPUCORE_ISNS2_N<br />
NO_XNET_CONNECTION=1<br />
1<br />
C7211<br />
33UF<br />
CPUCORE_ISUMN<br />
CPUCORE_ISEN1<br />
CPUCORE_ISUMP<br />
1<br />
2<br />
33UF<br />
OUT<br />
OUT<br />
C7221<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
OUT<br />
OUT<br />
CPUCORE_ISUMN<br />
CPUCORE_ISEN2<br />
CPUCORE_ISUMP<br />
53<br />
53<br />
53<br />
53<br />
68<br />
68<br />
1<br />
C7212<br />
33UF<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
67<br />
67<br />
67<br />
67<br />
67<br />
67<br />
68<br />
68<br />
68<br />
68<br />
R7214<br />
2<br />
1<br />
2<br />
200K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
C7223<br />
2.2UF<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
NO_XNET_CONNECTION=1<br />
R7224<br />
2<br />
1<br />
2<br />
200K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
C7213<br />
2.2UF<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
NO_XNET_CONNECTION=1<br />
1<br />
1<br />
1<br />
2<br />
CPUCORE_ISNS2_N<br />
1<br />
2<br />
C7214<br />
2.2UF<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
C7224<br />
2.2UF<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
CPUCORE_ISNS1_N<br />
53<br />
53<br />
1<br />
2<br />
68<br />
1<br />
2<br />
68<br />
C7215<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
C7225<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
PPVCC_S0_CPU<br />
100<br />
Vout = 0.55 - 1.5V<br />
IccMax = 32A<br />
F = 750kHz<br />
1<br />
2.4G DESENSE<br />
68<br />
68<br />
CRITICAL<br />
C7230<br />
12PF<br />
68<br />
68<br />
68<br />
68 67<br />
68 67<br />
68<br />
5%<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
CPUCORE1_GL0<br />
CPUCORE2_GL0<br />
CPUSA_GL0<br />
CPUCORE1_DRVH<br />
CPUCORE2_DRVH<br />
CPUCORE_FCCM<br />
CPUSA_FCCM<br />
CPUSA_DRVH<br />
1<br />
2<br />
5G DESENSE<br />
CRITICAL<br />
C7231<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
CRITICAL<br />
C7232<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
PP<br />
PP<br />
PP<br />
PP<br />
PP<br />
PP<br />
PP<br />
PP<br />
PP7210<br />
PP7220<br />
PP7270<br />
PP7211<br />
PP7221<br />
PP7212<br />
PP7272<br />
PP7271<br />
2.4G DESENSE 5G DESENSE<br />
1<br />
CRITICAL<br />
C7233<br />
3.0PF<br />
+/-0.1PF<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
D<br />
C<br />
B<br />
100<br />
PPBUS_HS_CPU<br />
PLACE_NEAR=U7220.32:2MM<br />
A<br />
101<br />
68<br />
67<br />
PP5V_S0<br />
68<br />
R7275<br />
1<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
PVCCCSA_AGND<br />
68 67<br />
CPU VCCSA<br />
67<br />
IN<br />
IN<br />
CPUSA_FCCM<br />
CPUSA_PWM<br />
CPUSA_DRVH<br />
C7277 1<br />
2.2UF<br />
20%<br />
25V<br />
2<br />
X6S-CERM<br />
0402<br />
VOLTAGE=5V<br />
PP5V_S0_VCCSA<br />
6<br />
1<br />
12<br />
3<br />
VIN<br />
ZCD_EN*<br />
PWM<br />
NC<br />
XW7270<br />
2<br />
SM<br />
2<br />
VCIN<br />
U7270<br />
SIC535CD<br />
MLP4535<br />
7<br />
10<br />
1<br />
11<br />
13<br />
68 PVCCCSA_AGND<br />
PLACE_NEAR=U7270.13:2MM<br />
4<br />
5<br />
8<br />
9<br />
14<br />
1<br />
2<br />
C7276<br />
2.2UF<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
CPUSA_GL0<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
CPUVR_SWSA<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
CPUSA_BOOTSA<br />
MIN_LINE_WIDTH=0.2500<br />
MIN_NECK_WIDTH=0.2000<br />
DIDT=TRUE<br />
68 68<br />
VDRV<br />
PGND<br />
PGND<br />
CGND<br />
BOOT<br />
PHASE<br />
VSWH<br />
GL<br />
GL<br />
NC<br />
MIN_LINE_WIDTH=0.2500<br />
MIN_NECK_WIDTH=0.2000<br />
DIDT=TRUE<br />
MIN_LINE_WIDTH=0.2500<br />
MIN_NECK_WIDTH=0.2000<br />
DIDT=TRUE<br />
CPUSA_PHASESA<br />
R7279 1<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
CPUSA_BPSA<br />
C7279 1<br />
0.22UF<br />
2<br />
10%<br />
25V<br />
X7R<br />
0402<br />
OMIT_TABLE<br />
0.47UH-20A-0.00494OHM<br />
1 2 PPVCCSA_CPU_R<br />
2.2<br />
IHLP2020BD-SM<br />
1<br />
R7278<br />
CPUSA_SW_SNUB<br />
DIDT=TRUE<br />
L7270<br />
5%<br />
1/10W<br />
MF-LF<br />
2<br />
603<br />
NOSTUFF<br />
1<br />
2<br />
C7278<br />
0.001UF<br />
10%<br />
50V<br />
X7R-CERM<br />
0402<br />
NOSTUFF<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.15V<br />
353S00497<br />
2<br />
152S00241 1<br />
CRITICAL<br />
R7270<br />
0.002<br />
1W 1%<br />
CYN<br />
0612<br />
1 2<br />
3 4<br />
R7272<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
1<br />
C7270<br />
33UF<br />
20%<br />
2 16V<br />
TANT-POLY<br />
CASE-B3<br />
CPUSA_ISNS_P<br />
CPUSA_ISNS_N<br />
NO_XNET_CONNECTION=1<br />
R7274<br />
1K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
CPUSA_ISUMN<br />
CPUSA_ISUMP<br />
NO_XNET_CONNECTION=1<br />
IC,FDMF5808A,DRMOS,IMVP8,50A,PQFN31,5X5<br />
IND,MLD,0.47UH,4.94MO,20A,5.4X5.2X2.4MM<br />
1<br />
2<br />
C7271<br />
33UF<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
55<br />
55<br />
67<br />
67<br />
U7210, U7220<br />
L7270<br />
1<br />
2<br />
C7272<br />
2.2UF<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
1<br />
2<br />
C7273<br />
2.2UF<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
CRITICAL<br />
CRITICAL<br />
1<br />
2<br />
2.4G DESENSE<br />
1<br />
CRITICAL<br />
C7280<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
C7274<br />
12PF<br />
5%<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
PART NUMBER QTY DESCRIPTION<br />
REFERENCE DES CRITICAL BOM OPTION<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
5G DESENSE<br />
CRITICAL<br />
C7281<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
BOM_COST_GROUP=CPU & CHIPSET<br />
1<br />
2<br />
PPVCCSA_S0_CPU<br />
100<br />
Vout = 0.55 - 1.15V<br />
IccMax = 5.1A<br />
F = 750kHz<br />
SYNC_MASTER=J79_JSHAO<br />
PAGE TITLE<br />
CORE & SA IMVP POWER BLOCK<br />
R<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
IV ALL RIGHTS RESERVED<br />
Apple Inc.<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
72 OF 145<br />
68 OF 119<br />
SYNC_DATE=12/03/2015<br />
SIZE<br />
D<br />
A<br />
8 7 6<br />
5 4 3<br />
2 1
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
D<br />
C<br />
C<br />
B<br />
B<br />
A<br />
SYNC_MASTER=J79_SILUCHEN<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
Empty<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
REVISION<br />
BRANCH<br />
SYNC_DATE=04/02/2015<br />
DRAWING NUMBER<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
73 OF 145<br />
69 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
100<br />
101<br />
70<br />
70<br />
PPBUS_HS_CPU<br />
PP5V_S0<br />
PVCCCGT_PH1_AGND<br />
CPU VCCGT/GTx Phase 1<br />
70<br />
R7416<br />
1<br />
1 2<br />
70 67<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
67<br />
IN<br />
IN<br />
VOLTAGE=5V<br />
PP5V_S0_VGT1<br />
C7417 1<br />
2.2UF<br />
20%<br />
2<br />
25V<br />
X6S-CERM<br />
0402<br />
CPUGT_FCCM<br />
CPUGT_PWM1<br />
PLACE_NEAR=U7410.32:2MM<br />
70 PVCCCGT_PH1_AGND<br />
NC<br />
NC<br />
8<br />
9<br />
2<br />
1<br />
30<br />
31<br />
3<br />
U7410<br />
FDMF5808A<br />
VIN<br />
BOOT<br />
VIN PQFN-COMBO-THICKSTNCL<br />
PHASE<br />
OMIT_TABLE<br />
FCCM<br />
SW<br />
PWM<br />
SW<br />
NC<br />
NC<br />
4<br />
32<br />
XW7410<br />
2<br />
SM<br />
VCC<br />
AGND<br />
AGND<br />
29<br />
CRITICAL<br />
1<br />
PVCC<br />
PGND<br />
PGND<br />
12<br />
28<br />
GL0<br />
GL1<br />
GH<br />
5<br />
7<br />
16<br />
24<br />
27<br />
33<br />
6<br />
1<br />
C7416<br />
2.2UF<br />
20%<br />
2<br />
25V<br />
X6S-CERM<br />
0402<br />
NC<br />
NC<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
CPUGT_BOOT1<br />
MIN_LINE_WIDTH=0.2500<br />
MIN_NECK_WIDTH=0.2000<br />
DIDT=TRUE<br />
CPUGT1_DRVH<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
CPUGT_SW1<br />
CPUGT_BP1<br />
MIN_LINE_WIDTH=0.2500<br />
MIN_NECK_WIDTH=0.2000<br />
DIDT=TRUE<br />
MIN_LINE_WIDTH=0.2500<br />
MIN_NECK_WIDTH=0.2000<br />
DIDT=TRUE<br />
CPUGT_PHASE1<br />
70<br />
R7419 1<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
C7419 1<br />
0.22UF<br />
2<br />
10%<br />
25V<br />
X7R<br />
0402<br />
0.22UH-20%-44A-0.0019OHM<br />
1 2 PPVCCGT_CPU_PH1<br />
1<br />
R7418<br />
5%<br />
1/10W<br />
MF-LF<br />
2<br />
603<br />
NOSTUFF<br />
CPUGT_SW1_SNUB<br />
1<br />
2<br />
2.2<br />
DIDT=TRUE<br />
L7410<br />
PILA082D-SM<br />
C7418<br />
0.001UF<br />
10%<br />
50V<br />
X7R-CERM<br />
0402<br />
NOSTUFF<br />
NO_XNET_CONNECTION=1<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.5V<br />
NO_XNET_CONNECTION=1<br />
R7412 1<br />
1K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
R7410<br />
0.00075<br />
1%<br />
1W<br />
MF<br />
0612-1<br />
2<br />
4<br />
1<br />
3<br />
1<br />
R7411<br />
2.2<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
NO_XNET_CONNECTION=1<br />
1<br />
R7413<br />
200K<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
1<br />
2<br />
C7410<br />
33UF<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
CPUGT_ISNS1_P<br />
CPUGT_ISNS1_N<br />
NO_XNET_CONNECTION=1<br />
1<br />
2<br />
C7411<br />
33UF<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
OUT<br />
OUT<br />
CPUGT_ISUMN<br />
CPUGT_ISEN1<br />
CPUGT_ISUMP<br />
55<br />
55<br />
70<br />
1<br />
2<br />
C7412<br />
33UF<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
OUT 67 70<br />
OUT 67<br />
OUT 67 70<br />
1<br />
2<br />
C7413<br />
2.2UF<br />
R7414<br />
2<br />
200K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
1<br />
NO_XNET_CONNECTION=1<br />
1<br />
C7414<br />
33UF<br />
20%<br />
2 16V<br />
TANT-POLY<br />
CASE-B3<br />
CPUGT_ISNS2_N<br />
R7415<br />
2<br />
200K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
1<br />
CPUGT_ISNS3_N<br />
NO_XNET_CONNECTION=1<br />
55<br />
1<br />
2<br />
70<br />
C7415<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
PPVCCGT_S0_CPU<br />
100<br />
Vout = 0.55 - 1.5V<br />
IccMax = 64A<br />
F = 750kHz<br />
55<br />
70<br />
D<br />
1<br />
2<br />
CRITICAL<br />
C7440<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7441<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
C<br />
100<br />
101<br />
70<br />
70<br />
PPBUS_HS_CPU<br />
PP5V_S0<br />
R7426<br />
1<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
PVCCCGT_PH2_AGND<br />
CPU VCCGT/GTx Phase 2<br />
70<br />
70 67<br />
67<br />
IN<br />
IN<br />
VOLTAGE=5V<br />
PP5V_S0_VGT2<br />
C7427 1<br />
2.2UF<br />
2<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
CPUGT_FCCM<br />
CPUGT_PWM2<br />
PLACE_NEAR=U7420.32:2MM<br />
70 PVCCCGT_PH2_AGND<br />
NC<br />
NC<br />
101<br />
8<br />
9<br />
2<br />
1<br />
30<br />
31<br />
70<br />
PP5V_S0<br />
3<br />
U7420<br />
FDMF5808A<br />
VIN<br />
BOOT<br />
VIN PQFN-COMBO-THICKSTNCL<br />
PHASE<br />
OMIT_TABLE<br />
FCCM<br />
SW<br />
PWM<br />
SW<br />
NC<br />
NC<br />
4<br />
32<br />
XW7420<br />
2<br />
SM<br />
VCC<br />
AGND<br />
AGND<br />
29<br />
CRITICAL<br />
1<br />
PVCC<br />
PGND<br />
PGND<br />
12<br />
28<br />
GL0<br />
GL1<br />
GH<br />
5<br />
7<br />
16<br />
24<br />
27<br />
33<br />
6<br />
1<br />
C7426<br />
2.2UF<br />
20%<br />
2<br />
25V<br />
X6S-CERM<br />
0402<br />
NC<br />
NC<br />
NC<br />
CPUGT_BOOT2<br />
MIN_LINE_WIDTH=0.2500<br />
MIN_NECK_WIDTH=0.2000<br />
DIDT=TRUE<br />
CPUGT_BP2<br />
MIN_LINE_WIDTH=0.2500<br />
MIN_NECK_WIDTH=0.2000<br />
DIDT=TRUE<br />
CPUGT_PHASE2<br />
CPUGT_SW2<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
MIN_LINE_WIDTH=0.2500<br />
MIN_NECK_WIDTH=0.2000<br />
DIDT=TRUE<br />
R7429 1<br />
0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
C7429 1<br />
0.22UF<br />
10%<br />
25V<br />
2<br />
X7R<br />
0402<br />
0.22UH-20%-44A-0.0019OHM<br />
1 2 PPVCCGT_CPU_PH2<br />
1<br />
R7428<br />
2.2<br />
5%<br />
1/10W<br />
MF-LF<br />
2<br />
603<br />
NOSTUFF<br />
CPUGT_SW2_SNUB<br />
1<br />
2<br />
DIDT=TRUE<br />
L7420<br />
PILA082D-SM<br />
C7428<br />
0.001UF<br />
10%<br />
50V<br />
X7R-CERM<br />
0402<br />
NOSTUFF<br />
NO_XNET_CONNECTION=1<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.5V<br />
NO_XNET_CONNECTION=1<br />
R7422 1<br />
1K<br />
1%<br />
1/20W<br />
201<br />
MF<br />
2<br />
2<br />
4<br />
R7420<br />
0.00075<br />
1%<br />
1W<br />
MF<br />
0612-1<br />
1<br />
3<br />
1<br />
R7421<br />
2.2<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
NO_XNET_CONNECTION=1<br />
1<br />
R7423<br />
200K<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
1<br />
2<br />
C7420<br />
33UF<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
CPUGT_ISNS2_P<br />
CPUGT_ISNS2_N<br />
NO_XNET_CONNECTION=1<br />
1<br />
2<br />
C7421<br />
33UF<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
OUT<br />
OUT<br />
CPUGT_ISUMN<br />
CPUGT_ISEN2<br />
CPUGT_ISUMP<br />
55<br />
55<br />
70<br />
1<br />
2<br />
C7490<br />
33UF<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
OUT<br />
OUT<br />
OUT<br />
67<br />
67<br />
67<br />
70<br />
70<br />
R7424<br />
2<br />
1<br />
2<br />
200K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
C7423<br />
2.2UF<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
NO_XNET_CONNECTION=1<br />
1<br />
CPUGT_ISNS1_N<br />
R7425<br />
2<br />
200K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
1<br />
1<br />
2<br />
C7424<br />
2.2UF<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
CPUGT_ISNS3_N<br />
NO_XNET_CONNECTION=1<br />
55<br />
1<br />
2<br />
70<br />
C7425<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
55<br />
70<br />
2.4G DESENSE<br />
1<br />
2<br />
2.4G DESENSE<br />
CRITICAL<br />
C7442<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
5G DESENSE<br />
1<br />
2<br />
5G DESENSE<br />
CRITICAL<br />
C7443<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
C<br />
B<br />
A<br />
100<br />
70<br />
101<br />
70<br />
PPBUS_HS_CPU<br />
PP5V_S0<br />
PVCCCGT_PH3_AGND<br />
CPU VCCGT/GTx Phase 3<br />
353S00497<br />
70<br />
R7436<br />
1<br />
1 2<br />
70 67<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
67<br />
IN<br />
IN<br />
VOLTAGE=5V<br />
PP5V_S0_VGT3<br />
C7437 1<br />
2.2UF<br />
2<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
CPUGT_FCCM<br />
CPUGT_PWM3<br />
PLACE_NEAR=U7430.32:2MM<br />
70 PVCCCGT_PH3_AGND<br />
101<br />
70<br />
PP5V_S0<br />
3 IC,FDMF808A,DRMOS,IMVP8,50A,PQFN31,5X5<br />
U7410, U7420, U7430 CRITICAL<br />
8<br />
9<br />
2<br />
1<br />
30<br />
31<br />
3<br />
U7430<br />
FDMF5808A<br />
VIN<br />
BOOT<br />
VIN PQFN-COMBO-THICKSTNCL<br />
PHASE<br />
OMIT_TABLE<br />
FCCM<br />
SW<br />
PWM<br />
SW<br />
4<br />
32<br />
XW7430<br />
2<br />
SM<br />
29<br />
CRITICAL<br />
1<br />
12<br />
28<br />
CPUGT_FCCM<br />
PART NUMBER QTY DESCRIPTION<br />
REFERENCE DES CRITICAL BOM OPTION<br />
NC<br />
NC<br />
NC<br />
NC<br />
70 67<br />
VCC<br />
AGND<br />
AGND<br />
PVCC<br />
PGND<br />
PGND<br />
GL0<br />
GL1<br />
GH<br />
5<br />
7<br />
16<br />
24<br />
27<br />
33<br />
6<br />
1<br />
C7436<br />
2.2UF<br />
20%<br />
2<br />
25V<br />
X6S-CERM<br />
0402<br />
NC<br />
MIN_LINE_WIDTH=0.2500<br />
MIN_NECK_WIDTH=0.2000<br />
DIDT=TRUE<br />
CPUGT3_GL0<br />
CPUGT_BOOT3<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
CPUGT_BP3<br />
MIN_LINE_WIDTH=0.2500<br />
MIN_NECK_WIDTH=0.2000<br />
DIDT=TRUE<br />
CPUGT3_DRVH<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
MIN_LINE_WIDTH=0.2500<br />
MIN_NECK_WIDTH=0.2000<br />
DIDT=TRUE<br />
CPUGT_PHASE3<br />
P2MM<br />
SM<br />
1<br />
PP<br />
PP7412<br />
CPUGT_SW3<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
70<br />
70<br />
70<br />
70<br />
R74391 0<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
2<br />
C7439 1<br />
0.22UF<br />
2<br />
10%<br />
25V<br />
X7R<br />
0402<br />
CPUGT1_DRVH<br />
CPUGT3_DRVH<br />
0.22UH-20%-44A-0.0019OHM<br />
1 2 PPVCCGT_CPU_PH3<br />
1<br />
R7438<br />
2.2<br />
5%<br />
1/10W<br />
MF-LF<br />
2<br />
603<br />
NOSTUFF<br />
CPUGT_SW_SNUB<br />
1<br />
2<br />
DIDT=TRUE<br />
L7430<br />
PILA082D-SM<br />
C7438<br />
0.001UF<br />
10%<br />
50V<br />
X7R-CERM<br />
0402<br />
NOSTUFF<br />
P2MM<br />
SM<br />
1<br />
PP<br />
P2MM<br />
SM<br />
1<br />
PP<br />
NO_XNET_CONNECTION=1<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.5V<br />
PP7411<br />
PP7431<br />
NO_XNET_CONNECTION=1<br />
R74321 1K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
70<br />
CPUGT3_GL0<br />
2<br />
4<br />
R7430<br />
0.00075<br />
1%<br />
1W<br />
MF<br />
0612-1<br />
1<br />
3<br />
1<br />
R7431<br />
2.2<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
NO_XNET_CONNECTION=1<br />
1<br />
R7433<br />
200K<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
P2MM<br />
SM<br />
1<br />
1<br />
2<br />
C7430<br />
33UF<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
CPUGT_ISNS3_P<br />
CPUGT_ISNS3_N<br />
NO_XNET_CONNECTION=1<br />
PP7430<br />
1<br />
2<br />
C7431<br />
33UF<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
CPUGT_ISUMN<br />
CPUGT_ISEN3<br />
CPUGT_ISUMP<br />
55<br />
55<br />
70<br />
1<br />
2<br />
C7491<br />
33UF<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
67<br />
67<br />
67<br />
70<br />
70<br />
R7434<br />
200K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
NO_XNET_CONNECTION=1<br />
BOM_COST_GROUP=CPU & CHIPSET<br />
2<br />
1<br />
2<br />
C7433<br />
2.2UF<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
1<br />
CPUGT_ISNS1_N<br />
R7435<br />
2<br />
200K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
1<br />
1<br />
2<br />
C7434<br />
2.2UF<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
CPUGT_ISNS2_N<br />
NO_XNET_CONNECTION=1<br />
SYNC_MASTER=J79_JSHAO<br />
55<br />
1<br />
C7435<br />
12PF<br />
5%<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
70<br />
55<br />
70<br />
GT & GTX IMVP POWER BLOCK<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PP<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
74 OF 145<br />
70 OF 119<br />
SYNC_DATE=09/25/2015<br />
SIZE<br />
D<br />
B<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
D<br />
C<br />
C<br />
B<br />
B<br />
A<br />
SYNC_MASTER=J79_SILUCHEN<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
Empty<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
SYNC_DATE=03/27/2015<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
75 OF 145<br />
71 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
100<br />
PPBUS_HS_OTH5V<br />
5V S4 - V5<br />
5.14V Norm<br />
100<br />
PPBUS_HS_OTH3V3<br />
104<br />
101<br />
72<br />
PP5V_S4<br />
3.3V DSW - V6<br />
C7664 1<br />
2.2UF<br />
20%<br />
2<br />
25V<br />
X6S-CERM<br />
0402<br />
C7663 1<br />
2.2UF<br />
2<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
D<br />
C<br />
104<br />
1<br />
101<br />
72<br />
C7606 1<br />
2.2UF<br />
2<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
C7608<br />
2.2UF<br />
20%<br />
2<br />
25V<br />
X6S-CERM<br />
0402<br />
PP5V_S4<br />
VOUT = 5V<br />
1.58A MAX OUTPUT<br />
F = 500 KHZ<br />
P5VS4_VFB1_R<br />
1<br />
R7677<br />
200<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
5VS4_VFB1_RR<br />
1<br />
R7678<br />
41.2K<br />
0.1%<br />
1/16W<br />
MF<br />
2 0402<br />
C7600 1 33UF<br />
2<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
1<br />
2<br />
C7607 1<br />
150UF<br />
2<br />
20%<br />
6.3V<br />
TANT-POLY<br />
CASE-B1S-1<br />
C7605<br />
150UF<br />
20%<br />
6.3V<br />
TANT-POLY<br />
CASE-B1S-1<br />
XW7675<br />
SM<br />
2<br />
1<br />
XW7671<br />
PLACE_NEAR=C7607.1:3MM<br />
PLACE_NEAR=L7600.1:3MM<br />
PLACE_NEAR=L7600.2:3MM<br />
SM<br />
2<br />
1<br />
1<br />
C7601<br />
2.2UF<br />
20%<br />
2<br />
25V<br />
X6S-CERM<br />
0402<br />
1<br />
OMIT_TABLE<br />
P5VS4_VSW<br />
2<br />
SM<br />
NO STUFF<br />
1<br />
R7674<br />
1 5%<br />
1/10W<br />
MF-LF<br />
2 603<br />
P5VS4_SNUBR<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
XW7670<br />
1<br />
L7600<br />
2.2UH-20%-4.5A-0.043OHM<br />
IHLP1616BZ-PIMA042T-COMBO<br />
2 MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
P5VS4_CSP1_R<br />
NO STUFF<br />
C7674 1 2<br />
0.0033UF<br />
10%<br />
50V<br />
CERM<br />
402<br />
Change R7677 to 200 Ohm 1% and R7678 to 41.2K 0.1% in Proto-2.<br />
1<br />
2<br />
C7602<br />
2.2UF<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
1<br />
6<br />
7<br />
8<br />
VIN<br />
CSD58879Q3D<br />
Q3D<br />
VSW<br />
PGND<br />
U7600<br />
9<br />
TG<br />
TGR<br />
BG<br />
3<br />
4<br />
5<br />
R7672 1<br />
4.87K 1%<br />
1/20W<br />
MF<br />
201 2<br />
1<br />
2<br />
C7603<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
P5VS4_TG<br />
MIN_LINE_WIDTH=0.6000<br />
MIN_NECK_WIDTH=0.2000<br />
GATE_NODE=TRUE<br />
DIDT=TRUE<br />
P5VS4_VBST_R<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
C7609<br />
0.1UF<br />
10%<br />
25V<br />
X6S-CERM<br />
0201<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
C7673<br />
0.1UF<br />
1 2<br />
10%<br />
6.3V<br />
X7R<br />
0201<br />
R7673<br />
698<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
R7609 1<br />
0<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
SKIP_5V3V3:AUDIBLE<br />
SWITCH_NODE=TRUE<br />
GATE_NODE=TRUE<br />
C7678 1<br />
270PF<br />
10%<br />
16V<br />
2<br />
X7R-CERM<br />
0201-1<br />
C7650 1<br />
1.0UF<br />
2<br />
25V<br />
10%<br />
X6S<br />
0402<br />
SKIP_5V3V3:INAUDIBLE<br />
1<br />
R7665<br />
1 5%<br />
1/20W<br />
MF<br />
2 201<br />
SWITCH_NODE=TRUE<br />
GATE_NODE=TRUE<br />
R7651 1 0<br />
5%<br />
1/20W<br />
MF<br />
0201 2<br />
77<br />
77 74<br />
NO STUFF<br />
1<br />
R7676<br />
10K<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
1<br />
2<br />
IN<br />
OUT<br />
P5VS4_VBST<br />
(P5VP3V3_VREF2)<br />
P5VP3V3_SKIPSEL<br />
DIDT=TRUE<br />
P5VS4_DRVH<br />
DIDT=TRUE<br />
P5VS4_SW<br />
DIDT=TRUE<br />
P5VS4_DRVL<br />
DIDT=TRUE<br />
P5VS4_CSP1<br />
P5VS4_CSN1<br />
P5VS4_VFB1<br />
P5VS4_COMP1<br />
P5VS4_EN<br />
P5VS4_PGOOD<br />
P5VS4_COMP1_R<br />
C7679<br />
4700PF<br />
10%<br />
10V<br />
X7R<br />
201<br />
R7650 1 0 5%<br />
1/20W<br />
MF<br />
0201 2<br />
R7675 1<br />
3.92K<br />
1%<br />
1/20W<br />
MF<br />
201 2<br />
6<br />
19<br />
14<br />
2<br />
V5SW<br />
SKIPSEL1<br />
SKIPSEL2<br />
OCSEL<br />
23<br />
VIN<br />
CRITICAL<br />
U7650<br />
QFN<br />
TPS51980A<br />
31 VBST1<br />
VBST2 26<br />
1 DRVH1<br />
DRVH2 24<br />
32 SW1<br />
SW2 25<br />
30 DRVL1<br />
DRVL2 27<br />
7 CSP1<br />
CSP2 18<br />
8 CSN1<br />
CSN2 17<br />
11 MODE<br />
RF 3<br />
9 VFB1<br />
VFB2 16<br />
10 COMP1<br />
COMP2 15<br />
4 EN1<br />
EN2 21<br />
5 PGOOD1<br />
PGOOD2 20<br />
GND<br />
28<br />
SM<br />
1<br />
PLACE_NEAR=U7650.28:1MM<br />
29<br />
2<br />
XW7650<br />
VREG5<br />
22<br />
VREG3<br />
THRM_PAD<br />
33<br />
13<br />
VREF2<br />
P5VP3V3_VREG3<br />
P5VP3V3_VREF2<br />
EN<br />
12<br />
C7652 1 0.22UF<br />
2<br />
P5VS5_EN<br />
P3V3S5_VBST<br />
DIDT=TRUE<br />
P3V3S5_DRVH<br />
DIDT=TRUE<br />
P3V3S5_SW<br />
DIDT=TRUE<br />
P3V3S5_DRVL<br />
DIDT=TRUE<br />
10% 10V<br />
CERM<br />
402<br />
P3V3S5_CSP2<br />
P3V3S5_CSN2<br />
P3V3S5_RF<br />
P3V3S5_VFB2<br />
P3V3S5_COMP2<br />
P3V3S5_EN<br />
S5_PWRGD<br />
1<br />
R7695<br />
3.92K<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
(P5VP3V3_VREF2)<br />
1<br />
2<br />
SWITCH_NODE=TRUE<br />
GATE_NODE=TRUE<br />
SWITCH_NODE=TRUE<br />
GATE_NODE=TRUE<br />
P3V3S5_COMP2_R<br />
1<br />
2<br />
C7653<br />
2.2UF<br />
20%<br />
10V<br />
X5R-CERM<br />
402<br />
IN<br />
IN<br />
OUT<br />
10%<br />
10V<br />
X7R-CERM<br />
201<br />
77<br />
77<br />
74<br />
NO STUFF<br />
C7699 1<br />
2700PF<br />
2<br />
CRITICAL<br />
C7651<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
PP5V_S5 101<br />
VOUT = 5V<br />
100MA MAX OUTPUT<br />
MIN_NECK_WIDTH=0.0520<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
77<br />
R7696 1<br />
10K<br />
1%<br />
1/20W<br />
201<br />
MF<br />
2<br />
1<br />
2<br />
R7685<br />
1<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
330PF<br />
10%<br />
16V<br />
X7R<br />
0201<br />
P3V3S5_TG<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
GATE_NODE=TRUE<br />
P3V3S5_VBST_R<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
1<br />
R7669<br />
0<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
R7655 1<br />
200K 1%<br />
1/20W<br />
MF<br />
201 2<br />
C7698<br />
C7671 1<br />
0.1UF<br />
2<br />
10%<br />
25V<br />
X6S-CERM<br />
0201<br />
R7686<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
C7693<br />
0.1UF<br />
1 2<br />
10%<br />
6.3V<br />
X7R<br />
0201<br />
R7693<br />
1.58K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
C7682 1<br />
12PF 5%<br />
25V<br />
2<br />
3<br />
4<br />
5<br />
NP0-C0G<br />
0201<br />
P3V3S5_DRVL_R<br />
DIDT=TRUE<br />
GATE_NODE=TRUE<br />
1<br />
R7692<br />
3.83K<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
P3V3S5_CSP2_R<br />
L7660<br />
1.0UH-20%-14A-0.0107OHM<br />
U7660<br />
PIMB062D-SM<br />
CSD58873Q3D<br />
Q3D<br />
TG<br />
TGR<br />
BG<br />
9<br />
PGND<br />
VIN<br />
VSW<br />
DIDT=TRUE<br />
1<br />
6<br />
7<br />
8<br />
1<br />
C7660<br />
33UF<br />
20%<br />
20%<br />
2 16V<br />
2 16V<br />
TANT-POLY<br />
TANT-POLY<br />
CASE-B3<br />
CASE-B3<br />
MIN_NECK_WIDTH=0.0520<br />
MIN_LINE_WIDTH=0.0900<br />
P3V3S5_SNUBR<br />
P3V3S5_VSW<br />
NO STUFF<br />
R7694 1<br />
10<br />
5%<br />
1/10W<br />
MF-LF<br />
603 2<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
1<br />
2<br />
NO STUFF<br />
C7694<br />
0.001UF<br />
10%<br />
50V<br />
X7R-CERM<br />
0402<br />
1<br />
C7661<br />
33UF<br />
1<br />
2<br />
PLACE_NEAR=L7660.2:3MM<br />
XW7690<br />
SM<br />
2<br />
1<br />
PLACE_NEAR=L7660.1:3MM<br />
PLACE_NEAR=C7665.1:3MM<br />
2<br />
SM<br />
2<br />
SM<br />
1<br />
2<br />
1<br />
2<br />
C7662<br />
33UF<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
C7665<br />
150UF<br />
20%<br />
6.3V<br />
TANT-POLY<br />
CASE-B1S-1<br />
XW7695<br />
1<br />
XW7691<br />
1<br />
C7666 1<br />
150UF<br />
2<br />
20%<br />
6.3V<br />
TANT-POLY<br />
CASE-B1S-1<br />
P3V3S5_VFB2_R<br />
R76971 402 1%<br />
1/20W<br />
MF<br />
201 2<br />
P3V3S5_VFB2_RR<br />
R7698 1<br />
23.2K<br />
0.1%<br />
1/16W<br />
MF<br />
0402 2<br />
1<br />
2<br />
C7675<br />
33UF<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
PP3V3_S5 101<br />
VOUT = 3.3V<br />
8.47A MAX OUTPUT<br />
F = 500 KHZ<br />
1<br />
2<br />
C7669 1<br />
2.2UF<br />
2<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
C7667<br />
150UF<br />
20%<br />
6.3V<br />
TANT-POLY<br />
CASE-B1S-1<br />
C7668 1<br />
150UF<br />
2<br />
20%<br />
6.3V<br />
TANT-POLY<br />
CASE-B1S-1<br />
1<br />
2<br />
C7670 1<br />
2.2UF<br />
2<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
C7672<br />
150UF<br />
20%<br />
6.3V<br />
TANT-POLY<br />
CASE-B1S-1<br />
C7676 1<br />
150UF<br />
2<br />
20%<br />
6.3V<br />
TANT-POLY<br />
CASE-B1S-1<br />
NO STUFF<br />
C<br />
B<br />
1<br />
R7679<br />
10K<br />
0.1%<br />
1/16W<br />
MF<br />
2 0402<br />
GND_5V3V3_AGND<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=0V<br />
R7699 1<br />
10K<br />
0.1%<br />
1/16W<br />
MF<br />
0402 2<br />
B<br />
1<br />
2<br />
CRITICAL<br />
C7610<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7611<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7612<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7613<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7614<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7615<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7683<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7684<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7685<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7686<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7687<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7688<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
2.4G DESENSE 5G DESENSE 2.4G DESENSE 5G DESENSE 2.4G DESENSE 5G DESENSE<br />
2.4G DESENSE<br />
5G DESENSE<br />
2.4G DESENSE 5G DESENSE<br />
2.4G DESENSE<br />
5G DESENSE<br />
A<br />
PART NUMBER QTY DESCRIPTION<br />
REFERENCE DES CRITICAL BOM OPTION<br />
152S00182<br />
1 IND,PWR,2.2UH,20%,4.5A,43MOHM,4X4MM<br />
L7600<br />
CRITICAL<br />
BOM_COST_GROUP=PLATFORM POWER<br />
SYNC_MASTER=J79_JSHAO<br />
Power - 5V 3.3V Supply<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
76 OF 145<br />
72 OF 119<br />
SYNC_DATE=03/23/2016<br />
SIZE<br />
D<br />
A
SYNC_MASTER=J79_JSHAO<br />
SYNC_DATE=04/12/2016<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
1V EDRAM & EOPIO<br />
D<br />
73<br />
PPVCCEDRAM_S0_REG_F<br />
100<br />
PPBUS_HS_CPU<br />
C7709 1<br />
33UF<br />
2<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
C7700 1<br />
33UF<br />
20%<br />
16V 2<br />
TANT-POLY<br />
CASE-B3<br />
1<br />
2<br />
C7701<br />
2.2UF<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
1<br />
2<br />
C7704<br />
2.2UF<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
D<br />
C<br />
C7715 1 0.1UF<br />
2<br />
10%<br />
6.3V<br />
X7R<br />
0201<br />
BYPASS=U7700.6::1mm<br />
1<br />
R7711<br />
30.9K<br />
0.1%<br />
0.05W<br />
MF<br />
2 0201<br />
PLACE_NEAR=U7700.8:5mm<br />
PVCCEDRAM_VREF_R<br />
1<br />
R7719<br />
3.09K<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
1<br />
R7712<br />
48.7K<br />
0.1%<br />
1/20W<br />
MF<br />
2<br />
0201<br />
PLACE_NEAR=U7700.8:5mm<br />
73<br />
101<br />
73<br />
PP5V_S0<br />
ALL_SYS_PWRGD<br />
BYPASS=U7700.12::1mm<br />
MIN_LINE_WIDTH=0.1160<br />
MIN_NECK_WIDTH=0.0600<br />
1<br />
2<br />
C7716<br />
0.01UF<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
C7703 1 10UF<br />
2<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-1<br />
Scrub S3 & S5 pins connections!<br />
1<br />
R7715<br />
1K<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
PVCCEDRAM_S3_EN<br />
PVCCEDRAM_VREF<br />
MIN_LINE_WIDTH=0.1160<br />
MIN_NECK_WIDTH=0.0600<br />
PLACE_NEAR=U7700.17:3mm<br />
PVCCEDRAM_REFIN<br />
PVCCEDRAM_MODE<br />
PVCCEDRAM_TRIP<br />
1<br />
R7713<br />
33K<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
PLACE_NEAR=U7700.19:3mm<br />
1<br />
R7714<br />
35.7K<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
BYPASS=U7700.2::1mm<br />
PLACE_NEAR=U7700.18:3mm<br />
C7702 1<br />
10UF<br />
20%<br />
10V<br />
2<br />
X5R-CERM<br />
0402-1<br />
12 V5IN<br />
VBST 15<br />
DRVH 14<br />
U7700<br />
17 S3<br />
SW 13<br />
TPS51916<br />
16 S5<br />
QFN<br />
DRVL 11<br />
6 VREF<br />
CRITICAL PGOOD 20<br />
8 REFIN<br />
VDDQSNS 9<br />
VTT 3<br />
19 MODE<br />
VTTSNS 1<br />
18 TRIP<br />
VTTREF 5<br />
PGND<br />
10<br />
7<br />
2<br />
VLDOIN<br />
GND<br />
VTT THRM<br />
GND PAD<br />
4<br />
21<br />
2<br />
XW7700<br />
1<br />
SM<br />
DIDT=TRUE<br />
PVCCEDRAM_VBST<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
PVCCEDRAM_VTT<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
GATE_NODE=TRUE DIDT=TRUE<br />
MIN_LINE_WIDTH=0.1160<br />
MIN_NECK_WIDTH=0.0600<br />
PVCCEDRAM_DRVH<br />
PVCCEDRAM_LL<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0700<br />
SWITCH_NODE=TRUE<br />
DIDT=TRUE<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
GATE_NODE=TRUE<br />
DIDT=TRUE<br />
PVCCEDRAM_VTTREF<br />
PVCCEDRAM_BOOT_RC<br />
PVCCEDRAM_DRVL<br />
C7740 1<br />
0.22UF<br />
20%<br />
10V<br />
2<br />
CERM-X5R<br />
0201<br />
R7730 1<br />
2.2 5%<br />
1/20W MF<br />
201 2<br />
R7731<br />
1<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R7732<br />
1<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
1<br />
2<br />
C7730<br />
0.1UF<br />
10%<br />
25V<br />
X6S-CERM<br />
0201<br />
GATE_NODE=TRUE DIDT=TRUE<br />
MIN_NECK_WIDTH=0.0520<br />
MIN_LINE_WIDTH=0.0900<br />
P1VEDRAM_DRVH_R<br />
GATE_NODE=TRUE DIDT=TRUE<br />
MIN_NECK_WIDTH=0.0520<br />
MIN_LINE_WIDTH=0.0900<br />
P1VEDRAM_DRVL_R<br />
3<br />
4<br />
5<br />
TG<br />
TGR<br />
BG<br />
Q7700<br />
CSD58873Q3D<br />
Q3D<br />
9<br />
PGND<br />
VIN<br />
VSW<br />
1<br />
6<br />
7<br />
8<br />
VOLTAGE=1.00V<br />
MIN_NECK_WIDTH=0.0520<br />
MIN_LINE_WIDTH=0.0900<br />
PPVCCEDRAM_PHASE<br />
1<br />
R7710<br />
2.2<br />
5%<br />
1/10W<br />
MF-LF<br />
2 603<br />
PVCCEDRAM_LL_SNUB<br />
DIDT=TRUE<br />
NOSTUFF<br />
NOSTUFF<br />
C7710 1 2<br />
0.001UF<br />
10%<br />
50V<br />
X7R-CERM<br />
0402<br />
L7700<br />
1UH-20%-11A-0.0127OHM<br />
IHLP2020BD-PIHA052D-COMBO<br />
1 2<br />
55<br />
55<br />
C7705 1<br />
10UF<br />
2<br />
20%<br />
4V<br />
X6S<br />
0402<br />
OUT<br />
OUT<br />
PPVCCEDRAM_S0_REG_R<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.00V<br />
ISNS_CPUEDRAM_P<br />
ISNS_CPUEDRAM_N<br />
C7706 1<br />
10UF<br />
2<br />
20%<br />
4V<br />
X6S<br />
0402<br />
3<br />
1<br />
2<br />
C7707<br />
220UF<br />
20%<br />
2V<br />
ELEC<br />
SM-COMBO<br />
OMIT<br />
R7718<br />
0.005<br />
1%<br />
1/3W<br />
MF<br />
0306-SHORT<br />
2 1<br />
4 3<br />
3<br />
1<br />
2<br />
C7708<br />
220UF<br />
20%<br />
2V<br />
ELEC<br />
SM-COMBO<br />
3<br />
1<br />
2<br />
C7711<br />
220UF<br />
20%<br />
2V<br />
ELEC<br />
SM-COMBO<br />
VOLTAGE=1.00V<br />
MIN_NECK_WIDTH=0.0520<br />
MIN_LINE_WIDTH=0.0900<br />
PPVCCEDRAM_S0_REG_F<br />
3<br />
1<br />
2<br />
C7714<br />
220UF<br />
20%<br />
2V<br />
ELEC<br />
SM-COMBO<br />
Vout = 1.05V<br />
5.2A MAX OUTPUT<br />
F = 500 KHZ<br />
C7712<br />
1<br />
270UF<br />
20%<br />
2 2V<br />
TANT<br />
CASE-B<br />
73<br />
2<br />
PLACE_NEAR=C7707.1:1mm<br />
XW7710<br />
1<br />
SM<br />
C<br />
PVCCEDRAM_AGND<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=0V<br />
BYPASS=U7700.8::1mm<br />
Calculated OCP: min=6.34A, typ=12.07A, max=22.35A<br />
PLACE_NEAR=U7700.21:1mm<br />
P1VOPC_SNS<br />
MIN_LINE_WIDTH=0.1160<br />
MIN_NECK_WIDTH=0.0600<br />
R7741<br />
10<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
P1VOPC_SNS_R<br />
MIN_LINE_WIDTH=0.1160<br />
MIN_NECK_WIDTH=0.0600<br />
PM_PCH_SYS_PWROK 73<br />
B<br />
6<br />
IN<br />
NC_CPU_MSM_L<br />
NC_CPU_MSM_L 102<br />
MAKE_BASE=TRUE<br />
THE FOLLOWING SHORTCUTS ARE USED:<br />
- OPC (EDRAM) IS POWERED FROM ONE VR.<br />
- LOAD SWITCHES ARE USED TO MEET THE TURN-ON TIMING.<br />
- MSM# IS NOT USED.<br />
104 73 48 14<br />
PM_PCH_SYS_PWROK<br />
MAKE_BASE=TRUE<br />
PM_PCH_SYS_PWROK 73<br />
B<br />
77 74 48<br />
ALL_SYS_PWRGD<br />
MAKE_BASE=TRUE<br />
ALL_SYS_PWRGD 73<br />
A<br />
6<br />
101<br />
PP1V0_S3<br />
CPU_ZVM_L<br />
C7790 1<br />
0.1UF<br />
10%<br />
10V<br />
2<br />
X5R-CERM<br />
0201<br />
ZVM is CMOS DC Output:<br />
NC<br />
V_OL Max = Vcc * 0.1V<br />
V_OH Min = Vcc * 0.9V<br />
Vcc referred to in these specs refers to VccST/IO<br />
IN<br />
LEVEL SHIFT<br />
6<br />
VCC<br />
U7790<br />
74AUP1G07GF<br />
SOT891<br />
2 A<br />
Y 4<br />
(OD)<br />
1 NC<br />
NC 5<br />
GND<br />
3<br />
NC<br />
PP3V3_S0 101<br />
NOSTUFF<br />
1<br />
R7791<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
SLG5AP031 EN:<br />
V_IL Max = 1V<br />
V_IH Min = 2V<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
PM_SLP_S3_L<br />
1<br />
R7792<br />
PM_OPC_ZVM_L<br />
14<br />
19<br />
26<br />
73<br />
48<br />
74<br />
77<br />
80<br />
92<br />
101<br />
104<br />
73<br />
PP5V_S0<br />
73<br />
C7760 1<br />
0.1UF<br />
2<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
PM_OPC_ZVM_L<br />
SWEOPIO_CNFG<br />
1<br />
R7760<br />
2.2M<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
2<br />
3<br />
U7760<br />
SLG5AP031<br />
TDFN<br />
4<br />
1<br />
9<br />
73<br />
PPVCCEDRAM_S0_REG_F<br />
5<br />
7<br />
6<br />
8<br />
SWEOPIO_G<br />
4<br />
5<br />
1 2 3<br />
Q7760<br />
FDMC7570S<br />
POWER33<br />
2.4G DESENSE<br />
CRITICAL<br />
C7762<br />
1<br />
12PF<br />
5%<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
4<br />
1<br />
2<br />
5G DESENSE<br />
Q7761<br />
FDMC7570S<br />
POWER33<br />
BOM_COST_GROUP=CPU & CHIPSET<br />
5<br />
3.0PF<br />
1 2 3<br />
CRITICAL<br />
C7763<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
C7761<br />
20UF<br />
20%<br />
2.5V<br />
X6S-CERM<br />
0402-1<br />
104 73 48 14<br />
PPVCCEDRAM_S0_CPU 100<br />
101<br />
74<br />
PP3V3_S0<br />
PM_PCH_SYS_PWROK<br />
Power - EOPIO EDRAM Supply<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
EN<br />
CNFG<br />
GND<br />
VCC<br />
D<br />
G<br />
S<br />
DONE<br />
THRM<br />
PAD<br />
NC<br />
G<br />
D<br />
S<br />
G<br />
D<br />
S<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
1<br />
R7790<br />
10K<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
77 OF 145<br />
73 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
C<br />
B<br />
A<br />
77<br />
74<br />
GND<br />
C7837 1<br />
1.0UF<br />
2<br />
PLACE_NEAR=U7800.M8:2MM<br />
77 74<br />
10%<br />
25V<br />
X6S<br />
0402<br />
77 49 48<br />
R7<strong>820</strong> 1<br />
1M<br />
1%<br />
1/20W<br />
201<br />
MF<br />
NOSTUFF<br />
2<br />
R7821 1<br />
0<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
77<br />
77<br />
74<br />
74<br />
PP3V3_PMICLDO<br />
MAKE_BASE=TRUE<br />
R7837<br />
100K<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
51<br />
51<br />
77<br />
77<br />
C7838 1<br />
1.0UF<br />
10%<br />
25V<br />
2<br />
PLACE_NEAR=U7800.N6:2MM<br />
IN<br />
77 74<br />
X6S<br />
0402<br />
BI<br />
IN<br />
74<br />
74<br />
74<br />
PP3V3_PMICLDO<br />
77<br />
GND<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
77<br />
74<br />
SMC_PM_G2_EN<br />
PP3V3_PMICLDO<br />
PPBUS_PMIC<br />
PMIC_VDCSNS<br />
PP3V3_PMICLDO<br />
GND<br />
SMBUS_SMC_5_G3_SDA<br />
SMBUS_SMC_5_G3_SCL<br />
P5VS4_PGOOD<br />
PP5V_S4<br />
74<br />
GND<br />
PP3V3_PMICLDO<br />
PMIC_SLAVEADDR<br />
PMIC_EN3V3SW<br />
PPBUS_PMIC<br />
PPBUS_PMIC<br />
C7830 1<br />
1UF<br />
2<br />
20%<br />
10V<br />
X6S-CERM<br />
0201<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
D11<br />
H2<br />
E5<br />
L1<br />
(OD)<br />
(OD)<br />
OMIT_TABLE<br />
U7800<br />
P650839A0D<br />
PBGA<br />
(8 OF 10)<br />
CRITICAL<br />
(PP)<br />
K13<br />
NC<br />
K11<br />
NC<br />
H11<br />
GND<br />
PM_PCH_PWROK<br />
BANJO - PMIC Control<br />
PMIC_SHUTDOWN_L<br />
PM_SLP_S0_L<br />
PP3V3_SUS<br />
F1 BAT1<br />
(OD) PCH_PWROK E11<br />
101<br />
E7<br />
(PP) D6<br />
OUT 14 74<br />
VSA<br />
PGA<br />
OUT 77<br />
G1 BAT2<br />
100 PP1V8_S3<br />
K9<br />
(PP)<br />
78<br />
(OD)<br />
G11<br />
VSB<br />
PGB C5<br />
OUT<br />
ALL_SYS_PWRGD<br />
ALL_SYS_PWRGD<br />
OUT 48 73 74 77<br />
77 74 PP3V3_PMICLDO<br />
K8 VSC<br />
PGC C6 NC_PMIC_PGC 102<br />
E2 ACIN (OD) RSMRST_L_PWRGD J11<br />
PM_RSMRST_L<br />
77 74 72 S5_PWRGD<br />
E6<br />
(PP) H3 NC_PMIC_PGD<br />
OUT 74 77<br />
IN<br />
VSD<br />
PGD<br />
102<br />
101 74 73 PP3V3_S0<br />
F4<br />
(PP)<br />
NC_PMIC_PGE 102<br />
G3<br />
D12<br />
VSE<br />
PGE C4<br />
VDCSNS<br />
PMIC_INT*<br />
SMC_PMIC_INT_L<br />
OUT 48 49<br />
100 PP1V8_S0<br />
E8 VSF<br />
(PP) PGF H4 NC_PMIC_PGF 102<br />
J3<br />
77 P5VS4_PGOOD<br />
(PP)<br />
NC_PMIC_PGG 102<br />
H9<br />
EC_RST*<br />
J10<br />
F3<br />
IN<br />
VSG<br />
PGG<br />
NVDC*<br />
104 92 80 77 74 73 48 26 19 14 PM_SLP_S3_L<br />
F5<br />
(OD) M6<br />
PVCCIO_EN<br />
74<br />
101 74 PP3V3_S5<br />
(LDO3V = 3S)<br />
K4<br />
IN<br />
VSH<br />
PGH<br />
OUT<br />
EC_ONOFF*<br />
77 76 P1V8SUS_PGOOD<br />
B12<br />
(OD) L12<br />
PM_SLP_S0S3_L<br />
74<br />
K2<br />
IN<br />
ENA<br />
LVA<br />
OUT<br />
PCH_PWRBTN*<br />
104 77 48 43 19 14 PM_SLP_S4_L<br />
C11<br />
(OD) L10<br />
PM_PCH_PWROK<br />
IN<br />
ENB<br />
LVB<br />
14 74<br />
(OD) DPWROK K12<br />
77 74 PP3V3_PMICLDO<br />
C12 ENC<br />
J13<br />
J2<br />
END<br />
ACSWON*<br />
104 77 14 PM_SLP_SUS_L<br />
F10<br />
P5VS4_PGOOD<br />
IN<br />
ENE<br />
77 72<br />
BAT1SWON* F2<br />
104 92 80 77 74 73 48 26 19 14 PM_SLP_S3_L<br />
J12<br />
IN<br />
ENF<br />
BAT2SWON* G2<br />
GND 74 77<br />
B10 ENG<br />
77 74 72 S5_PWRGD<br />
77 74 67 CPUVR_PGOOD<br />
L11<br />
E4<br />
IN<br />
ENH<br />
VCCST_PWRGD<br />
CPU_VCCST_PWRGD<br />
14<br />
(Pull up on Chipset Page)<br />
104 74 48 19 14 PM_SLP_S0_L<br />
L6<br />
IN<br />
ENLVA<br />
101 74 73 PP3V3_S0<br />
PP3V3_PMICLDO 74 77<br />
100 PP3V0_G3H<br />
PLACE_NEAR=U7800.C13:2MM<br />
1<br />
R7866<br />
C7880<br />
PP5V_PMICLDO_R<br />
0<br />
1UF<br />
1 2<br />
PP5V_PMICLDO<br />
20%<br />
74 75<br />
PM_PCH_PWROK<br />
VOLTAGE=5V<br />
10V<br />
74 14<br />
2<br />
5%<br />
X6S-CERM<br />
1/20W<br />
0201<br />
77 74 73 48 ALL_SYS_PWRGD<br />
MF<br />
GND 74 77<br />
C7841 1 201<br />
1<br />
C7831<br />
1UF<br />
1UF<br />
20%<br />
20%<br />
10V<br />
X6S-CERM 2<br />
2<br />
10V<br />
X6S-CERM<br />
0201<br />
0201<br />
101 74 PP3V3_S5<br />
OMIT_TABLE<br />
100 PP3V0_G3H<br />
B13<br />
U7800<br />
VBATTBKUP<br />
(OD) TRIP* H10 GND 74 77<br />
P650839A0D<br />
PBGA<br />
77 74 GND<br />
J4 VCOMP<br />
(10 OF 10)<br />
NC0 A1<br />
NC<br />
75 74 PVCCIO_EN<br />
NC1 A13<br />
CRITICAL<br />
NC<br />
NC2 N1<br />
NC<br />
NC3 N13<br />
NC<br />
U7800<br />
P650839A0D<br />
PBGA<br />
(7 OF 10)<br />
OMIT_TABLE<br />
R7865<br />
H1 SDA<br />
TEMP_ALERT* L2<br />
100 PPBUS_G3H<br />
0<br />
1 2<br />
J1 SCLK<br />
VOUT3V3SW M7 PP3V3_PMICLDO<br />
74 77<br />
5%<br />
1/20W<br />
MF<br />
L3 SLAVEADDR<br />
LDO3V N8<br />
201<br />
K3 EN3V3SW<br />
VREF1V25 B1 PP1V25_PMICVREF<br />
74<br />
CRITICAL<br />
M5 EN5VSW<br />
LDO5V N7 PP5V_PMICLDO 74 75 76<br />
N5 VIN5VSW<br />
M8 VINLDO3<br />
R7864<br />
PMIC_SLAVEADDR<br />
0<br />
N6 VIN<br />
74<br />
1 2 PP3V3_PMICLDO<br />
74 77<br />
5%<br />
PLACE_NEAR=U7800.N7:2MM<br />
PLACE_NEAR=U7800.N7:2MM<br />
PLACE_NEAR=U7800.B1:2MM<br />
PLACE_NEAR=U7800.N8:2MM<br />
1/20W<br />
MF<br />
1<br />
C7836<br />
1<br />
C7835<br />
1<br />
C7834<br />
1<br />
C7833<br />
201<br />
10UF 10UF 0.47UF 10UF<br />
NOSTUFF<br />
20%<br />
20%<br />
10%<br />
20%<br />
2<br />
6.3V<br />
2<br />
6.3V<br />
2<br />
10V<br />
2<br />
6.3V<br />
CERM-X6S<br />
CERM-X6S<br />
X7R<br />
CERM-X6S<br />
104 92 80 77 74 73 48 26 19 14 PM_SLP_S3_L<br />
0402<br />
0402<br />
0402<br />
0402<br />
1<br />
R7808<br />
SYNC_MASTER=J79_JSHAO<br />
100K<br />
PAGE TITLE<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
74 PM_SLP_S0S3_L<br />
PM_SLP_S0S3_L<br />
77<br />
MAKE_BASE=TRUE<br />
Apple Inc.<br />
PP5V_PMICLDO<br />
PP1V25_PMICVREF<br />
MIN_LINE_WIDTH=0.0900<br />
76 74 75<br />
74<br />
R<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0700<br />
MIN_NECK_WIDTH=0.0520<br />
75 74 PVCCIO_EN<br />
PVCCIO_EN<br />
75<br />
VOLTAGE=5V<br />
VOLTAGE=1.25V<br />
MAKE_BASE=TRUE<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
77 74 76<br />
74<br />
77<br />
ACOK<br />
PWRBTNIN<br />
VINPP<br />
ECVCC<br />
E1<br />
M13<br />
VDDIO0<br />
VDDIO1<br />
D3<br />
VDD5_VPROGOTP<br />
AGND1<br />
AGND2<br />
AGND3<br />
AGND4<br />
C1<br />
K1<br />
L13<br />
D13<br />
DS3_VREN<br />
1HZ<br />
SYS_PWROK<br />
OUT<br />
77<br />
104 74 48 19 14<br />
IN<br />
74<br />
77 74<br />
77<br />
74<br />
PP3V3_PMICLDO<br />
GND<br />
C7839 1 2.2UF<br />
2<br />
PLACE_NEAR=U7800.D1:2MM<br />
C7<br />
D9<br />
10%<br />
10V<br />
X6S-CERM<br />
0402<br />
F6<br />
F7<br />
F8<br />
G5<br />
G6<br />
G7<br />
G8<br />
H5<br />
H6<br />
H7<br />
H8<br />
J5<br />
J6<br />
J7<br />
J8<br />
K6<br />
K7<br />
74<br />
OMIT_TABLE<br />
U7800<br />
P650839A0D<br />
C13<br />
D1<br />
PBGA<br />
(1 OF 10)<br />
CRITICAL<br />
PVCCIO_EN<br />
L8<br />
PP3V3_S5 74 101<br />
1<br />
2<br />
C7840<br />
PLACE_NEAR=U7800.L8:2MM<br />
1UF<br />
20%<br />
10V<br />
X6S-CERM<br />
0201<br />
GND 74 77<br />
C8<br />
P3V3SUS_PGOOD<br />
P1V8S3_EN<br />
BOM_COST_GROUP=PLATFORM POWER<br />
77<br />
101<br />
74<br />
74<br />
74<br />
77 74 67<br />
77 74<br />
73<br />
101<br />
PP3V3_PMICLDO<br />
PMIC_SHUTDOWN_L<br />
PP3V3_S0<br />
CPUVR_PGOOD<br />
PP3V3_SUS<br />
PM_RSMRST_L<br />
1<br />
R7801<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
1<br />
R7804<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
1<br />
R7860<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
1<br />
R7861<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
1<br />
R7810<br />
4.7K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
PPBUS_PMIC<br />
1<br />
R7802<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
1<br />
R7805<br />
1<br />
R7807<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
VOLTAGE=13.1V<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
PMIC-1 & Power Control<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
SHUTDOWN*<br />
STANDBY*<br />
V3P3A_RTC<br />
AGND<br />
VDDPG<br />
VDDLV<br />
RESET*<br />
NC<br />
IV ALL RIGHTS RESERVED<br />
REVISION<br />
BRANCH<br />
74<br />
DRAWING NUMBER<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
78 OF 145<br />
74 OF 119<br />
SYNC_DATE=09/09/2015<br />
SIZE<br />
D<br />
D<br />
C<br />
B<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
1.2V VDDQ - V10 (Banjo#1 VR4)<br />
Calculated OCP: min=9.83A, typ=18.18A, max=32.64A<br />
R7900 1<br />
11K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
Check R7901<br />
R7901 1<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
77<br />
7<br />
74<br />
77<br />
76 74<br />
IN<br />
IN<br />
OUT<br />
IN<br />
PP5V_PMICLDO<br />
P1V2S3_ILIM<br />
GND<br />
PM_MEMVTT_EN<br />
PVCCIO_EN<br />
PM_SLP_S4_L<br />
B4<br />
D2<br />
D4<br />
E3<br />
B5<br />
C2<br />
VREGVR4<br />
ILIMVR4<br />
OMIT_TABLE<br />
DDRID<br />
DDR_VTT_CTRL<br />
PGVR4<br />
ENVR4<br />
(OD)<br />
U7800<br />
P650839A0D<br />
PBGA<br />
(5 OF 10)<br />
CRITICAL<br />
PGNDVR4<br />
A4<br />
VBSTVR4<br />
DRVHVR4<br />
SWVR4<br />
DRVLVR4<br />
FBVR4+<br />
FBVR4-<br />
B3<br />
A2<br />
A3<br />
A5<br />
C3<br />
D5<br />
P1V2_VBST<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
P1V2_DRVH<br />
P1V2_SW<br />
P1V2_DRVL<br />
P1V2S3_FB_P<br />
P1V2S3_FB_N<br />
R7902<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE SWITCH_NODE=TRUE<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
GATE_NODE=TRUE<br />
1<br />
R7903<br />
0<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
P1V2_VBST_R<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
1<br />
R7904<br />
10<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
100<br />
C7904<br />
0.1UF<br />
1 2<br />
20%<br />
16V<br />
X6S-CERM<br />
0201<br />
DIDT=TRUE<br />
PPBUS_HS_CPU<br />
DIDT=TRUE<br />
GATE_NODE=TRUE<br />
GATE_NODE=TRUE<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
P1V2_DRVL_R<br />
DIDT=TRUE<br />
GATE_NODE=TRUE<br />
P1V2S3_FB_R_P<br />
P1V2_DRVH_R<br />
R7905<br />
R7906<br />
0<br />
1<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
1 2<br />
3<br />
4<br />
5<br />
TG<br />
TGR<br />
BG<br />
U7900<br />
CSD58873Q3D<br />
Q3D<br />
9<br />
PGND<br />
VIN<br />
VSW<br />
1<br />
6<br />
7<br />
8<br />
DIDT=TRUE<br />
MIN_NECK_WIDTH=0.0520<br />
MIN_LINE_WIDTH=0.0900<br />
P1V2_PHASE<br />
P1V2_SW_SNUB<br />
NOSTUFF<br />
NOSTUFF<br />
DIDT=TRUE<br />
C7900 1<br />
33UF<br />
20%<br />
16V 2<br />
TANT-POLY<br />
CASE-B3<br />
R7917 1<br />
2.2<br />
5%<br />
1/10W<br />
MF-LF<br />
603<br />
2<br />
C7917 1 2<br />
0.001UF<br />
10%<br />
50V<br />
X7R-CERM<br />
0402<br />
L7900<br />
0.56UH-20%-19A-0.0065OHM<br />
53<br />
53<br />
C7901 1<br />
33UF<br />
2<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
1 2<br />
PILA062D-SM-COMBO<br />
PP1V2_S3_REG_R<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.2V<br />
OUT<br />
OUT<br />
ISNS_CPUDDR_P<br />
ISNS_CPUDDR_N<br />
1<br />
2<br />
C7902<br />
2.2UF<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
1<br />
2<br />
OMIT<br />
R7918<br />
0.005<br />
1%<br />
1/3W<br />
MF<br />
0306-SHORT<br />
1 2<br />
3 4<br />
XW7904<br />
SM<br />
1 2<br />
C7903<br />
2.2UF<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
1<br />
2<br />
C7905<br />
270UF<br />
20%<br />
2V<br />
TANT<br />
CASE-B<br />
C7906 1<br />
270UF<br />
20%<br />
2<br />
2V<br />
TANT<br />
CASE-B<br />
3<br />
1<br />
2<br />
C7907<br />
220UF<br />
20%<br />
2V<br />
ELEC<br />
SM-COMBO<br />
C7908 1<br />
220UF<br />
2 3<br />
20%<br />
2V<br />
ELEC<br />
SM-COMBO<br />
1<br />
2<br />
5G DESENSE<br />
CRITICAL<br />
C7921<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
10UF<br />
1<br />
2<br />
2.4G DESENSE<br />
C7913<br />
20%<br />
2<br />
4V<br />
X6S<br />
0402<br />
C7914 1<br />
10UF<br />
2<br />
20%<br />
4V<br />
X6S<br />
0402<br />
CRITICAL<br />
C7922<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
PP1V2_S3 78 100<br />
Vout = 1.2V<br />
IccMax = 8.21A<br />
F = 600kHz<br />
D<br />
P1V2S3_FB_R_N<br />
1 2<br />
XW7903<br />
SM<br />
C<br />
0.6V VTT - V13 (Banjo#1 LDO1)<br />
C<br />
100<br />
PP1V2_S3<br />
C7935 1<br />
10UF<br />
20%<br />
4V<br />
X6S 2<br />
0402<br />
C7930 1<br />
10UF<br />
2<br />
20%<br />
4V<br />
X6S<br />
0402<br />
XW7931<br />
SM<br />
1 2<br />
PMIC_VINLDO1S<br />
A6<br />
B6<br />
F9<br />
VINLDO1_0<br />
VINLDO1_1<br />
VINLDO1S<br />
OMIT_TABLE<br />
U7800<br />
P650839A0D<br />
PBGA<br />
(9 OF 10)<br />
CRITICAL<br />
PGNDLDO1_0<br />
A7<br />
PGNDLDO1_1<br />
B7<br />
VOUTLDO1_0<br />
VOUTLDO1_1<br />
FBLDO1<br />
A8<br />
B8<br />
D8<br />
PVTT_FB<br />
R7930<br />
10<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
XW7930<br />
SM<br />
1 2<br />
1<br />
C7931<br />
15UF<br />
20%<br />
2<br />
2V<br />
X6S<br />
0402<br />
PVTT_FB_R<br />
1<br />
2<br />
C7932<br />
15UF<br />
20%<br />
2V<br />
X6S<br />
0402<br />
1<br />
2<br />
C7933<br />
15UF<br />
20%<br />
2V<br />
X6S<br />
0402<br />
1<br />
2<br />
C7934<br />
15UF<br />
20%<br />
2V<br />
X6S<br />
0402<br />
1<br />
2<br />
C7936<br />
15UF<br />
20%<br />
2V<br />
X6S<br />
0402<br />
1<br />
2<br />
C7937<br />
15UF<br />
20%<br />
2V<br />
X6S<br />
0402<br />
PP0V6_S0_DDRVTT 100<br />
Vout = 0.6V<br />
IccMax = 0.512A<br />
1<br />
2<br />
CRITICAL<br />
C7940<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7941<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
2.4G DESENSE<br />
5G DESENSE<br />
B<br />
B<br />
A<br />
100<br />
75<br />
0.95V VCCIO - V6 (Banjo#1 VR3)<br />
PPBUS_HS_CPU<br />
R7961 1<br />
7.5K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
XW7964<br />
SM<br />
1 2<br />
Calculated OCP: min=3.95A, typ=7.38A, max=13.3A<br />
77<br />
74<br />
OUT<br />
IN<br />
PMIC_VINVR3<br />
PVCCIO_ILIM_LS<br />
PVCCIO_PGOOD<br />
PVCCIO_EN<br />
G9<br />
D10<br />
C9<br />
B9<br />
E9<br />
VINVR3<br />
ILIMVR3HS<br />
ILIMVR3LS<br />
PGVR3<br />
ENVR3<br />
OMIT_TABLE<br />
U7800<br />
P650839A0D<br />
PBGA<br />
(4 OF 10)<br />
CRITICAL<br />
PGNDVR3<br />
A10<br />
VBSTVR3<br />
DRVHVR3<br />
SWVR3<br />
DRVLVR3<br />
FBVR3+<br />
FBVR3-<br />
B11<br />
A12<br />
A11<br />
A9<br />
C10<br />
D7<br />
PVCCIO_VBST<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
PVCCIO_DRVH<br />
PVCCIO_SW<br />
PVCCIO_DRVL<br />
PVCCIO_FB_P<br />
PVCCIO_FB_N<br />
R7962 1<br />
0<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
1<br />
R7964<br />
0<br />
2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
PVCCIO_VBST_R<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
C7963<br />
0.1UF<br />
MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE GATE_NODE=TRUE<br />
MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE SWITCH_NODE=TRUE<br />
MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE GATE_NODE=TRUE<br />
R7963 1<br />
10<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
1<br />
20%<br />
2<br />
16V<br />
X6S-CERM<br />
0201<br />
CPU_VCCIOSENSE_P<br />
CPU_VCCIOSENSE_N<br />
100<br />
75<br />
PPBUS_HS_CPU<br />
3<br />
4<br />
5<br />
IN<br />
IN<br />
TG<br />
8<br />
8<br />
U7960<br />
CSD58889Q3D<br />
Q3D<br />
TGR<br />
BG<br />
9<br />
PGND<br />
VIN<br />
VSW<br />
1<br />
6<br />
7<br />
8<br />
DIDT=TRUE<br />
MIN_NECK_WIDTH=0.2000<br />
MIN_LINE_WIDTH=0.6000<br />
PVCCIO_PHASE<br />
NOSTUFF<br />
C7960 1<br />
33UF<br />
20%<br />
16V 2<br />
TANT-POLY<br />
CASE-B3<br />
R7969 1<br />
2.2<br />
5%<br />
1/10W<br />
MF-LF<br />
603<br />
2<br />
PVCCIO_SW_SNUB<br />
DIDT=TRUE<br />
1<br />
2<br />
L7960<br />
1UH-20%-11A-0.0127OHM<br />
NOSTUFF<br />
C7961<br />
2.2UF<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
1 2<br />
IHLP2020BD-PIHA052D-COMBO<br />
C7969 1 2<br />
0.001UF<br />
10%<br />
50V<br />
X7R-CERM<br />
0402<br />
1<br />
2<br />
C7962<br />
2.2UF<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
C7964 1<br />
10UF<br />
2<br />
20%<br />
4V<br />
X6S<br />
0402<br />
C7965 1<br />
10UF<br />
2<br />
20%<br />
4V<br />
X6S<br />
0402<br />
C7966<br />
220UF<br />
20%<br />
2V<br />
ELEC<br />
SM-COMBO<br />
BOM_COST_GROUP=PLATFORM POWER<br />
3<br />
1<br />
2<br />
3<br />
1<br />
2<br />
C7967<br />
220UF<br />
20%<br />
2V<br />
ELEC<br />
SM-COMBO<br />
1<br />
2<br />
2.4G DESENSE<br />
5G DESENSE<br />
PPVCCIO_S0_CPU 100<br />
SYNC_MASTER=J79_JSHAO<br />
PAGE TITLE<br />
CRITICAL<br />
C7970<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C7971<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
Vout = 0.95V<br />
IccMax = 3.1A<br />
F = 500kHz<br />
PMIC-1 1.2V 0.6V VCCIO<br />
R<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
IV ALL RIGHTS RESERVED<br />
Apple Inc.<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
79 OF 145<br />
75 OF 119<br />
SYNC_DATE=12/03/2015<br />
SIZE<br />
D<br />
A<br />
8 7 6<br />
5 4 3<br />
2 1
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
1V - V11 (Banjo#1 VR1)<br />
100<br />
PPBUS_G3H<br />
PP1V0_SUS 101<br />
D<br />
76 75 74<br />
PP5V_PMICLDO<br />
C8016 1<br />
1UF<br />
2<br />
R8000 1<br />
6.04K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
20%<br />
10V<br />
X6S-CERM<br />
0201<br />
77<br />
77<br />
78<br />
OUT<br />
IN<br />
P1VSUS_ILIM<br />
P1VSUS_PGOOD<br />
P1V0PCH_PGOOD<br />
Calculated OCP: min=3.98A, typ=7.42A, max=13.66A<br />
M10<br />
L9<br />
M9<br />
M12<br />
VREGVR1<br />
ILIMVR1<br />
PGVR1<br />
ENVR1<br />
OMIT_TABLE<br />
U7800<br />
P650839A0D<br />
PBGA<br />
(2 OF 10)<br />
CRITICAL<br />
PGNDVR1<br />
N10<br />
VBSTVR1<br />
DRVHVR1<br />
SWVR1<br />
DRVLVR1<br />
FBVR1+<br />
FBVR1-<br />
M11<br />
N12<br />
N11<br />
N9<br />
K10<br />
J9<br />
P1VS4_VBST<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
P1VS4_DRVH<br />
P1VS4_SW<br />
P1VS4_DRVL<br />
P1VS4_FB_P<br />
P1VS4_FB_N<br />
DIDT=TRUE<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_LINE_WIDTH=0.0900<br />
1<br />
R8002<br />
0<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
MIN_NECK_WIDTH=0.0520<br />
MIN_NECK_WIDTH=0.0520<br />
MIN_NECK_WIDTH=0.0520<br />
P1VS4_VBST_R<br />
1<br />
R8001<br />
0<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
1<br />
R8003<br />
10<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
MIN_NECK_WIDTH=0.0520<br />
MIN_LINE_WIDTH=0.0900<br />
DIDT=TRUE<br />
1<br />
DIDT=TRUE<br />
DIDT=TRUE<br />
DIDT=TRUE<br />
C8003<br />
0.1UF<br />
20%<br />
2<br />
16V<br />
X6S-CERM<br />
0201<br />
P1VS4_FB_R_P<br />
P1VS4_FB_R_N<br />
GATE_NODE=TRUE<br />
SWITCH_NODE=TRUE<br />
GATE_NODE=TRUE<br />
3<br />
4<br />
5<br />
TG<br />
U8000<br />
CSD58889Q3D<br />
Q3D<br />
TGR<br />
BG<br />
9<br />
PGND<br />
VIN<br />
VSW<br />
1<br />
6<br />
7<br />
8<br />
DIDT=TRUE<br />
MIN_NECK_WIDTH=0.2000<br />
MIN_LINE_WIDTH=0.6000<br />
P1VS4_PHASE<br />
NOSTUFF<br />
C8000 1<br />
2.2UF<br />
2<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
R8009 1<br />
2.2<br />
5%<br />
1/10W<br />
MF-LF<br />
603<br />
2<br />
P1VS4_SW_SNUB<br />
DIDT=TRUE<br />
C8001 1<br />
2.2UF<br />
2<br />
1UH-20%-11A-0.0127OHM<br />
1 2 PP1V_PCH_REG_R<br />
NOSTUFF<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
L8000<br />
IHLP2020BD-PIHA052D-COMBO<br />
C8009 1 2<br />
0.001UF<br />
10%<br />
50V<br />
X7R-CERM<br />
0402<br />
53<br />
53<br />
1<br />
2<br />
C8002<br />
33UF<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.0V<br />
OUT<br />
OUT<br />
ISNS_1V0_P<br />
ISNS_1V0_N<br />
XW8003<br />
SM<br />
1 2<br />
1 2<br />
XW8004<br />
SM<br />
OMIT<br />
R8004<br />
0.005<br />
1%<br />
1/3W<br />
MF<br />
0306-SHORT<br />
1 2<br />
3 4<br />
C8004 1<br />
10UF<br />
20%<br />
4V<br />
2<br />
X6S<br />
0402<br />
1<br />
2<br />
2.4G DESENSE 5G DESENSE<br />
2.4G DESENSE 5G DESENSE<br />
C8005 1<br />
10UF<br />
2<br />
20%<br />
4V<br />
X6S<br />
0402<br />
CRITICAL<br />
C8010<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
3<br />
1<br />
2<br />
CRITICAL<br />
C8011<br />
1<br />
3.0PF<br />
+/-0.1PF<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
C8006<br />
220UF<br />
20%<br />
2V<br />
ELEC<br />
SM-COMBO<br />
3<br />
C8007<br />
220UF<br />
20%<br />
2V<br />
ELEC<br />
SM-COMBO<br />
Vout = 1.0V<br />
IccMax = 3.29A<br />
F = 500kHz<br />
1<br />
2<br />
1<br />
2<br />
CRITICAL<br />
C8017<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
CRITICAL<br />
C8018<br />
1<br />
3.0PF<br />
+/-0.1PF<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
D<br />
PP1V8_SUS 100<br />
C<br />
101<br />
C8024 1<br />
2.2UF<br />
2<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
PP3V3_S5<br />
C8020 1<br />
2.2UF<br />
20%<br />
25V<br />
2<br />
X6S-CERM<br />
0402<br />
1<br />
2<br />
76 75 74<br />
C8021<br />
150UF<br />
20%<br />
6.3V<br />
TANT-POLY<br />
CASE-B1S-1<br />
PP5V_PMICLDO<br />
1<br />
2<br />
C8025<br />
1UF<br />
20%<br />
10V<br />
X6S-CERM<br />
0201<br />
77 74<br />
77<br />
OUT<br />
IN<br />
1.8V - V8 (Banjo#1 VR2)<br />
P1V8SUS_PGOOD<br />
PM_SLP_SUS_L<br />
F12<br />
F13<br />
E13<br />
E12<br />
F11<br />
VINVR2_0<br />
VINVR2_1<br />
VREGVR2<br />
PGVR2<br />
ENVR2<br />
OMIT_TABLE<br />
U7800<br />
P650839A0D<br />
G12<br />
PBGA<br />
(3 OF 10)<br />
CRITICAL<br />
PGNDVR2_1<br />
PGNDVR2_0<br />
G13<br />
SWVR2_0<br />
SWVR2_1<br />
FBVR2+<br />
FBVR2-<br />
H12<br />
H13<br />
G10<br />
E10<br />
P1V8SUS_SW<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
P1V8SUS_FB_P<br />
P1V8SUS_FB_N<br />
R8020 1<br />
100<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
NOSTUFF<br />
R8029 1<br />
2.2<br />
5%<br />
1/10W<br />
MF-LF<br />
603<br />
2<br />
1<br />
R8021<br />
10<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
0.47UH-20%-4.0A-28MOHM<br />
1 2 PP1V8_SUS_REG_R<br />
DIDT=TRUE<br />
P1V8SUS_FB_R_P<br />
PIFE25201B-SM<br />
P1V8S3_SW_SNUB<br />
NOSTUFF<br />
L8020<br />
0.001UF<br />
10%<br />
50V<br />
X7R-CERM<br />
0402<br />
53<br />
53<br />
C8029 1 2<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.8V<br />
OUT<br />
OUT<br />
XW8021<br />
SM<br />
1 2<br />
ISNS_1V8_SUS_P<br />
ISNS_1V8_SUS_N<br />
P1V8SUS_FB_RC<br />
OMIT<br />
R8024<br />
0.005<br />
1%<br />
1/3W<br />
MF<br />
0306-SHORT<br />
1 2<br />
3 4<br />
R8025 1<br />
100<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
1<br />
2<br />
C8022<br />
100UF<br />
20%<br />
6.3V<br />
TANT-POLY<br />
CASE-A3-LLP<br />
1<br />
2<br />
C8023<br />
100UF<br />
20%<br />
6.3V<br />
TANT-POLY<br />
CASE-A3-LLP<br />
2.4G DESENSE<br />
Vout = 1.8V<br />
IccMax = 0.7A<br />
F = 2MHz<br />
1<br />
2<br />
CRITICAL<br />
C8030<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
5G DESENSE<br />
C8026<br />
20UF<br />
1<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402<br />
CRITICAL<br />
C8031<br />
3.0PF<br />
+/-0.1PF<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
C8027<br />
20UF<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402<br />
C<br />
B<br />
A<br />
100<br />
76<br />
PPBUS_G3H<br />
1.0V PCH CORE - V11 (Banjo#1 VR5)<br />
0.7V LPM<br />
R8007 1<br />
7.68K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
PMIC_VINVR5<br />
P1V0PCH_ILIM_LS<br />
P1V0PCH_PGOOD<br />
P3V3SUS_PGOOD<br />
Calculated OCP: min=3.98A, typ=7.42A, max=13.4A<br />
77<br />
77<br />
OUT<br />
IN<br />
XW8054<br />
SM<br />
1 2<br />
L7<br />
K5<br />
L5<br />
M4<br />
M2<br />
VINVR5<br />
ILIMVR5HS<br />
ILIMVR5LS<br />
PGVR5<br />
ENVR5<br />
OMIT_TABLE<br />
U7800<br />
P650839A0D<br />
PBGA<br />
(6 OF 10)<br />
CRITICAL<br />
PGNDVR5<br />
N3<br />
VBSTVR5<br />
DRVHVR5<br />
SWVR5<br />
DRVLVR5<br />
FBVR5+<br />
FBVR5-<br />
M3<br />
M1<br />
N2<br />
N4<br />
G4<br />
L4<br />
P1V0PCH_VBST<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
P1V0PCH_DRVH<br />
P1V0PCH_SW<br />
P1V0PCH_DRVL<br />
P1V0PCH_FB_P<br />
P1V0PCH_FB_N<br />
R8051<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_LINE_WIDTH=0.0900<br />
1<br />
R8052<br />
0<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
P1V0PCH_VBST_R<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
MIN_NECK_WIDTH=0.0520<br />
MIN_NECK_WIDTH=0.0520<br />
MIN_NECK_WIDTH=0.0520<br />
1<br />
R8053<br />
10<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
100<br />
DIDT=TRUE<br />
DIDT=TRUE<br />
DIDT=TRUE<br />
76<br />
PPBUS_G3H<br />
C8053<br />
0.1UF<br />
1 2<br />
20%<br />
16V<br />
X6S-CERM<br />
0201<br />
GATE_NODE=TRUE<br />
SWITCH_NODE=TRUE<br />
GATE_NODE=TRUE<br />
P1V0PCH_FB_R_P<br />
P1V0PCH_FB_R_N<br />
3<br />
4<br />
5<br />
TG<br />
TGR<br />
BG<br />
U8050<br />
CSD58889Q3D<br />
Q3D<br />
9<br />
PGND<br />
VIN<br />
VSW<br />
1<br />
6<br />
7<br />
8<br />
DIDT=TRUE<br />
MIN_NECK_WIDTH=0.2000<br />
MIN_LINE_WIDTH=0.6000<br />
P1V0PCH_PHASE<br />
NOSTUFF<br />
P1V0PCH_SW_SNUB<br />
DIDT=TRUE<br />
C8013 1<br />
33UF<br />
2<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
R8059 1<br />
2.2<br />
5%<br />
1/10W<br />
MF-LF<br />
603<br />
2<br />
NOSTUFF<br />
P1V8SUS_FB_R_N<br />
1<br />
2<br />
2.2UF<br />
C8059 1 2<br />
0.001UF<br />
C8014<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
L8050<br />
1UH-20%-11A-0.0127OHM<br />
IHLP2020BD-PIHA052D-COMBO<br />
1 2<br />
10%<br />
50V<br />
X7R-CERM<br />
0402<br />
55<br />
55<br />
1<br />
2<br />
C8015<br />
2.2UF<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
1 2<br />
XW8020<br />
SM<br />
P1V0PCH_REG_R<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=0.85V<br />
ISNS_PCHPRIMCORE_P<br />
ISNS_PCHPRIMCORE_N<br />
C8028 1<br />
0.01UF<br />
10%<br />
25V<br />
2<br />
X5R-CERM<br />
0201<br />
OMIT<br />
R8054<br />
0.005<br />
1%<br />
1/3W<br />
MF<br />
0306-SHORT<br />
2 1<br />
4 3<br />
XW8053<br />
SM<br />
1 2<br />
1 2<br />
XW8052<br />
SM<br />
C8054 1<br />
10UF<br />
2<br />
20% 4V<br />
X6S<br />
0402<br />
C8055 1<br />
10UF<br />
2<br />
20% 4V<br />
X6S<br />
0402<br />
BOM_COST_GROUP=PLATFORM POWER<br />
3<br />
1<br />
C8056<br />
220UF<br />
20%<br />
2 2V<br />
ELEC<br />
SM-COMBO<br />
SYNC_MASTER=J79_JSHAO<br />
2.4G DESENSE<br />
3<br />
1<br />
5G DESENSE<br />
PPVCCPRIMCORE_SUS_PCH 100<br />
1<br />
2<br />
CRITICAL<br />
C8060<br />
12PF<br />
5%<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
C8057<br />
220UF<br />
20%<br />
2V<br />
ELEC<br />
SM-COMBO<br />
1<br />
2<br />
CRITICAL<br />
C8061<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
Vout = 1.0V<br />
IccMax = 2.58A<br />
F = 500kHz<br />
PMIC-1 1V 1.8V VCCPCH<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
OUT<br />
OUT<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
80 OF 145<br />
76 OF 119<br />
SYNC_DATE=12/03/2015<br />
SIZE<br />
D<br />
B<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
KEEP THESE RAILS ON WHEN USING XDP<br />
D<br />
C<br />
74 49 48<br />
104 74 14<br />
104 48 19 14<br />
104 77 74 48 43 19 14<br />
104 92 80 74 73 48 26 19 14<br />
S5 Enables<br />
SMC_PM_G2_EN<br />
MAKE_BASE=TRUE<br />
SUS Enables<br />
PM_SLP_SUS_L<br />
MAKE_BASE=TRUE<br />
S4 Enables<br />
PM_SLP_S5_L<br />
MAKE_BASE=TRUE<br />
S3 Enables<br />
PM_SLP_S4_L<br />
MAKE_BASE=TRUE<br />
S0 Enables<br />
PM_SLP_S3_L<br />
MAKE_BASE=TRUE<br />
R8110<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
PMIC_EN_P3V3S5<br />
PM_SLP_SUS_L 76<br />
PM_SLP_SUS_L 78<br />
PM_SLP_S5_L 78<br />
PM_SLP_S5_L 78<br />
PM_SLP_S5_L 77<br />
PM_SLP_S4_L 75<br />
PM_SLP_S3_L 77<br />
PM_SLP_S3_L 78<br />
PM_SLP_S3_L 78<br />
77<br />
77<br />
77<br />
74<br />
101<br />
74 72<br />
77 76<br />
74<br />
74<br />
74<br />
74<br />
74 73 48<br />
72<br />
PP3V3_PMICLDO<br />
MAKE_BASE=TRUE<br />
PP5V_S4<br />
P5VS4_PGOOD<br />
MAKE_BASE=TRUE<br />
P1V0PCH_PGOOD<br />
MAKE_BASE=TRUE<br />
GND<br />
MAKE_BASE=TRUE<br />
P3V3SUS_PGOOD<br />
MAKE_BASE=TRUE<br />
GND<br />
MAKE_BASE=TRUE<br />
ALL_SYS_PWRGD<br />
MAKE_BASE=TRUE<br />
S5_PWRGD<br />
PP3V3_PMICLDO 74<br />
PP5V_S4 74<br />
P5VS4_PGOOD 74<br />
P5VS4_PGOOD 74<br />
P1V0PCH_PGOOD 76 78<br />
GND 75<br />
P3V3SUS_PGOOD 76<br />
GND 74<br />
ALL_SYS_PWRGD 67<br />
S5_PWRGD<br />
MAKE_BASE=TRUE<br />
48<br />
I14<br />
I17<br />
I19<br />
I28<br />
I29<br />
74<br />
67<br />
75<br />
76<br />
76<br />
74<br />
77<br />
76<br />
CPUVR_PGOOD<br />
PVCCIO_PGOOD<br />
P1VSUS_PGOOD<br />
P1V8SUS_PGOOD<br />
P1V0PCH_PGOOD<br />
1<br />
1<br />
1<br />
1<br />
1<br />
P2MM<br />
SM<br />
PP<br />
P2MM<br />
SM<br />
PP<br />
P2MM<br />
SM<br />
PP<br />
P2MM<br />
SM<br />
PP<br />
P2MM<br />
SM<br />
PP<br />
PP8100<br />
PP8101<br />
PP8102<br />
PP8106<br />
PP8107<br />
77 17<br />
104 77 74 48 43 19 14<br />
77 17<br />
77 74<br />
IN<br />
IN<br />
101<br />
IN<br />
IN<br />
101<br />
77<br />
77<br />
17<br />
XDP_PRESENT_L<br />
PM_SLP_S4_L<br />
17<br />
PP3V3_SUS<br />
XDP:YES<br />
C8192 1<br />
0.1UF<br />
10%<br />
10V<br />
2<br />
XDP_PRESENT_L<br />
PM_SLP_S0S3_L<br />
X5R-CERM<br />
0201<br />
XDP:NO<br />
R8193<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
(INV)<br />
PP3V3_SUS<br />
XDP:YES<br />
C8194 1<br />
0.1UF<br />
10%<br />
10V<br />
2<br />
X5R-CERM<br />
0201<br />
XDP:NO<br />
R8195<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
(INV)<br />
6<br />
3<br />
5<br />
1<br />
6<br />
3<br />
2<br />
5<br />
1<br />
2<br />
XDP:YES<br />
U8192<br />
74AUP1T97GM<br />
SOT886<br />
4<br />
XDP:YES<br />
U8194<br />
SOT886<br />
XDP:YES<br />
1<br />
R8192<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
74AUP1T97GM<br />
4<br />
P1V0S3_EN<br />
P1VS0SW_EN_RC<br />
XDP:YES<br />
1<br />
R8194<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
(S4# OR XDP)<br />
OUT 78<br />
(S3# AND S0# OR XDP)<br />
OUT 77<br />
D<br />
C<br />
48 17 14<br />
PM_RSMRST_L<br />
MAKE_BASE=TRUE<br />
PM_RSMRST_L 74<br />
77<br />
IN<br />
S0i Enables<br />
P1VS0SW_EN_RC<br />
MAKE_BASE=TRUE<br />
P1VS0SW_EN_RC<br />
OUT<br />
78<br />
77<br />
74<br />
GND<br />
MAKE_BASE=TRUE<br />
100<br />
PP3V3_G3H<br />
77 74<br />
IN<br />
PM_SLP_S0S3_L<br />
MAKE_BASE=TRUE<br />
PM_SLP_S0S3_L<br />
OUT<br />
78<br />
77<br />
SSD_PWR_REQ<br />
MAKE_BASE=TRUE<br />
SSD_PWR_REQ<br />
IN<br />
84<br />
88<br />
77<br />
IN<br />
77<br />
PMIC_EN_P3V3S5<br />
SSD_PWR_REQ<br />
C8190 1<br />
0.1UF<br />
10%<br />
10V<br />
2<br />
X5R-CERM<br />
0201<br />
2<br />
1<br />
NC<br />
5<br />
6<br />
3<br />
U8190<br />
74LVC1G32<br />
SOT891<br />
4<br />
PM_EN_PVXS5<br />
MAKE_BASE=TRUE<br />
PM_EN_PVXS5 77<br />
PM_EN_PVXS5 77<br />
B<br />
NC<br />
1<br />
R8190<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
B<br />
77<br />
PM_EN_PVXS5<br />
R8160<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
P5VS5_EN<br />
OUT<br />
72<br />
A<br />
77 PM_EN_PVXS5<br />
0<br />
P3V3S5_EN<br />
77 PM_SLP_S5_L<br />
R8165 1<br />
100<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
NO STUFF<br />
P3V3S5_EN_RD<br />
R8162<br />
NO STUFF<br />
P5VS4_EN_RD<br />
R8163<br />
P5VS4_EN<br />
1 2 1 2<br />
OUT 72<br />
OUT 72<br />
77 PM_SLP_S3_L<br />
0<br />
1 2<br />
5%<br />
5%<br />
1/20W<br />
5%<br />
MF<br />
R81641 1/20W<br />
MF<br />
1/20W<br />
201<br />
201<br />
R8167 1 MF<br />
100<br />
201<br />
5%<br />
100<br />
1/20W<br />
5%<br />
1/20W<br />
D8164<br />
201<br />
MF D8163<br />
2<br />
MF<br />
SM-201<br />
SM-201<br />
201<br />
2<br />
K A<br />
K A<br />
SM-201<br />
RB521ZS-30<br />
NO STUFF<br />
1<br />
2<br />
C8155<br />
1UF<br />
10%<br />
25V<br />
X6S-CERM<br />
0402<br />
NO STUFF<br />
0<br />
RB521ZS-30<br />
NO STUFF<br />
1<br />
2<br />
C8154<br />
1UF<br />
10%<br />
25V<br />
X6S-CERM<br />
0402<br />
NO STUFF<br />
R8166<br />
D8165<br />
NO STUFF<br />
K A<br />
P5VS0_EN_RD<br />
RB521ZS-30<br />
NO STUFF<br />
1<br />
2<br />
P5VS0_EN<br />
C8156<br />
1UF<br />
10%<br />
25V<br />
X6S-CERM<br />
0402<br />
NO STUFF<br />
BOM_COST_GROUP=PLATFORM POWER<br />
78<br />
SYNC_MASTER=J79_SILUCHEN<br />
PMIC-1 Aliases & TPs<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
OUT<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
81 OF 145<br />
77 OF 119<br />
SYNC_DATE=07/17/2015<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
C<br />
B<br />
A<br />
101<br />
57<br />
77<br />
101<br />
PP3V3_S5<br />
78 50<br />
IN<br />
IN<br />
PP3V3_S5<br />
77<br />
IN<br />
101<br />
PM_SLP_S5_L<br />
3.3V SUS Switch<br />
PM_SLP_SUS_L<br />
3.3V S4 Switch<br />
PP3V3_S5<br />
3.3V S0 Switch<br />
C<strong>820</strong>6 1<br />
4700PF<br />
2<br />
10%<br />
10V<br />
X7R<br />
201<br />
CUMULUS_IPD<br />
C<strong>820</strong>7 1<br />
4700PF<br />
10%<br />
10V<br />
2<br />
R<strong>820</strong>9<br />
0<br />
1 2<br />
X7R<br />
201<br />
5%<br />
1/20W<br />
MF<br />
201<br />
Part<br />
Type<br />
R(on)<br />
@ 3.6V<br />
Current<br />
Part<br />
Type<br />
R(on)<br />
@ 3.3V<br />
Current<br />
EDP: 416mA<br />
PP3V3_SUS 101<br />
U<strong>820</strong>0<br />
TPS22934<br />
36.4 mOhm Typ<br />
46 mOhm Max<br />
R(on)<br />
@ 4A<br />
Current<br />
Load Switch<br />
63 mOhm Typ<br />
77 mOhm Max<br />
1A Max<br />
SLG5AP1569V<br />
Load Switch<br />
1A Max<br />
Part<br />
Type<br />
EDP: 16mA<br />
PP3V3_S4 101<br />
EDP: 0.04 A<br />
Part<br />
Type<br />
R(on)<br />
@ 4A<br />
Current<br />
5V S0 Switch (Cumulus vs Kona)<br />
3.3V Sensor Switch<br />
SMC_SENSOR_PWR_EN<br />
101<br />
77<br />
LOADISNS<br />
C8210 1<br />
1.0UF<br />
2<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
C<strong>820</strong>0 1<br />
1.0UF<br />
20%<br />
6.3V<br />
2<br />
P3V3S4_EN_R<br />
C<strong>820</strong>9 1<br />
0.1UF<br />
2<br />
NOSTUFF<br />
PP3V3_S5<br />
77<br />
X5R<br />
0201-1<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
IN<br />
P3V3S0_RAMP<br />
PM_SLP_S3_L<br />
101<br />
PP5V_S4<br />
P5VS4_FET_RAMP<br />
IN<br />
A2<br />
B2<br />
2<br />
1<br />
P5VS0_EN<br />
TPS22934<br />
DSBGA<br />
LOADISNS<br />
VIN<br />
ON<br />
U8210<br />
CRITICAL<br />
GND<br />
B1<br />
VIN<br />
ON<br />
U<strong>820</strong>0<br />
SLG5AP1569V<br />
STDFN<br />
CRITICAL<br />
GND<br />
4<br />
C<strong>820</strong>4 1<br />
4700PF<br />
10%<br />
10V<br />
2<br />
C<strong>820</strong>5 1<br />
1UF<br />
10%<br />
2<br />
VOUT<br />
X7R<br />
201<br />
P3V3S4_RAMP<br />
10V<br />
X5R<br />
402<br />
CUMULUS_IPD<br />
A1<br />
VOUT<br />
C<strong>820</strong>3 1<br />
1UF<br />
10%<br />
10V<br />
2<br />
X5R<br />
402<br />
3<br />
SLG5AP1445V<br />
7<br />
TDFN8<br />
CAP<br />
D 3<br />
1<br />
U<strong>820</strong>9<br />
SLG5AP1453V<br />
7<br />
TDFN<br />
CAP<br />
D 3<br />
CRITICAL<br />
2 ON<br />
S 5<br />
8<br />
1<br />
U<strong>820</strong>5<br />
CRITICAL<br />
2 ON<br />
S 5<br />
8<br />
PP3V3_S4SW_SNS_FET_R<br />
7<br />
TDFN8<br />
CAP<br />
D 3<br />
VOLTAGE=3.3V<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
1<br />
U<strong>820</strong>3<br />
SLG5AP1445V<br />
CRITICAL<br />
2 ON<br />
S 5<br />
VDD<br />
GND<br />
VDD<br />
GND<br />
VDD<br />
GND<br />
8<br />
CUMULUS_IPD<br />
U8210<br />
1<br />
2<br />
LOADISNS<br />
C<strong>820</strong>8<br />
0.1UF<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
R8210<br />
0<br />
1 2<br />
5%<br />
1/16W<br />
MF-LF<br />
402<br />
101 PP5V_S0<br />
U<strong>820</strong>5<br />
1<br />
U<strong>820</strong>3<br />
PP3V3_S0 101<br />
EDP: 0.04 A<br />
SLG5AP1445V<br />
Load Switch<br />
7.8 mOhm Typ<br />
TBD mOhm Max<br />
4A Max<br />
CRITICAL<br />
C8216<br />
12PF<br />
Part<br />
Type<br />
7.8 mOhm Typ<br />
TBD mOhm Max<br />
R(on)<br />
SLG5AP1445V<br />
Load Switch<br />
4A Max<br />
Current<br />
PP3V3_S4SW_SNS 101<br />
1<br />
2<br />
1<br />
101<br />
C8289<br />
100PF<br />
5%<br />
25V<br />
C0G<br />
0201<br />
CRITICAL<br />
C8217<br />
3.0PF<br />
U<strong>820</strong>9<br />
PP3V3_S5<br />
76<br />
77<br />
S3_STATE:YES<br />
SLG5AP1443V<br />
Load Switch<br />
17 mOhm Typ<br />
19 mOhm Max<br />
2.5A<br />
101<br />
10%<br />
10V<br />
X7R<br />
201<br />
101<br />
1<br />
2<br />
P1V0SUSFUSE_RAMP<br />
PP3V3_S5<br />
101<br />
101<br />
PP3V3_SUS<br />
0.1UF<br />
P1V0PCH_PGOOD<br />
PP3V3_S5<br />
C8288<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
PM_SLP_S5_L<br />
PP3V3_S5<br />
P1V8S3_RAMP<br />
P1V8S3_EN<br />
1.8V S4 LDO<br />
1.8V S3 Switch<br />
1.8V S0 Switch<br />
P1V8S0_RAMP<br />
PM_SLP_S3_L<br />
U8212<br />
NCP703SN18TG<br />
TSOP5<br />
1.2V S0 SW Switch<br />
VCCPLLOC:S0G<br />
1.0V SUS FUSE Switch<br />
1<br />
U8288<br />
SLG5AP1635V<br />
7<br />
STDFN<br />
CAP<br />
D 3<br />
2 ON<br />
S 5<br />
8<br />
C8221 1<br />
1UF<br />
2<br />
1<br />
3<br />
GND<br />
2<br />
SLG5AP1453V<br />
SLG5AP1453V<br />
7<br />
TDFN<br />
CAP<br />
D 3<br />
VCCPLLOC:S0G<br />
Part<br />
Type<br />
R(on)<br />
@ 5.3A<br />
Current<br />
PP1V8_S4 100<br />
EDP: 0.020 A<br />
0<br />
SOD523<br />
5%<br />
K<br />
A<br />
1/20W<br />
MF<br />
201 PMEG3010EB/S500<br />
PP1V8_S3 100<br />
EDP: 0.550 A<br />
Part<br />
Type<br />
R(on)<br />
@ 5.3A<br />
Current<br />
PP1V8_S0 100<br />
EDP: 0.140 A<br />
Part<br />
Type<br />
PP1V0_SUS 101<br />
R8288 1 NOSTUFF<br />
0<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
PP1V0_SUSFUSE<br />
8<br />
VOLTAGE=1.0V<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
EDP: TBD<br />
5<br />
4<br />
1<br />
2<br />
R(on)<br />
@ 5.3A<br />
1UF<br />
10%<br />
10V<br />
X5R<br />
402<br />
Current<br />
C8212<br />
U8215<br />
SLG5AP1453V<br />
Load Switch<br />
7.8 mOhm Typ<br />
9.6 mOhm Max<br />
5.3A Max<br />
PP1V8_SUS 100<br />
S3_STATE:NO<br />
R8281 1 2<br />
U8220<br />
Part<br />
Type<br />
U8218<br />
R(on)<br />
@ 25C<br />
Current<br />
Ton Total<br />
7.8 mOhm Typ<br />
9.6 mOhm Max<br />
5.3A Max<br />
SLG5AP1453V<br />
Load Switch<br />
7.8 mOhm Typ<br />
9.6 mOhm Max<br />
5.3A Max<br />
R(discharge)<br />
D8215<br />
SOD523<br />
PMEG3010EB/S500<br />
D8216<br />
SLG5AP1453V<br />
Load Switch<br />
PP1V8_SUS 100<br />
PP1V2_S3 100<br />
R8220 1 2<br />
5%<br />
+/-0.1PF<br />
10%<br />
VDD<br />
2<br />
25V<br />
2<br />
25V<br />
10V<br />
NP0-C0G<br />
NP0-C0G<br />
X5R<br />
U8220<br />
VCCPLLOC:S3<br />
0201<br />
0201<br />
402<br />
0<br />
SLG5AP1453V<br />
5%<br />
1/20W<br />
P1V2S0SW_RAMP<br />
7<br />
TDFN<br />
MF<br />
CAP<br />
D 3<br />
201<br />
2.4G DESENSE 5G DESENSE<br />
77 PM_SLP_S0S3_L<br />
2 5 PP1V2_S0SW 100<br />
C8222 1 IN<br />
ON<br />
S<br />
4700PF<br />
EDP: 0.260 A<br />
GND<br />
10%<br />
10V<br />
X7R 2 VCCPLLOC:S0G<br />
201<br />
LOADISNS<br />
IN<br />
C8215 1<br />
4700PF<br />
2<br />
10%<br />
10V<br />
X7R<br />
201<br />
77<br />
C8219 1<br />
4700PF<br />
2<br />
IN<br />
74<br />
77<br />
IN<br />
IN<br />
C8211 1<br />
1UF<br />
2<br />
10%<br />
10V<br />
X5R<br />
402<br />
S3_STATE:YES<br />
VDD<br />
GND<br />
C8214 1<br />
1UF<br />
10%<br />
10V<br />
2<br />
X5R<br />
402<br />
C8218 1<br />
1UF<br />
2<br />
10%<br />
10V<br />
X5R<br />
402<br />
IN<br />
EN<br />
1<br />
8<br />
1<br />
VDD<br />
U8215<br />
1<br />
U8218<br />
2 ON<br />
S 5<br />
8<br />
S3_STATE:YES<br />
7<br />
TDFN<br />
CAP<br />
D 3<br />
2 ON<br />
S 5<br />
GND<br />
8<br />
VDD<br />
GND<br />
OUT<br />
NC1<br />
NC<br />
12<br />
K<br />
A<br />
U8288<br />
PP1V2_S3 75 100<br />
SLG5AP1635V<br />
Load Switch<br />
20 mOhm Typ<br />
28 mOhm Max<br />
2.5A Max<br />
C8223 1<br />
1000PF<br />
2<br />
10%<br />
25V<br />
X7R<br />
0201<br />
39us max @ 1V<br />
300 Ohm Max<br />
101<br />
101<br />
PP3V3_SUS<br />
PP1V0_SUS<br />
HSIO has turn-on requirement of<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
Page Notes<br />
Power aliases required by this page:<br />
PPVOUT_S0_LCDBKLT<br />
79<br />
80<br />
104<br />
- =PPVIN_S0SW_LCDBKLTFET (9-12.6V LCD BACKLIGHT INPUT)<br />
- =PP5V_S0_BKLT (5V BACKLIGHT DRIVER INPUT)<br />
PLACE_NEAR=D8410.K:5MM<br />
PLACE_NEAR=D8410.K:5MM<br />
PLACE_NEAR=D8410.K:5MM<br />
PLACE_NEAR=D8410.K:5MM<br />
PLACE_NEAR=D8410.K:5MM<br />
D<br />
C<br />
100<br />
PPBUS_G3H<br />
740S0159<br />
CRITICAL<br />
F8400<br />
3AMP-32V<br />
1 2<br />
79<br />
0603<br />
52<br />
52<br />
PPVIN_S0SW_LCDBKLT_F<br />
OUT<br />
OUT<br />
ISNS_LCDBKLT_P<br />
ISNS_LCDBKLT_N<br />
R8400<br />
0.025<br />
1%<br />
1W<br />
MF<br />
0612-1<br />
2 1<br />
4 3<br />
107S00034<br />
PLATFORM_RESET NO LONGER GATES THE BKLT_EN AS BOTH COME FROM PCH NOW<br />
5<br />
IN<br />
79<br />
EDP_BKLT_EN<br />
PPVIN_S0SW_LCDBKLT_R<br />
1<br />
2<br />
C8400<br />
1000PF<br />
10%<br />
16V<br />
X7R-1<br />
0201<br />
79<br />
1<br />
R8401<br />
80.6K<br />
1%<br />
1/16W<br />
MF-LF<br />
2 402<br />
1<br />
R8402<br />
63.4K<br />
1%<br />
1/16W<br />
MF-LF<br />
2 402<br />
R8442<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
GND_BKLT_SGND<br />
101<br />
1<br />
R8440<br />
1M<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
79<br />
LCDBKLT_EN_L<br />
PP5V_S0<br />
GND_BKLT_SGND<br />
1<br />
2<br />
CRITICAL<br />
FDC638APZ_SBMS001<br />
79<br />
4<br />
Q8400<br />
SSOT6-HF<br />
3<br />
PLACE_NEAR=U8400.5:5MM<br />
79<br />
BKLT_SD<br />
BKLT_SENSE_OUT<br />
BKLT_EN_R<br />
NO STUFF<br />
C8442<br />
33PF<br />
5%<br />
25V<br />
NPO-C0G<br />
0201<br />
6<br />
5<br />
2<br />
1<br />
R8444 1 0 5%<br />
1/16W<br />
MF-LF<br />
402 2<br />
C8440 1<br />
1UF<br />
10%<br />
10V<br />
2<br />
X5R<br />
402<br />
1<br />
2<br />
NOSTUFF<br />
C8401<br />
0.001UF<br />
10%<br />
50V<br />
CERM<br />
402<br />
79<br />
79<br />
1<br />
R8445<br />
5%<br />
1/16W<br />
MF-LF<br />
2 402<br />
PP5V_S0_BKLT_A<br />
PP5V_S0_BKLT_D<br />
1<br />
2<br />
0<br />
1UF<br />
10%<br />
10V<br />
X5R<br />
402<br />
11<br />
9<br />
10<br />
19<br />
17<br />
12<br />
15<br />
16<br />
79<br />
C8441<br />
PPVIN_S0SW_LCDBKLT<br />
MIN_LINE_WIDTH=2.0000<br />
MIN_NECK_WIDTH=0.2000<br />
VOLTAGE=12.9V<br />
MAKE_BASE=TRUE<br />
PLACE_NEAR=U8400.18:5MM<br />
5<br />
U8400<br />
LP8548B1SQ_-04<br />
SD<br />
VSENSE_N<br />
VSENSE_P<br />
EN<br />
PWM_KEYB<br />
SCL<br />
SDA<br />
VDDD<br />
SENSE_OUT<br />
(IPU)<br />
(IPU)<br />
18<br />
VDDA<br />
LLP<br />
CRITICAL<br />
SW<br />
SW<br />
FB<br />
GD<br />
ISET_KEYB<br />
KEYB1<br />
KEYB2<br />
SW2<br />
FB2<br />
2<br />
1<br />
21<br />
4<br />
20<br />
13<br />
14<br />
6<br />
8<br />
PLACE_NEAR=L8410.1:5MM<br />
LCDBKLT_SW<br />
PLACEMENT_NOTE:<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
VOLTAGE=55V<br />
MIN_NECK_WIDTH=0.2000<br />
MIN_LINE_WIDTH=2.0000<br />
LCDBKLT_FB<br />
LCDBKLT_FET_DRV<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
1<br />
2<br />
C8410<br />
4.7UF<br />
10%<br />
25V<br />
X6S-CERM<br />
0603<br />
MIN_LINE_WIDTH=0.6000<br />
MIN_NECK_WIDTH=0.2000<br />
VOLTAGE=5V<br />
GATE_NODE=TRUE<br />
DIDT=TRUE<br />
PLACE_NEAR=L8410.1:5MM<br />
10%<br />
25V<br />
X6S-CERM<br />
0603<br />
SANDWICH C8210 AND C8211<br />
79<br />
1<br />
2<br />
C8411<br />
4.7UF<br />
LCDBKLT_FET_DRV_R<br />
10<br />
PLACE_NEAR=Q8401.5:3MM<br />
CRITICAL<br />
L8410<br />
15UH-20%-1.9A-0.24OHM<br />
1<br />
2<br />
1<br />
R8433<br />
1%<br />
1/16W<br />
MF-LF<br />
2 402<br />
1 2<br />
C8412<br />
0.1UF<br />
10%<br />
25V<br />
X5R<br />
402<br />
PLACE_NEAR=L8410.1:5MM<br />
PIME062D-SM<br />
152S00253<br />
4<br />
79<br />
PPVIN_SW_LCDBKLT_SW<br />
5<br />
1 2 3<br />
371S0704 or 371S00077 (Combo)<br />
CRITICAL<br />
Q8401<br />
SI7812DN<br />
PWRPK-1212-8<br />
PLACE_NEAR=U8400.1:3MM<br />
PLACE_NEAR=L8410.2:3MM<br />
CRITICAL<br />
D8410<br />
SOD123-COMBO<br />
A K<br />
PMEG10020ELR-DFLS2100<br />
XW8410<br />
SM<br />
PLACE_NEAR=D8410::2MM<br />
2<br />
1<br />
LCDBKLT_TB_XWR<br />
18.2K<br />
1%<br />
1/16W<br />
MF-LF<br />
2 402<br />
1<br />
2<br />
C8460<br />
2.2UF<br />
10%<br />
100V<br />
X5R<br />
1206<br />
1<br />
C8461<br />
2.2UF<br />
10%<br />
2<br />
100V<br />
X5R<br />
1206<br />
PLACE_NEAR=D8410.K:5MM<br />
PLACE_NEAR=D8410.K:5MM<br />
PLACE_NEAR=D8410.K:5MM<br />
PLACE_NEAR=D8410.K:5MM<br />
PLACE_NEAR=D8410.K:5MM<br />
PLACE_NEAR=D8410.K:5MM<br />
1<br />
2<br />
NOSTUFF<br />
C8430<br />
100PF<br />
5%<br />
100V<br />
C0G-CERM<br />
0603<br />
1<br />
2<br />
C8462<br />
2.2UF<br />
10%<br />
100V<br />
X5R<br />
1206<br />
1<br />
2<br />
C8463<br />
2.2UF<br />
10%<br />
100V<br />
X5R<br />
1206<br />
1<br />
2<br />
10%<br />
100V<br />
X5R<br />
1206<br />
1<br />
2<br />
J79 DISPLAY<br />
C8464<br />
2.2UF<br />
PLACE_NEAR=D8410.K:5MM<br />
PLACE_NEAR=D8410.K:5MM<br />
PLACE_NEAR=D8410.K:5MM<br />
PLACE_NEAR=D8410.K:5MM<br />
PLACE_NEAR=D8410.K:5MM<br />
1<br />
2<br />
1<br />
2<br />
1<br />
R8431<br />
150K<br />
1%<br />
1/16W<br />
MF-LF<br />
2 402<br />
C8465<br />
2.2UF<br />
10%<br />
100V<br />
X5R<br />
1206<br />
C8470<br />
2.2UF<br />
10%<br />
100V<br />
X5R<br />
1206<br />
1<br />
R8432<br />
1<br />
2<br />
1<br />
C8466<br />
2.2UF<br />
10%<br />
100V<br />
X5R<br />
1206<br />
C8471<br />
2.2UF<br />
10%<br />
2<br />
100V<br />
X5R<br />
1206<br />
1<br />
2<br />
1<br />
2<br />
C8467<br />
2.2UF<br />
10%<br />
100V<br />
X5R<br />
1206<br />
C8472<br />
2.2UF<br />
10%<br />
100V<br />
X5R<br />
1206<br />
1<br />
2<br />
1<br />
2<br />
C8468<br />
2.2UF<br />
10%<br />
100V<br />
X5R<br />
1206<br />
C8473<br />
2.2UF<br />
10%<br />
100V<br />
X5R<br />
1206<br />
1<br />
C8469<br />
2.2UF<br />
10%<br />
2<br />
100V<br />
X5R<br />
1206<br />
C8474<br />
12PF<br />
5%<br />
100V<br />
C0G<br />
0201<br />
C8475<br />
12PF<br />
5%<br />
100V<br />
C0G<br />
0201<br />
Vout = 46V Typ, 55V Max<br />
Iout = 0.12A Typ, 0.15A Max<br />
Fs = 625kHz Typ (+/- 7%)<br />
1<br />
2<br />
D<br />
C<br />
GND_SW<br />
GND_SW<br />
GND_SW2<br />
GNDD<br />
GNDA<br />
THRM<br />
PAD<br />
B<br />
BKLT_PWM_KEYB<br />
1<br />
R8447<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
24<br />
23<br />
7<br />
3<br />
22<br />
XW8400<br />
SM<br />
1 2<br />
25<br />
B<br />
101<br />
79<br />
PP5V_S0<br />
GND_BKLT_SGND<br />
MIN_LINE_WIDTH=0.4000<br />
MIN_NECK_WIDTH=0.2000<br />
VOLTAGE=0V<br />
79<br />
102<br />
102<br />
IN<br />
BI<br />
I2C_BKLT_SCL<br />
I2C_BKLT_SDA<br />
I2C ID DEDICATED.ONLY CONNECTS TO JERRY<br />
1<br />
R8452<br />
1.8K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
1<br />
R8453<br />
1.8K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
R8451<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
PLACE_NEAR=U8400.16:10MM<br />
PLACE_NEAR=U8400.15:10MM<br />
R8450<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
0201<br />
BKLT_SCL<br />
BKLT_SDA<br />
LINE WIDTHS<br />
PBUS LINE WIDTHS<br />
LCD BKLT LINE WIDTHS<br />
A<br />
PP5V_S0_BKLT_A<br />
MIN_LINE_WIDTH=2.0000<br />
MIN_NECK_WIDTH=0.2000<br />
VOLTAGE=5V<br />
PP5V_S0_BKLT_D<br />
MIN_LINE_WIDTH=2.0000<br />
MIN_NECK_WIDTH=0.2000<br />
VOLTAGE=5V<br />
BKLT_SD<br />
79<br />
MIN_LINE_WIDTH=0.2500<br />
MIN_NECK_WIDTH=0.2000<br />
79<br />
79<br />
PPVIN_S0SW_LCDBKLT_F<br />
MIN_LINE_WIDTH=2.0000<br />
MIN_NECK_WIDTH=0.2000<br />
VOLTAGE=12.9V<br />
PPVIN_S0SW_LCDBKLT_R<br />
MIN_LINE_WIDTH=2.0000<br />
MIN_NECK_WIDTH=0.2000<br />
VOLTAGE=12.9V<br />
PPVIN_S0SW_LCDBKLT<br />
MIN_LINE_WIDTH=2.0000<br />
MIN_NECK_WIDTH=0.2000<br />
VOLTAGE=12.9V<br />
79<br />
79<br />
79<br />
LCDBKLT_FET_DRV_R<br />
MIN_LINE_WIDTH=0.6000<br />
MIN_NECK_WIDTH=0.2000<br />
VOLTAGE=5V<br />
GATE_NODE=TRUE<br />
DIDT=TRUE<br />
79<br />
PPVIN_SW_LCDBKLT_SW<br />
MIN_LINE_WIDTH=2.0000<br />
MIN_NECK_WIDTH=0.2000<br />
VOLTAGE=55V<br />
SWITCH_NODE=TRUE<br />
MIN_LINE_WIDTH=0.5000<br />
MIN_NECK_WIDTH=0.1500<br />
VOLTAGE=55V<br />
DIDT=TRUE<br />
PPVOUT_S0_LCDBKLT<br />
79<br />
79<br />
80<br />
104<br />
BOM_COST_GROUP=DISPLAY<br />
SYNC_MASTER=J79_RUENJOU<br />
LCD Backlight Driver<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
84 OF 145<br />
79 OF 119<br />
SYNC_DATE=09/09/2015<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
LCD PANEL INTERFACE (eDP) + Camera (MIPI)<br />
101<br />
PP5V_S0<br />
CRITICAL<br />
1<br />
D<br />
R8515<br />
150K<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
PANEL_P5V_EN<br />
LCD_PWR_SLEW<br />
VDD<br />
U8500<br />
SLG5AP1443V<br />
TDFN<br />
7 CAP<br />
D 3<br />
2 ON<br />
S 5<br />
GND<br />
8<br />
VOLTAGE=5V<br />
PP5V_S0SW_LCD<br />
80<br />
104<br />
106<br />
D<br />
R8517<br />
330<br />
1 2<br />
5% 201<br />
1/20W<br />
MF<br />
PANEL_P5V_EN_D<br />
D8517<br />
A<br />
SC2<br />
K<br />
DSF01S30SCAP<br />
1<br />
2<br />
R8518<br />
330<br />
1 2<br />
5% 201<br />
1/20W<br />
MF<br />
C8515<br />
0.1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
R8516<br />
200K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
PANEL_P3V3_EN_D<br />
1<br />
2<br />
C8509<br />
2200PF<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
PANEL_P3V3_EN<br />
D8518<br />
K<br />
SC2<br />
A<br />
DSF01S30SCAP<br />
1<br />
2<br />
C8511<br />
0.1UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
1<br />
1<br />
2<br />
C8516<br />
0.47UF<br />
10%<br />
2<br />
6.3V<br />
CERM-X5R<br />
0201<br />
C8512<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
101<br />
LCD_PWR_SLEW_3V3<br />
1<br />
2<br />
PP3V3_S5<br />
C8513<br />
2200PF<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
CRITICAL<br />
1<br />
VDD<br />
U8501<br />
SLG5AP1443V<br />
TDFN<br />
7 CAP<br />
D 3<br />
2 ON<br />
S 5<br />
GND<br />
8<br />
1<br />
2<br />
VOLTAGE=3.3V<br />
PP3V3_S0SW_LCD_R<br />
C8510<br />
1.0UF<br />
20% 6.3V<br />
X5R<br />
0201-1<br />
54<br />
54<br />
ISNS_LCDPANEL_P<br />
ISNS_LCDPANEL_N<br />
OMIT<br />
R8520<br />
0.005<br />
1%<br />
1/3W<br />
MF<br />
0306-SHORT<br />
1 2<br />
3 4<br />
NO_XNET_CONNECTION=1<br />
PP3V3_S0SW_LCD<br />
MIN_NECK_WIDTH=0.0520<br />
MIN_LINE_WIDTH=0.0900<br />
VOLTAGE=3.3V<br />
80<br />
104<br />
106<br />
104 48<br />
104 5<br />
BKLT_PWM_TCON2MLB<br />
BKLT_PWM_MLB2TCON<br />
J8500<br />
20759-042E-02<br />
F-ST-SM<br />
MAKE_BASE=TRUE<br />
BKLT_PWM_TCON2MLB<br />
MAKE_BASE=TRUE<br />
BKLT_PWM_MLB2TCON<br />
80<br />
80<br />
Move to CSA 20<br />
Move to CSA 92<br />
C<br />
80 5<br />
104 80 66 59 50<br />
IN<br />
EDP_PANEL_PWR_EN<br />
SMC_RESET_L<br />
U8510 BYPASS<br />
NO_STUFF<br />
R8590<br />
0<br />
1 2<br />
5% 1/20W<br />
MF 0201<br />
NO_STUFF<br />
R8591<br />
0<br />
1 2<br />
5% 1/20W<br />
MF 0201<br />
NO_STUFF<br />
R8592<br />
0<br />
1 2<br />
5% 1/20W<br />
MF 0201<br />
PANEL_FET_EN_DLY<br />
BUF_EDP_PANEL_PWR_EN<br />
BUF_SMC_RESET_L<br />
48<br />
80<br />
80<br />
80<br />
104<br />
80 5<br />
104 92 77 74 73 48 26 19 14<br />
104 80 66 59 50<br />
IN<br />
IN<br />
IN<br />
EDP_PANEL_PWR_EN<br />
PM_SLP_S3_L<br />
SMC_RESET_L<br />
100<br />
57<br />
PP3V3_G3H<br />
2<br />
CRITICAL<br />
EDP_PANEL_PWR_EN<br />
1<br />
SLG4AP4998<br />
PANEL_FET_EN_DLY<br />
4 PM_SLP_S3_L<br />
PANEL_PWR_EN_CONN 8<br />
STQFN<br />
12 SMC_RESET_INPUT_L SMC_RESET_OUTPUT_L 9<br />
U8510<br />
7<br />
VDD<br />
GND<br />
80<br />
PANEL_FET_EN_DLY<br />
X604_DISP_PWR_EN<br />
X604_DISP_SMC_RST_L<br />
NC0<br />
NC1<br />
3<br />
6<br />
10<br />
5<br />
11<br />
NC_U8510_5<br />
NC_U8510_11<br />
BUF_SMC_RESET_L<br />
DFR_DISP_PWR_EN<br />
DFR_DISP_SMC_RST_L<br />
BUF_EDP_PANEL_PWR_EN<br />
NO_TEST=1<br />
NO_TEST=1<br />
48<br />
80<br />
OUT<br />
OUT<br />
42<br />
42<br />
80<br />
104<br />
104 80 79<br />
104 80<br />
PPVOUT_S0_LCDBKLT<br />
EDP_INT_AUX_N<br />
EDP_INT_AUX_P<br />
EDP_INT_ML_N<br />
EDP_INT_ML_P<br />
EDP_INT_ML_N<br />
EDP_INT_ML_P<br />
EDP_INT_ML_N<br />
EDP_INT_ML_P<br />
EDP_INT_ML_N<br />
EDP_INT_ML_P<br />
MIPI_DATA_CONN_N<br />
MIPI_DATA_CONN_P<br />
MIPI_CLK_CONN_N<br />
MIPI_CLK_CONN_P<br />
PP5V_S0SW_LCD<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
PP3V3_S0SW_LCD<br />
BUF_EDP_PANEL_PWR_EN<br />
DP_INT_HPD<br />
104 80 80 104<br />
GND_VOID=TRUE<br />
5 6<br />
GND_VOID=TRUE<br />
5 80 104<br />
104 80<br />
104 80<br />
104 80<br />
104 80<br />
104 80<br />
104 80<br />
104 80<br />
104 80<br />
105 104 38<br />
105 104 38<br />
105 104 38<br />
105 104 38<br />
106 104 80<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
43 44<br />
PWR<br />
SIGNAL<br />
1 2<br />
3 4<br />
7 8<br />
9 10<br />
11 12<br />
13 14<br />
15 16<br />
17 18<br />
19 20<br />
21 22<br />
23 24<br />
25 26<br />
27 28<br />
29 30<br />
31 32<br />
33 34<br />
35 36<br />
37 38<br />
39 40<br />
41 42<br />
PWR<br />
45 46<br />
LCD_IRQ_L<br />
BKLT_PWM_TCON2MLB<br />
BKLT_PWM_MLB2TCON<br />
I2C_BKLT_SDA<br />
102<br />
I2C_BKLT_SCL<br />
102<br />
SMBUS_SMC_0_S0_SDA 51 104<br />
SMBUS_SMC_0_S0_SCL 51 104<br />
I2C_ALS_SDA<br />
I2C_ALS_SCL<br />
I2C_CAM_SCL<br />
I2C_CAM_SDA<br />
PP5V_S0_ALSCAM_F<br />
80<br />
16<br />
42<br />
42<br />
37<br />
37<br />
80<br />
80<br />
104<br />
104<br />
104<br />
104<br />
104<br />
38<br />
38<br />
104<br />
106<br />
104<br />
104<br />
38<br />
104<br />
106<br />
C<br />
B<br />
47<br />
GND<br />
48<br />
49 50<br />
B<br />
51 52<br />
101 PP3V3_S0<br />
NO_STUFF<br />
NO_XNET_CONNECTION=1<br />
1<br />
R8503<br />
1M<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
5<br />
5<br />
5<br />
5<br />
5<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
EDP_INT_ML_P<br />
EDP_INT_ML_N<br />
EDP_INT_ML_P<br />
EDP_INT_ML_N<br />
EDP_INT_ML_P<br />
MAKE_BASE=TRUE<br />
EDP_INT_ML_P<br />
MAKE_BASE=TRUE<br />
EDP_INT_ML_N<br />
MAKE_BASE=TRUE<br />
EDP_INT_ML_P<br />
MAKE_BASE=TRUE<br />
EDP_INT_ML_N<br />
MAKE_BASE=TRUE<br />
EDP_INT_ML_P<br />
80<br />
80<br />
80<br />
80<br />
80<br />
104<br />
104<br />
104<br />
104<br />
104<br />
C8500 1 1000PF<br />
2<br />
10%<br />
100V<br />
X7R-CERM<br />
0603<br />
PPVOUT_S0_LCDBKLT<br />
79<br />
80<br />
104<br />
53 54<br />
55 56<br />
57 58<br />
59 60<br />
61 62<br />
63 64<br />
65 66<br />
67 68<br />
SIGNAL_MODEL=EDP<br />
104 80 5<br />
DP_INT_HPD<br />
104 80<br />
104 80<br />
EDP_INT_AUX_N<br />
EDP_INT_AUX_P<br />
5<br />
5<br />
IN<br />
IN<br />
EDP_INT_ML_N<br />
EDP_INT_ML_P<br />
MAKE_BASE=TRUE<br />
EDP_INT_ML_N<br />
MAKE_BASE=TRUE<br />
EDP_INT_ML_P<br />
80<br />
80<br />
104<br />
104<br />
A<br />
R85011 100K<br />
5%<br />
1/20W<br />
MF<br />
201 2<br />
NO_STUFF<br />
NO_XNET_CONNECTION=1<br />
1R8502<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
LCD Panel HPD & AUX strapping<br />
1M<br />
5<br />
5<br />
5<br />
IN<br />
BI<br />
BI<br />
EDP_INT_ML_N<br />
EDP_INT_AUX_P<br />
EDP_INT_AUX_N<br />
MAKE_BASE=TRUE<br />
EDP_INT_ML_N<br />
MAKE_BASE=TRUE<br />
EDP_INT_AUX_P<br />
MAKE_BASE=TRUE<br />
EDP_INT_AUX_N<br />
80<br />
80<br />
80<br />
104<br />
104<br />
104<br />
BOM_COST_GROUP=DISPLAY<br />
SYNC_MASTER=J79_RUENJOU<br />
eDP Display Connector<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
85 OF 145<br />
80 OF 119<br />
SYNC_DATE=09/12/2015<br />
SIZE<br />
D<br />
A
D<br />
C<br />
B<br />
A<br />
CONFIG<br />
00 - 2<br />
01 - 4<br />
CONFIG<br />
000 - TEABERRY<br />
001 - XB58 GS<br />
010 - RESERVED<br />
011 - RESERVED<br />
100 - RESERVED<br />
101 - RESERVED<br />
110 - RESERVED<br />
111 - RESERVED<br />
LANDING1<br />
R8601<br />
NOSTUFF<br />
NOSTUFF<br />
10 - 8 ASSEMBLE<br />
11 - RESERVED ASSEMBLE<br />
1<br />
2<br />
1<br />
2<br />
NOSTUFF<br />
ASSEMBLE<br />
NOSTUFF<br />
ASSEMBLE<br />
OPERATION MODE (ODT, CLK FREQ, ETC)<br />
C8657<br />
0.01UF<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
C8650<br />
0.01UF<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
131S00077<br />
117S0002<br />
8<br />
OP_MODE2<br />
R8614<br />
NOSTUFF<br />
NOSTUFF<br />
NOSTUFF<br />
NOSTUFF<br />
ASSEMBLE<br />
ASSEMBLE<br />
ASSEMBLE<br />
ASSEMBLE<br />
1<br />
NAND LANDINGS<br />
1<br />
2<br />
1<br />
C8658<br />
0.01UF<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
C8652<br />
0.01UF<br />
10%<br />
2<br />
10V<br />
X7R-CERM<br />
0201<br />
S3XCLK:INT<br />
LANDING0<br />
R8660<br />
OP_MODE1<br />
R8615<br />
NOSTUFF<br />
NOSTUFF<br />
ASSEMBLE<br />
ASSEMBLE<br />
NOSTUFF<br />
NOSTUFF<br />
ASSEMBLE<br />
ASSEMBLE<br />
S3X_XTALO<br />
PLACE_NEAR=Y8600.1:1.0MM<br />
1<br />
2<br />
C8600<br />
9.5PF<br />
+/-0.1PF<br />
50V<br />
CER-C0G<br />
0201<br />
CAP,9.5PF,50V,0201<br />
RES,MF,0 OHM,1/20W,0201<br />
1.60X1.20MM-SM<br />
OP_MODE0<br />
R8680<br />
NOSTUFF<br />
ASSEMBLE<br />
NOSTUFF<br />
ASSEMBLE<br />
NOSTUFF<br />
ASSEMBLE<br />
NOSTUFF<br />
ASSEMBLE<br />
PLACE_NEAR=U8600.AJ18:2.0MM<br />
24MHZ-30PPM-60OHM<br />
S3XCLK:INT<br />
1<br />
2<br />
1<br />
2<br />
C8659<br />
0.01UF<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
C8654<br />
0.01UF<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
Y8600<br />
1 3<br />
2 4<br />
S3X_XTALI<br />
S3XCLK:INT<br />
R8602<br />
C8601<br />
C8601<br />
ROMBOOT2<br />
R8617<br />
000 - MLC SD/TOS 1Y/1Z(W/ HARD RESET)<br />
NOSTUFF<br />
001 - MLC SD/TOS 1Y/1Z (W/O HARD RESET)<br />
NOSTUFF<br />
010 - RESERVED<br />
NOSTUFF<br />
011 - MLC HYNIX 3D-V2 NOSTUFF<br />
100 - RESERVED<br />
ASSEMBLE<br />
101 - RESERVED<br />
ASSEMBLE<br />
110 - RESERVED<br />
ASSEMBLE<br />
111 - RESERVED<br />
ASSEMBLE<br />
PP1V8_SSD_COLD<br />
1 CRITICAL<br />
1K<br />
1 2<br />
1%<br />
1/20W S3XCLK:INT<br />
MF<br />
201<br />
PLACE_NEAR=U8600.AK18:2.0MM<br />
PLACE_NEAR=U8600.AJ18:2.0MM<br />
1<br />
R8600<br />
1M<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
PLACE_NEAR=Y8600.3:1.0MM<br />
C8601<br />
1<br />
9.5PF<br />
+/-0.1PF<br />
2<br />
50V<br />
CER-C0G<br />
0201<br />
OMIT_TABLE<br />
CONFIG<br />
CONFIG<br />
CAPACITY2<br />
R8664<br />
000 - 32GB<br />
NOSTUFF<br />
001 - 64GB NOSTUFF<br />
010 - 128GB<br />
NOSTUFF<br />
011 - 256GB<br />
NOSTUFF<br />
100 - 512GB<br />
ASSEMBLE<br />
101 - 1024GB<br />
ASSEMBLE<br />
110 - 2048GB<br />
ASSEMBLE<br />
111 - RESERVED<br />
ASSEMBLE<br />
ANI01_VREF<br />
ANI23_VREF<br />
ANI45_VREF<br />
S3X_XTALO_R<br />
Buffered SSD_RESET_L to Mitigate EPO Issue<br />
91 88 84<br />
1<br />
C8660<br />
0.01UF<br />
10%<br />
2<br />
10V<br />
X7R-CERM<br />
0201<br />
1<br />
2<br />
C8656<br />
0.01UF<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
PP1V8_SSD_COLD<br />
1<br />
2<br />
SSD_RESET_LB_L<br />
CRITICAL<br />
C8602<br />
0.1UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
2<br />
1<br />
5<br />
ANI67_VREF<br />
6<br />
3<br />
1<br />
R8605<br />
34.8<br />
PART NUMBER QTY DESCRIPTION<br />
REFERENCE DES CRITICAL BOM OPTION<br />
7<br />
NC<br />
104 88 87 86 85 84 82 81 19<br />
IN<br />
NC<br />
A<br />
B<br />
NC<br />
19<br />
81<br />
2<br />
VCC<br />
GND<br />
82<br />
84<br />
1%<br />
1/20W<br />
MF<br />
201<br />
S3XCLK:INT<br />
S3XCLK:EXT<br />
U8601<br />
74AUP1G08GF<br />
SOT891<br />
Y<br />
85<br />
4<br />
86<br />
6<br />
87<br />
88<br />
104<br />
86<br />
86<br />
87<br />
87<br />
1<br />
R8606<br />
34.8<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
ERN_L<br />
ANI47_ZQ<br />
ANI03_ZQ<br />
R8603<br />
3.01K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
NAND CONFIGURATION<br />
PRODUCT CAPACITY<br />
104 88 87 86 85 84 82 81 19<br />
81<br />
<br />
ROMBOOT1<br />
R8618<br />
NOSTUFF<br />
NOSTUFF<br />
ASSEMBLE<br />
ASSEMBLE<br />
NOSTUFF<br />
NOSTUFF<br />
ASSEMBLE<br />
ASSEMBLE<br />
CAPACITY1<br />
R8663<br />
NOSTUFF<br />
NOSTUFF<br />
ASSEMBLE<br />
ASSEMBLE<br />
NOSTUFF<br />
NOSTUFF<br />
ASSEMBLE<br />
ASSEMBLE<br />
102<br />
102<br />
PP1V8_SSD_COLD<br />
88<br />
5<br />
102<br />
ROMBOOT0<br />
R8616<br />
NOSTUFF<br />
ASSEMBLE<br />
NOSTUFF<br />
ASSEMBLE<br />
NOSTUFF<br />
ASSEMBLE<br />
NOSTUFF<br />
ASSEMBLE<br />
CAPACITY0<br />
R8662<br />
NOSTUFF<br />
ASSEMBLE<br />
NOSTUFF<br />
ASSEMBLE<br />
NOSTUFF<br />
ASSEMBLE<br />
NOSTUFF<br />
ASSEMBLE<br />
NC_S3X_DT0<br />
NC_S3X_DT1<br />
IN<br />
1<br />
R8615<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
NC<br />
NC<br />
S3X_PCIE_REF<br />
S3X_GPIO0<br />
NC_S3X_GPIO1<br />
S3X_PFN<br />
F18<br />
G18<br />
AK18<br />
AJ18<br />
T26<br />
T25<br />
T5<br />
T6<br />
H17<br />
AD11<br />
AD10<br />
AE11<br />
DTO0<br />
DTO1<br />
XI0<br />
XO0<br />
ANI03_ZQ_PD<br />
ANI03_ZQ_PU<br />
ANI47_ZQ_PD<br />
ANI47_ZQ_PU<br />
REXT<br />
GPIO0<br />
GPIO1<br />
GPIO2<br />
U8600<br />
S3X<br />
BGA-H1P35<br />
OMIT_TABLE<br />
A19<br />
A18<br />
A17<br />
A16<br />
A15<br />
A14<br />
A13<br />
A12<br />
A11<br />
A10<br />
C17<br />
C16<br />
C15<br />
C14<br />
C13<br />
C12<br />
C11<br />
C10<br />
J21<br />
AF17<br />
AG18<br />
AD17<br />
G16<br />
G17<br />
F12<br />
AE18<br />
AF18<br />
AH18<br />
E12<br />
AG20<br />
AH19<br />
AH17<br />
AD20<br />
AF19<br />
E8<br />
F8<br />
AF20<br />
AE20<br />
AG17<br />
AH20<br />
AD21<br />
AE17<br />
F11<br />
G12<br />
E11<br />
G10<br />
E9<br />
G11<br />
H10<br />
C8<br />
F10<br />
G9<br />
E10<br />
B8<br />
A8<br />
B7<br />
A7<br />
H18<br />
AD12<br />
G21<br />
B23<br />
J20<br />
AH16<br />
B26<br />
C20<br />
C21<br />
PCIE_CLK100M_SSD_LB_P<br />
PCIE_CLK100M_SSD_LB_N<br />
PCIE_SSD_D2R_C_P<br />
PCIE_SSD_D2R_C_N<br />
PCIE_SSD_D2R_C_P<br />
PCIE_SSD_D2R_C_N<br />
PCIE_SSD_D2R_C_P<br />
PCIE_SSD_D2R_C_N<br />
PCIE_SSD_D2R_C_P<br />
PCIE_SSD_D2R_C_N<br />
PCIE_SSD_R2D_LB_P<br />
PCIE_SSD_R2D_LB_N<br />
PCIE_SSD_R2D_P<br />
PCIE_SSD_R2D_N<br />
PCIE_SSD_R2D_P<br />
PCIE_SSD_R2D_N<br />
PCIE_SSD_R2D_P<br />
PCIE_SSD_R2D_N<br />
NC_S3X_DDR_ATO 102<br />
S3X_COLD_BOOT_L<br />
S3X_EXT_SE_24MHZ_CLK_IN<br />
S3X_CLK_IN_SEL<br />
NC_S3X_PCIE_ATB0 102<br />
NC_S3X_PCIE_ATB1 102<br />
S3X_PCIE_CLKREQ_L<br />
S3X_JTAG_TRST_L<br />
S3X_RESET_L<br />
S3X_HOLD_RESET<br />
S3X_PERST_L<br />
S3X_JTAG_SEL<br />
S3X_JTAG_TCK<br />
S3X_JTAG_TDI<br />
S3X_JTAG_TDO<br />
S3X_JTAG_TMS<br />
S3X_I2C_SCL<br />
S3X_I2C_SDA<br />
S3X_PMIC_CTRL0<br />
88<br />
S3X_PMIC_CTRL1<br />
88<br />
NC_S3X_PMIC_CTRL_2 102<br />
S3X_PMIC_EXT_CLK_DIS<br />
S3X_PMIC_LOW_PWR<br />
S3X_RET_LPSR_CLEAR<br />
S3X_SPI_CLK<br />
SSD_BOOT_LB_L<br />
84<br />
S3X_SPI_MISO<br />
S3X_SPI_MOSI<br />
S3X_BOOTSTRAP0<br />
NC_S3X_BOOTSTRAP1 102<br />
ERN_L<br />
81<br />
S3X_BOOTSTRAP3<br />
S3X_BOOTSTRAP4<br />
S3X_BOOTSTRAP5<br />
NC_S3X_BOOTSTRAP6 102<br />
S3X_SMC_OOB_UART_R2D<br />
S3X_SMC_OOB_UART_D2R<br />
S3X_DEBUG_UART_R2D<br />
S3X_DEBUG_UART_D2R<br />
S3X_RET_EN_L<br />
S3X_DDR_PHY_DATA_VREF<br />
S3X_DDR_PHY_ZQ<br />
S3X_DDR_VREFI_ALIVE<br />
S3X_DDR_VREFI_ZQ<br />
S3X_DDR_VREFO<br />
S3X_DDR_ZQ<br />
S3X_DDR_CKE0<br />
S3X_DDR_CKE1<br />
NOSTUFF<br />
1<br />
2<br />
84<br />
88<br />
R8610<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
NOSTUFF<br />
1<br />
R8611<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
PLACE_NEAR=U8600.B26:3.0MM<br />
1/20W<br />
IN 88<br />
2<br />
BI<br />
IN 84 104<br />
R8624<br />
1 2<br />
1<br />
R8607<br />
240<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
104<br />
84<br />
94<br />
84 104<br />
88<br />
84<br />
88<br />
84<br />
88<br />
81<br />
81<br />
81<br />
81<br />
81<br />
81<br />
81<br />
81<br />
94<br />
104<br />
85<br />
91<br />
91<br />
84<br />
84<br />
84<br />
84<br />
84<br />
84<br />
85<br />
88<br />
88<br />
88<br />
105 15<br />
105 15<br />
91<br />
91<br />
105 15<br />
105 15<br />
105 15<br />
105 15<br />
104 88 87 86 85 84 82 81 19<br />
84<br />
84<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
104<br />
1<br />
2<br />
105<br />
105<br />
104 88 87 86 85 84 82 81 19<br />
88<br />
88<br />
91<br />
88<br />
C8620<br />
1000PF<br />
10%<br />
16V<br />
X7R-1<br />
0201<br />
NAND_CFG0<br />
1<br />
R8616<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
1<br />
2<br />
1<br />
R8604<br />
100K<br />
0.1%<br />
MF<br />
0201-1<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
88<br />
88<br />
1<br />
R8612<br />
10K<br />
PCIE_SSD_D2R_LB_P<br />
PCIE_SSD_D2R_LB_N<br />
GND_VOID=TRUE<br />
PCIE_SSD_D2R_P<br />
GND_VOID=TRUE<br />
PCIE_SSD_D2R_N<br />
GND_VOID=TRUE<br />
PCIE_SSD_D2R_P<br />
GND_VOID=TRUE<br />
PCIE_SSD_D2R_N<br />
GND_VOID=TRUE<br />
PCIE_SSD_D2R_P<br />
PCIE_SSD_D2R_N<br />
PP1V8_SSD_COLD<br />
PP1V8_SSD_COLD<br />
C8621<br />
1000PF<br />
10%<br />
16V<br />
X7R-1<br />
0201<br />
NAND_CFG2<br />
1<br />
R8617<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
BYPASS=U8600.AH16::3.0MM<br />
BYPASS=U8600.J20::3.0MM<br />
BYPASS=U8600.B23::3.0MM<br />
BYPASS=U8600.AD12::3.0MM<br />
5%<br />
1/20W<br />
MF<br />
201<br />
1<br />
R8676<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
R8629<br />
10K<br />
1 2<br />
1<br />
2<br />
C8622<br />
1000PF<br />
10%<br />
16V<br />
X7R-1<br />
0201<br />
NAND_CFG1<br />
1<br />
R8618<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
1<br />
R8677<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
S3XCLK:INT<br />
BOM_COST_GROUP=SSD<br />
88<br />
GND_VOID=TRUE<br />
C8610<br />
GND_VOID=TRUE<br />
1<br />
2<br />
C8611<br />
C8613<br />
C8612<br />
C8614<br />
C8615<br />
C8617<br />
GND_VOID=TRUE<br />
C8623<br />
1000PF<br />
10%<br />
16V<br />
X7R-1<br />
0201<br />
C8616<br />
88<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
1K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
9 0006939272 ENGINEERING RELEASED<br />
S3XCLK:EXT<br />
1<br />
R8674<br />
1R8609<br />
2<br />
1K<br />
1<br />
R8660<br />
0.22UF<br />
1 2<br />
0.22UF<br />
1 2<br />
0.22UF<br />
1 2<br />
0.22UF<br />
1 2<br />
0.22UF<br />
1 2<br />
0.22UF<br />
1 2<br />
0.22UF<br />
1 2<br />
0.22UF<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
R8608<br />
240<br />
1%<br />
1/20W<br />
MF<br />
2<br />
PACK_TYPE=201<br />
2 1<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
GND_VOID=TRUE<br />
PCIE_SSD_D2R_C_P<br />
GND_VOID=TRUE<br />
PCIE_SSD_D2R_C_N<br />
GND_VOID=TRUE<br />
PCIE_SSD_D2R_C_P<br />
GND_VOID=TRUE<br />
PCIE_SSD_D2R_C_N<br />
GND_VOID=TRUE<br />
PCIE_SSD_D2R_C_P<br />
GND_VOID=TRUE<br />
PCIE_SSD_D2R_C_N<br />
GND_VOID=TRUE<br />
PCIE_SSD_D2R_C_P<br />
GND_VOID=TRUE<br />
PCIE_SSD_D2R_C_N<br />
CAPACITY0<br />
1<br />
R8662<br />
10K<br />
SYNC_MASTER=J79_RUENJOU<br />
S3XCLK:EXT<br />
R8698<br />
33<br />
1 2<br />
5%<br />
1/20W MF 201<br />
PLACE_NEAR=U1900.16:2.0MM<br />
1<br />
R8699<br />
0<br />
PLACE_NEAR=U8600.G21:3.0MM<br />
1<br />
5%<br />
1/20W<br />
MF<br />
2 201 S3XCLK:INT<br />
CAPACITY1<br />
1<br />
R8663<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
SYSCLK_CLK24M_SSD<br />
CAPACITY2<br />
1<br />
R8664<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
81<br />
81<br />
81<br />
81<br />
81<br />
81<br />
81<br />
81<br />
S3X CORE PCIE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
SYM 3 OF 7<br />
4<br />
REFCLK_P<br />
REFCLK_M<br />
PCIE_TX0_P<br />
PCIE_TX0_M<br />
PCIE_TX1_P<br />
PCIE_TX1_M<br />
PCIE_TX2_P<br />
PCIE_TX2_M<br />
PCIE_TX3_P<br />
PCIE_TX3_M<br />
PCIE_RX0_P<br />
PCIE_RX0_M<br />
PCIE_RX1_P<br />
PCIE_RX1_M<br />
PCIE_RX2_P<br />
PCIE_RX2_M<br />
PCIE_RX3_P<br />
PCIE_RX3_M<br />
DDR_ATO<br />
BOOT_FROM_LPSR<br />
CLK_IN<br />
CLK_IN_SEL<br />
PCIE_ATB0<br />
PCIE_ATB1<br />
PCIE_CLKREQ*<br />
JTAG_TRST*<br />
RESET*<br />
HOLD_RESET<br />
PERST*<br />
JTAG_SEL<br />
JTAG_TCK<br />
JTAG_TDI<br />
JTAG_TDO<br />
JTAG_TMS<br />
I2C_SCL<br />
I2C_SDA<br />
PMIC_CTRL0<br />
PMIC_CTRL1<br />
PMIC_CTRL2<br />
PMIC_EXT_CLK_DIS<br />
PMIC_LOW_PWR<br />
RET_LPSR_CLEAR<br />
SPI_CLK<br />
SPI_CS*<br />
SPI_MISO<br />
SPI_MOSI<br />
SPI_NOR_CLK<br />
SPI_NOR_CS*<br />
SPI_NOR_SIO0<br />
SPI_NOR_SO1<br />
SPI_NOR_SO2<br />
SPI_NOR_SO3<br />
SPI_NOR_RFN<br />
UART0_RX<br />
UART0_TX<br />
UART1_RX<br />
UART1_TX<br />
RETEN_EN<br />
DDR_PHY_DATA_VREF<br />
DDR_PHY_ZQ<br />
DDR_VREFI_ALIVE<br />
DDR_VREFI_ZQ<br />
DDR_VREFO<br />
DDR_ZQ<br />
DDR_CKE0<br />
DDR_CKE1<br />
IN<br />
IN<br />
OUT<br />
BI<br />
IN<br />
OUT<br />
BI<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
OUT<br />
3<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
18<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
2016-08-30<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
86 OF 145<br />
81 OF 119<br />
SYNC_DATE=08/20/2015<br />
SIZE<br />
D<br />
D<br />
C<br />
B<br />
A
82 OF 119<br />
VOLTAGE=0.9V<br />
VOLTAGE=1.8V<br />
VOLTAGE=0.9V<br />
VOLTAGE=0.9V<br />
VOLTAGE=1.8V<br />
VOLTAGE=1.8V<br />
NC_S3X_VDD_S 102<br />
87 OF 145<br />
9.0.0<br />
dvt-fab09-0<br />
PP1V8_SSD_COLD<br />
PP1V8_PLL_AVDD47<br />
PP0V9_PLL_DVDD811<br />
PP1V8_PLL_AVDD811<br />
PP1V8_PLL_C_AVDD<br />
PP1V8_SSD_HOT<br />
PP1V2_SSD_COLD<br />
PP0V9_SSD_FIXED<br />
S3X_VSSA18_PLL8<br />
S3X_VSSA18_PLL4<br />
S3X_VSSA18_PLL9<br />
S3X_VSSA18_PLL10<br />
S3X_VSSA18_PLL5<br />
PP1V8_SSD_COLD<br />
PP1V8_SSD_COLD<br />
PP1V8_SSD_COLD<br />
PP1V2_SSD_HOT<br />
PP0V9_SSD_REG<br />
PP1V2_SSD_COLD<br />
S3X_VDDR12_CK_PLANE<br />
S3X_VDDR12_CK_PLANE<br />
PP0V9_PLL_DVDD47<br />
PP0V9_SSD_REG<br />
PP0V9_SSD_REG<br />
PP0V9_PLL_C_DVDD03<br />
PP0V9_SSD_REG<br />
PP1V8_SSD_COLD<br />
PP1V8_PLL_AVDD47<br />
PP1V8_PLL_AVDD811<br />
PP1V2_SSD_COLD<br />
S3X_VSSA18_PLL7<br />
S3X_VSSA18_PLL6<br />
PP1V2_SSD_HOT<br />
PP1V8_SSD_COLD<br />
PP1V2_SSD_HOT<br />
PP0V9_SSD_REG<br />
S3X_VSSA18_PLL_C<br />
S3X_VSSA18_PLL11<br />
PP1V2_SSD_COLD<br />
SYNC_DATE=06/18/2015<br />
SYNC_MASTER=J79_RIO<br />
S3X POWER<br />
BOM_COST_GROUP=SSD<br />
L8704<br />
RES,MF,0 OHM,1/20W,0201<br />
117S0002 1 CRITICAL<br />
1%<br />
201<br />
25.5<br />
MF<br />
1/20W<br />
R8702<br />
1 2<br />
1%<br />
25.5<br />
201<br />
MF<br />
1/20W<br />
R8701<br />
1 2<br />
6.3V<br />
10%<br />
0.1UF<br />
BYPASS=U8600.W17::1.5MM<br />
X7R<br />
0201<br />
C8798<br />
1<br />
2<br />
20%<br />
0402<br />
4V<br />
X6S<br />
10UF<br />
C8757<br />
1<br />
2<br />
0402<br />
4V<br />
X6S<br />
20%<br />
10UF<br />
C8756<br />
1<br />
2<br />
4V<br />
20%<br />
0402<br />
X6S<br />
10UF<br />
C8755<br />
1<br />
2<br />
4V<br />
0402<br />
X6S<br />
20%<br />
10UF<br />
C8754<br />
1<br />
2<br />
0402<br />
X6S<br />
6.3V<br />
20%<br />
4.7UF<br />
C8753<br />
1<br />
2<br />
X6S<br />
0402<br />
6.3V<br />
4.7UF<br />
20%<br />
C8752<br />
1<br />
2<br />
4.7UF<br />
0402<br />
20%<br />
6.3V<br />
X6S<br />
C8751<br />
1<br />
2<br />
0402<br />
20%<br />
6.3V<br />
X6S<br />
4.7UF<br />
C8750<br />
1<br />
2<br />
20%<br />
6.3V<br />
0.22UF<br />
X6S-CERM<br />
0201<br />
C8749<br />
1<br />
2<br />
6.3V<br />
0201<br />
20%<br />
X6S-CERM<br />
0.22UF<br />
C8748<br />
1<br />
2<br />
20%<br />
6.3V<br />
X6S-CERM<br />
0201<br />
0.22UF<br />
C8747<br />
1<br />
2<br />
0201<br />
0.22UF<br />
X6S-CERM<br />
6.3V<br />
20%<br />
C8746<br />
1<br />
2<br />
X6S-CERM<br />
0201<br />
0.22UF<br />
6.3V<br />
20%<br />
C8745<br />
1<br />
2<br />
0201<br />
20%<br />
6.3V<br />
X6S-CERM<br />
0.22UF<br />
C8744<br />
1<br />
2<br />
6.3V<br />
20%<br />
0201<br />
X6S-CERM<br />
0.22UF<br />
C8743<br />
1<br />
2<br />
20%<br />
X6S-CERM<br />
6.3V<br />
0201<br />
0.22UF<br />
C8742<br />
1<br />
2<br />
6.3V<br />
X7R<br />
10%<br />
0201<br />
0.1UF<br />
C8741<br />
1<br />
2<br />
0.1UF<br />
0201<br />
6.3V<br />
X7R<br />
10%<br />
C8740<br />
1<br />
2<br />
0.1UF<br />
6.3V<br />
0201<br />
10%<br />
X7R<br />
C8730<br />
1<br />
2<br />
0.22UF<br />
0201<br />
6.3V<br />
X6S-CERM<br />
20%<br />
C8731<br />
1<br />
2<br />
0201-1<br />
6.3V<br />
X5R<br />
20%<br />
1.0UF<br />
C8732<br />
1<br />
2<br />
20%<br />
2.2UF<br />
6.3V<br />
X5R-CERM<br />
0201<br />
C8733<br />
1<br />
2<br />
6.3V<br />
X5R-CERM<br />
2.2UF<br />
20%<br />
0201<br />
C8725<br />
1<br />
2<br />
0.22UF<br />
20%<br />
0201<br />
6.3V<br />
X6S-CERM<br />
C8723<br />
1<br />
2<br />
1.0UF<br />
0201-1<br />
X5R<br />
20%<br />
6.3V<br />
C8724<br />
1<br />
2<br />
10%<br />
X7R<br />
0201<br />
6.3V<br />
0.1UF<br />
C8720<br />
1<br />
2<br />
0201<br />
0.1UF<br />
10%<br />
X7R<br />
6.3V<br />
C8710<br />
1<br />
2<br />
0201<br />
6.3V<br />
0.22UF<br />
20%<br />
X6S-CERM<br />
C8713<br />
1<br />
2<br />
0201-1<br />
6.3V<br />
X5R<br />
20%<br />
1.0UF<br />
C8714<br />
1<br />
2<br />
X6S<br />
6.3V<br />
0402<br />
4.7UF<br />
20%<br />
C8707<br />
1<br />
2<br />
6.3V<br />
X5R-CERM<br />
0201<br />
20%<br />
2.2UF<br />
C8706<br />
1<br />
2<br />
20%<br />
X5R<br />
6.3V<br />
0201-1<br />
1.0UF<br />
C8705<br />
1<br />
2<br />
20%<br />
1.0UF<br />
6.3V<br />
0201-1<br />
X5R<br />
C8704<br />
1<br />
2<br />
0201<br />
0.22UF<br />
20%<br />
X6S-CERM<br />
6.3V<br />
C8703<br />
1<br />
2<br />
X6S-CERM<br />
6.3V<br />
20%<br />
0.22UF<br />
0201<br />
C8702<br />
1<br />
2<br />
X7R<br />
0201<br />
0.1UF<br />
6.3V<br />
10%<br />
BYPASS=U8600.U7::1.5MM<br />
C8797<br />
1<br />
2<br />
0201<br />
6.3V<br />
X7R<br />
0.1UF<br />
10%<br />
BYPASS=U8600.Y7::1.5MM<br />
C8796<br />
1<br />
2<br />
6.3V<br />
X7R<br />
10%<br />
0.1UF<br />
0201<br />
BYPASS=U8600.N7::1.5MM<br />
C8795<br />
1<br />
2<br />
0.1UF<br />
6.3V<br />
X7R<br />
10%<br />
0201<br />
BYPASS=U8600.K7::1.5MM<br />
C8794<br />
1<br />
2<br />
0.1UF<br />
6.3V<br />
X7R<br />
10%<br />
0201<br />
BYPASS=U8600.N24::1.5MM<br />
C8793<br />
1<br />
2<br />
0.1UF<br />
10%<br />
0201<br />
X7R<br />
6.3V<br />
BYPASS=U8600.K24::1.5MM<br />
C8792<br />
1<br />
2<br />
6.3V<br />
0.1UF<br />
10%<br />
X7R<br />
0201<br />
BYPASS=U8600.U24::1.5MM<br />
C8791<br />
1<br />
2<br />
10%<br />
0.1UF<br />
0201<br />
6.3V<br />
X7R<br />
BYPASS=U8600.Y24::1.5MM<br />
C8790<br />
1<br />
2<br />
1%<br />
1/20W<br />
25.5<br />
MF<br />
201<br />
R8700<br />
1 2<br />
0201<br />
0.1UF<br />
10%<br />
X7R<br />
6.3V<br />
BYPASS=U8600.K17::1.5MM<br />
C8718<br />
1<br />
2<br />
0201<br />
0.1UF<br />
10%<br />
X7R<br />
6.3V<br />
C8717<br />
1<br />
2<br />
0402<br />
4V<br />
CERM<br />
1UF<br />
20%<br />
C8770<br />
1<br />
2<br />
3<br />
4<br />
20%<br />
1UF<br />
CERM<br />
4V<br />
0402<br />
C8771<br />
1<br />
2<br />
3<br />
4<br />
0402<br />
4V<br />
CERM<br />
1UF<br />
20%<br />
C8772<br />
1<br />
2<br />
3<br />
4<br />
20%<br />
CERM<br />
4V<br />
0402<br />
1UF<br />
C8773<br />
1<br />
2<br />
3<br />
4<br />
0402<br />
4V<br />
CERM<br />
1UF<br />
20%<br />
C8759<br />
1<br />
2<br />
3<br />
4<br />
20%<br />
1UF<br />
CERM<br />
4V<br />
0402<br />
C8758<br />
1<br />
2<br />
3<br />
4<br />
22NH-100MA<br />
0201<br />
L8702<br />
1 2<br />
22NH-100MA<br />
0201<br />
L8701<br />
1 2<br />
22NH-100MA<br />
0201<br />
L8700<br />
1 2<br />
BOMOPTION=OMIT_TABLE<br />
0201<br />
22NH-100MA<br />
L8704<br />
1 2<br />
0201<br />
6.3V<br />
10%<br />
X7R<br />
0.1UF<br />
BYPASS=U8600.K20::1.5MM<br />
C8719<br />
1<br />
2<br />
0201<br />
X7R<br />
6.3V<br />
0.1UF<br />
10%<br />
BYPASS=L8704.2::1.0MM<br />
C8765<br />
1 2<br />
X7R<br />
10%<br />
6.3V<br />
0.1UF<br />
0201<br />
C8780<br />
1<br />
2<br />
X7R<br />
10%<br />
0201<br />
6.3V<br />
BYPASS=U8600.AK4::1.5MM<br />
0.1UF<br />
C8783<br />
1<br />
2<br />
X7R<br />
10%<br />
0201<br />
6.3V<br />
0.1UF<br />
C8789<br />
1<br />
2<br />
0.1UF<br />
6.3V<br />
10%<br />
X7R<br />
0201<br />
C8727<br />
1<br />
2<br />
0.1UF<br />
6.3V<br />
0201<br />
10%<br />
X7R<br />
C8726<br />
1<br />
2<br />
0.1UF<br />
6.3V<br />
0201<br />
10%<br />
X7R<br />
C8708<br />
1<br />
2<br />
10%<br />
0.1UF<br />
6.3V<br />
0201<br />
X7R<br />
C8785<br />
1<br />
2<br />
0.1UF<br />
6.3V<br />
0201<br />
10%<br />
X7R<br />
C8709<br />
1<br />
2<br />
BYPASS=U8600.AE16::1.5MM<br />
0.1UF<br />
6.3V<br />
0201<br />
X7R<br />
10%<br />
C8737<br />
1<br />
2<br />
0201<br />
X7R<br />
BYPASS=U8600.AG14::1.5MM<br />
0.1UF<br />
6.3V<br />
10%<br />
C8736<br />
1<br />
2<br />
6.3V<br />
0201<br />
10%<br />
X7R<br />
BYPASS=U8600.A25::1.5MM<br />
0.1UF<br />
C8716<br />
1<br />
2<br />
0.1UF<br />
6.3V<br />
0201<br />
10%<br />
X7R<br />
BYPASS=U8600.A21::1.5MM<br />
C8784<br />
1<br />
2<br />
X7R<br />
10%<br />
0201<br />
6.3V<br />
0.1UF<br />
C8701<br />
1<br />
2<br />
0.1UF<br />
6.3V<br />
0201<br />
10%<br />
X7R<br />
C8700<br />
1<br />
2<br />
6.3V<br />
0.1UF<br />
10%<br />
X7R<br />
0201<br />
C8764<br />
1<br />
2<br />
6.3V<br />
0.1UF<br />
10%<br />
X7R<br />
0201<br />
C8763<br />
1<br />
2<br />
6.3V<br />
10%<br />
X7R<br />
0201<br />
0.1UF<br />
C8762<br />
1<br />
2<br />
6.3V<br />
0.1UF<br />
10%<br />
X7R<br />
0201<br />
C8761<br />
1<br />
2<br />
6.3V<br />
0.1UF<br />
10%<br />
X7R<br />
0201<br />
BYPASS=U8600.J19::1.5MM<br />
C8760<br />
1<br />
2<br />
6.3V<br />
0.1UF<br />
10%<br />
X7R<br />
0201<br />
BYPASS=U8600.H20::1.5MM<br />
C8735<br />
1<br />
2<br />
6.3V<br />
0.1UF<br />
10%<br />
X7R<br />
0201<br />
BYPASS=U8600.G19::1.5MM<br />
C8734<br />
1<br />
2<br />
0201<br />
0.1UF<br />
10%<br />
X7R<br />
6.3V<br />
C8722<br />
1<br />
2<br />
6.3V<br />
X7R<br />
10%<br />
0.1UF<br />
0201<br />
C8721<br />
1<br />
2<br />
0201<br />
0.1UF<br />
10%<br />
X7R<br />
6.3V<br />
C8712<br />
1<br />
2<br />
6.3V<br />
X7R<br />
10%<br />
0.1UF<br />
0201<br />
C8711<br />
1<br />
2<br />
6.3V<br />
X7R<br />
10%<br />
0.1UF<br />
0201<br />
BYPASS=U8600.J14::1.5MM<br />
C8766<br />
1<br />
2<br />
S3X<br />
BGA-H1P35<br />
OMIT_TABLE<br />
U8600<br />
AA11<br />
AA13<br />
AA15<br />
AA17<br />
AA19<br />
AA21<br />
AA23<br />
K22<br />
L9<br />
L11<br />
L13<br />
L15<br />
L17<br />
L19<br />
L21<br />
L23<br />
M8<br />
M10<br />
M12<br />
M14<br />
M16<br />
M18<br />
M20<br />
M22<br />
N9<br />
N11<br />
N13<br />
N15<br />
N17<br />
N19<br />
N21<br />
N23<br />
P8<br />
P10<br />
P12<br />
P14<br />
P16<br />
P18<br />
P20<br />
P22<br />
R9<br />
R11<br />
R13<br />
R15<br />
R17<br />
R19<br />
R21<br />
R23<br />
T8<br />
T10<br />
T12<br />
T14<br />
T16<br />
T18<br />
T20<br />
T22<br />
U9<br />
U11<br />
U13<br />
U15<br />
U17<br />
U19<br />
U21<br />
U23<br />
V8<br />
V10<br />
V12<br />
V16<br />
V18<br />
V20<br />
V22<br />
W9<br />
W11<br />
W13<br />
W15<br />
W19<br />
W21<br />
W23<br />
Y10<br />
Y12<br />
Y14<br />
Y16<br />
Y18<br />
Y20<br />
Y22<br />
V14<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
BGA-H1P35<br />
S3X<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
CKPLUS_WAIVE=PWRTERM2GND<br />
U8600<br />
H15<br />
J13<br />
J15<br />
J12<br />
J14<br />
J17<br />
J16<br />
H16<br />
K13<br />
K15<br />
K12<br />
K14<br />
K17<br />
K16<br />
A28<br />
AJ3<br />
AJ28<br />
AK15<br />
AK16<br />
B21<br />
B19<br />
A23<br />
A27<br />
AJ8<br />
AJ15<br />
AJ16<br />
AJ23<br />
AK3<br />
AK28<br />
K20<br />
AA7<br />
AA8<br />
AA9<br />
AA10<br />
AB19<br />
J25<br />
L25<br />
R25<br />
AA25<br />
U25<br />
L24<br />
AB25<br />
R24<br />
W24<br />
R7<br />
L7<br />
W7<br />
AB6<br />
J6<br />
L6<br />
R6<br />
U6<br />
AA6<br />
Y25<br />
V25<br />
K25<br />
P25<br />
K6<br />
P6<br />
Y6<br />
V6<br />
W18<br />
Y23<br />
V24<br />
K23<br />
P24<br />
K8<br />
P7<br />
Y8<br />
V7<br />
W17<br />
Y19<br />
A21<br />
A25<br />
AB12<br />
AB16<br />
K19<br />
AB30<br />
AB29<br />
AB28<br />
J30<br />
AC25<br />
V26<br />
W25<br />
Y26<br />
M26<br />
P26<br />
R27<br />
J23<br />
AB20<br />
AB22<br />
AB24<br />
AC21<br />
AC23<br />
K26<br />
N25<br />
AA27<br />
H22<br />
H24<br />
H26<br />
J27<br />
J28<br />
J29<br />
L27<br />
N27<br />
AB27<br />
U27<br />
W27<br />
H5<br />
J1<br />
AB1<br />
AB2<br />
AB3<br />
J7<br />
J9<br />
J11<br />
K10<br />
AB4<br />
AB7<br />
J2<br />
J3<br />
J4<br />
AB9<br />
K5<br />
AB11<br />
L4<br />
M5<br />
N4<br />
N6<br />
P5<br />
R4<br />
U4<br />
V5<br />
W4<br />
W6<br />
AC6<br />
AC8<br />
Y5<br />
AC10<br />
AA4<br />
AB13<br />
AC12<br />
AC14<br />
AD13<br />
AE14<br />
AF13<br />
AF15<br />
AG14<br />
AH13<br />
AH15<br />
AB15<br />
AC16<br />
AD15<br />
AE16<br />
AG16<br />
AK13<br />
AK4<br />
AK6<br />
AK25<br />
AK27<br />
AK8<br />
AK10<br />
AK12<br />
AK14<br />
AK17<br />
AK19<br />
AK21<br />
AK23<br />
G19<br />
H20<br />
J19<br />
K18<br />
6.3V 20% X5R 0201-1<br />
1.0UF<br />
BYPASS=U8600.K20::1.5MM<br />
C8715<br />
1 2<br />
0402<br />
X6S<br />
10UF<br />
20%<br />
4V<br />
C8787<br />
1<br />
2<br />
10UF<br />
0402<br />
4V<br />
20%<br />
X6S<br />
C8786<br />
1<br />
2<br />
0402<br />
X6S<br />
20%<br />
4V<br />
10UF<br />
BYPASS=U8600.W17::1.5MM<br />
C8788<br />
1<br />
2<br />
X6S-CERM<br />
6.3V<br />
0.22UF<br />
0201<br />
20%<br />
C8782<br />
1<br />
2<br />
6.3V<br />
0.1UF<br />
10%<br />
X7R<br />
0201<br />
C8781<br />
1<br />
2<br />
82<br />
88<br />
88<br />
82<br />
88<br />
83<br />
83<br />
83<br />
83<br />
83<br />
104<br />
88<br />
87<br />
86<br />
85<br />
84<br />
82<br />
81<br />
19<br />
104<br />
88<br />
87<br />
86<br />
85<br />
84<br />
82<br />
81<br />
19<br />
104 88 87 86 85 84 82 81 19<br />
88<br />
82<br />
104<br />
88<br />
82<br />
88<br />
82<br />
82<br />
82<br />
104<br />
88<br />
82<br />
104<br />
88<br />
82<br />
104<br />
88<br />
82<br />
104<br />
88<br />
87<br />
86<br />
85<br />
84<br />
82<br />
81<br />
19<br />
82<br />
82<br />
88<br />
82<br />
83<br />
83<br />
88 82<br />
104 88 87 86 85 84 82 81 19<br />
88 82<br />
104 88 82<br />
83<br />
83<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
3<br />
6<br />
BRANCH<br />
REVISION<br />
DRAWING NUMBER<br />
SIZE<br />
D<br />
R<br />
IV ALL RIGHTS RESERVED<br />
SHEET<br />
PAGE TITLE<br />
C<br />
A<br />
D<br />
2 1<br />
PAGE<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
A<br />
B<br />
C<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
D<br />
B<br />
8 7 5 4 2 1<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
Apple Inc.<br />
CRITICAL<br />
PART NUMBER QTY BOM OPTION<br />
REFERENCE DES<br />
DESCRIPTION<br />
SYM 5 OF 7<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD<br />
VDD_S<br />
SYM 4 OF 7<br />
VDDCA<br />
VDDCA<br />
VDDIO_47<br />
VDDIO_47<br />
VDD12_DDRAC_CK<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDRQ12<br />
VDDRQ12<br />
VDDRQ12<br />
VDDRQ12<br />
VDDRQ12<br />
VDDRQ12<br />
VDDRQ12<br />
VDDRQ12<br />
VDDRQ12<br />
VDDRQ12<br />
VDDA18_TS<br />
VDDA18_PLL11<br />
VDDA18_PLL_C<br />
VDDA18_PLL10<br />
VDDA18_PLL8<br />
VDDA18_PLL9<br />
VDDA18_PLL6<br />
VDDA18_PLL5<br />
VDDA18_PLL7<br />
VDDA18_PLL4<br />
VDD18_EFUSE2<br />
VDD18_EFUSE3<br />
VDD18_XTAL<br />
VDD_PLL_C<br />
VDD_PLL6<br />
VDD_PLL5<br />
VDD_PLL4<br />
VDD_47<br />
VDD_03<br />
VDD_03<br />
VDD2<br />
VDD2<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_47<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDIO_03<br />
VDDRQ12_AC<br />
VDDIO18_DDR_PLLAC<br />
VDD1<br />
VDD1<br />
VDD1<br />
VDD1<br />
PCI_VDD_CLK_1<br />
PCI_VDD_CLK_1<br />
PCI_VDD_CLK_1<br />
PCI_VDD_CLK_1<br />
PCI_VDD_CLK_2<br />
PCI_VDD_CLK_2<br />
VDDIO18_DDR_PLL_D<br />
VDDIO18_DDR_PLL_D<br />
VDDIO_03<br />
VDDIO_03<br />
VDD_PLL7<br />
VDD_PLL8<br />
VDD_PLL9<br />
VDD_PLL10<br />
VDD_PLL11<br />
VDD18_EFUSE0<br />
VDD18_EFUSE1<br />
VDDIO_47<br />
VDDRQ12<br />
VDDRQ12<br />
VDDRQ12<br />
VDDRQ12<br />
VDDRQ12<br />
VDDRQ12<br />
VDD_47<br />
VDD_47<br />
VDD_47<br />
VDD_47<br />
VDD_47<br />
VDD_47<br />
VDD_47<br />
VDD_47<br />
VDD_03<br />
VDD_03<br />
VDD_03<br />
VDD_03<br />
VDD_03<br />
VDD_03<br />
VDD_03<br />
VDD2<br />
VDD2<br />
VDD2<br />
VDD2<br />
VDD2<br />
VDD2<br />
VDD2<br />
VDDRQ12_AC<br />
VDDRQ12_AC<br />
VDDRQ12_AC_AON<br />
VDDRQ12<br />
VDDRQ12<br />
VDDRQ12<br />
VDDRQ12<br />
VDDRQ12<br />
VDDRQ12<br />
VDDRQ12<br />
VDDRQ12<br />
VDDRQ12<br />
VDDRQ12<br />
VDDRQ12<br />
VDDRQ12<br />
VDD1<br />
VDD1<br />
PCI_VDD_1<br />
PCI_VDD_1<br />
PCI_VDD_1<br />
PCI_VDD_2<br />
PCI_VDD_2<br />
PCI_VDD_2<br />
PCI_AVDD_H<br />
PCI_VDD_1<br />
<br />
<br />
051-00777
dvt-fab09-0<br />
88 OF 145<br />
9.0.0<br />
83 OF 119<br />
NC_S3X_VSS_S 102<br />
S3X_VSSA18_PLL_C<br />
S3X_VSSA18_PLL11<br />
S3X_VSSA18_PLL10<br />
S3X_VSSA18_PLL9<br />
S3X_VSSA18_PLL8<br />
S3X_VSSA18_PLL4<br />
S3X_VSSA18_PLL5<br />
S3X_VSSA18_PLL6<br />
S3X_VSSA18_PLL7<br />
PAGE_TITLE=S3X GND<br />
BOM_COST_GROUP=SSD<br />
SYNC_MASTER=J79_RIO<br />
SYNC_DATE=06/18/2015<br />
S3X<br />
BGA-H1P35<br />
OMIT_TABLE<br />
U8600<br />
G23<br />
G24<br />
G25<br />
G26<br />
G27<br />
H3<br />
H4<br />
H6<br />
H7<br />
H8<br />
H11<br />
H12<br />
H13<br />
H14<br />
H19<br />
H21<br />
H23<br />
H25<br />
H27<br />
H28<br />
J5<br />
J8<br />
J10<br />
J18<br />
J22<br />
J24<br />
J26<br />
K4<br />
K9<br />
K11<br />
K21<br />
K27<br />
L3<br />
L5<br />
L8<br />
L10<br />
L12<br />
L14<br />
L16<br />
L18<br />
L20<br />
L22<br />
L26<br />
L28<br />
M3<br />
M4<br />
M6<br />
M7<br />
M9<br />
M11<br />
M13<br />
M15<br />
M17<br />
M19<br />
M21<br />
M23<br />
M24<br />
M25<br />
M27<br />
M28<br />
N3<br />
N5<br />
N8<br />
N10<br />
N12<br />
N14<br />
N16<br />
N18<br />
N20<br />
N22<br />
N26<br />
N28<br />
P4<br />
P9<br />
P11<br />
P13<br />
P15<br />
P17<br />
P19<br />
P21<br />
P23<br />
P27<br />
R3<br />
R5<br />
R8<br />
R10<br />
R12<br />
R14<br />
R16<br />
R18<br />
R20<br />
R22<br />
R26<br />
R28<br />
T3<br />
T4<br />
T7<br />
T9<br />
T11<br />
T13<br />
T15<br />
T17<br />
T19<br />
T21<br />
T23<br />
T24<br />
T27<br />
T28<br />
U5<br />
U8<br />
U10<br />
U12<br />
U14<br />
U16<br />
U18<br />
U20<br />
U22<br />
U26<br />
V3<br />
V4<br />
V9<br />
V11<br />
V13<br />
V19<br />
V21<br />
V23<br />
V27<br />
V28<br />
W3<br />
W5<br />
W8<br />
W10<br />
W12<br />
W14<br />
W16<br />
W20<br />
W22<br />
W26<br />
W28<br />
Y3<br />
Y4<br />
Y9<br />
Y11<br />
Y13<br />
Y15<br />
Y17<br />
Y21<br />
Y27<br />
Y28<br />
V15<br />
S3X<br />
BGA-H1P35<br />
OMIT_TABLE<br />
U8600<br />
A1<br />
A2<br />
A9<br />
A20<br />
A29<br />
A30<br />
AA5<br />
AA12<br />
AA14<br />
AA16<br />
AA18<br />
AA20<br />
AA22<br />
AA24<br />
AA26<br />
AB5<br />
AB8<br />
AB10<br />
AB14<br />
AB17<br />
AB18<br />
AB21<br />
AB23<br />
AB26<br />
AC3<br />
AC4<br />
AC5<br />
AC7<br />
AC9<br />
AC11<br />
AC13<br />
AC15<br />
AC17<br />
AC18<br />
AC19<br />
AC20<br />
AC22<br />
AC24<br />
AC26<br />
AC27<br />
AC28<br />
AD4<br />
AD5<br />
AD6<br />
AD7<br />
AD8<br />
AD9<br />
AD14<br />
AD16<br />
AD18<br />
AD19<br />
AD24<br />
AD25<br />
AD26<br />
AD27<br />
AE3<br />
AE4<br />
AE5<br />
AE6<br />
AE7<br />
AE8<br />
AE9<br />
AE10<br />
AE12<br />
AE13<br />
AE15<br />
AE19<br />
AE21<br />
AE22<br />
AE23<br />
AE25<br />
AE26<br />
AE27<br />
AE28<br />
AF3<br />
AF4<br />
AF5<br />
AF7<br />
AF8<br />
AF9<br />
AF11<br />
AF12<br />
AF14<br />
AF16<br />
AF27<br />
AF28<br />
AG3<br />
AG4<br />
AG13<br />
AG15<br />
AG19<br />
AG21<br />
AG23<br />
AG25<br />
AG27<br />
AG28<br />
AH4<br />
AH14<br />
AH27<br />
AJ1<br />
AJ2<br />
AJ4<br />
AJ6<br />
AJ10<br />
AJ12<br />
AJ13<br />
AJ14<br />
AJ17<br />
AJ19<br />
AJ21<br />
AJ25<br />
AJ27<br />
AJ29<br />
AJ30<br />
AK1<br />
AK2<br />
AK29<br />
AK30<br />
B1<br />
B2<br />
B9<br />
B10<br />
B11<br />
B12<br />
B13<br />
B14<br />
B15<br />
B16<br />
B17<br />
B18<br />
B27<br />
B28<br />
B29<br />
B30<br />
C5<br />
C7<br />
C9<br />
C18<br />
C22<br />
C23<br />
C24<br />
C25<br />
C26<br />
C27<br />
D3<br />
D9<br />
D10<br />
D11<br />
D12<br />
D13<br />
D14<br />
D15<br />
D16<br />
D17<br />
D18<br />
D27<br />
D28<br />
E3<br />
E13<br />
E14<br />
E15<br />
E16<br />
E17<br />
E18<br />
E27<br />
E28<br />
F3<br />
F5<br />
F7<br />
F9<br />
F13<br />
F14<br />
F15<br />
F16<br />
F17<br />
F19<br />
F20<br />
F22<br />
F24<br />
F25<br />
F26<br />
F27<br />
F28<br />
G4<br />
G13<br />
G14<br />
G15<br />
G20<br />
G22<br />
Y24<br />
U24<br />
K24<br />
N24<br />
K7<br />
N7<br />
Y7<br />
U7<br />
V17<br />
82<br />
82<br />
82<br />
82<br />
82<br />
82<br />
82<br />
82<br />
82<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
3<br />
6<br />
BRANCH<br />
REVISION<br />
DRAWING NUMBER<br />
SIZE<br />
D<br />
R<br />
IV ALL RIGHTS RESERVED<br />
SHEET<br />
PAGE TITLE<br />
C<br />
A<br />
D<br />
2 1<br />
PAGE<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
A<br />
B<br />
C<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
D<br />
B<br />
8 7 5 4 2 1<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
Apple Inc.<br />
SYM 7 OF 7<br />
VSS_S<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
SYM 6 OF 7<br />
VSS_PLL7<br />
VSS_PLL6<br />
VSS_PLL5<br />
VSS_PLL4<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS_PLL8<br />
VSS_PLL9<br />
VSS_PLL10<br />
VSS_PLL11<br />
VSS_PLL_C<br />
<br />
<br />
051-00777
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
104 81<br />
104 94 81<br />
104 94 81<br />
104 81<br />
104 88<br />
87 86 85 84 82 81 19<br />
104 88<br />
S3X_JTAG_TDI<br />
S3X_JTAG_TMS<br />
S3X_JTAG_TCK<br />
S3X_JTAG_SEL<br />
SSD_DBG_UART_R2D<br />
PP1V8_SSD_COLD<br />
JTAG (DEBUG 1)<br />
NC<br />
S3X_DBG<br />
J8992<br />
DF40PB-20DS-0.4V<br />
22<br />
21<br />
F-ST-SM<br />
1 2<br />
3 4<br />
5 6<br />
7 8<br />
9 10<br />
11 12<br />
13 14<br />
15 16<br />
17 18<br />
19 20<br />
23<br />
S3X_JTAG_TDO<br />
S3X_JTAG_TRST_L<br />
SSD_BOOT_LB_L<br />
S3X_HOLD_RESET<br />
SSD_DBG_UART_D2R<br />
SSD_RESET_LB_L<br />
PP1V8_SSD_COLD<br />
81 104<br />
81 104<br />
81 88 91<br />
81<br />
19 88 104<br />
81 88 91<br />
19 81 82<br />
84<br />
85<br />
86<br />
87<br />
88<br />
104<br />
101<br />
101<br />
88<br />
PP3V3_S4<br />
PP3V3_S5_SSD<br />
5%<br />
5%<br />
R8901 100K<br />
1 2<br />
1/20W MF<br />
1/20W MF<br />
201<br />
R8902 100K<br />
1 2<br />
201<br />
PD_L<br />
STORAGE_EN<br />
91<br />
88<br />
104<br />
91<br />
91<br />
105 15<br />
105 15<br />
105 15<br />
GND_VOID=TRUE<br />
PCIE_SSD_R2D_LB_C_P<br />
PCIE_SSD_R2D_LB_C_N<br />
GND_VOID=TRUE<br />
PCIE_SSD_R2D_C_P<br />
GND_VOID=TRUE<br />
PCIE_SSD_R2D_C_N<br />
GND_VOID=TRUE<br />
PCIE_SSD_R2D_C_P<br />
GND_VOID=TRUE<br />
PCIE_SSD_R2D_C_N<br />
GND_VOID=TRUE<br />
PCIE_SSD_R2D_C_P<br />
PCIE_SSD_R2D_C_N<br />
C8910<br />
GND_VOID=TRUE<br />
C8911<br />
C8913<br />
C8912<br />
C8914<br />
C8915<br />
C8917<br />
GND_VOID=TRUE<br />
C8916<br />
0.22UF<br />
1 2<br />
0.22UF<br />
1 2<br />
0.22UF<br />
1 2<br />
0.22UF<br />
1 2<br />
0.22UF<br />
1 2<br />
0.22UF<br />
1 2<br />
0.22UF<br />
1 2<br />
0.22UF<br />
1 2<br />
GND_VOID=TRUE<br />
PCIE_SSD_R2D_LB_P<br />
GND_VOID=TRUE<br />
PCIE_SSD_R2D_LB_N<br />
GND_VOID=TRUE<br />
PCIE_SSD_R2D_P<br />
GND_VOID=TRUE<br />
PCIE_SSD_R2D_N<br />
GND_VOID=TRUE<br />
PCIE_SSD_R2D_P<br />
GND_VOID=TRUE<br />
PCIE_SSD_R2D_N<br />
105 15 81<br />
105 15<br />
105 15<br />
GND_VOID=TRUE<br />
PCIE_SSD_R2D_P<br />
GND_VOID=TRUE<br />
PCIE_SSD_R2D_N<br />
81<br />
81<br />
81<br />
81<br />
81<br />
81<br />
81<br />
D<br />
24<br />
3<br />
C<br />
88<br />
77<br />
SSD_PWR_REQ<br />
P2MM<br />
SM<br />
1<br />
PP<br />
PP8901<br />
91<br />
SSD_PWR_EN_LB_L<br />
1<br />
R8903<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
1<br />
G<br />
D<br />
2<br />
S<br />
Q8901<br />
DMN32D2LFB4<br />
DFN1006H4-3<br />
SYM_VER_1<br />
C<br />
B<br />
B<br />
A<br />
BOM_COST_GROUP=SSD<br />
SYNC_MASTER=J79_RUENJOU<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
Connector<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
89 OF 145<br />
84 OF 119<br />
SYNC_DATE=09/09/2015<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
U9010: Top side under S3X<br />
DEVICE 2-WIRE ADDRESS ADD0 PIN CONNECTION<br />
1001000 GND<br />
1001001 V+<br />
1001010 SDA<br />
1001011 SCL<br />
D<br />
104 88 87 86 84 82 81 19<br />
PP1V8_SSD_COLD<br />
88 85 81<br />
88 85 81<br />
BI<br />
BI<br />
1<br />
R9010<br />
4.7K<br />
5%<br />
1/20W<br />
MF<br />
2201<br />
1<br />
R9011<br />
4.7K<br />
5%<br />
1/20W<br />
MF<br />
2201<br />
S3X_I2C_SDA<br />
S3X_I2C_SCL<br />
6<br />
1<br />
5<br />
U9010<br />
HPA00330AI<br />
SDA<br />
SCL<br />
V+<br />
SOT563<br />
ADD0<br />
ALERT<br />
4<br />
3<br />
S3X_I2C_SDA<br />
NC<br />
81<br />
1<br />
BYPASS=U9011.5::3.0MM<br />
C9010<br />
0.01UF<br />
10%<br />
2 10V<br />
X5R-CERM<br />
0201<br />
85 88<br />
BYPASS=U9010.5::3.0MM<br />
1<br />
2<br />
C9011<br />
0.01UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
C9012<br />
0.01UF<br />
10%<br />
2 10V<br />
X5R-CERM<br />
0201<br />
BYPASS=U9012.5::3.0MM<br />
1<br />
BYPASS=U9013.5::3.0MM<br />
1 C9013<br />
0.01UF<br />
10%<br />
2 10V<br />
X5R-CERM<br />
0201<br />
GND<br />
2<br />
C<br />
6<br />
1<br />
5<br />
V+<br />
U9011<br />
HPA00330AI<br />
SOT563<br />
SDA<br />
ADD0<br />
SCL<br />
ALERT<br />
4<br />
3<br />
S3X_I2C_SCL<br />
NC<br />
81<br />
85<br />
88<br />
U9011: Bottom side under Piccolo<br />
C<br />
GND<br />
2<br />
6<br />
1<br />
5<br />
V+<br />
U9012<br />
HPA00330AI<br />
SOT563<br />
SDA<br />
ADD0<br />
SCL<br />
ALERT<br />
4<br />
3<br />
NC<br />
U9012: Bottom side near north NAND<br />
B<br />
GND<br />
2<br />
B<br />
6<br />
1<br />
5<br />
V+<br />
U9013<br />
HPA00330AI<br />
SOT563<br />
SDA<br />
ADD0<br />
SCL<br />
ALERT<br />
4<br />
3<br />
NC<br />
U9013: Top side near south NAND<br />
GND<br />
2<br />
A<br />
BOM_COST_GROUP=SSD<br />
SYNC_MASTER=J79_RUENJOU<br />
NAND VR, I2C ROM, TEMP SENSORS<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
SYNC_DATE=09/12/2015<br />
dvt-fab09-0<br />
90 OF 145<br />
85 OF 119<br />
SIZE<br />
D<br />
A
NAND INTERFACE 0/1 TOP<br />
NAND INTERFACE 2/3 TOP<br />
86 OF 119<br />
NC_ANI0_NCE7<br />
NC_ANI2_NCE5<br />
NC_ANI0_NCE4<br />
NC_ANI0_NCE6<br />
NC_ANI1_NCE5<br />
NC_ANI3_NCE5<br />
NC_ANI3_NCE6<br />
NC_ANI3_NCE7<br />
NC_ANI2_NCE7<br />
NC_ANI0_NCE5<br />
NC_ANI1_NCE6<br />
NC_ANI1_NCE7<br />
NC_ANI1_RNB 102<br />
NC_ANI3_RNB 102<br />
NC_ANI2_NCE6<br />
NC_ANI2_NCE4<br />
NC_ANI1_NCE4<br />
NC_ANI3_NCE4<br />
91 OF 145<br />
9.0.0<br />
dvt-fab09-0<br />
PP3V3_2V7_NAND_VCC<br />
ANI2_IO<br />
ANI2_IO<br />
ANI3_IO<br />
NAND_ZQ_U9120<br />
NAND_WP_L<br />
ANI1_IO<br />
ANI1_IO<br />
ANI1_IO<br />
ANI0_NCE<br />
ANI0_IO<br />
ANI0_IO<br />
ANI0_IO<br />
ANI0_ALE<br />
ANI0_RNB<br />
ANI3_IO<br />
ANI2_RNB<br />
ANI3_IO<br />
ANI3_IO<br />
ANI3_CLE<br />
ANI2_NRE_N<br />
ANI3_DQS_P<br />
ANI2_DQS_P<br />
ANI2_IO<br />
ANI2_IO<br />
ANI2_CLE<br />
ANI3_IO<br />
ANI3_IO<br />
ANI23_VREF<br />
ANI3_NRE_N<br />
ANI3_ALE<br />
PP1V8_SSD_COLD<br />
ANI3_IO<br />
ANI3_IO<br />
ANI2_IO<br />
ANI2_IO<br />
ANI2_ALE<br />
ANI2_NCE<br />
ANI2_NWE<br />
ANI2_NRE_P<br />
ANI2_DQS_N<br />
NAND_WP_L<br />
ANI3_NCE<br />
ANI3_NWE<br />
ANI3_NRE_P<br />
ANI3_DQS_N<br />
ANI2_NCE<br />
ANI3_NCE<br />
ANI2_NCE<br />
ANI3_NCE<br />
ANI2_NCE<br />
ANI3_NCE<br />
ANI2_IO<br />
ANI2_IO<br />
ANI1_IO<br />
ANI1_IO<br />
ANI1_IO<br />
ANI0_IO<br />
ANI1_CLE<br />
ANI1_DQS_P<br />
ANI0_IO<br />
ANI0_IO<br />
ANI0_IO<br />
ANI1_IO<br />
ANI1_IO<br />
ANI01_VREF<br />
ANI1_NRE_N<br />
ANI1_ALE<br />
PP1V8_SSD_COLD<br />
ANI1_IO<br />
ANI1_IO<br />
ANI1_IO<br />
ANI0_IO<br />
ANI0_IO<br />
ANI0_ALE<br />
ANI0_NWE<br />
ANI1_NCE<br />
ANI1_NWE<br />
ANI1_NRE_P<br />
ANI1_DQS_N<br />
ANI0_NCE<br />
ANI1_NCE<br />
ANI0_NCE<br />
ANI1_NCE<br />
ANI0_NCE<br />
ANI1_NCE<br />
ANI0_IO<br />
ANI0_IO<br />
ANI2_DQS_N<br />
ANI2_DQS_P<br />
ANI01_VREF<br />
ANI2_IO<br />
ANI3_IO<br />
PP1V8_SSD_COLD<br />
PP3V3_2V7_NAND_VCC<br />
PP1V8_SSD_COLD<br />
ANI0_IO<br />
ANI0_IO<br />
ANI0_NCE<br />
ANI0_IO<br />
ANI0_IO<br />
ANI0_IO<br />
ANI0_NCE<br />
ANI0_NCE<br />
ANI0_NWE<br />
ANI1_IO<br />
ANI1_IO<br />
ANI1_IO<br />
ANI1_IO<br />
ANI1_IO<br />
ANI1_NCE<br />
ANI1_NCE<br />
ANI1_NCE<br />
ANI1_NWE<br />
ANI1_ALE<br />
ANI3_IO<br />
ANI3_IO<br />
ANI3_IO<br />
ANI3_IO<br />
ANI3_IO<br />
ANI3_IO<br />
ANI3_IO<br />
ANI3_NCE<br />
ANI3_NCE<br />
ANI3_NCE<br />
ANI2_ALE<br />
ANI2_NWE<br />
ANI2_CLE<br />
ANI2_RNB<br />
ANI0_CLE<br />
ANI2_IO<br />
ANI1_CLE<br />
ANI3_CLE<br />
ANI3_NWE<br />
ANI2_NRE_P<br />
ANI2_NRE_N<br />
ANI23_VREF<br />
ANI1_NRE_P<br />
ANI1_NRE_N<br />
ANI1_DQS_P<br />
ANI3_NRE_P<br />
ANI3_NRE_N<br />
ANI3_DQS_P<br />
ANI3_DQS_N<br />
ANI23_VREF<br />
ANI01_VREF<br />
ANI2_NCE<br />
ANI2_NCE<br />
ANI2_NCE<br />
ANI2_NCE<br />
ANI2_IO<br />
ANI2_IO<br />
ANI2_IO<br />
ANI2_IO<br />
ANI2_IO<br />
ANI0_NRE_N<br />
ANI1_NCE<br />
ANI2_IO<br />
ANI1_DQS_N<br />
ANI3_NCE<br />
ANI0_NRE_P<br />
ANI0_DQS_P<br />
ANI0_DQS_N<br />
ANI3_ALE<br />
NAND_ZQ_U9100<br />
ANI0_RNB<br />
ANI0_DQS_N<br />
ANI0_DQS_P<br />
ANI0_NRE_P<br />
ANI0_NRE_N<br />
ANI0_CLE<br />
ANI0_NCE<br />
PP3V3_2V7_NAND_VCC<br />
SYNC_DATE=09/25/2015<br />
SYNC_MASTER=J79_RUENJOU<br />
ANI[3:0]<br />
BOM_COST_GROUP=SSD<br />
86 81<br />
102<br />
102<br />
102<br />
102<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
102<br />
102<br />
102<br />
102<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
0201-1<br />
X5R<br />
20%<br />
6.3V<br />
1.0UF<br />
C9102<br />
1<br />
2<br />
20%<br />
X5R<br />
0201-1<br />
6.3V<br />
1.0UF<br />
C9104 1 2<br />
86<br />
86<br />
0201-1<br />
X5R<br />
1.0UF<br />
6.3V<br />
20%<br />
C9122<br />
1<br />
2<br />
86<br />
86<br />
86<br />
86 25V<br />
NP0-C0G<br />
3.0PF<br />
+/-0.1PF<br />
0201<br />
C9128 1 2<br />
12PF<br />
NP0-C0G<br />
25V<br />
5%<br />
0201<br />
C9127 1 2<br />
0201-1<br />
X5R<br />
1.0UF<br />
6.3V<br />
20%<br />
C9103<br />
1<br />
2<br />
OMIT_TABLE<br />
LGA<br />
1Z-64GB-2P-MLC-DDP<br />
NAND-15NM-64GB-2.8V<br />
U9120<br />
J7<br />
E7<br />
N1<br />
A1<br />
L1<br />
C1<br />
J1<br />
E1<br />
H2<br />
F2<br />
L7<br />
C7<br />
M4<br />
L3<br />
B4<br />
C3<br />
D4<br />
K4<br />
OA0<br />
OB8<br />
OE8<br />
OF0<br />
N3<br />
A3<br />
N5<br />
A5<br />
M2<br />
B2<br />
M6<br />
B6<br />
L5<br />
C5<br />
K6<br />
D6<br />
K2<br />
D2<br />
J3<br />
E3<br />
G0<br />
G1<br />
G5<br />
G7<br />
H6<br />
J5<br />
H4<br />
E5<br />
F4<br />
OA8<br />
OC0<br />
OD0<br />
OF8<br />
OB0<br />
OC8<br />
OD8<br />
OE0<br />
G8<br />
N7<br />
A7<br />
F6<br />
G3<br />
NAND-15NM-64GB-2.8V<br />
1Z-64GB-2P-MLC-DDP<br />
LGA<br />
OMIT_TABLE<br />
U9100<br />
J7<br />
E7<br />
N1<br />
A1<br />
L1<br />
C1<br />
J1<br />
E1<br />
H2<br />
F2<br />
L7<br />
C7<br />
M4<br />
L3<br />
B4<br />
C3<br />
D4<br />
K4<br />
OA0<br />
OB8<br />
OE8<br />
OF0<br />
N3<br />
A3<br />
N5<br />
A5<br />
M2<br />
B2<br />
M6<br />
B6<br />
L5<br />
C5<br />
K6<br />
D6<br />
K2<br />
D2<br />
J3<br />
E3<br />
G0<br />
G1<br />
G5<br />
G7<br />
H6<br />
J5<br />
H4<br />
E5<br />
F4<br />
OA8<br />
OC0<br />
OD0<br />
OF8<br />
OB0<br />
OC8<br />
OD8<br />
OE0<br />
G8<br />
N7<br />
A7<br />
F6<br />
G3<br />
OMIT_TABLE<br />
BGA-H1P35<br />
S3X<br />
U8600<br />
AH23<br />
AK22<br />
AE29<br />
AE30<br />
AC29<br />
AD30<br />
AD29<br />
AD28<br />
AG30<br />
AG29<br />
AH30<br />
AH29<br />
AG22<br />
AD23<br />
AF21<br />
AD22<br />
AF22<br />
AF23<br />
AJ20<br />
AK20<br />
AF29<br />
AF30<br />
AH28<br />
AH22<br />
AH21<br />
AJ22<br />
AC30<br />
AK26<br />
AG24<br />
V29<br />
V30<br />
T29<br />
U30<br />
U29<br />
U28<br />
Y30<br />
Y29<br />
AA30<br />
AA29<br />
AJ24<br />
AG26<br />
AH26<br />
AF24<br />
AF26<br />
AK24<br />
AE24<br />
AH24<br />
W29<br />
W30<br />
AA28<br />
AF25<br />
AH25<br />
AJ26<br />
T30<br />
E20<br />
A22<br />
F30<br />
F29<br />
H29<br />
G28<br />
G29<br />
G30<br />
D29<br />
D30<br />
C29<br />
C30<br />
B22<br />
C19<br />
D22<br />
E22<br />
F21<br />
D19<br />
D21<br />
E21<br />
E30<br />
E29<br />
C28<br />
E19<br />
B20<br />
D20<br />
H30<br />
E25<br />
E26<br />
N30<br />
N29<br />
R29<br />
P28<br />
P29<br />
P30<br />
L29<br />
L30<br />
K29<br />
K30<br />
A26<br />
D24<br />
A24<br />
D25<br />
D23<br />
E24<br />
D26<br />
B25<br />
M30<br />
M29<br />
K28<br />
F23<br />
E23<br />
B24<br />
R30<br />
0402<br />
6.3V<br />
20UF<br />
CERM-X5R<br />
20%<br />
C9191<br />
1<br />
2<br />
0402<br />
20%<br />
6.3V<br />
20UF<br />
CERM-X5R<br />
C9189<br />
1<br />
2<br />
0402<br />
20%<br />
6.3V<br />
20UF<br />
CERM-X5R<br />
C9187<br />
1<br />
2<br />
0402<br />
20%<br />
6.3V<br />
20UF<br />
CERM-X5R<br />
C9188<br />
1<br />
2<br />
102<br />
102<br />
102<br />
102<br />
86<br />
86<br />
86<br />
102<br />
102<br />
102<br />
86<br />
86<br />
86<br />
86<br />
102<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86 81<br />
201<br />
1%<br />
1/20W<br />
MF<br />
300<br />
R9192<br />
1 2<br />
300<br />
1/20W<br />
1%<br />
MF<br />
201<br />
R9190<br />
1 2<br />
201<br />
5%<br />
1/20W<br />
MF<br />
10K<br />
1 R9102<br />
2<br />
201<br />
5%<br />
1/20W<br />
MF<br />
10K<br />
1 R9100<br />
2<br />
86<br />
81<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
81<br />
86<br />
86<br />
86<br />
86<br />
81<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
81<br />
10%<br />
CERM-X5R<br />
6.3V<br />
0.1UF<br />
0201<br />
C9114 1 2<br />
0.1UF<br />
CERM-X5R<br />
6.3V<br />
10%<br />
0201<br />
C9113 1 2<br />
6.3V<br />
20%<br />
0201<br />
X6S-CERM<br />
0.22UF<br />
C9123<br />
1<br />
2<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
1.0UF<br />
C9124 1 2<br />
0201<br />
CERM-X5R<br />
6.3V<br />
10%<br />
0.1UF<br />
C9134 1 2<br />
0201<br />
CERM-X5R<br />
6.3V<br />
10%<br />
0.1UF<br />
C9133 1 2<br />
0201<br />
6.3V<br />
10%<br />
0.1UF<br />
CERM-X5R<br />
C9126 1 2<br />
6.3V<br />
10%<br />
0.1UF<br />
0201<br />
CERM-X5R<br />
C9120 1 2<br />
10%<br />
0.1UF<br />
0201<br />
CERM-X5R<br />
6.3V<br />
C9106 1 2<br />
NOSTUFF<br />
1K<br />
201<br />
5%<br />
MF<br />
1/20W<br />
1 R9101<br />
2<br />
0.22UF<br />
20%<br />
6.3V<br />
X6S-CERM<br />
0201<br />
C9125 1 2<br />
20%<br />
6.3V<br />
0201<br />
X6S-CERM<br />
0.22UF<br />
C9105 1 2<br />
6.3V<br />
0.22UF<br />
20%<br />
0201<br />
X6S-CERM<br />
C9101 1 2<br />
6.3V<br />
0201<br />
0.22UF<br />
X6S-CERM<br />
20%<br />
C9121 1 2<br />
0201<br />
6.3V<br />
10%<br />
0.1UF<br />
CERM-X5R<br />
C9100 1 2<br />
101 88 87 86<br />
88<br />
87 86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
104 88 87 86 85 84 82 81 19<br />
86<br />
86<br />
86<br />
86<br />
88<br />
87<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
104<br />
88<br />
87<br />
86<br />
85<br />
84<br />
82<br />
81<br />
19<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
104<br />
88<br />
87<br />
86<br />
85<br />
84<br />
82<br />
81<br />
19<br />
101 88 87 86<br />
104<br />
88<br />
87<br />
86<br />
85<br />
84<br />
82<br />
81<br />
19<br />
86 86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86 86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
3<br />
6<br />
BRANCH<br />
REVISION<br />
DRAWING NUMBER<br />
SIZE<br />
D<br />
R<br />
IV ALL RIGHTS RESERVED<br />
SHEET<br />
PAGE TITLE<br />
C<br />
A<br />
D<br />
2 1<br />
PAGE<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
A<br />
B<br />
C<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
D<br />
B<br />
8 7 5 4 2 1<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
Apple Inc.<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
IN<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
VCC<br />
IO6-0<br />
IO3-0<br />
CE7*<br />
CE6*<br />
CE5*<br />
CE4*<br />
CE3*<br />
CE2*<br />
DQS1*<br />
RE1*<br />
WE1*<br />
CE1*<br />
WP*<br />
DQS0*<br />
RE0*<br />
WE0*<br />
CE0*<br />
ALE0<br />
VCCQ<br />
IO1-0<br />
IO2-0<br />
NC_G5<br />
IO6-1<br />
IO5-1<br />
IO2-1<br />
GND<br />
ALE1<br />
RE1<br />
VREF<br />
IO0-1<br />
IO4-1<br />
CLE0<br />
IO7-0<br />
IO5-0<br />
IO0-0<br />
DQS0<br />
DQS1<br />
RE0<br />
NC_G1<br />
CLE1<br />
IO4-0<br />
IO1-1<br />
IO3-1<br />
NC_G0<br />
ZQ<br />
R/B*<br />
NC_G7<br />
IO7-1<br />
VCC<br />
IO6-0<br />
IO3-0<br />
CE7*<br />
CE6*<br />
CE5*<br />
CE4*<br />
CE3*<br />
CE2*<br />
DQS1*<br />
RE1*<br />
WE1*<br />
CE1*<br />
WP*<br />
DQS0*<br />
RE0*<br />
WE0*<br />
CE0*<br />
ALE0<br />
VCCQ<br />
IO1-0<br />
IO2-0<br />
NC_G5<br />
IO6-1<br />
IO5-1<br />
IO2-1<br />
GND<br />
ALE1<br />
RE1<br />
VREF<br />
IO0-1<br />
IO4-1<br />
CLE0<br />
IO7-0<br />
IO5-0<br />
IO0-0<br />
DQS0<br />
DQS1<br />
RE0<br />
NC_G1<br />
CLE1<br />
IO4-0<br />
IO1-1<br />
IO3-1<br />
NC_G0<br />
ZQ<br />
R/B*<br />
NC_G7<br />
IO7-1<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
SYM 1 OF 7<br />
ANI0_IO3<br />
ANI0_NCE(2)<br />
ANI0_IO5<br />
ANI0_IO4<br />
ANI0_IO7<br />
ANI0_IO6<br />
ANI0_NCE(1)<br />
ANI0_NCE(0)<br />
ANI0_NCE(4)<br />
ANI0_NCE(3)<br />
ANI0_NCE(6)<br />
ANI0_ALE<br />
ANI0_NWE<br />
ANI0_RNB<br />
ANI1_IO0<br />
ANI1_IO1<br />
ANI1_IO2<br />
ANI1_IO3<br />
ANI1_IO4<br />
ANI1_IO5<br />
ANI1_IO6<br />
ANI1_IO7<br />
ANI1_NCE(0)<br />
ANI1_NCE(1)<br />
ANI1_NCE(2)<br />
ANI1_NCE(4)<br />
ANI1_NCE(3)<br />
ANI1_NCE(5)<br />
ANI1_NWE<br />
ANI1_PPM_IN<br />
ANI0_PPM_OUT<br />
ANI0_PPM_IN<br />
ANI1_ALE<br />
ANI3_IO0<br />
ANI3_IO1<br />
ANI3_IO2<br />
ANI3_IO3<br />
ANI3_IO4<br />
ANI3_IO5<br />
ANI3_IO6<br />
ANI3_IO7<br />
ANI2_IO7<br />
ANI2_IO6<br />
ANI3_NCE(0)<br />
ANI3_NCE(1)<br />
ANI3_NCE(2)<br />
ANI3_NCE(3)<br />
ANI3_NCE(4)<br />
ANI3_NCE(5)<br />
ANI3_NCE(6)<br />
ANI3_NCE(7)<br />
ANI2_NCE(0)<br />
ANI2_NCE(1)<br />
ANI2_NCE(2)<br />
ANI2_NCE(3)<br />
ANI2_NCE(4)<br />
ANI2_NCE(5)<br />
ANI2_NCE(7)<br />
ANI2_ALE<br />
ANI2_NWE<br />
ANI2_CLE<br />
ANI2_RNB<br />
ANI2_PPM_IN<br />
ANI2_IO5<br />
ANI2_IO4<br />
ANI2_IO3<br />
ANI0_CLE<br />
ANI0_NCE(7)<br />
ANI0_NCE(5)<br />
ANI2_PPM_OUT<br />
ANI3_PPM_OUT<br />
ANI3_PPM_IN<br />
ANI2_IO2<br />
ANI2_IO1<br />
ANI2_IO0<br />
ANI0_VREF<br />
ANI1_NCE(6)<br />
ANI1_NCE(7)<br />
ANI1_CLE<br />
ANI1_RNB<br />
ANI1_PPM_OUT<br />
ANI3_ALE<br />
ANI3_CLE<br />
ANI3_NWE<br />
ANI3_RNB<br />
ANI0_NRE_P<br />
ANI0_NRE_N<br />
ANI0_DQS_P<br />
ANI0_DQS_N<br />
ANI2_NRE_P<br />
ANI2_NRE_N<br />
ANI2_DQS_P<br />
ANI2_DQS_N<br />
ANI2_VREF<br />
ANI1_NRE_P<br />
ANI1_NRE_N<br />
ANI1_DQS_P<br />
ANI1_DQS_N<br />
ANI1_VREF<br />
ANI3_NRE_P<br />
ANI3_NRE_N<br />
ANI3_DQS_P<br />
ANI3_DQS_N<br />
ANI3_VREF<br />
ANI2_NCE(6)<br />
ANI0_IO2<br />
ANI0_IO1<br />
ANI0_IO0<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
BI<br />
BI<br />
OUT<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
OUT<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
<br />
<br />
051-00777
NAND INTERFACE 6/7<br />
NAND INTERFACE 4/5<br />
87 OF 119<br />
NC_ANI5_NCE4<br />
NC_ANI5_NCE5<br />
NC_ANI5_NCE6<br />
NC_ANI5_NCE7<br />
NC_ANI7_NCE4<br />
NC_ANI7_NCE5<br />
NC_ANI7_NCE6<br />
NC_ANI7_RNB<br />
NC_ANI4_NCE7<br />
NC_ANI6_NCE5<br />
NC_ANI4_NCE5<br />
NC_ANI4_NCE4<br />
NC_ANI4_NCE6<br />
NC_ANI6_NCE4<br />
NC_ANI6_NCE6<br />
NC_ANI6_NCE7<br />
NC_ANI5_RNB<br />
NC_ANI7_NCE7<br />
92 OF 145<br />
9.0.0<br />
dvt-fab09-0<br />
ANI4_IO<br />
ANI4_IO<br />
ANI4_ALE<br />
ANI5_NRE_N<br />
ANI5_IO<br />
ANI5_NCE<br />
ANI5_NCE<br />
ANI5_DQS_P<br />
ANI5_DQS_N<br />
ANI45_VREF<br />
ANI7_IO<br />
ANI7_IO<br />
ANI7_IO<br />
ANI7_IO<br />
ANI7_IO<br />
ANI7_NCE<br />
ANI7_NCE<br />
ANI7_NCE<br />
ANI7_ALE<br />
ANI7_CLE<br />
ANI7_NWE<br />
ANI6_NRE_P<br />
ANI6_NRE_N<br />
ANI6_DQS_P<br />
ANI6_DQS_N<br />
ANI67_VREF<br />
ANI7_NRE_P<br />
ANI7_NRE_N<br />
ANI7_DQS_P<br />
ANI7_DQS_N<br />
ANI67_VREF<br />
ANI4_IO<br />
ANI4_IO<br />
ANI4_IO<br />
ANI4_IO<br />
ANI5_IO<br />
ANI5_IO<br />
ANI5_IO<br />
ANI5_IO<br />
ANI5_NRE_P<br />
ANI5_IO<br />
ANI5_IO<br />
ANI6_RNB<br />
ANI6_NWE<br />
PP1V8_SSD_COLD<br />
ANI5_NCE<br />
ANI5_IO<br />
ANI4_IO<br />
ANI4_IO<br />
ANI7_NCE<br />
ANI7_IO<br />
ANI7_IO<br />
ANI5_CLE<br />
ANI5_ALE<br />
ANI4_NCE<br />
ANI6_CLE<br />
ANI4_NRE_P<br />
ANI4_NCE<br />
ANI4_NCE<br />
ANI4_NCE<br />
PP1V8_SSD_COLD<br />
ANI7_IO<br />
ANI4_IO<br />
ANI4_IO<br />
ANI4_NCE<br />
ANI4_NCE<br />
ANI5_NCE<br />
ANI4_NCE<br />
ANI5_DQS_N<br />
ANI5_NRE_P<br />
ANI5_NCE<br />
NAND_WP_L<br />
ANI4_DQS_N<br />
ANI4_NWE<br />
ANI4_NCE<br />
ANI4_ALE<br />
ANI4_IO<br />
ANI4_IO<br />
ANI5_IO<br />
ANI5_IO<br />
ANI5_IO<br />
PP1V8_SSD_COLD<br />
PP3V3_2V7_NAND_VCC<br />
ANI5_NRE_N<br />
ANI45_VREF<br />
ANI4_CLE<br />
ANI4_IO<br />
ANI4_IO<br />
ANI4_IO<br />
ANI4_DQS_P<br />
ANI5_DQS_P<br />
ANI4_NRE_N<br />
ANI4_IO<br />
ANI5_IO<br />
ANI4_RNB<br />
ANI5_IO<br />
ANI6_IO<br />
ANI6_IO<br />
ANI7_NCE<br />
ANI6_NCE<br />
ANI7_NCE<br />
ANI6_NCE<br />
ANI7_NCE<br />
ANI6_NCE<br />
ANI7_DQS_N<br />
ANI7_NRE_P<br />
ANI7_NWE<br />
ANI7_NCE<br />
NAND_WP_L<br />
ANI6_DQS_N<br />
ANI6_NRE_P<br />
ANI6_NWE<br />
ANI6_NCE<br />
ANI6_ALE<br />
ANI6_IO<br />
ANI6_IO<br />
ANI7_IO<br />
ANI7_IO<br />
ANI7_IO<br />
PP1V8_SSD_COLD<br />
ANI7_ALE<br />
ANI7_NRE_N<br />
ANI67_VREF<br />
ANI7_IO<br />
ANI7_IO<br />
ANI6_CLE<br />
ANI6_IO<br />
ANI6_IO<br />
ANI6_IO<br />
ANI7_DQS_P<br />
ANI7_CLE<br />
ANI6_IO<br />
ANI7_IO<br />
ANI7_IO<br />
ANI7_IO<br />
ANI5_IO<br />
NAND_ZQ_U9200<br />
ANI4_CLE<br />
ANI5_NCE<br />
ANI5_NCE<br />
ANI4_NRE_P<br />
NAND_ZQ_U9220<br />
ANI4_NWE<br />
ANI4_RNB<br />
ANI4_NRE_N<br />
ANI4_DQS_P<br />
ANI4_DQS_N<br />
ANI45_VREF<br />
ANI6_IO<br />
ANI6_IO<br />
ANI6_IO<br />
ANI6_IO<br />
ANI6_IO<br />
ANI6_IO<br />
ANI6_IO<br />
ANI6_IO<br />
ANI6_NCE<br />
ANI6_NCE<br />
ANI6_NCE<br />
ANI6_NCE<br />
ANI6_ALE<br />
ANI5_NWE<br />
ANI5_NCE<br />
ANI5_NWE<br />
ANI5_ALE<br />
ANI5_CLE<br />
ANI5_IO<br />
ANI5_IO<br />
ANI6_DQS_P<br />
ANI6_RNB<br />
ANI6_NRE_N<br />
PP3V3_2V7_NAND_VCC<br />
SYNC_DATE=09/25/2015<br />
SYNC_MASTER=J79_RUENJOU<br />
BOM_COST_GROUP=SSD<br />
ANI[7:4]<br />
12PF<br />
0201<br />
5%<br />
25V<br />
NP0-C0G<br />
C9227 1 2<br />
NP0-C0G<br />
0201<br />
+/-0.1PF<br />
3.0PF<br />
25V<br />
C9228 1 2<br />
OMIT_TABLE<br />
LGA<br />
1Z-64GB-2P-MLC-DDP<br />
NAND-15NM-64GB-2.8V<br />
U9220<br />
J7<br />
E7<br />
N1<br />
A1<br />
L1<br />
C1<br />
J1<br />
E1<br />
H2<br />
F2<br />
L7<br />
C7<br />
M4<br />
L3<br />
B4<br />
C3<br />
D4<br />
K4<br />
OA0<br />
OB8<br />
OE8<br />
OF0<br />
N3<br />
A3<br />
N5<br />
A5<br />
M2<br />
B2<br />
M6<br />
B6<br />
L5<br />
C5<br />
K6<br />
D6<br />
K2<br />
D2<br />
J3<br />
E3<br />
G0<br />
G1<br />
G5<br />
G7<br />
H6<br />
J5<br />
H4<br />
E5<br />
F4<br />
OA8<br />
OC0<br />
OD0<br />
OF8<br />
OB0<br />
OC8<br />
OD8<br />
OE0<br />
G8<br />
N7<br />
A7<br />
F6<br />
G3<br />
OMIT_TABLE<br />
LGA<br />
1Z-64GB-2P-MLC-DDP<br />
NAND-15NM-64GB-2.8V<br />
U9200<br />
J7<br />
E7<br />
N1<br />
A1<br />
L1<br />
C1<br />
J1<br />
E1<br />
H2<br />
F2<br />
L7<br />
C7<br />
M4<br />
L3<br />
B4<br />
C3<br />
D4<br />
K4<br />
OA0<br />
OB8<br />
OE8<br />
OF0<br />
N3<br />
A3<br />
N5<br />
A5<br />
M2<br />
B2<br />
M6<br />
B6<br />
L5<br />
C5<br />
K6<br />
D6<br />
K2<br />
D2<br />
J3<br />
E3<br />
G0<br />
G1<br />
G5<br />
G7<br />
H6<br />
J5<br />
H4<br />
E5<br />
F4<br />
OA8<br />
OC0<br />
OD0<br />
OF8<br />
OB0<br />
OC8<br />
OD8<br />
OE0<br />
G8<br />
N7<br />
A7<br />
F6<br />
G3<br />
S3X<br />
BGA-H1P35<br />
OMIT_TABLE<br />
U8600<br />
D7<br />
F6<br />
F1<br />
F2<br />
H2<br />
G3<br />
G2<br />
G1<br />
D2<br />
D1<br />
C2<br />
C1<br />
G6<br />
E7<br />
E6<br />
G7<br />
D8<br />
A6<br />
H9<br />
G8<br />
E1<br />
E2<br />
C3<br />
B6<br />
C6<br />
D6<br />
H1<br />
F4<br />
A3<br />
N1<br />
N2<br />
R2<br />
P3<br />
P2<br />
P1<br />
L2<br />
L1<br />
K2<br />
K1<br />
B3<br />
D4<br />
E4<br />
B4<br />
A4<br />
D5<br />
B5<br />
A5<br />
M1<br />
M2<br />
K3<br />
G5<br />
E5<br />
C4<br />
R1<br />
AJ9<br />
AK9<br />
AE2<br />
AE1<br />
AC2<br />
AD1<br />
AD2<br />
AD3<br />
AG1<br />
AG2<br />
AH1<br />
AH2<br />
AK11<br />
AJ11<br />
AH10<br />
AH9<br />
AH12<br />
AH11<br />
AG9<br />
AG11<br />
AF2<br />
AF1<br />
AH3<br />
AG10<br />
AF10<br />
AG12<br />
AC1<br />
AG6<br />
AH6<br />
V2<br />
V1<br />
T2<br />
U1<br />
U2<br />
U3<br />
Y1<br />
Y2<br />
AA1<br />
AA2<br />
AK5<br />
AK7<br />
AJ7<br />
AJ5<br />
AH5<br />
AH7<br />
AG7<br />
AG5<br />
W2<br />
W1<br />
AA3<br />
AG8<br />
AH8<br />
AF6<br />
T1<br />
6.3V<br />
20%<br />
X5R<br />
0201-1<br />
1.0UF<br />
C9216<br />
1<br />
2<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
C9215<br />
1<br />
2 1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
C9217 1 2<br />
20%<br />
6.3V<br />
0.22UF<br />
0201<br />
X6S-CERM<br />
C9218 1 2<br />
CERM-X5R<br />
6.3V<br />
0.1UF<br />
10%<br />
0201<br />
C9219 1 2<br />
6.3V<br />
10%<br />
0201<br />
CERM-X5R<br />
0.1UF<br />
C9220 1 2<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
0.1UF<br />
C9221 1 2<br />
102<br />
102<br />
87<br />
102<br />
87<br />
87<br />
102<br />
102<br />
102<br />
102<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
81<br />
102<br />
102<br />
102<br />
102<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87 81<br />
102<br />
1%<br />
1/20W<br />
MF<br />
201<br />
300<br />
R9292<br />
1 2<br />
300<br />
MF<br />
1%<br />
201<br />
1/20W<br />
R9290<br />
1 2<br />
1/20W<br />
5%<br />
MF<br />
10K<br />
201<br />
1 R9201<br />
2<br />
87<br />
87<br />
201<br />
5%<br />
1/20W<br />
MF<br />
10K<br />
1 R9200<br />
2<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87 81<br />
102<br />
102<br />
102<br />
102<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
81<br />
102<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
81<br />
87<br />
87<br />
102<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
81<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
0201-1<br />
X5R<br />
20%<br />
6.3V<br />
1.0UF<br />
C9203<br />
1<br />
2<br />
X5R<br />
6.3V<br />
20%<br />
1.0UF<br />
0201-1<br />
C9204 1 2<br />
0201<br />
CERM-X5R<br />
0.1UF<br />
6.3V<br />
10%<br />
C9212 1 2<br />
0201<br />
CERM-X5R<br />
6.3V<br />
10%<br />
0.1UF<br />
C9214 1 2<br />
CERM-X5R<br />
0201<br />
10%<br />
6.3V<br />
0.1UF<br />
C9213 1 2<br />
CERM-X5R<br />
0201<br />
6.3V<br />
10%<br />
0.1UF<br />
C9206 1 2<br />
6.3V<br />
0201<br />
CERM-X5R<br />
10%<br />
0.1UF<br />
C9200 1 2<br />
1.0UF<br />
20%<br />
X5R<br />
6.3V<br />
0201-1<br />
C9202<br />
1<br />
2<br />
X6S-CERM<br />
0201<br />
0.22UF<br />
6.3V<br />
20%<br />
C9205 1 2<br />
X6S-CERM<br />
20%<br />
0.22UF<br />
6.3V<br />
0201<br />
C9201 1 2<br />
0.22UF<br />
20%<br />
X6S-CERM<br />
0201<br />
6.3V<br />
C9211 1 2<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
104<br />
88<br />
87<br />
86<br />
85<br />
84<br />
82<br />
81<br />
19<br />
87<br />
87<br />
87<br />
87<br />
104<br />
88<br />
87<br />
86<br />
85<br />
84<br />
82<br />
81<br />
19<br />
87<br />
87<br />
88<br />
87<br />
86<br />
87<br />
87<br />
87<br />
104<br />
88<br />
87<br />
86<br />
85<br />
84<br />
82<br />
81<br />
19<br />
101 88 87 86<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
88<br />
87<br />
86<br />
87<br />
87<br />
87<br />
87<br />
104<br />
88<br />
87<br />
86<br />
85<br />
84<br />
82<br />
81<br />
19<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
3<br />
6<br />
BRANCH<br />
REVISION<br />
DRAWING NUMBER<br />
SIZE<br />
D<br />
R<br />
IV ALL RIGHTS RESERVED<br />
SHEET<br />
PAGE TITLE<br />
C<br />
A<br />
D<br />
2 1<br />
PAGE<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
A<br />
B<br />
C<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
D<br />
B<br />
8 7 5 4 2 1<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
Apple Inc.<br />
VCC<br />
IO6-0<br />
IO3-0<br />
CE7*<br />
CE6*<br />
CE5*<br />
CE4*<br />
CE3*<br />
CE2*<br />
DQS1*<br />
RE1*<br />
WE1*<br />
CE1*<br />
WP*<br />
DQS0*<br />
RE0*<br />
WE0*<br />
CE0*<br />
ALE0<br />
VCCQ<br />
IO1-0<br />
IO2-0<br />
NC_G5<br />
IO6-1<br />
IO5-1<br />
IO2-1<br />
GND<br />
ALE1<br />
RE1<br />
VREF<br />
IO0-1<br />
IO4-1<br />
CLE0<br />
IO7-0<br />
IO5-0<br />
IO0-0<br />
DQS0<br />
DQS1<br />
RE0<br />
NC_G1<br />
CLE1<br />
IO4-0<br />
IO1-1<br />
IO3-1<br />
NC_G0<br />
ZQ<br />
R/B*<br />
NC_G7<br />
IO7-1<br />
VCC<br />
IO6-0<br />
IO3-0<br />
CE7*<br />
CE6*<br />
CE5*<br />
CE4*<br />
CE3*<br />
CE2*<br />
DQS1*<br />
RE1*<br />
WE1*<br />
CE1*<br />
WP*<br />
DQS0*<br />
RE0*<br />
WE0*<br />
CE0*<br />
ALE0<br />
VCCQ<br />
IO1-0<br />
IO2-0<br />
NC_G5<br />
IO6-1<br />
IO5-1<br />
IO2-1<br />
GND<br />
ALE1<br />
RE1<br />
VREF<br />
IO0-1<br />
IO4-1<br />
CLE0<br />
IO7-0<br />
IO5-0<br />
IO0-0<br />
DQS0<br />
DQS1<br />
RE0<br />
NC_G1<br />
CLE1<br />
IO4-0<br />
IO1-1<br />
IO3-1<br />
NC_G0<br />
ZQ<br />
R/B*<br />
NC_G7<br />
IO7-1<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
NC<br />
SYM 2 OF 7<br />
ANI4_IO5<br />
ANI4_NCE(0)<br />
ANI4_NCE(5)<br />
ANI4_ALE<br />
ANI4_CLE<br />
ANI4_NWE<br />
ANI4_PPM_IN<br />
ANI4_NRE_N<br />
ANI5_NRE_N<br />
ANI4_PPM_OUT<br />
ANI4_NRE_P<br />
ANI5_IO7<br />
ANI5_NCE(0)<br />
ANI5_NCE(1)<br />
ANI5_NCE(2)<br />
ANI5_NCE(3)<br />
ANI5_NCE(4)<br />
ANI5_NCE(5)<br />
ANI5_NCE(6)<br />
ANI5_NCE(7)<br />
ANI4_DQS_P<br />
ANI4_DQS_N<br />
ANI5_DQS_P<br />
ANI5_DQS_N<br />
ANI4_VREF<br />
ANI5_VREF<br />
ANI4_RNB<br />
ANI6_IO0<br />
ANI6_IO1<br />
ANI6_IO2<br />
ANI6_IO3<br />
ANI6_IO4<br />
ANI6_IO5<br />
ANI6_IO6<br />
ANI6_IO7<br />
ANI7_IO0<br />
ANI7_IO1<br />
ANI7_IO2<br />
ANI7_IO3<br />
ANI7_IO4<br />
ANI7_IO5<br />
ANI7_IO6<br />
ANI7_IO7<br />
ANI6_NCE(3)<br />
ANI6_NCE(7)<br />
ANI7_NCE(0)<br />
ANI7_NCE(1)<br />
ANI7_NCE(2)<br />
ANI7_NCE(3)<br />
ANI7_NCE(4)<br />
ANI7_NCE(5)<br />
ANI7_NCE(6)<br />
ANI7_NCE(7)<br />
ANI6_ALE<br />
ANI6_CLE<br />
ANI7_ALE<br />
ANI7_CLE<br />
ANI7_NWE<br />
ANI7_RNB<br />
ANI6_PPM_OUT<br />
ANI6_NRE_P<br />
ANI6_NRE_N<br />
ANI6_DQS_P<br />
ANI6_DQS_N<br />
ANI6_VREF<br />
ANI7_PPM_IN<br />
ANI7_PPM_OUT<br />
ANI7_NRE_P<br />
ANI7_NRE_N<br />
ANI7_DQS_P<br />
ANI7_DQS_N<br />
ANI7_VREF<br />
ANI4_IO0<br />
ANI6_NCE(4)<br />
ANI6_NCE(0)<br />
ANI6_NCE(1)<br />
ANI6_NCE(2)<br />
ANI5_PPM_IN<br />
ANI5_RNB<br />
ANI5_NWE<br />
ANI5_CLE<br />
ANI5_ALE<br />
ANI4_NCE(1)<br />
ANI4_NCE(4)<br />
ANI5_PPM_OUT<br />
ANI4_IO4<br />
ANI4_IO6<br />
ANI4_IO1<br />
ANI4_IO3<br />
ANI4_IO2<br />
ANI4_NCE(2)<br />
ANI4_NCE(3)<br />
ANI4_NCE(6)<br />
ANI4_NCE(7)<br />
ANI5_IO6<br />
ANI5_IO5<br />
ANI5_IO4<br />
ANI5_IO3<br />
ANI5_IO2<br />
ANI5_NRE_P<br />
ANI6_NCE(6)<br />
ANI6_NCE(5)<br />
ANI5_IO1<br />
ANI5_IO0<br />
ANI4_IO7<br />
ANI6_PPM_IN<br />
ANI6_RNB<br />
ANI6_NWE<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
BI<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
OUT<br />
BI<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
OUT<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
<br />
<br />
051-00777
SYNC_MASTER=J79_RUENJOU<br />
SYNC_DATE=09/24/2015<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
C<br />
88<br />
101<br />
84 PP3V3_S5_SSD<br />
1<br />
2<br />
C9300<br />
0.1UF<br />
20%<br />
16V<br />
X6S-CERM<br />
0201<br />
VOLTAGE=0.9V<br />
P0V9_FIXED_SW<br />
VR_P1V8_HOT_FB<br />
SWITCH_NODE=TRUE<br />
P1V8_HOT_SW<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
88 84<br />
101<br />
PP3V3_S5_SSD<br />
1 C9313<br />
0.1UF<br />
20%<br />
2<br />
16V<br />
X6S-CERM<br />
0201<br />
U9300<br />
D2331<br />
WLCSP<br />
SYM 1 OF 8<br />
L6<br />
OMIT_TABLE<br />
VDD_BUCK0_01<br />
BUCK0_FB_DIS J4<br />
VOLTAGE=0.9V<br />
101 88 84 PP3V3_S5_SSD<br />
M6 VDD_BUCK0_01<br />
L5 P0V9_REG_SW0<br />
M5 DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
1<br />
2<br />
C9320<br />
10UF<br />
20%<br />
6.3V<br />
CERM-X6S<br />
0402<br />
1<br />
2<br />
C9301<br />
4.7UF<br />
20%<br />
6.3V<br />
X6S<br />
0402<br />
1<br />
2<br />
C9321<br />
10UF<br />
20%<br />
6.3V<br />
CERM-X6S<br />
0402<br />
1<br />
2<br />
C9302<br />
4.7UF<br />
20%<br />
6.3V<br />
X6S<br />
0402<br />
1<br />
C9329<br />
0.1UF<br />
20%<br />
2<br />
16V<br />
X6S-CERM<br />
0201<br />
M1<br />
M2<br />
H1<br />
VDD_BUCK1<br />
VDD_BUCK1<br />
VDD_BUCK5<br />
U9300<br />
D2331<br />
WLCSP<br />
SYM 2 OF 8<br />
OMIT_TABLE<br />
BUCK1_FB_DIS<br />
BUCK1_LX0<br />
BUCK5_FB_DIS<br />
BUCK5_LX0<br />
VSS(VSS_BUCK1_5)<br />
BUCK0_LX0<br />
BUCK0_LX0<br />
BUCK0_LX1<br />
BUCK0_LX1<br />
VSS(VSS_BUCK0)<br />
VSS(VSS_BUCK0)<br />
VSS(VSS_BUCK0)<br />
K3<br />
L1<br />
J3<br />
J1<br />
K1<br />
L7<br />
M7<br />
L8<br />
M4<br />
M8<br />
P0V9_REG_SW1<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
VOLTAGE=0.9V<br />
VR_P0V9_FIXED_FB<br />
DIDT=TRUE<br />
VOLTAGE=1.8V<br />
1UH-20%-2.2A-0.072OHM<br />
2<br />
1 2 82 PP0V9_SSD_FIXED<br />
VOLTAGE=0.9V<br />
1UH-20%-1.01A-0.202OHM<br />
1 2 PP1V8_SSD_HOT<br />
VR_P0V9_REG_FB<br />
L9320<br />
1UH-20%-3.8A-0.035OHM<br />
1 2<br />
PIFE32251B-SM<br />
L9321<br />
1UH-20%-3.8A-0.035OHM<br />
1 2<br />
PIFE32251B-SM<br />
L9300<br />
0806<br />
L9310<br />
PSB12101T-SM<br />
104 82<br />
VOLTAGE=1.8V<br />
PP0V9_SSD_REG<br />
VOLTAGE=0.9V<br />
1<br />
C9328<br />
1000PF<br />
10%<br />
2<br />
25V<br />
X7R<br />
0201<br />
1<br />
2<br />
1<br />
2<br />
C9310<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402<br />
C9322<br />
22UF<br />
20UF<br />
1<br />
R9320<br />
0<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
1<br />
R9300<br />
0 5%<br />
1/20W<br />
MF<br />
201<br />
1<br />
R9310<br />
0<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
20%<br />
10V<br />
X5R-CERM<br />
0603-1<br />
1<br />
2<br />
1<br />
2<br />
1<br />
2<br />
C9303<br />
20UF<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402<br />
C9311<br />
C9323<br />
22UF<br />
4.7UF<br />
20%<br />
6.3V<br />
X6S<br />
0402<br />
C9317 1<br />
12PF<br />
2<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
20%<br />
10V<br />
X5R-CERM<br />
0603-1<br />
1<br />
2<br />
1<br />
2<br />
1<br />
2<br />
1<br />
C9307<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
C9304<br />
2.2UF<br />
20%<br />
10V<br />
CER-X6S<br />
0402<br />
C9312<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
C9324<br />
22UF<br />
1000PF<br />
10%<br />
2<br />
25V<br />
X7R<br />
0201<br />
C9318 1<br />
3.0PF<br />
2<br />
20%<br />
10V<br />
X5R-CERM<br />
0603-1<br />
1<br />
1<br />
2<br />
1<br />
2<br />
C9308<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
C9305<br />
2.2UF<br />
20%<br />
10V<br />
CER-X6S<br />
0402<br />
19<br />
C9325<br />
22UF<br />
20%<br />
2<br />
10V<br />
X5R-CERM<br />
0603-1<br />
101<br />
88<br />
84<br />
81<br />
PICCOLO I2C INTERFACE ADDRESSES<br />
WRITE:78H<br />
READ:79H<br />
PP3V3_S5_SSD<br />
50<br />
SSD_DBG_UART_R2D_R<br />
1<br />
2<br />
12PF<br />
IN<br />
C9326<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
R9357<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
1<br />
2<br />
3.0PF<br />
1<br />
R9358<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
NOSTUFF<br />
1<br />
R9373<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
81<br />
104 84<br />
C9327<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
IN<br />
R9377 1<br />
1K 1%<br />
1/20W<br />
201<br />
MF<br />
2<br />
101 88 87 86<br />
81<br />
81<br />
81<br />
85 81<br />
S3X_PMIC_LOW_PWR<br />
S3X_PMIC_EXT_CLK_DIS<br />
85 81<br />
S3X_DEBUG_UART_D2R<br />
S3X_SMC_OOB_UART_D2R<br />
SSD_DBG_UART_R2D<br />
SMC_OOB1_R2D_L<br />
89 88<br />
88<br />
BI<br />
IN<br />
BI<br />
S3X_PMIC_CTRL0<br />
S3X_PMIC_CTRL1<br />
S3X_RET_LPSR_CLEAR<br />
S3X_PCIE_CLKREQ_L<br />
P2V7NAND_PGOOD<br />
PICCOLO_POK2<br />
PP3V3_2V7_NAND_VCC<br />
89 88<br />
81<br />
81<br />
81<br />
S3X_I2C_SCL<br />
S3X_I2C_SDA<br />
1<br />
R9376<br />
1K<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
101<br />
G5<br />
G7<br />
H6<br />
H8<br />
D8<br />
C8<br />
88<br />
P2V7NAND_PGOOD<br />
84<br />
E7<br />
C6<br />
C4<br />
C5<br />
E8<br />
K2<br />
F5<br />
F6<br />
LS1P8_IN1<br />
LS1P8_IN2<br />
LS3P3_IN1<br />
LS3P3_IN2<br />
POK1<br />
POK2<br />
PMIC_LOW_POWER<br />
PMIC_EXT_CLK_DIS<br />
PMIC_CTRL0/DEBUG<br />
PMIC_CTRL1<br />
RET_LPSR_CLEAR<br />
PCIE_CLKREQ_L_1.8V<br />
I2C_SCL<br />
I2C_SDA<br />
U9300<br />
D2331<br />
WLCSP<br />
SYM 6 OF 8<br />
OMIT_TABLE<br />
PP3V3_S5_SSD<br />
88<br />
PICCOLO_POK2<br />
U9300<br />
D2331<br />
WLCSP<br />
SYM 4 OF 8<br />
OMIT_TABLE<br />
PFN<br />
PERST*<br />
RESET*<br />
BOOT_FROM_LPSR<br />
LS1P8_OUT1<br />
LS1P8_OUT2<br />
LS3P3_OUT1<br />
LS3P3_OUT2<br />
20K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
LPDDR3_RET*<br />
VEN1<br />
VEN2<br />
G6<br />
G8<br />
H5<br />
H7<br />
D7<br />
C7<br />
1<br />
R9375<br />
C3<br />
J2<br />
D3<br />
G4<br />
C2<br />
S3X_PFN<br />
S3X_PERST_L<br />
S3X_RESET_L<br />
S3X_COLD_BOOT_L<br />
S3X_RET_EN_L<br />
S3X_DEBUG_UART_R2D<br />
S3X_SMC_OOB_UART_R2D<br />
SSD_DBG_UART_D2R_R<br />
SMC_OOB_UART_D2R_R<br />
PICCOLO_VEN1<br />
NC_PICCOLO_VEN2<br />
PP1V8_SSD_COLD<br />
NOSTUFF<br />
1<br />
R9371<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
89<br />
105<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
1/20W<br />
MF<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
81<br />
81<br />
81<br />
81<br />
81<br />
R9378<br />
1 2<br />
100<br />
5% 201<br />
1<br />
R9372<br />
10K<br />
19<br />
OUT<br />
OUT<br />
81<br />
81<br />
81<br />
1/20W<br />
MF<br />
SSD_DBG_UART_D2R<br />
R9379<br />
1 2<br />
82<br />
100<br />
201<br />
5%<br />
SMC_OOB1_D2R_L<br />
84<br />
85<br />
86<br />
87<br />
88<br />
104<br />
19<br />
OUT<br />
84<br />
50<br />
104<br />
D<br />
C<br />
91 84 81<br />
SSD_BOOT_LB_L<br />
B<br />
A<br />
101<br />
89<br />
91<br />
88<br />
1<br />
84 PP3V3_S5_SSD<br />
C9330<br />
0.1UF<br />
20%<br />
2<br />
16V<br />
X6S-CERM<br />
0201<br />
101<br />
88<br />
101<br />
88<br />
PPVIN_2V7NAND_LB<br />
1<br />
84 PP3V3_S5_SSD<br />
84 PP3V3_S5_SSD<br />
1<br />
C9350<br />
150UF<br />
20%<br />
2 6.3V<br />
TANT-POLY<br />
CASE-B1S-1<br />
R9350 1<br />
1.3M<br />
1%<br />
1/20W<br />
MF<br />
0201 2<br />
C9362<br />
220PF<br />
10%<br />
2<br />
25V<br />
X7R-CERM<br />
201<br />
1<br />
2<br />
1<br />
C9331<br />
4.7UF<br />
20%<br />
6.3V<br />
X6S<br />
0402<br />
C9333<br />
0.1UF<br />
20%<br />
2<br />
16V<br />
X6S-CERM<br />
0201<br />
1<br />
IUVD VDIVIDER:<br />
3S - 215K<br />
2S 348K<br />
1<br />
R9351<br />
215K<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
1<br />
2<br />
1<br />
2<br />
C9332<br />
4.7UF<br />
20%<br />
6.3V<br />
X6S<br />
0402<br />
C9351<br />
0.1UF<br />
20%<br />
2<br />
16V<br />
X6S-CERM<br />
0201<br />
R9351<br />
1<br />
R9355<br />
10K<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
C9347<br />
10UF<br />
20%<br />
6.3V<br />
CERM-X6S<br />
0402<br />
88 87 86<br />
101<br />
88 82<br />
1<br />
2<br />
1<br />
2<br />
C9348<br />
10UF<br />
20%<br />
6.3V<br />
CERM-X6S<br />
0402<br />
PP3V3_2V7_NAND_VCC<br />
88<br />
C9352<br />
0.1UF<br />
20%<br />
16V<br />
X6S-CERM<br />
0201<br />
PICCOLO_IUVD<br />
10%<br />
6.3V<br />
X7R<br />
0201<br />
PICCOLO_VPP_OTP<br />
PP1V2_SSD_HOT<br />
1<br />
2<br />
A2<br />
A6<br />
B6<br />
104 88 87 86 85 84 82 81 19<br />
C9353<br />
0.1UF<br />
F1<br />
F3<br />
E2<br />
E6<br />
A1<br />
B1<br />
VDD_BUCK3<br />
VDD_BUCK4_01<br />
VDD_BUCK4_01<br />
WLCSP<br />
SYM 3 OF 8<br />
OMIT_TABLE<br />
PP1V8_SSD_COLD<br />
VSENSE1<br />
VSENSE2<br />
IUVD<br />
VPP_OTP<br />
1.2V_COLD_IN<br />
1.2V_COLD_IN<br />
U9300<br />
D2331<br />
J5<br />
H4<br />
D5<br />
B2<br />
V_BUF_1.8V<br />
VCORE_A<br />
VCORE_D<br />
VPUMP<br />
U9300<br />
D2331<br />
WLCSP<br />
SYM 7 OF 8<br />
OMIT_TABLE<br />
BUCK3_FB_DIS<br />
BUCK3_LX0<br />
BUCK3_LX0<br />
VSS(VSS_BUCK3_4)<br />
VSS(VSS_BUCK3_4)<br />
BUCK4_FB_DIS<br />
BUCK4_LX0<br />
BUCK4_LX0<br />
BUCK4_LX1<br />
BUCK4_LX1<br />
VSS(VSS_BUCK4)<br />
VSS(VSS_BUCK4)<br />
PICCOLO_VPUMP<br />
VREF<br />
IREF<br />
VCC_DIS<br />
VDD_RTC<br />
1.2V_COLD_OUT<br />
G2<br />
F2<br />
E1<br />
G1<br />
C1<br />
D2<br />
A3<br />
B3<br />
A4<br />
B4<br />
E5<br />
A5<br />
B5<br />
A7<br />
B7<br />
A8<br />
B8<br />
1<br />
2<br />
VR_P1V2_HOT_FB<br />
P1V2_HOT_SW<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
VR_P1V8_COLD_FB<br />
P1V8_COLD_SW0<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
P1V8_COLD_SW1<br />
C9354<br />
0.01UF<br />
10%<br />
25V<br />
X7R<br />
402<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
VOLTAGE=1.8V<br />
PICCOLO_VREF<br />
PICCOLO_IREF<br />
PP3V3_2V7_NAND_VCC<br />
82<br />
PICCOLO_VDD_RTC<br />
PP1V2_SSD_COLD<br />
1<br />
C9356<br />
22UF<br />
20%<br />
2<br />
10V<br />
X5R-CERM<br />
0603-1<br />
1<br />
R9330<br />
0<br />
1 2<br />
VOLTAGE=1.2V<br />
VOLTAGE=1.8V<br />
NOSTUFF<br />
1/20W 5%<br />
MF<br />
201<br />
C9357<br />
22UF<br />
20%<br />
2<br />
10V<br />
X5R-CERM<br />
0603-1<br />
R9340<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
86<br />
87<br />
88<br />
VOLTAGE=1.2V<br />
1<br />
101<br />
PP1V2_SSD_HOT<br />
VOLTAGE=1.2V<br />
1.0UH-20%-2.7A-55MOHM<br />
104 88 87 86 85<br />
84 82<br />
1 2 81 19 PP1V8_SSD_COLD<br />
C9358<br />
1000PF<br />
10%<br />
2<br />
25V<br />
X7R<br />
0201<br />
L9330<br />
1UH-20%-2.2A-0.072OHM<br />
1 2<br />
0806<br />
L9340<br />
PIFE25201B-SM<br />
L9341<br />
1.0UH-20%-2.7A-55MOHM<br />
1 2<br />
PIFE25201B-SM<br />
1<br />
2<br />
C9377<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
88 82<br />
1<br />
2<br />
C9378<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
VOLTAGE=1.8V<br />
1<br />
PLACE_NEAR=U9300.F2:1.0MM<br />
1<br />
2<br />
1<br />
22UF<br />
C9359<br />
0.1UF<br />
10%<br />
6.3V<br />
X7R<br />
0201<br />
C9334<br />
22UF<br />
20%<br />
2<br />
10V<br />
X5R-CERM<br />
0603-1<br />
C9340<br />
20%<br />
2<br />
10V<br />
X5R-CERM<br />
0603-1<br />
1<br />
1<br />
2<br />
C9344<br />
22UF<br />
20%<br />
2<br />
10V<br />
X5R-CERM<br />
0603-1<br />
C9363<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
1<br />
22UF<br />
22UF<br />
1<br />
R9360<br />
200K<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
C9335<br />
20%<br />
2<br />
10V<br />
X5R-CERM<br />
0603-1<br />
C9341<br />
20%<br />
2<br />
10V<br />
X5R-CERM<br />
0603-1<br />
1<br />
C9345<br />
22UF<br />
20%<br />
2<br />
10V<br />
X5R-CERM<br />
0603-1<br />
C9364<br />
1<br />
3.0PF<br />
+/-0.1PF<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
C9342<br />
22UF<br />
20%<br />
2<br />
10V<br />
X5R-CERM<br />
0603-1<br />
1<br />
2<br />
1<br />
2<br />
1<br />
2<br />
1<br />
C9336<br />
C9346<br />
0.01UF<br />
10%<br />
10V<br />
X5R-CERM<br />
0201<br />
C9365<br />
12PF<br />
5%<br />
1000PF<br />
10%<br />
2<br />
25V<br />
X7R<br />
0201<br />
25V<br />
NP0-C0G<br />
0201<br />
C9361<br />
0.1UF<br />
10%<br />
6.3V<br />
X7R<br />
0201<br />
1<br />
C9343<br />
22UF<br />
20%<br />
2<br />
10V<br />
X5R-CERM<br />
0603-1<br />
1<br />
2<br />
1<br />
2<br />
1<br />
2<br />
C9337<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
C9367<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
C9366<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
**NEED PID GPIO OPTION TABLE**<br />
101<br />
C9368<br />
1<br />
3.0PF<br />
+/-0.1PF<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
88<br />
C9338<br />
1<br />
3.0PF<br />
+/-0.1PF<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
84 PP3V3_S5_SSD<br />
1<br />
R9380<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
1<br />
R9383<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
91<br />
91 84 81<br />
88 84<br />
91<br />
D4<br />
E4<br />
F4<br />
F8<br />
K4<br />
G3<br />
IN<br />
IN<br />
IN<br />
BI<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
91 88<br />
1<br />
R9386<br />
0<br />
MF<br />
1/20W 5%<br />
2 201<br />
88<br />
PICCOLO_PID0<br />
PICCOLO_PID1<br />
LPSR_EN_LB_L<br />
PICCOLO_NOR_CS_L<br />
IN<br />
STORAGE_LB_EN<br />
SSD_RESET_LB_L<br />
PD_L<br />
SSD_PCIE_CLKREQ_LB_L<br />
U9300<br />
D2331<br />
WLCSP<br />
SYM 8 OF 8<br />
OMIT_TABLE<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
D1<br />
H3<br />
K5<br />
L3<br />
H2<br />
J7<br />
F7<br />
K8<br />
K7<br />
L2<br />
L4<br />
K6<br />
M3<br />
89 88<br />
BOM_COST_GROUP=SSD<br />
88<br />
PID0<br />
PID1<br />
LPSR_EN*<br />
NOR_CS*<br />
STORAGE_EN<br />
STORAGE_RST*<br />
PD*<br />
PCIE_CLKREQ*<br />
P2V7NAND_PGOOD<br />
PICCOLO_POK2<br />
U9300<br />
D2331<br />
WLCSP<br />
SYM 5 OF 8<br />
OMIT_TABLE<br />
PAGE TITLE<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
R<br />
PP9305<br />
PP9306<br />
E3<br />
D6<br />
J8<br />
J6<br />
88<br />
88 84<br />
91 88<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
88<br />
101<br />
88<br />
84<br />
PICCOLO_PGOOD<br />
PICCOLO_WP_L<br />
PP3V3_S5_SSD<br />
SSD_PWR_REQ<br />
NC_PICCOLO_24M_CLK_REQ 102<br />
PICCOLO_IUVD<br />
PD_L<br />
LPSR_EN_LB_L<br />
1<br />
R9385<br />
5%<br />
MF<br />
1/20W<br />
2 201<br />
PICCOLO_NOR_CS_L<br />
PICCOLO PMIC<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
IV ALL RIGHTS RESERVED<br />
PGOOD<br />
WP*<br />
STORAGE_LATCH<br />
PP<br />
PP<br />
24_CLK_REQ<br />
Apple Inc.<br />
0<br />
NAND_WP_L<br />
REVISION<br />
BRANCH<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1<br />
DRAWING NUMBER<br />
PAGE<br />
SHEET<br />
PP<br />
PP<br />
PP<br />
PP<br />
1<br />
R9384<br />
10K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
OUT<br />
OUT<br />
PP9301<br />
PP9302<br />
PP9303<br />
PP9304<br />
051-00777<br />
9.0.0<br />
86<br />
77<br />
dvt-fab09-0<br />
93 OF 145<br />
88 OF 119<br />
87<br />
84<br />
SIZE<br />
D<br />
B<br />
A<br />
8 7 6<br />
5 4 3<br />
2 1
SYNC_MASTER=J79_JSHAO<br />
SYNC_DATE=12/18/2015<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
101<br />
89<br />
PP3V3_2V7_NAND_VCC<br />
91<br />
PP5V_S4_P2V7NAND_LB<br />
91 88<br />
PPVIN_2V7NAND_LB<br />
D<br />
C<br />
XW9430<br />
SM<br />
P2V7NAND_RFB_N<br />
0.1%<br />
1/20W<br />
MF<br />
0201-1<br />
NO_XNET_CONNECTION=1<br />
P2V7NAND_RFB_P<br />
Change R3505 and R3531 to 0.1% when available<br />
1<br />
2<br />
2<br />
1<br />
R9403 1<br />
10K<br />
2<br />
C9426<br />
10PF<br />
5%<br />
50V<br />
C0G<br />
0201<br />
2<br />
XW9431<br />
1<br />
SM<br />
1<br />
R9404<br />
10K<br />
0.1%<br />
1/20W<br />
MF<br />
2 0201-1<br />
1<br />
R9431<br />
10K<br />
0.1%<br />
1/20W<br />
MF<br />
2 0201-1<br />
NO_XNET_CONNECTION=1<br />
1<br />
R9402<br />
10K<br />
0.1%<br />
1/20W<br />
MF<br />
2 0201-1<br />
1<br />
2<br />
88<br />
10PF<br />
5%<br />
50V<br />
C0G<br />
0201<br />
IN<br />
C9423 1<br />
0.01UF<br />
2<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
C9415<br />
PICCOLO_VEN1<br />
1<br />
R9417<br />
191K<br />
0.1%<br />
1/20W<br />
MF<br />
2 0201<br />
1<br />
R9418<br />
95.3K<br />
0.1%<br />
1/20W<br />
MF<br />
2 0201<br />
1<br />
2<br />
P2V7NAND_SET_R<br />
R9400<br />
16.9K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
R9420<br />
2<br />
0<br />
5%<br />
1/20W<br />
MF<br />
201<br />
1<br />
C9417<br />
22PF<br />
5%<br />
50V<br />
C0G<br />
0201<br />
PP2V7_NAND_VCC<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=2.7V<br />
1<br />
2<br />
C9422<br />
1UF<br />
10%<br />
16V<br />
X6S-CERM<br />
0402<br />
89<br />
R9413 1<br />
100K<br />
1%<br />
1/20W<br />
MF<br />
201 2<br />
P2V7NAND_EN<br />
P2V7NAND_SENSE_DIV<br />
P2V7NAND_SREF<br />
P2V7NAND_VO<br />
P2V7NAND_OCSET<br />
P2V7NAND_PGOOD_R<br />
P2V7NAND_RTN_DIV<br />
P2V7NAND_FSEL<br />
P2V7NAND_SET0<br />
P2V7NAND_SET1<br />
15<br />
10<br />
7<br />
12<br />
11<br />
14<br />
4<br />
13<br />
8<br />
9<br />
6<br />
5<br />
R9401 1<br />
10<br />
5%<br />
1/20W<br />
MF<br />
201 2<br />
EN<br />
FB<br />
SREF<br />
VO<br />
OCSET<br />
PGOOD<br />
RTN<br />
FSEL<br />
SET0<br />
SET1<br />
VID0<br />
VID1<br />
19<br />
ISL95870AH<br />
CRITICAL<br />
3<br />
VCC<br />
U9400<br />
GND<br />
20<br />
UTQFN<br />
2<br />
1<br />
R9406<br />
5%<br />
1/16W<br />
MF-LF<br />
2 402<br />
PVCC<br />
PGND<br />
2.2<br />
PP2V7_NAND_PVCC<br />
BOOT<br />
UGATE<br />
PHASE<br />
LGATE<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=2.7V<br />
1<br />
2<br />
18<br />
17<br />
16<br />
1<br />
C9421<br />
2.2UF<br />
20%<br />
10V<br />
CER-X6S<br />
0402<br />
R9409 1<br />
2.2<br />
5%<br />
1/20W<br />
MF<br />
201 2<br />
P2V7NAND_VBST<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
P2V7NAND_DRVH_R<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
GATE_NODE=TRUE<br />
DIDT=TRUE<br />
P2V7NAND_LL<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
SWITCH_NODE=TRUE<br />
DIDT=TRUE<br />
P2V7NAND_DRVL_R<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
GATE_NODE=TRUE<br />
DIDT=TRUE<br />
P2V7NAND_BOOT_RC<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
1<br />
2<br />
C9416<br />
0.1UF<br />
10%<br />
16V<br />
X7R-CERM<br />
0402<br />
R9415<br />
2<br />
R9414<br />
2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
0<br />
0<br />
5%<br />
1/20W<br />
MF<br />
201<br />
1<br />
P2V7NAND_DRVH<br />
1<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
GATE_NODE=TRUE<br />
3 TG<br />
DIDT=TRUE<br />
4 TGR<br />
P2V7NAND_DRVL<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
GATE_NODE=TRUE<br />
DIDT=TRUE<br />
5<br />
Q9401<br />
CSD58873Q3D<br />
Q3D<br />
BG<br />
1<br />
2<br />
9<br />
152S00270<br />
6<br />
7 P2V7NAND_SW 1 2 P2V7NAND_R<br />
8<br />
PIMB062D-SM MIN_LINE_WIDTH=0.1160<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0600<br />
MIN_NECK_WIDTH=0.0520<br />
SWITCH_NODE=TRUE<br />
DIDT=TRUE<br />
NOSTUFF<br />
R9435 1<br />
2.2<br />
5%<br />
1/10W<br />
MF-LF<br />
603 2<br />
P2V7NAND_SNUB<br />
NOSTUFF<br />
C9435<br />
0.001UF<br />
10%<br />
50V<br />
CERM<br />
402<br />
PGND<br />
C9403 1<br />
33UF<br />
20%<br />
2<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
VIN<br />
VSW<br />
1<br />
C9402 1<br />
33UF<br />
2<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
L9400<br />
C9400<br />
2.2UF<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
2.2UH-20%-12A-0.0245OHM<br />
NO_XNET_CONNECTION=1<br />
1<br />
2<br />
NO_XNET_CONNECTION=1<br />
2<br />
1<br />
1<br />
2<br />
C9401<br />
2.2UF<br />
20%<br />
25V<br />
X6S-CERM<br />
0402<br />
NO_XNET_CONNECTION=1<br />
R9421<br />
2.49K<br />
1%<br />
1/20W<br />
201<br />
MF<br />
C9470<br />
0.01UF<br />
10%<br />
10V<br />
X7R-CERM<br />
0201<br />
NO_XNET_CONNECTION=1<br />
2<br />
R9430<br />
0.003<br />
1%<br />
1/2W<br />
MF<br />
0306<br />
1 2<br />
3 4<br />
1<br />
2<br />
1<br />
1<br />
C9404<br />
1000PF<br />
10%<br />
2<br />
25V<br />
X7R<br />
0201<br />
ISNS_SSDNAND_P 57<br />
ISNS_SSDNAND_N 57<br />
R9472<br />
2.49K<br />
1/20W<br />
1%<br />
201<br />
MF<br />
NOSTUFF<br />
R9410 1<br />
200<br />
5%<br />
1/16W<br />
MF-LF<br />
402 2<br />
C9405 1<br />
2.2UF<br />
20%<br />
10V<br />
2<br />
CER-X6S<br />
0402<br />
1<br />
2<br />
VOUT = 3.3V<br />
FREQ = 500 KHZ<br />
MAX OCP = 8.51A<br />
Nom OCP = 7.06A<br />
MIN OCP = 5.16A<br />
NOSTUFF<br />
C9409<br />
150UF<br />
C9406 1<br />
2.2UF<br />
20%<br />
10V<br />
2<br />
CER-X6S<br />
0402<br />
20%<br />
6.3V<br />
POLY-TANT<br />
CASE-BL-SM<br />
1<br />
C9408<br />
150UF<br />
20%<br />
2 6.3V<br />
TANT-POLY<br />
CASE-B1S-1<br />
PP3V3_2V7_NAND_VCC 89<br />
101<br />
C9410 1<br />
1000PF<br />
2<br />
10%<br />
25V<br />
X7R<br />
0201<br />
1<br />
C9407<br />
150UF<br />
20%<br />
2 6.3V<br />
TANT-POLY<br />
CASE-B1S-1<br />
D<br />
C<br />
P2V7NAND_AGND<br />
MIN_LINE_WIDTH=0.4000<br />
MIN_NECK_WIDTH=0.2000<br />
XW9400<br />
SM<br />
1 2<br />
PLACE_NEAR=U9400.3:1MM<br />
1<br />
2<br />
CRITICAL<br />
C9430<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C9431<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C9432<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
C9433<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
2.4G DESENSE 5G DESENSE<br />
2.4G DESENSE 5G DESENSE<br />
B<br />
88<br />
P2V7NAND_PGOOD<br />
R9411<br />
2<br />
0<br />
1/20W 5%<br />
MF<br />
201<br />
1<br />
P2V7NAND_PGOOD_R<br />
89<br />
B<br />
A<br />
BOM_COST_GROUP=SSD<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
SSD NAND VR<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
94 OF 145<br />
89 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
D<br />
C<br />
C<br />
B<br />
B<br />
A<br />
SYNC_MASTER=J14<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
Empty<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
SYNC_DATE=10/23/2012<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
95 OF 145<br />
90 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
D<br />
PCH Side<br />
101<br />
104 14<br />
104 13<br />
104 84<br />
100<br />
PPBUS_G3H<br />
PP5V_S4<br />
SSD_BOOT_L<br />
SSD_PWR_EN_L<br />
STORAGE_EN<br />
LIFEBOAT<br />
J9600<br />
20759-042E-02<br />
F-ST-SM<br />
43 44<br />
PWR<br />
SIGNAL<br />
1 2<br />
3 4<br />
5 6<br />
7 8<br />
9 10<br />
SSD Side<br />
PPVIN_2V7NAND_LB<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=13.1V<br />
88<br />
PP5V_S4_P2V7NAND_LB<br />
SSD_BOOT_LB_L<br />
SSD_PWR_EN_LB_L<br />
STORAGE_LB_EN<br />
89<br />
89<br />
81<br />
84<br />
88<br />
84<br />
88<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=5V<br />
C<br />
104 19 16<br />
102<br />
105 15<br />
105 15<br />
105 15<br />
105 15<br />
15<br />
15<br />
SSD_RESET_L<br />
SSD_CLKREQ_L<br />
PCIE_SSD_D2R_P<br />
PCIE_SSD_D2R_N<br />
PCIE_SSD_R2D_C_P<br />
PCIE_SSD_R2D_C_N<br />
PCIE_CLK100M_SSD_P<br />
PCIE_CLK100M_SSD_N<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
11 12<br />
13 14<br />
15 16<br />
17 18<br />
19 20<br />
21 22<br />
23 24<br />
25 26<br />
27 28<br />
29 30<br />
31 32<br />
33 34<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
SSD_RESET_LB_L<br />
SSD_PCIE_CLKREQ_LB_L<br />
PCIE_SSD_D2R_LB_P<br />
PCIE_SSD_D2R_LB_N<br />
PCIE_SSD_R2D_LB_C_P<br />
PCIE_SSD_R2D_LB_C_N<br />
PCIE_CLK100M_SSD_LB_P<br />
PCIE_CLK100M_SSD_LB_N<br />
81<br />
88<br />
81<br />
81<br />
84<br />
84<br />
81<br />
81<br />
84 88<br />
105<br />
105<br />
C<br />
104<br />
102<br />
SSD_SR_EN_L<br />
35 36<br />
37 38<br />
LPSR_EN_LB_L<br />
88<br />
39 40<br />
41 42<br />
PWR<br />
101 PP3V3_S5<br />
45 46<br />
PP3V3_S5_SSD_LB 101<br />
47<br />
GND<br />
48<br />
49 50<br />
51 52<br />
53 54<br />
55 56<br />
57 58<br />
59 60<br />
61 62<br />
63 64<br />
65 66<br />
67 68<br />
SIGNAL_MODEL=LIFEBOAT<br />
B<br />
B<br />
A<br />
BOM_COST_GROUP=SSD<br />
SYNC_MASTER=J79_RUENJOU<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
LIFEBOAT<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
SYNC_DATE=09/09/2015<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
96 OF 145<br />
91 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
PP3V3_UPC_TA_LDO 94<br />
D<br />
1<br />
RB090<br />
3.3K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
94<br />
94<br />
92<br />
TBT_T_ROM_HOLD_L<br />
RB091 1<br />
3.3K<br />
1/20W<br />
5%<br />
MF<br />
201<br />
2<br />
TBT_T_SPI_CLK<br />
TBT_T_SPI_CS_L<br />
TBT_T_ROM_WP_L<br />
1<br />
RB093<br />
3.3K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
6<br />
1<br />
3<br />
7<br />
CLK<br />
CS*<br />
WP*(IO2)<br />
HOLD*(IO3)<br />
8<br />
UB090<br />
8MBIT-3.0V<br />
RB092 1<br />
3.3K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
W25Q80DVUXIE<br />
USON DI(IO0)<br />
DO(IO1)<br />
OMIT_TABLE<br />
CRITICAL<br />
GND<br />
VCC<br />
EPAD<br />
5<br />
2<br />
1<br />
2<br />
CB090<br />
1UF<br />
10%<br />
6.3V<br />
CERM<br />
402<br />
TBT_T_SPI_MOSI<br />
TBT_T_SPI_MISO<br />
94<br />
94<br />
94<br />
94<br />
94<br />
94<br />
94<br />
94<br />
94<br />
94<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
PCIE_TBT_T_R2D_P<br />
PCIE_TBT_T_R2D_N<br />
PCIE_TBT_T_R2D_P<br />
PCIE_TBT_T_R2D_N<br />
NC_PCIE_TBT_T_R2D_P<br />
NC_PCIE_TBT_T_R2D_N<br />
NC_PCIE_TBT_T_R2D_P<br />
NC_PCIE_TBT_T_R2D_N<br />
Y23<br />
Y22<br />
T23<br />
T22<br />
M23<br />
M22<br />
H23<br />
H22<br />
PCIE_RX0_P<br />
PCIE_RX0_N<br />
PCIE_RX1_P<br />
PCIE_RX1_N<br />
PCIE_RX2_P<br />
PCIE_RX2_N<br />
PCIE_RX3_P<br />
PCIE_RX3_N<br />
UB000<br />
TBT-AR-4C-CNTRL<br />
SYM 1 OF 2<br />
FCBGA<br />
OMIT_TABLE<br />
CRITICAL<br />
PCIE GEN3<br />
PCIE_TX0_P<br />
PCIE_TX0_N<br />
PCIE_TX1_P<br />
PCIE_TX1_N<br />
PCIE_TX2_P<br />
PCIE_TX2_N<br />
PCIE_TX3_P<br />
PCIE_TX3_N<br />
V23<br />
V22<br />
P23<br />
P22<br />
K23<br />
K22<br />
F23<br />
F22<br />
PCIE_TBT_T_D2R_C_P<br />
PCIE_TBT_T_D2R_C_N<br />
PCIE_TBT_T_D2R_C_P<br />
PCIE_TBT_T_D2R_C_N<br />
NC_PCIE_TBT_T_D2R_C_P<br />
NC_PCIE_TBT_T_D2R_C_N<br />
NC_PCIE_TBT_T_D2R_C_P<br />
NC_PCIE_TBT_T_D2R_C_N<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
94<br />
94<br />
94<br />
94<br />
94<br />
94<br />
94<br />
94<br />
D<br />
4<br />
9<br />
C<br />
B<br />
A<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
BI<br />
BI<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
BI<br />
BI<br />
100K<br />
100K<br />
DP_T_SNK0_ML_C_P<br />
DP_T_SNK0_ML_C_N<br />
DP_T_SNK0_ML_C_P<br />
DP_T_SNK0_ML_C_N<br />
DP_T_SNK0_ML_C_P<br />
DP_T_SNK0_ML_C_N<br />
DP_T_SNK0_ML_C_P<br />
DP_T_SNK0_ML_C_N<br />
DP_T_SNK0_AUXCH_C_P<br />
DP_T_SNK0_AUXCH_C_N<br />
DP_T_SNK1_ML_C_P<br />
DP_T_SNK1_ML_C_N<br />
DP_T_SNK1_ML_C_P<br />
DP_T_SNK1_ML_C_N<br />
DP_T_SNK1_ML_C_P<br />
DP_T_SNK1_ML_C_N<br />
DP_T_SNK1_ML_C_P<br />
DP_T_SNK1_ML_C_N<br />
DP_T_SNK1_AUXCH_C_P<br />
DP_T_SNK1_AUXCH_C_N<br />
RB062<br />
1 2<br />
5% 1/20W MF 201<br />
RB072<br />
1 2<br />
5% 1/20W MF 201<br />
1M<br />
1 2<br />
5%<br />
1M<br />
1 2<br />
5% 1/20W MF 201<br />
1M<br />
1 2<br />
5%<br />
1M<br />
1 2<br />
5%<br />
RB060<br />
1/20W MF 201<br />
RB061<br />
RB070<br />
1/20W<br />
MF<br />
RB071<br />
1/20W MF<br />
201<br />
201<br />
DP_TA_HPD<br />
DP_TB_HPD<br />
TBT_TA_LSTX<br />
TBT_TA_LSRX<br />
TBT_TB_LSTX<br />
TBT_TB_LSRX<br />
SNK0 AC Coupling<br />
CB020 1 2<br />
0.1UF<br />
CB021 1 2<br />
0.1UF<br />
CB022 1 2<br />
0.1UF<br />
CB023 1 2<br />
0.1UF<br />
CB024 1 2<br />
0.1UF<br />
CB025 1 2<br />
0.1UF<br />
CB026 1 2<br />
0.1UF<br />
CB027 1 2<br />
0.1UF<br />
CB028 1 2<br />
0.1UF<br />
CB029 1 2<br />
0.1UF<br />
10% 16V 0201<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
SNK1 AC Coupling<br />
CB030 1 2<br />
0.1UF<br />
CB031 1 2<br />
0.1UF<br />
CB032 1 2<br />
0.1UF<br />
CB033 1 2<br />
0.1UF<br />
CB034 1 2<br />
0.1UF<br />
CB035 1 2<br />
0.1UF<br />
CB036 1 2<br />
0.1UF<br />
CB037 1 2<br />
0.1UF<br />
CB038 1 2<br />
0.1UF<br />
CB039 1 2<br />
92<br />
92<br />
92<br />
92<br />
0.1UF<br />
95<br />
95<br />
96<br />
96<br />
92<br />
92<br />
94<br />
96<br />
95<br />
DP_T_SNK0_ML_P<br />
DP_T_SNK0_ML_N<br />
0201<br />
10% 16V 0201<br />
X5R-CERM<br />
10% 16V 0201<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
DP_T_SNK0_ML_P<br />
DP_T_SNK0_ML_N<br />
DP_T_SNK0_ML_P<br />
0201<br />
DP_T_SNK0_ML_N<br />
0201<br />
10% 16V 0201<br />
X5R-CERM<br />
10% 16V 0201<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
DP_T_SNK0_ML_P<br />
DP_T_SNK0_ML_N<br />
DP_T_SNK0_AUXCH_P<br />
0201<br />
DP_T_SNK0_AUXCH_N<br />
0201<br />
DP_T_SNK1_ML_P<br />
0201<br />
DP_T_SNK1_ML_N<br />
0201<br />
10% 16V 0201<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
DP_T_SNK1_ML_P<br />
DP_T_SNK1_ML_N<br />
0201<br />
10% 16V 0201<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
10% 16V<br />
X5R-CERM<br />
DP_T_SNK1_ML_P<br />
DP_T_SNK1_ML_N<br />
0201<br />
DP_T_SNK1_ML_P<br />
0201<br />
DP_T_SNK1_ML_N<br />
0201<br />
DP_T_SNK1_AUXCH_P<br />
0201<br />
10% 16V 0201<br />
X5R-CERM<br />
DP_T_SNK1_AUXCH_N<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
95<br />
95<br />
BI<br />
BI<br />
PLACE_NEAR=UB000.H6:2MM<br />
PLACE_NEAR=UB000.J6:2MM<br />
GND_VOID=TRUE<br />
DP_TA_AUXCH_P<br />
DP_TA_AUXCH_N<br />
94 34<br />
GND_VOID=TRUE<br />
2<br />
0201 16V 10%<br />
X5R-CERM<br />
10K PU ON CLOCKS PAGE<br />
94 34<br />
OUT<br />
RB031 1<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
TF<br />
OUT<br />
1 2<br />
1/20W 4.75K<br />
0.5%<br />
0201<br />
RB055<br />
2 1<br />
0201 16V 10%<br />
X5R-CERM 0.1UF<br />
PLACE_NEAR=UB000.H19:2MM<br />
RB030 1<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201 2<br />
1<br />
RB054 1<br />
499<br />
2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
CB010<br />
CB011<br />
0.1UF<br />
2<br />
14K<br />
105 15<br />
105 15<br />
19<br />
RB050<br />
94<br />
94<br />
94<br />
94<br />
PCIE_CLK100M_TBT_T_P<br />
PCIE_CLK100M_TBT_T_N<br />
TBT_T_CLKREQ_L<br />
94 28 26<br />
DP_T_SNK0_ML_P<br />
DP_T_SNK0_ML_N<br />
DP_T_SNK0_ML_P<br />
DP_T_SNK0_ML_N<br />
DP_T_SNK0_ML_P<br />
DP_T_SNK0_ML_N<br />
DP_T_SNK0_ML_P<br />
DP_T_SNK0_ML_N<br />
DP_T_SNK0_AUXCH_P<br />
DP_T_SNK0_AUXCH_N<br />
DP_T_SNK0_HPD<br />
DP_T_SNK0_DDC_CLK<br />
DP_T_SNK0_DDC_DATA<br />
DP_T_SNK1_ML_P<br />
DP_T_SNK1_ML_N<br />
DP_T_SNK1_ML_P<br />
DP_T_SNK1_ML_N<br />
DP_T_SNK1_ML_P<br />
DP_T_SNK1_ML_N<br />
DP_T_SNK1_ML_P<br />
DP_T_SNK1_ML_N<br />
DP_T_SNK1_AUXCH_P<br />
DP_T_SNK1_AUXCH_N<br />
DP_T_SNK1_HPD<br />
DP_T_SNK1_DDC_CLK<br />
DP_T_SNK1_DDC_DATA<br />
94 26<br />
94 28<br />
94 26<br />
DP_T_SNK_RBIAS<br />
JTAG_TBT_TDI<br />
JTAG_TBT_T_TMS<br />
JTAG_TBT_TCK<br />
JTAG_ISP_TDO<br />
USBC_TA_D2R_P<br />
USBC_TA_D2R_N<br />
USBC_TA_R2D_C_P<br />
USBC_TA_R2D_C_N<br />
USBC_TA_R2D_C_P<br />
USBC_TA_R2D_C_N<br />
USBC_TA_D2R_P<br />
USBC_TA_D2R_N<br />
DP_TA_AUXCH_C_P<br />
DP_TA_AUXCH_C_N<br />
USB_UPC_TA_P<br />
USB_UPC_TA_N<br />
95 92 TBT_TA_LSTX<br />
OUT<br />
95 92 TBT_TA_LSRX<br />
IN<br />
95 94 92 DP_TA_HPD<br />
IN<br />
TBT_TA_USB2_RBIAS<br />
RIO_TBTTHMSNS_D1_P<br />
USE NEAREST GND BALL<br />
(AC22) FOR THERM_D_N<br />
TBT_T_RBIAS<br />
TBT_T_RSENSE<br />
V19<br />
T19<br />
AC5<br />
AB7<br />
AC7<br />
AB9<br />
AC9<br />
AB11<br />
AC11<br />
AB13<br />
AC13<br />
Y11<br />
W11<br />
AA2<br />
Y5<br />
R4<br />
AB15<br />
AC15<br />
AB17<br />
AC17<br />
AB19<br />
AC19<br />
AB21<br />
AC21<br />
Y12<br />
W12<br />
Y6<br />
Y8<br />
N4<br />
1<br />
Y18<br />
1% 201 MF<br />
1/20W<br />
PLACE_NEAR=UB000.Y18:2MM<br />
56<br />
97<br />
97<br />
97<br />
97<br />
97<br />
97<br />
97<br />
97<br />
94<br />
94<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
IN<br />
BI<br />
IN<br />
BI<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
BI<br />
BI<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
IN<br />
IN<br />
IN<br />
OUT<br />
Y4<br />
V4<br />
T4<br />
W4<br />
H6<br />
J6<br />
A15<br />
B15<br />
A17<br />
B17<br />
A19<br />
B19<br />
B21<br />
A21<br />
Y15<br />
W15<br />
E20<br />
D20<br />
A5<br />
A4<br />
M4<br />
H19<br />
AC23<br />
AB23<br />
V18<br />
AC1<br />
L15<br />
N15<br />
C23<br />
C22<br />
L4<br />
N16<br />
R2<br />
R1<br />
N2<br />
N1<br />
L2<br />
L1<br />
J2<br />
J1<br />
W19<br />
Y19<br />
G1<br />
N6<br />
U1<br />
U2<br />
V1<br />
V2<br />
W1<br />
W2<br />
Y1<br />
Y2<br />
AA1<br />
J4<br />
E2<br />
D4<br />
H4<br />
F2<br />
D2<br />
F1<br />
E1<br />
AB5<br />
F4<br />
D22<br />
D23<br />
AB3<br />
AC4<br />
AC3<br />
AB4<br />
B7<br />
A7<br />
A9<br />
B9<br />
A11<br />
B11<br />
A13<br />
B13<br />
Y16<br />
W16<br />
E19<br />
D19<br />
B4<br />
B5<br />
G2<br />
F19<br />
D6<br />
A23<br />
B23<br />
E18<br />
W13<br />
W18<br />
AB2<br />
TBT_T_PCI_RESET_L<br />
TBT_T_PCIE_BIAS<br />
NC_DP_T_SRC_ML_P<br />
NC_DP_T_SRC_ML_N<br />
NC_DP_T_SRC_ML_P<br />
NC_DP_T_SRC_ML_N<br />
NC_DP_T_SRC_ML_P<br />
NC_DP_T_SRC_ML_N<br />
NC_DP_T_SRC_ML_P<br />
NC_DP_T_SRC_ML_N<br />
NC_DP_T_SRC_AUX_P<br />
NC_DP_T_SRC_AUX_N<br />
DP_T_SRC_HPD<br />
DP_T_SRC_RBIAS<br />
I2C_TBT_T_SDA<br />
I2C_TBT_T_SCL<br />
TBT_T_ROM_WP_L<br />
92<br />
TBT_T_TMU_CLK_OUT<br />
SMC_PME_S4_DARK_L<br />
TBT_T_CIO_PLUG_EVENT_L<br />
DDI2_MUX_SEL<br />
DDI1_MUX_SEL<br />
TBT_T_TMU_CLK_IN<br />
I2C_TBT_TA_INT_L<br />
I2C_TBT_TB_INT_L<br />
TBT_T_USB_PWR_EN<br />
TBT_T_FORCE_PWR<br />
PM_BATLOW_L<br />
PM_SLP_S3_L<br />
TBT_T_CIO_PWR_EN<br />
TBT_T_TEST_EN<br />
TBT_T_TEST_PWR_GOOD<br />
USBC_T_RESET_L<br />
TBT_T_XTAL25M_IN<br />
TBT_T_XTAL25M_OUT<br />
UPC_T_SPI_MOSI 28 94<br />
UPC_T_SPI_MISO 28 94<br />
UPC_T_SPI_CS_L 28 94<br />
UPC_T_SPI_CLK 28<br />
94<br />
USBC_TB_D2R_P<br />
USBC_TB_D2R_N<br />
USBC_TB_R2D_C_P<br />
USBC_TB_R2D_C_N<br />
USBC_TB_R2D_C_P<br />
USBC_TB_R2D_C_N<br />
USBC_TB_D2R_P<br />
USBC_TB_D2R_N<br />
DP_TB_AUXCH_C_P<br />
DP_TB_AUXCH_C_N<br />
USB_UPC_TB_P<br />
USB_UPC_TB_N<br />
TBT_TB_LSTX<br />
TBT_TB_LSRX<br />
DP_TB_HPD<br />
TBT_TB_USB2_RBIAS<br />
499<br />
1%<br />
1/20W<br />
MF<br />
2 201<br />
BOM_COST_GROUP=TBT<br />
94<br />
94<br />
94<br />
94<br />
PLACE_NEAR=UB000.F19:2MM<br />
1<br />
RB053<br />
94<br />
92<br />
92<br />
92<br />
96<br />
96<br />
94<br />
94<br />
94<br />
94<br />
94<br />
94<br />
94<br />
94<br />
94<br />
94<br />
94<br />
98<br />
To SPI Flash<br />
96<br />
97<br />
97<br />
97<br />
97<br />
97<br />
97<br />
97<br />
97<br />
19<br />
94<br />
94<br />
26<br />
94<br />
34<br />
28<br />
94<br />
94<br />
14<br />
94<br />
95<br />
PLACE_NEAR=<br />
UB000.N6:2MM<br />
RB052<br />
1/20W MF 201<br />
1 2<br />
1% 14K<br />
34<br />
28<br />
95<br />
19<br />
96<br />
96<br />
PU at PCH<br />
26<br />
PU at PCH<br />
1<br />
RB029<br />
100<br />
5%<br />
48<br />
1/20W<br />
MF<br />
2<br />
201<br />
CB012 1 2<br />
0.1UF<br />
CB013 1<br />
0.1UF<br />
73<br />
3.01K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
74<br />
77<br />
SYNC_MASTER=J79_GREG<br />
PLACE_NEAR=UB000.N16:2MM<br />
RB051<br />
1 2<br />
PP3V3_S5_TBT_T_SW 92 98<br />
1<br />
RB036<br />
2.2K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
80<br />
104<br />
1<br />
RB025<br />
100<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
94<br />
GND_VOID=TRUE<br />
DP_TB_AUXCH_P<br />
10% 16V 0201<br />
X5R-CERM<br />
2<br />
10% X5R-CERM 16V 0201<br />
DP_TB_AUXCH_N<br />
GND_VOID=TRUE<br />
PP3V3_S5_TBT_T_SW 92 98<br />
1<br />
RB034<br />
2.2K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
1<br />
RB037<br />
2.2K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
94<br />
not used<br />
1<br />
RB027<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
1<br />
RB035<br />
2.2K<br />
5%<br />
1/20W<br />
MF<br />
2 201<br />
LAST_MODIFIED=Tue Aug 30 11:06:29 2016<br />
USB-C HIGH SPEED 1<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
NC<br />
PCIE_REFCLK_100_IN_P<br />
PCIE_REFCLK_100_IN_N<br />
PCIE_CLKREQ*<br />
DPSNK0_ML0_P<br />
DPSNK0_ML0_N<br />
DPSNK0_ML1_P<br />
DPSNK0_ML1_N<br />
DPSNK0_ML2_P<br />
DPSNK0_ML2_N<br />
DPSNK0_ML3_P<br />
DPSNK0_ML3_N<br />
DPSNK0_AUX_P<br />
DPSNK0_AUX_N<br />
DPSNK0_HPD<br />
DPSNK0_DDC_CLK<br />
DPSNK0_DDC_DATA<br />
DPSNK1_ML0_P<br />
DPSNK1_ML0_N<br />
DPSNK1_ML1_P<br />
DPSNK1_ML1_N<br />
DPSNK1_ML2_P<br />
DPSNK1_ML2_N<br />
DPSNK1_ML3_P<br />
DPSNK1_ML3_N<br />
DPSNK1_AUX_P<br />
DPSNK1_AUX_N<br />
DPSNK1_HPD<br />
DPSNK1_DDC_CLK<br />
DPSNK1_DDC_DATA<br />
DPSNK_RBIAS<br />
TDI<br />
TMS<br />
TCK<br />
TDO<br />
RBIAS<br />
RSENSE<br />
PA_RX1_P<br />
PA_RX1_N<br />
PA_TX1_P<br />
PA_TX1_N<br />
PA_TX0_P<br />
PA_TX0_N<br />
PA_RX0_P<br />
PA_RX0_N<br />
PA_DPSRC_AUX_P<br />
PA_DPSRC_AUX_N<br />
PA_USB2_D_P<br />
PA_USB2_D_N<br />
PA_LSTX<br />
PA_LSRX<br />
PA_DPSRC_HPD<br />
PA_USB2_RBIAS<br />
THERMDA<br />
THERMDA<br />
PCIE_ATEST<br />
TEST_EDM<br />
FUSE_VQPS_64<br />
FUSE_VQPS_128<br />
MONDC_CIO_0<br />
MONDC_CIO_1<br />
SINK PORT 0<br />
SINK PORT 1<br />
PORT A<br />
TBT PORTS<br />
DEBUG<br />
MISC<br />
SOURCE PORT 0<br />
PORT B POC GPIO LC GPIO<br />
PERST*<br />
PCIE_RBIAS<br />
DPSRC_ML0_P<br />
DPSRC_ML0_N<br />
DPSRC_ML1_P<br />
DPSRC_ML1_N<br />
DPSRC_ML2_P<br />
DPSRC_ML2_N<br />
DPSRC_ML3_P<br />
DPSRC_ML3_N<br />
DPSRC_AUX_P<br />
DPSRC_AUX_N<br />
DPSRC_HPD<br />
DPSRC_RBIAS<br />
GPIO_0<br />
GPIO_1<br />
GPIO_2<br />
GPIO_3<br />
GPIO_4<br />
GPIO_5<br />
GPIO_6<br />
GPIO_7<br />
GPIO_8<br />
POC_GPIO_0<br />
POC_GPIO_1<br />
POC_GPIO_2<br />
POC_GPIO_3<br />
POC_GPIO_4<br />
POC_GPIO_5<br />
POC_GPIO_6<br />
TEST_EN<br />
TEST_PWR_GOOD<br />
RESET*<br />
XTAL_25_IN<br />
XTAL_25_OUT<br />
EE_DI<br />
EE_DO<br />
EE_CS*<br />
EE_CLK<br />
PB_RX1_P<br />
PB_RX1_N<br />
PB_TX1_P<br />
PB_TX1_N<br />
PB_TX0_P<br />
PB_TX0_N<br />
PB_RX0_P<br />
PB_RX0_N<br />
PB_DPSRC_AUX_P<br />
PB_DPSRC_AUX_N<br />
PB_USB2_D_P<br />
PB_USB2_D_N<br />
PB_LSTX<br />
PB_LSRX<br />
PB_DPSRC_HPD<br />
PB_USB2_RBIAS<br />
MONDC_SVR<br />
ATEST_P<br />
ATEST_N<br />
USB2_ATEST<br />
MONDC_DPSNK_0<br />
MONDC_DPSNK_1<br />
MONDC_DPSRC<br />
NC<br />
NC<br />
NC<br />
BI<br />
BI<br />
OUT<br />
IN<br />
IN<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
BI<br />
OUT<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
DRAWING<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
IN<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
IN<br />
BI<br />
94<br />
BI<br />
BI<br />
96<br />
96<br />
BI<br />
94<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
SYNC_DATE=07/28/2015<br />
9.0.0<br />
dvt-fab09-0<br />
110 OF 145<br />
92 OF 119<br />
SIZE<br />
D<br />
C<br />
B<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
C<br />
B<br />
A<br />
1<br />
CB130<br />
1.0UF<br />
20%<br />
2<br />
6.3V<br />
X5R<br />
0201-1<br />
1<br />
2<br />
CB131<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
1<br />
1<br />
2<br />
CB145 1<br />
1.0UF<br />
20%<br />
6.3V<br />
2<br />
X5R<br />
0201-1<br />
CB184<br />
1.0UF<br />
CB132<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
1<br />
2<br />
CB133<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
20%<br />
20%<br />
2<br />
6.3V<br />
X5R<br />
2<br />
6.3V<br />
X5R<br />
0201-1<br />
0201-1<br />
1<br />
2<br />
1<br />
CB164<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
CB185<br />
1.0UF<br />
CB146 1<br />
1.0UF<br />
20%<br />
6.3V<br />
2<br />
X5R<br />
0201-1<br />
1<br />
2<br />
SOURCED BY INTERNAL SWITCH<br />
1<br />
2<br />
CB147 1<br />
1.0UF<br />
20%<br />
6.3V<br />
2<br />
X5R<br />
0201-1<br />
CB134<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
CB165<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
SOURCED BY INTERNAL SWITCH<br />
SOURCED BY INTERNAL SWITCH<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
1<br />
2<br />
1<br />
2<br />
CB135<br />
CB166<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
1<br />
2<br />
CB136<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
PP0V9_TBT_T_DP<br />
SOURCED BY INTERNAL SWITCH<br />
1<br />
2<br />
1<br />
2<br />
SOURCED BY INTERNAL SWITCH<br />
CB120<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
94<br />
CB167<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
94<br />
94<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=0.9V<br />
PP0V9_TBT_T_PCIE<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=0.9V<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=0.9V<br />
PP0V9_TBT_T_USB<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=0.9V<br />
PP0V9_TBT_T_CIO<br />
PP3V3_TBT_T_ANA_PCIE<br />
PP3V3_TBT_T_ANA_USB2<br />
1<br />
2<br />
CB121<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
SOURCED BY<br />
INTERNAL SWITCH<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
L8<br />
L11<br />
L12<br />
M8<br />
T11<br />
T12<br />
L6<br />
M6<br />
V11<br />
V12<br />
V13<br />
M13<br />
M15<br />
M16<br />
L19<br />
N19<br />
L18<br />
M18<br />
N18<br />
R15<br />
R16<br />
R8<br />
R9<br />
R11<br />
R12<br />
L16<br />
J16<br />
A6<br />
A8<br />
A10<br />
A12<br />
A14<br />
A16<br />
A18<br />
A20<br />
A22<br />
B6<br />
B8<br />
B10<br />
B12<br />
B14<br />
B16<br />
B18<br />
B20<br />
B22<br />
D8<br />
D9<br />
D11<br />
D12<br />
D13<br />
D15<br />
D16<br />
D18<br />
E8<br />
E9<br />
E11<br />
E15<br />
E16<br />
E22<br />
E23<br />
F9<br />
F20<br />
F16<br />
G22<br />
G23<br />
H1<br />
H2<br />
H12<br />
H13<br />
H15<br />
H16<br />
H20<br />
J5<br />
J19<br />
J20<br />
J18<br />
J22<br />
J23<br />
K1<br />
K2<br />
L5<br />
L20<br />
L22<br />
L23<br />
M1<br />
M2<br />
M5<br />
M19<br />
M20<br />
N5<br />
N20<br />
N22<br />
N23<br />
P1<br />
P2<br />
R5<br />
R18<br />
R19<br />
R20<br />
R22<br />
VCC0P9_DP<br />
VCC0P9_DP<br />
VCC0P9_DP<br />
VCC0P9_DP<br />
VCC0P9_DP<br />
VCC0P9_DP<br />
VCC0P9_ANA_DPSRC<br />
VCC0P9_ANA_DPSRC<br />
VCC0P9_ANA_DPSNK<br />
VCC0P9_ANA_DPSNK<br />
VCC0P9_ANA_DPSNK<br />
VCC0P9_PCIE<br />
VCC0P9_PCIE<br />
VCC0P9_PCIE<br />
VCC0P9_ANA_PCIE_1<br />
VCC0P9_ANA_PCIE_1<br />
VCC0P9_ANA_PCIE_2<br />
VCC0P9_ANA_PCIE_2<br />
VCC0P9_ANA_PCIE_2<br />
VCC0P9_USB<br />
VCC0P9_USB<br />
VCC0P9_CIO<br />
VCC0P9_CIO<br />
VCC0P9_CIO<br />
VCC0P9_CIO<br />
VCC3P3_ANA_PCIE<br />
VCC3P3_ANA_USB2<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
UB000<br />
TBT-AR-4C-CNTRL<br />
SYM 2 OF 2<br />
FCBGA<br />
OMIT_TABLE<br />
CRITICAL<br />
GND VCC<br />
VCC3P3_LC<br />
VCC3P3_SX<br />
VCC3P3_S0<br />
VCC3P3A<br />
VCC3P3_SVR<br />
VCC3P3_SVR<br />
VCC3P3_SVR<br />
VCC0P9_SVR<br />
VCC0P9_SVR<br />
VCC0P9_SVR_ANA<br />
VCC0P9_SVR_ANA<br />
VCC0P9_SVR_ANA<br />
VCC0P9_SVR_ANA<br />
VCC0P9_SVR_ANA<br />
VCC0P9_SVR_ANA<br />
VCC0P9_SVR_SENSE<br />
SVR_IND<br />
SVR_IND<br />
SVR_IND<br />
SVR_VSS<br />
SVR_VSS<br />
SVR_VSS<br />
VCC0P9_LVR<br />
VCC0P9_LVR<br />
VCC0P9_LVR<br />
VCC0P9_LVR_SENSE<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS_ANA<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
VSS<br />
R6<br />
F8<br />
R13<br />
H9<br />
A2<br />
A3<br />
B3<br />
L9<br />
M9<br />
E12<br />
E13<br />
F11<br />
F12<br />
F13<br />
F15<br />
J9<br />
C1<br />
C2<br />
D1<br />
A1<br />
B1<br />
B2<br />
F18<br />
H18<br />
J11<br />
H11<br />
R23<br />
T1<br />
T2<br />
T5<br />
T20<br />
U23<br />
U22<br />
V5<br />
V6<br />
V8<br />
V9<br />
V15<br />
V16<br />
V20<br />
W5<br />
W6<br />
W8<br />
W9<br />
W20<br />
W22<br />
W23<br />
Y9<br />
Y13<br />
Y20<br />
AA22<br />
AA23<br />
AB6<br />
AB8<br />
AB10<br />
AB12<br />
AB14<br />
AB16<br />
AB18<br />
AB20<br />
AB22<br />
AC6<br />
AC8<br />
AC10<br />
AC12<br />
AC14<br />
AC16<br />
AC18<br />
AC20<br />
AC22<br />
D5<br />
E4<br />
E5<br />
E6<br />
F5<br />
F6<br />
H5<br />
H8<br />
J8<br />
J12<br />
J13<br />
J15<br />
L13<br />
M12<br />
N8<br />
N9<br />
N11<br />
N12<br />
N13<br />
T6<br />
T8<br />
T9<br />
T13<br />
T15<br />
T16<br />
T18<br />
AB1<br />
AC2<br />
M11<br />
PP3V3_TBT_T_LC<br />
PP3V3_S5_TBT_T_SW<br />
1<br />
2<br />
CB175<br />
10UF<br />
20%<br />
20%<br />
6.3V<br />
2<br />
6.3V<br />
CERM-X5R CERM-X5R<br />
0402-4<br />
0402-4<br />
BYPASS=UB000.A2:A1:3MM<br />
PP0V9_TBT_T_SVR<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=0.9V<br />
DIDT=TRUE<br />
SWITCH_NODE=TRUE<br />
VR0V9_IND_TBT_T<br />
PP0V9_TBT_T_LVR<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=0.9V<br />
CB192 1<br />
1.0UF<br />
2<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
1<br />
Add XW or alias on<br />
support page<br />
XW<br />
XWB100<br />
SM<br />
1 2<br />
CB191<br />
CB176<br />
10UF<br />
PLACE_NEAR=UB000.AC22:2MM<br />
NO_XNET_CONNECTION=1<br />
VOLTAGE=3.3V<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
SOURCED BY<br />
INTERNAL SWITCH<br />
PP3V3_TBT_T_F<br />
1<br />
1.0UF<br />
1.0UF<br />
20%<br />
20%<br />
6.3V<br />
2<br />
6.3V<br />
X5R<br />
X5R<br />
0201-1<br />
0201-1<br />
1<br />
2<br />
1210<br />
CB177<br />
10UF<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402-4<br />
LB150<br />
0.68UH-20%-6.1A-0.020OHM<br />
RIO_TBTTHMSNS_D1_N<br />
1<br />
2<br />
CB178<br />
10UF<br />
CB190 1 2<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402-4<br />
5%<br />
2<br />
25V<br />
NP0-C0G<br />
1 2 0201<br />
CB193 1<br />
1.0UF<br />
2<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
94<br />
CB154 1<br />
10UF<br />
2<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402-4<br />
2x 10uF outside BGA area<br />
P0V9_TBT_T_SVR_AGND<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=0V<br />
56<br />
1<br />
2<br />
1<br />
47UF<br />
20%<br />
6.3V<br />
CER-X5R<br />
0603<br />
CB117<br />
12PF<br />
CB150<br />
CB155 1<br />
10UF<br />
20%<br />
6.3V<br />
2<br />
CERM-X5R<br />
0402-4<br />
CB194 1<br />
47UF<br />
20%<br />
6.3V<br />
CER-X5R 2<br />
0603<br />
1<br />
2<br />
1<br />
2<br />
47UF<br />
20%<br />
6.3V<br />
CER-X5R<br />
0603<br />
CB195 1<br />
47UF<br />
20%<br />
6.3V<br />
2<br />
CER-X5R<br />
0603<br />
CB110<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
CB151<br />
1<br />
2<br />
CB111<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
BOM_COST_GROUP=TBT<br />
1<br />
2<br />
CB152<br />
47UF<br />
1 2<br />
20%<br />
6.3V<br />
CER-X5R<br />
0603<br />
0603<br />
LB190<br />
1.0UH-20%-2.1A-0.128OHM<br />
CRITICAL<br />
1<br />
2<br />
CB112<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
INTERNAL SWITCHING VR OUTPUT<br />
1<br />
2<br />
94 98<br />
FROM USB-C PORT<br />
CONTROLLER (UPC)<br />
CB181<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
PP3V3_TBT_T_S0 94 101<br />
1<br />
CB113<br />
1.0UF<br />
20%<br />
2<br />
6.3V<br />
X5R<br />
0201-1<br />
SYNC_MASTER=J79_GREG<br />
1<br />
2<br />
CB114<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
1<br />
2<br />
CB180<br />
0.1UF<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
ISOLATE GND OF SVR_IND CAPS<br />
AND GND OF VCC3P3_SVR CAPS<br />
FROM SYSTEM GND IN LAYOUT<br />
(SEE INTEL LAYOUT GUIDELINES)<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
1<br />
2<br />
CB115<br />
1.0UF<br />
20%<br />
6.3V<br />
X5R<br />
0201-1<br />
USB-C HIGH SPEED 2<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
OUT<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
94<br />
1<br />
SOURCED BY<br />
INTERNAL SWITCH<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
CB116<br />
1.0UF<br />
20%<br />
2<br />
6.3V<br />
X5R<br />
0201-1<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
SYNC_DATE=08/28/2015<br />
9.0.0<br />
dvt-fab09-0<br />
111 OF 145<br />
93 OF 119<br />
SIZE<br />
D<br />
D<br />
C<br />
B<br />
A
SYNC_MASTER=J79_GREG<br />
SYNC_DATE=07/05/2016<br />
D<br />
C<br />
B<br />
A<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
92<br />
TMU CLKs<br />
92 TBT_T_TMU_CLK_OUT<br />
MAKE_BASE=TRUE<br />
TBT_T_TMU_CLK_OUT<br />
92<br />
92<br />
92<br />
Ridge 0.9V SVR XW<br />
DP SRC OPTIONS<br />
IF DP SRC NOT USED<br />
96<br />
NC_DP_T_SRC_ML_P<br />
NC_DP_T_SRC_ML_P<br />
NC_DP_T_SRC_ML_P<br />
NC_DP_T_SRC_ML_P<br />
NC_DP_T_SRC_ML_N<br />
NC_DP_T_SRC_ML_N<br />
NC_DP_T_SRC_ML_N<br />
NC_DP_T_SRC_ML_N<br />
NC_DP_T_SRC_AUX_P<br />
NC_DP_T_SRC_AUX_N<br />
AR xtal<br />
92<br />
92<br />
94 92<br />
92 34<br />
92 34<br />
95 92<br />
95<br />
94<br />
93<br />
IN<br />
OUT<br />
RIDGE JTAG ISOLATION<br />
Ridge<br />
PWR ENs<br />
Ridge<br />
PDs<br />
93<br />
1<br />
2<br />
P0V9_TBT_T_SVR_AGND<br />
TBT_T_XTAL25M_OUT<br />
TBT_T_XTAL25M_IN<br />
T RIDGE DEBUG CONN<br />
TBT_T_CIO_PLUG_EVENT_L<br />
DP_T_SNK0_HPD<br />
DP_T_SNK1_HPD<br />
DP_TA_HPD<br />
TBT_POC_RESET<br />
PP3V3_TBT_T_LC<br />
92 26<br />
92 26<br />
1M<br />
5%<br />
1/20W<br />
MF<br />
201<br />
8<br />
NOSTUFF<br />
RB206<br />
JTAG_TBT_TCK<br />
JTAG_TBT_TDI<br />
USBC_DBG 505070-1220<br />
94 16<br />
94 16<br />
92 DP_T_SNK0_DDC_CLK<br />
MAKE_BASE=TRUE<br />
DP_T_SNK0_DDC_CLK<br />
DP_T_SNK0_DDC_DATA<br />
MAKE_BASE=TRUE<br />
DP_T_SNK0_DDC_DATA<br />
92<br />
DP_T_SNK1_DDC_CLK<br />
MAKE_BASE=TRUE<br />
DP_T_SNK1_DDC_CLK<br />
92<br />
RB246 1<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
TBT_T_CIO_PWR_EN<br />
TBT_T_USB_PWR_EN<br />
201<br />
RB225<br />
92 DP_T_SNK1_DDC_DATA<br />
MAKE_BASE=TRUE<br />
DP_T_SNK1_DDC_DATA<br />
DP_T_SRC_HPD<br />
NC_DP_T_SRC_ML_P<br />
NC_DP_T_SRC_ML_P<br />
NC_DP_T_SRC_ML_P<br />
NC_DP_T_SRC_ML_P<br />
NC_DP_T_SRC_ML_N<br />
NC_DP_T_SRC_ML_N<br />
NC_DP_T_SRC_ML_N<br />
NC_DP_T_SRC_ML_N<br />
NC_DP_T_SRC_AUX_P<br />
NC_DP_T_SRC_AUX_N<br />
JB201<br />
M-ST-SM<br />
13 14<br />
1 2<br />
3 4<br />
5 6<br />
7 8<br />
9 10<br />
11 12<br />
15 16<br />
MF<br />
15<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
25MHZ-25PPM-20PF-50OHM<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
201 MF 1/20W<br />
101<br />
19<br />
TBT_X_TMU_CLK_IN 26<br />
TBT_T_XTAL25M_OUT_R<br />
Place on bottom<br />
TBT_T_PCI_RESET_L 19 92<br />
USBC_T_RESET_L<br />
92 98<br />
PP3V3_S5_TBT_T_SW 93 98<br />
PP0V9_TBT_T_PCIE<br />
93<br />
PP0V9_TBT_T_USB<br />
93<br />
PP0V9_TBT_T_CIO<br />
16<br />
14<br />
MAKE_BASE=TRUE<br />
TBT_X_TMU_CLK_IN<br />
RB224 100K<br />
1 2<br />
5% 1/20W MF 201<br />
NO_XNET_CONNECTION=1<br />
TBT_DBG<br />
15<br />
RB243 1 2<br />
15<br />
RB244 1 2<br />
100K<br />
92<br />
RB207<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
1<br />
RB245<br />
1/20W<br />
201<br />
MF<br />
CRITICAL<br />
YB200<br />
2.00X1.60-SM<br />
PLACE_NEAR=UB000.V2:5mm<br />
PLACE_NEAR=U0500.J1:10mm<br />
TBT_DBG<br />
5%<br />
XWB200<br />
SHORT-L6-SM<br />
1 2<br />
5%<br />
13<br />
XDP_JTAG_ISP_TCK 17<br />
5<br />
5%<br />
1/20W<br />
MF<br />
201<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
1/20W MF 201<br />
XDP_JTAG_ISP_TDI 17<br />
5% 1/20W<br />
MF<br />
PLACE_NEAR=U0500.J2:10mm<br />
5%<br />
2<br />
2<br />
2 4<br />
1 3<br />
5%<br />
5%<br />
1<br />
1<br />
7<br />
100K<br />
100K<br />
201<br />
PP3V3_S0<br />
RB271<br />
RB272<br />
RB270 100K<br />
1 2<br />
1/20W<br />
RB240<br />
1M<br />
1 2<br />
RB267 100K<br />
1 2<br />
1/20W MF 201<br />
5% 1/20W MF 201<br />
MF<br />
1<br />
2<br />
5% 1/20W MF 201<br />
CB202<br />
20PF<br />
5%<br />
25V<br />
C0G<br />
0201<br />
0201<br />
2 C0G<br />
25V<br />
5%<br />
1<br />
20PF<br />
CB203<br />
201<br />
93<br />
RB268 100K<br />
1 2<br />
RB269 100K<br />
1 2<br />
ACE A/B RPD STRAPPING<br />
95<br />
95<br />
96<br />
96<br />
USBC_TA_CC2<br />
USBC_TB_CC1<br />
USBC_TB_CC2<br />
ACE FET DCIN Bypass Caps<br />
100<br />
30 29<br />
96 95<br />
PPDCIN_G3H<br />
ACE PDs<br />
95<br />
95<br />
96<br />
96<br />
95<br />
95<br />
99 94<br />
FUSES FOR UPC<br />
95<br />
96<br />
USBC_TA_CC1<br />
UPC_TA_DBG3<br />
UPC_TA_DBG4<br />
UPC_TB_DBG3<br />
UPC_TB_DBG4<br />
UPC_TA_DBG1<br />
UPC_TA_DBG2<br />
UPC_T_5V_EN<br />
94<br />
94<br />
94 92<br />
CB211 1 0.1UF<br />
2<br />
94<br />
94<br />
51 48 28<br />
94<br />
96 95<br />
95<br />
96<br />
94<br />
95<br />
96<br />
94<br />
10%<br />
35V<br />
CER-X5R<br />
0201<br />
PP20V_USBC_TA_VBUS<br />
PP20V_USBC_TB_VBUS<br />
I2C_TBT_TB_INT_L<br />
I2C_UPC_T_SCL2<br />
I2C_UPC_T_SDA2<br />
SMC_USBC_INT_L<br />
TBT_T_SPI_CLK_DBG<br />
UPC_TA_UART_TX<br />
T ACE-SMC I2C SERIES R'S<br />
I2C_UPC_T_SDA2<br />
I2C_UPC_T_SDA2<br />
MAKE_BASE=TRUE<br />
I2C_UPC_T_SDA2<br />
I2C_UPC_T_SCL2<br />
I2C_UPC_T_SCL2<br />
MAKE_BASE=TRUE<br />
I2C_UPC_T_SCL2<br />
6<br />
USB2 AR PDs<br />
T ACEs DEBUG CONN<br />
5%<br />
5%<br />
1/20W<br />
1/20W<br />
ACE Debug Support<br />
6AMP-32V-0.0095OHM<br />
1 2 PP20V_USBC_TA_VBUS_F<br />
6AMP-32V-0.0095OHM<br />
1 2 PP20V_USBC_TB_VBUS_F<br />
MF<br />
RB242 1<br />
33 2<br />
MF<br />
PLACE_NEAR=U5000:5mm<br />
33<br />
RB241 1 2<br />
201<br />
PLACE_NEAR=U5000:5mm<br />
201<br />
Place on bottom<br />
I2C_TBT_TA_INT_L<br />
I2C_TBT_T_SDA<br />
I2C_TBT_T_SCL<br />
TBT_T_CIO_PWR_EN<br />
TBT_T_USB_PWR_EN<br />
UPC_TA_UART_RX<br />
SMBUS_SMC_4_G3H_SDA 51<br />
SMBUS_SMC_4_G3H_SDA 51<br />
SMBUS_SMC_4_G3H_SCL 51<br />
SMBUS_SMC_4_G3H_SCL 51<br />
USB_UPC_TA_P<br />
USB_UPC_TA_N<br />
USB_UPC_TB_P<br />
USB_UPC_TB_N<br />
NONE<br />
95<br />
96<br />
92 94<br />
92 94<br />
92 94<br />
16 94<br />
16 94<br />
95 96<br />
RB220 1<br />
0 2<br />
5% 1/20W MF 201<br />
RB221 1<br />
0 2<br />
5% 1/20W MF 201<br />
5%<br />
RB222 1<br />
0 2<br />
1/20W MF<br />
RB223 1<br />
0 2<br />
5% 1/20W MF<br />
201<br />
201<br />
28<br />
101<br />
16<br />
95<br />
96<br />
13<br />
96<br />
96<br />
95<br />
96<br />
15<br />
95<br />
15<br />
95<br />
15<br />
96<br />
15<br />
96<br />
92<br />
95<br />
95<br />
96<br />
96<br />
96<br />
95<br />
96<br />
99<br />
93<br />
94<br />
94<br />
XDP_USB_EXTC_OC_L<br />
XDP_USB_EXTD_OC_L<br />
JTAG_TBT_T_TMS<br />
S3X_JTAG_TCK<br />
S3X_JTAG_TMS<br />
NC_USBC_TB_RESET_L<br />
USB_UPC_PCH_TA_N<br />
USB_UPC_PCH_TA_N<br />
USB_UPC_PCH_TA_P<br />
USB_UPC_PCH_TA_P<br />
USB_UPC_PCH_TB_N<br />
USB_UPC_PCH_TB_N<br />
USB_UPC_PCH_TB_P<br />
USB_UPC_PCH_TB_P<br />
PP3V3_UPC_TA_LDO<br />
PP3V3_UPC_TA_LDO<br />
PP3V3_UPC_TA_LDO<br />
PP3V3_UPC_TB_LDO<br />
PP3V3_UPC_TB_LDO<br />
PP20V_USBC_TA_VBUS<br />
PP20V_USBC_TB_VBUS<br />
PP5V_S4_T_USBC<br />
PP5V_S4_T_USBC<br />
PP5V_S4_T_USBC<br />
PP3V3_TBT_T_S0<br />
GND ALIASES<br />
POWER ALIASES<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
S3X_JTAG_TCK<br />
MAKE_BASE=TRUE<br />
S3X_JTAG_TMS<br />
MAKE_BASE=TRUE<br />
NC_USBC_TB_RESET_L 102<br />
MAKE_BASE=TRUE<br />
USB_UPC_PCH_TB_P<br />
MAKE_BASE=TRUE<br />
PP3V3_UPC_TB_LDO<br />
MAKE_BASE=TRUE<br />
PP20V_USBC_TA_VBUS<br />
MAKE_BASE=TRUE<br />
PP20V_USBC_TB_VBUS<br />
MAKE_BASE=TRUE<br />
PP5V_S4_T_USBC<br />
MAKE_BASE=TRUE<br />
PP3V3_TBT_T_S0<br />
XDP_USB_EXTC_OC_L<br />
XDP_USB_EXTD_OC_L<br />
MAKE_BASE=TRUE<br />
JTAG_TBT_T_TMS<br />
MAKE_BASE=TRUE<br />
USB_UPC_PCH_TA_N<br />
MAKE_BASE=TRUE<br />
USB_UPC_PCH_TA_P<br />
MAKE_BASE=TRUE<br />
USB_UPC_PCH_TB_N<br />
MAKE_BASE=TRUE<br />
PP3V3_UPC_TA_LDO<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=5V<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
AR/ACE SPI BUS SERIES R'S<br />
MAKE_BASE=TRUE<br />
95 GND<br />
96 GND<br />
95 UPC_TA_DBG_UART_TX<br />
USBC_TA_CC1<br />
95 97 104<br />
OMIT<br />
96 GND<br />
95 GND<br />
MAKE_BASE=TRUE<br />
RB289 1 95 GND<br />
96 GND<br />
100<br />
TBT_T_SPI_CLK_DBG<br />
USBC_TA_CC2<br />
NOSTUFF<br />
96 GND<br />
GND<br />
RB290 1 2<br />
94<br />
95 97 104<br />
95<br />
5% 1/20W MF 201<br />
NONE<br />
96 GND<br />
96 GND<br />
TBT_T_SPI_CLK<br />
15<br />
MAKE_BASE=TRUE<br />
NONE<br />
92<br />
RB280 1 2 UPC_TA_SPI_CLK<br />
IN 95<br />
NONE<br />
5% 1/20W MF 201<br />
USBC_TB_CC1<br />
96 97 104<br />
402<br />
96 GND<br />
95 GND<br />
2<br />
TBT_T_SPI_CS_L<br />
15<br />
92<br />
96 GND<br />
RB281 1 2 UPC_TA_SPI_CS_L<br />
IN 95<br />
MAKE_BASE=TRUE<br />
5% 1/20W MF 201<br />
95 UPC_TA_DBG_UART_RX<br />
USBC_TB_CC2<br />
TBT_T_SPI_MOSI<br />
15<br />
96 97 104<br />
92<br />
RB282 1 2 UPC_TA_SPI_MOSI<br />
IN 95<br />
5% 1/20W MF 201<br />
UPC_TB_DBG_UART_TX<br />
NC/NO TEST<br />
TBT_T_SPI_MISO<br />
15<br />
96<br />
92<br />
RB283 1 2 UPC_TA_SPI_MISO<br />
OUT 95<br />
5% 1/20W MF 201<br />
OMIT<br />
15<br />
ROM<br />
RB284 UPC_T_SPI_CLK<br />
RB288 1 1 2<br />
IN 28 92<br />
5% 1/20W MF 201<br />
NO_TEST=1<br />
15<br />
NOSTUFF<br />
UPC_T_SPI_CS_L<br />
96 NC_UPC_TB_I2C_ADDR<br />
RB285 1 2<br />
IN 28 92<br />
IN<br />
5% 1/20W MF 201<br />
NONE<br />
15<br />
NONE<br />
UPC_T_SPI_MOSI<br />
CB212 1 CB213 1 CB214<br />
RB286 1 1 2<br />
IN 28 92<br />
402<br />
2<br />
5% 1/20W MF 201<br />
0.1UF 0.1UF 0.1UF<br />
15<br />
UPC_T_SPI_MISO<br />
10%<br />
10%<br />
10%<br />
35V<br />
35V<br />
35V<br />
UPC_TB_DBG_UART_RX<br />
RB287 1 2<br />
OUT 28 92<br />
96<br />
5% 1/20W MF 201<br />
CER-X5R 2 CER-X5R 2 CER-X5R 2<br />
0201<br />
0201<br />
0201<br />
SIGNAL ALIASES<br />
TBT to ACE<br />
RB260 1<br />
100K 2<br />
MAKE_BASE=TRUE<br />
5% 1/20W MF 201<br />
96 95 92 TBT_T_CIO_PWR_EN<br />
TBT_T_CIO_PWR_EN<br />
16 94<br />
RB261 MAKE_BASE=TRUE<br />
1<br />
100K 2<br />
TBT_T_USB_PWR_EN<br />
TBT<br />
Pri ACE<br />
5% 1/20W MF 201<br />
96 95 92<br />
TBT_T_USB_PWR_EN<br />
16 94<br />
MAKE_BASE=TRUE<br />
Alpine Ridge U2800<br />
U3100<br />
RB262 1<br />
100K 2<br />
92 PM_BATLOW_L<br />
PM_BATLOW_L<br />
14 28 48<br />
(MASTER)<br />
(Write: 0x70 Read: 0x71)<br />
5% 1/20W MF 201<br />
MAKE_BASE=TRUE<br />
RB263 100K<br />
95 UPC_T_5V_EN<br />
UPC_T_5V_EN<br />
94 99<br />
MAKE_BASE=TRUE92<br />
I2C_TBT_T_SCL<br />
I2C_TBT_T_SCL 95<br />
1 2 94<br />
5% 1/20W MF 201<br />
MAKE_BASE=TRUE92<br />
I2C_TBT_T_SDA<br />
I2C_TBT_T_SDA 95<br />
96 UPC_T_5V_EN<br />
94<br />
RB264 100K<br />
MAKE_BASE=TRUE92<br />
I2C_TBT_TA_INT_L<br />
I2C_TBT_TA_INT_L 95<br />
1 2<br />
MAKE_BASE=TRUE<br />
94<br />
5% 1/20W MF 201<br />
MAKE_BASE=TRUE92<br />
I2C_TBT_TB_INT_L<br />
92 28 26 JTAG_ISP_TDO<br />
JTAG_ISP_TDO<br />
5 28<br />
94<br />
RB265 100K<br />
MAKE_BASE=TRUE<br />
1 2<br />
5% 1/20W MF 201<br />
96 95 94 TBT_POC_RESET<br />
TBT_POC_RESET<br />
16 28<br />
MAKE_BASE=TRUE<br />
RB232 1<br />
100K 2<br />
TBT_T_CIO_PLUG_EVENT_L<br />
TBT_T_CIO_PLUG_EVENT_L<br />
5% 1/20W MF 201<br />
USBC_DBG<br />
0603<br />
FB201<br />
JB200<br />
505070-1220<br />
M-ST-SM<br />
13 14<br />
1 2<br />
3 4<br />
5 6<br />
7 8<br />
9 10<br />
11 12<br />
15 16<br />
0603 CRITICAL<br />
FB200<br />
92<br />
92<br />
92<br />
92<br />
<br />
5<br />
PLACE_NEAR=QB300:5MM<br />
CRITICAL<br />
PLACE_NEAR=QB400:5MM<br />
96<br />
97<br />
97<br />
95<br />
92<br />
5<br />
5<br />
28<br />
81<br />
81<br />
17<br />
17<br />
94<br />
92<br />
84<br />
84<br />
104<br />
104<br />
92<br />
92<br />
92<br />
92<br />
15<br />
15<br />
15<br />
15<br />
105<br />
105<br />
105<br />
105<br />
105<br />
105<br />
105<br />
105<br />
PCIE_TBT_T_D2R_C_P<br />
PCIE_TBT_T_D2R_C_N<br />
PCIE_TBT_T_D2R_C_P<br />
PCIE_TBT_T_D2R_C_N<br />
MAKE_BASE=TRUE<br />
NC_PCIE_TBT_T_D2R_C_P<br />
NO_TEST=1<br />
MAKE_BASE=TRUE<br />
NC_PCIE_TBT_T_D2R_C_N<br />
NO_TEST=1<br />
MAKE_BASE=TRUE<br />
NC_PCIE_TBT_T_D2R_C_P<br />
NO_TEST=1<br />
MAKE_BASE=TRUE<br />
NC_PCIE_TBT_T_D2R_C_N<br />
NO_TEST=1<br />
PCIE_TBT_T_R2D_C_P<br />
MAKE_BASE=TRUE<br />
NC_PCIE_TBT_T_R2D_P<br />
NO_TEST=1<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
MAKE_BASE=TRUE<br />
NC_PCIE_TBT_T_R2D_P<br />
NO_TEST=1<br />
MAKE_BASE=TRUE<br />
NC_PCIE_TBT_T_R2D_N<br />
NO_TEST=1<br />
Ridge PCIE Caps<br />
D2R<br />
R2D<br />
PCIE_TBT_T_R2D_C_N<br />
2 1<br />
0201 X5R 6.3V 20% 0.22UF<br />
GND_VOID=TRUE<br />
PCIE_TBT_T_R2D_C_P<br />
2 1<br />
0201 X5R 6.3V 20% 0.22UF<br />
PCIE_TBT_T_R2D_C_N<br />
2 1<br />
0201 X5R 6.3V 20% 0.22UF<br />
NC_PCIE_TBT_T_R2D_N<br />
BOM_COST_GROUP=TBT<br />
0201<br />
0201<br />
0201<br />
2<br />
X5R 6.3V 20%<br />
X5R<br />
6.3V<br />
X5R 6.3V<br />
2<br />
20%<br />
2<br />
20%<br />
2<br />
0201 X5R 6.3V 20%<br />
GND_VOID=TRUE<br />
1<br />
1<br />
1<br />
1<br />
CB250<br />
0.22UF<br />
CB251<br />
0.22UF<br />
CB252<br />
0.22UF<br />
CB253<br />
0.22UF<br />
GND_VOID=TRUE<br />
2 1<br />
0201 X5R 6.3V 20% 0.22UF<br />
GND_VOID=TRUE<br />
CB240<br />
CB241<br />
CB242<br />
CB243<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
Sec ACE<br />
U3200<br />
(Write: 0x7E Read: 0x7F)<br />
I2C_TBT_T_SCL 96<br />
I2C_TBT_T_SDA 96<br />
I2C_TBT_TB_INT_L 96<br />
GND_VOID=TRUE<br />
PCIE_TBT_T_D2R_P<br />
GND_VOID=TRUE<br />
PCIE_TBT_T_D2R_N<br />
GND_VOID=TRUE<br />
PCIE_TBT_T_D2R_P<br />
GND_VOID=TRUE<br />
PCIE_TBT_T_D2R_N<br />
NC_PCIE_TBT_T_D2R_C_P 92<br />
NC_PCIE_TBT_T_D2R_C_N 92<br />
NC_PCIE_TBT_T_D2R_C_P 92<br />
NC_PCIE_TBT_T_D2R_C_N 92<br />
PCIE_TBT_T_R2D_P<br />
PCIE_TBT_T_R2D_N<br />
PCIE_TBT_T_R2D_P<br />
PCIE_TBT_T_R2D_N<br />
NC_PCIE_TBT_T_R2D_P 92<br />
NC_PCIE_TBT_T_R2D_N 92<br />
NC_PCIE_TBT_T_R2D_P 92<br />
NC_PCIE_TBT_T_R2D_N 92<br />
USB-C Support<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
4<br />
3<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
9.0.0<br />
Ace<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
051-00777<br />
AR<br />
dvt-fab09-0<br />
112 OF 145<br />
94 OF 119<br />
15<br />
15<br />
15<br />
15<br />
92<br />
92<br />
92<br />
92<br />
105<br />
105<br />
SIZE<br />
D<br />
D<br />
C<br />
B<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
PRIMARY ACE USB-C PORT CONTROLLER (UPC)<br />
D<br />
QB300<br />
FDPC4044<br />
PWR-CLIP-33<br />
D<br />
S2<br />
G2<br />
G1<br />
S1<br />
C<br />
B<br />
A<br />
PULL R3109 AND R3108 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES<br />
PULL R3109 AND R3108 DOWN TO GND FOR 2ND RIDGE'S ACES<br />
GND 94<br />
1M<br />
1 2<br />
5%<br />
1M<br />
1 2<br />
5%<br />
1M<br />
1 2<br />
5%<br />
RB309<br />
1/20W<br />
RB308<br />
1/20W<br />
RB305<br />
1/20W MF<br />
MF<br />
I2C_UPC_TA_DBG_CTL_SCL<br />
201<br />
I2C_UPC_TA_DBG_CTL_SDA<br />
MF 201<br />
201<br />
UPC_TA_UART_RX<br />
94<br />
94<br />
BI<br />
BI<br />
95<br />
95<br />
94<br />
USB_UPC_PCH_TA_P<br />
USB_UPC_PCH_TA_N<br />
94<br />
95<br />
96<br />
PP3V3_UPC_TA_LDO<br />
PU to PP3V3_S4 if convenient<br />
for layout.<br />
Otherwise PU to PP3V3_UPC_TA_LDO<br />
1<br />
CAP FOR PP_5V0 ON VR PAGE<br />
LB300<br />
90-OHM-0.1A<br />
EXCX4CE<br />
SYM_VER-1<br />
2 3<br />
NO_XNET_CONNECTION=1<br />
92<br />
92<br />
NO_XNET_CONNECTION=1<br />
TESTPOINTS MUST BE<br />
PRESENT FOR GPIO0, GPIO1<br />
(EVEN IN PRODUCTION)<br />
NEED 0.1%<br />
REAR PORT:<br />
CONNECT UPC SPI TO ROM<br />
FRONT PORT:<br />
GROUND UPC SPI<br />
BI<br />
BI<br />
4<br />
96<br />
30<br />
29<br />
CRITICAL<br />
RB303 1<br />
15K<br />
0.1%<br />
1/20W<br />
TF-LF<br />
0201<br />
2<br />
TO SMC<br />
PLACE_NEAR=UB300.L5:5mm<br />
PLACE_NEAR=UB300.K5:5mm<br />
1<br />
RB310<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
1<br />
RB311<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
94<br />
28<br />
94<br />
100<br />
PP20V_USBC_TA_VBUS<br />
PP3V3_UPC_TA_LDO<br />
PP3V3_G3H<br />
GND<br />
PP5V_S4_T_USBC<br />
94<br />
GND I2C_ADDR<br />
PRIMARY ONLY<br />
TBT_POC_RESET<br />
USBC_T_RESET_L_R<br />
UPC_TA_DBG_UART_TX<br />
UPC_TA_DBG_UART_RX<br />
TBT_T_CIO_PWR_EN<br />
TBT_T_USB_PWR_EN<br />
DP_TA_HPD<br />
GND<br />
UPC_T_5V_EN<br />
SMC_PME_S4_DARK_L<br />
XDP_USB_EXTC_OC_L<br />
GND<br />
I2C_TBT_T_SDA<br />
I2C_TBT_T_SCL<br />
I2C_TBT_TA_INT_L<br />
I2C_UPC_T_SDA2<br />
I2C_UPC_T_SCL2<br />
SMC_USBC_INT_L<br />
FUSE<br />
Add on<br />
support page<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=20V<br />
PRIMARY ONLY<br />
PRIMARY ONLY<br />
GND 94<br />
PIN D6 IS UNDOCUMENTED RESET<br />
CAN GROUND PIN D6 IN PRODUCTION<br />
USBC_TA_CC1<br />
USBC_TA_CC2<br />
GROUND<br />
NC or GND to dissipate heat<br />
PPDCIN_G3H 29 30 94 96 100<br />
MAX 100uF TOTAL ON RAIL<br />
P3V3_TBT_T_SX_EN_R 98<br />
MIN_LINE_WIDTH=0.0900<br />
94 MIN_LINE_WIDTH=0.0900<br />
PP1V1_UPC_TA_LDO_BMC<br />
MIN_NECK_WIDTH=0.0520<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.8V<br />
VOLTAGE=1.8V<br />
96 94<br />
98<br />
94<br />
94<br />
96 94 92<br />
96 94 92<br />
94 92<br />
94<br />
96 30 29 28<br />
94<br />
94<br />
94<br />
94<br />
94<br />
94<br />
94<br />
51<br />
94<br />
94<br />
94<br />
94<br />
96 95 94<br />
96 94<br />
92<br />
92<br />
94<br />
94<br />
94<br />
94<br />
IN<br />
OUT<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
BI<br />
BI<br />
OUT<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
OUT<br />
IN<br />
OUT<br />
IN<br />
OUT<br />
BI<br />
BI<br />
BI<br />
BI<br />
95<br />
95<br />
GND<br />
UPC_TA_R_OSC<br />
I2C_UPC_TA_DBG_CTL_SCL<br />
I2C_UPC_TA_DBG_CTL_SDA<br />
UPC_TA_SPI_CLK<br />
UPC_TA_SPI_MOSI<br />
UPC_TA_SPI_MISO<br />
UPC_TA_SPI_CS_L<br />
TP_UPC_TA_SWD_DATA<br />
TP_UPC_TA_SWD_CLK<br />
UPC_TA_UART_RX<br />
UPC_TA_UART_TX<br />
TBT_TA_LSTX<br />
TBT_TA_LSRX<br />
USB_UPC_TA_F_P<br />
USB_UPC_TA_F_N<br />
DP_TA_AUXCH_P<br />
DP_TA_AUXCH_N<br />
UPC_TA_DBG1<br />
UPC_TA_DBG2<br />
UPC_TA_DBG3<br />
UPC_TA_DBG4<br />
1<br />
2<br />
CB300<br />
10UF<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402-1<br />
E11<br />
F11<br />
B2<br />
C2<br />
D10<br />
G11<br />
C10<br />
E10<br />
G10<br />
D7<br />
H6<br />
F10<br />
F1<br />
G2<br />
E4<br />
D5<br />
D1<br />
D2<br />
C1<br />
A5<br />
B5<br />
B6<br />
A3<br />
B4<br />
A4<br />
B3<br />
F4<br />
G4<br />
F2<br />
E2<br />
L4<br />
K4<br />
L5<br />
K5<br />
J1<br />
J2<br />
L2<br />
K2<br />
L3<br />
K3<br />
94<br />
MRESET<br />
RESET*<br />
GPIO0<br />
GPIO1<br />
GPIO2<br />
GPIO3<br />
GPIO4<br />
GPIO5<br />
GPIO6<br />
GPIO7<br />
GPIO8<br />
BUSPOWERZ<br />
I2C_ADDR<br />
R_OSC<br />
DEBUG_CTL1<br />
DEBUG_CTL2<br />
I2C_SDA1<br />
I2C_SCL1<br />
I2C_IRQ1*<br />
I2C_SDA2<br />
I2C_SCL2<br />
I2C_IRQ2*<br />
SPI_CLK<br />
SPI_MOSI<br />
SPI_MISO<br />
SPI_SSZ<br />
SWD_DATA<br />
SWD_CLK<br />
UART_RX<br />
UART_TX<br />
LSX_R2P<br />
LSX_P2R<br />
USB_RP_P<br />
USB_RP_N<br />
AUX_P<br />
AUX_N<br />
DEBUG1<br />
DEBUG2<br />
DEBUG3<br />
DEBUG4<br />
PP20V_USBC_TA_VBUS_F<br />
A11<br />
B11<br />
C11<br />
D11<br />
PP_5V0<br />
PP_5V0<br />
PP_5V0<br />
PP_5V0<br />
1<br />
CB301<br />
1UF<br />
10%<br />
2<br />
35V<br />
X5R<br />
0402<br />
A6<br />
A7<br />
A8<br />
B7<br />
PP_HV<br />
PP_HV<br />
PP_HV<br />
PP_HV<br />
H10<br />
H11<br />
J10<br />
J11<br />
K11<br />
UB300<br />
CD3215A<br />
BGA<br />
CRITICAL<br />
OMIT_TABLE<br />
K1<br />
A2<br />
A1<br />
D6<br />
E5<br />
E6<br />
E7<br />
F5<br />
G5<br />
H4<br />
H5<br />
G8<br />
H8<br />
L1<br />
B8<br />
D8<br />
E8<br />
F6<br />
F7<br />
F8<br />
G6<br />
G7<br />
5<br />
4<br />
H1<br />
B1<br />
3<br />
2<br />
G1<br />
H2<br />
1<br />
UPC_TA_GATE1<br />
UPC_TA_GATE2<br />
E1<br />
8<br />
H7<br />
B10<br />
A10<br />
B9<br />
A9<br />
L9<br />
L10<br />
K9<br />
K10<br />
K6<br />
L6<br />
K7<br />
L7<br />
K8<br />
L8<br />
L11<br />
USBC_TA_CC1<br />
USBC_TA_CC2<br />
USBC_TA_SBU1<br />
USBC_TA_SBU2<br />
UPC_TA_SS<br />
USBC_TA_USB_TOP_P<br />
USBC_TA_USB_TOP_N<br />
USBC_TA_USB_BOT_P<br />
USBC_TA_USB_BOT_N<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.1V<br />
1<br />
2<br />
PP1V8_UPC_TA_LDOD<br />
CB309<br />
0.47UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
94<br />
94<br />
97<br />
97<br />
97<br />
97<br />
97<br />
97<br />
PP1V8_UPC_TA_LDOA<br />
CB304<br />
2.2UF<br />
BOM_COST_GROUP=USB-C<br />
1<br />
20%<br />
2<br />
4V<br />
X5R-CERM<br />
0201<br />
CB314<br />
1<br />
220PF<br />
10%<br />
2<br />
16V<br />
CER-X7R<br />
0201<br />
1<br />
1<br />
2<br />
CB305<br />
1.0UF<br />
20%<br />
2<br />
6.3V<br />
X5R<br />
0201-1<br />
CB313<br />
220PF<br />
10%<br />
16V<br />
CER-X7R<br />
0201<br />
104 94 97<br />
104 94 97<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.2000<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.2000<br />
SYNC_MASTER=J79_GREG<br />
1<br />
2<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
PP3V3_UPC_TA_LDO<br />
CB306<br />
0.47UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
CB308<br />
10UF<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402-1<br />
USB-C PORT CONTROLLER A<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PP_CABLE<br />
VBUS<br />
VBUS<br />
VBUS<br />
VBUS<br />
PORT MUX DIGITAL CORE I/O AND CONTROL<br />
HV FET/SENSE<br />
TYPE-C<br />
VIN_3V3<br />
VDDIO<br />
NC NC<br />
LDO_3V3<br />
VOUT_3V3<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
LDO_1V8A<br />
LDO_1V8D<br />
GND<br />
GND<br />
LDO_BMC<br />
SS<br />
SENSEP<br />
SENSEN<br />
HV_GATE1<br />
HV_GATE2<br />
C_CC1<br />
C_CC2<br />
RPD_G1<br />
RPD_G2<br />
C_USB_TP<br />
C_USB_TN<br />
C_USB_BP<br />
C_USB_BN<br />
C_SBU1<br />
C_SBU2<br />
NC<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
1<br />
2<br />
94<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
113 OF 145<br />
95 OF 119<br />
SYNC_DATE=02/28/2016<br />
SIZE<br />
D<br />
C<br />
B<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
SECONDARY ACE USB-C PORT CONTROLLER (UPC)<br />
D<br />
QB400<br />
FDPC4044<br />
PWR-CLIP-33<br />
D<br />
S2<br />
G2<br />
G1<br />
S1<br />
94<br />
PP20V_USBC_TB_VBUS<br />
FUSE<br />
Add on<br />
support page<br />
94<br />
PP20V_USBC_TB_VBUS_F<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=20V<br />
1<br />
2<br />
CB401<br />
1UF<br />
10%<br />
35V<br />
X5R<br />
0402<br />
5<br />
4<br />
3<br />
2<br />
NC NC<br />
1<br />
8<br />
UPC_TB_GATE1<br />
UPC_TB_GATE2<br />
PPDCIN_G3H 29 30 94 95 100<br />
MAX 100uF TOTAL ON RAIL<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
PP3V3_UPC_TB_LDO<br />
94<br />
95<br />
30<br />
29<br />
94<br />
100<br />
28<br />
94<br />
PP3V3_UPC_TB_LDO<br />
PP3V3_G3H<br />
GND<br />
PP5V_S4_T_USBC<br />
CAP FOR PP_5V0 ON VR PAGE<br />
1<br />
2<br />
CB400<br />
10UF<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402-1<br />
A11<br />
B11<br />
C11<br />
D11<br />
PP_5V0<br />
PP_5V0<br />
PP_5V0<br />
PP_5V0<br />
A6<br />
A7<br />
A8<br />
B7<br />
PP_HV<br />
PP_HV<br />
PP_HV<br />
PP_HV<br />
H10<br />
PP_CABLE<br />
H11<br />
J10<br />
J11<br />
K11<br />
VBUS<br />
VBUS<br />
VBUS<br />
VBUS<br />
H1<br />
VIN_3V3<br />
B1<br />
VDDIO<br />
G1<br />
H2<br />
LDO_3V3<br />
VOUT_3V3<br />
K1<br />
A2<br />
LDO_1V8A<br />
LDO_1V8D<br />
E1<br />
LDO_BMC<br />
PP1V1_UPC_TB_LDO_BMC<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.1V<br />
PP1V8_UPC_TB_LDOD<br />
1<br />
2<br />
CB404<br />
2.2UF<br />
20%<br />
4V<br />
X5R-CERM<br />
0201<br />
P3V3_TBT_T_SX_EN_R 98<br />
PP1V8_UPC_TB_LDOA<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.8V<br />
1<br />
CB405<br />
1.0UF<br />
20%<br />
2<br />
6.3V<br />
X5R<br />
0201-1<br />
1<br />
2<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
CB406<br />
0.47UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
1<br />
2<br />
CB408<br />
10UF<br />
20%<br />
6.3V<br />
CERM-X5R<br />
0402-1<br />
C<br />
B<br />
PULL R3209 AND R3208 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES<br />
PULL R3209 AND R3208 DOWN TO GND FOR 2ND RIDGE'S ACES<br />
GND 94<br />
1M<br />
1 2<br />
5% 1/20W MF 201<br />
1M<br />
1 2<br />
5%<br />
1M<br />
1 2<br />
5%<br />
RB409<br />
RB408<br />
1/20W MF 201<br />
RB405<br />
1/20W MF 201<br />
I2C_UPC_TB_DBG_CTL_SCL<br />
I2C_UPC_TB_DBG_CTL_SDA<br />
UPC_TA_UART_TX<br />
94 BI<br />
94 BI<br />
96<br />
96<br />
94<br />
95<br />
96<br />
USB_UPC_PCH_TB_P<br />
USB_UPC_PCH_TB_N<br />
1<br />
LB400<br />
90-OHM-0.1A<br />
EXCX4CE<br />
SYM_VER-1<br />
2 3<br />
TESTPOINTS MUST BE<br />
PRESENT FOR GPIO0, GPIO1<br />
(EVEN IN PRODUCTION)<br />
REAR PORT:<br />
CONNECT UPC SPI TO ROM<br />
FRONT PORT:<br />
GROUND UPC SPI<br />
4<br />
CRITICAL<br />
RB403 1<br />
15K<br />
0.1%<br />
1/20W<br />
TF-LF<br />
0201<br />
2<br />
NEED 0.1%<br />
TO SMC<br />
PLACE_NEAR=UB400.L5:5mm<br />
PLACE_NEAR=UB400.K5:5mm<br />
95 94<br />
94<br />
95 94 92<br />
95 94 92<br />
IN<br />
OUT<br />
IN<br />
IN<br />
94<br />
94<br />
92<br />
94<br />
94<br />
95 30 29 28<br />
94<br />
94<br />
94<br />
94<br />
94<br />
94<br />
94<br />
96<br />
96<br />
94<br />
51<br />
94<br />
94<br />
94<br />
94<br />
96 95 94<br />
95 94<br />
92<br />
92<br />
TBT_POC_RESET<br />
NC_USBC_TB_RESET_L<br />
UPC_TB_DBG_UART_TX<br />
UPC_TB_DBG_UART_RX<br />
TBT_T_CIO_PWR_EN<br />
TBT_T_USB_PWR_EN<br />
DP_TB_HPD<br />
GND<br />
UPC_T_5V_EN<br />
SMC_PME_S4_DARK_L<br />
XDP_USB_EXTD_OC_L<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
GND<br />
NC_UPC_TB_I2C_ADDR<br />
UPC_TB_R_OSC<br />
I2C_UPC_TB_DBG_CTL_SCL<br />
I2C_UPC_TB_DBG_CTL_SDA<br />
BI<br />
BI<br />
OUT<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
OUT<br />
IN<br />
OUT<br />
IN<br />
OUT<br />
IN<br />
OUT<br />
I2C_TBT_T_SDA<br />
I2C_TBT_T_SCL<br />
I2C_TBT_TB_INT_L<br />
I2C_UPC_T_SDA2<br />
I2C_UPC_T_SCL2<br />
SMC_USBC_INT_L<br />
GND<br />
GND<br />
GND<br />
GND<br />
TP_UPC_TB_SWD_DATA<br />
TP_UPC_TB_SWD_CLK<br />
UPC_TA_UART_TX<br />
UPC_TA_UART_RX<br />
TBT_TB_LSTX<br />
TBT_TB_LSRX<br />
USB_UPC_TB_F_P<br />
USB_UPC_TB_F_N<br />
DP_TB_AUXCH_P<br />
DP_TB_AUXCH_N<br />
E11<br />
F11<br />
B2<br />
C2<br />
D10<br />
G11<br />
C10<br />
E10<br />
G10<br />
D7<br />
H6<br />
F10<br />
F1<br />
G2<br />
E4<br />
D5<br />
D1<br />
D2<br />
C1<br />
A5<br />
B5<br />
B6<br />
A3<br />
B4<br />
A4<br />
B3<br />
F4<br />
G4<br />
F2<br />
E2<br />
L4<br />
K4<br />
L5<br />
K5<br />
J1<br />
J2<br />
MRESET<br />
RESET*<br />
GPIO0<br />
GPIO1<br />
GPIO2<br />
GPIO3<br />
GPIO4<br />
GPIO5<br />
GPIO6<br />
GPIO7<br />
GPIO8<br />
BUSPOWERZ<br />
I2C_ADDR<br />
R_OSC<br />
DEBUG_CTL1<br />
DEBUG_CTL2<br />
I2C_SDA1<br />
I2C_SCL1<br />
I2C_IRQ1*<br />
I2C_SDA2<br />
I2C_SCL2<br />
I2C_IRQ2*<br />
SPI_CLK<br />
SPI_MOSI<br />
SPI_MISO<br />
SPI_SSZ<br />
SWD_DATA<br />
SWD_CLK<br />
UART_RX<br />
UART_TX<br />
LSX_R2P<br />
LSX_P2R<br />
USB_RP_P<br />
USB_RP_N<br />
AUX_P<br />
AUX_N<br />
UB400<br />
CD3215A<br />
BGA<br />
PORT MUX DIGITAL CORE I/O AND CONTROL<br />
HV FET/SENSE<br />
TYPE-C<br />
CRITICAL<br />
OMIT_TABLE<br />
SS<br />
SENSEP<br />
SENSEN<br />
HV_GATE1<br />
HV_GATE2<br />
C_CC1<br />
C_CC2<br />
RPD_G1<br />
RPD_G2<br />
C_USB_TP<br />
C_USB_TN<br />
C_USB_BP<br />
C_USB_BN<br />
C_SBU1<br />
C_SBU2<br />
NC<br />
H7<br />
B10<br />
A10<br />
B9<br />
A9<br />
L9<br />
L10<br />
K9<br />
K10<br />
K6<br />
L6<br />
K7<br />
L7<br />
K8<br />
L8<br />
L11<br />
USBC_TB_CC1<br />
USBC_TB_CC2<br />
UPC_TB_SS<br />
USBC_TB_CC1<br />
USBC_TB_CC2<br />
USBC_TB_USB_TOP_P<br />
USBC_TB_USB_TOP_N<br />
USBC_TB_USB_BOT_P<br />
USBC_TB_USB_BOT_N<br />
USBC_TB_SBU1<br />
USBC_TB_SBU2<br />
CB409<br />
0.47UF<br />
10%<br />
6.3V<br />
CERM-X5R<br />
0201<br />
GROUND<br />
NC or GND to dissipate heat<br />
1<br />
2<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
94<br />
94<br />
97<br />
97<br />
97<br />
97<br />
97<br />
97<br />
1<br />
2<br />
CB414<br />
220PF<br />
10%<br />
16V<br />
CER-X7R<br />
0201<br />
1<br />
2<br />
BI<br />
BI<br />
CB413<br />
220PF<br />
10%<br />
16V<br />
CER-X7R<br />
0201<br />
94 97<br />
94 97<br />
104<br />
104<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.2000<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.2000<br />
C<br />
B<br />
PU to PP3V3_S4 if convenient<br />
for layout.<br />
Otherwise PU to PP3V3_UPC_TB_LDO<br />
94<br />
PP3V3_UPC_TB_LDO<br />
NO_XNET_CONNECTION=1<br />
1<br />
RB410<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
94<br />
94<br />
94<br />
94<br />
BI<br />
BI<br />
BI<br />
BI<br />
S3X_JTAG_TCK<br />
S3X_JTAG_TMS<br />
UPC_TB_DBG3<br />
UPC_TB_DBG4<br />
L2<br />
K2<br />
L3<br />
K3<br />
DEBUG1<br />
DEBUG2<br />
DEBUG3<br />
DEBUG4<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
GND<br />
A<br />
92<br />
92<br />
BI<br />
BI<br />
NO_XNET_CONNECTION=1<br />
RB411 1<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
A1<br />
D6<br />
E5<br />
E6<br />
E7<br />
F5<br />
G5<br />
H4<br />
H5<br />
G8<br />
H8<br />
L1<br />
B8<br />
D8<br />
E8<br />
F6<br />
F7<br />
F8<br />
G6<br />
G7<br />
GND 94<br />
PIN D6 IS UNDOCUMENTED RESET<br />
CAN GROUND PIN D6 IN PRODUCTION<br />
BOM_COST_GROUP=USB-C<br />
SYNC_MASTER=J79_GREG<br />
USB-C PORT CONTROLLER B<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
114 OF 145<br />
96 OF 119<br />
SYNC_DATE=02/28/2016<br />
SIZE<br />
D<br />
A
SYNC_MASTER=J79_GREG<br />
SYNC_DATE=07/05/2016<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
94<br />
VOLTAGE=20V<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
PP20V_USBC_TB_VBUS<br />
CRITICAL<br />
DB570<br />
DSN2<br />
NSR20F40NX_G<br />
K<br />
A<br />
OMIT_TABLE<br />
CB554 1<br />
1UF<br />
2<br />
10%<br />
25V<br />
X5R<br />
402<br />
K<br />
A<br />
XWB550<br />
SM<br />
2 1<br />
1610<br />
ESDA25P35-1U1M<br />
DB502<br />
VOLTAGE=20V<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
PP20V_USBC_TB_VBUS_CONN<br />
BYPASS=JB500.58::2MM<br />
1<br />
2<br />
CRITICAL<br />
CB550<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
1<br />
CRITICAL<br />
CB551<br />
0.01UF<br />
10%<br />
2<br />
25V<br />
X5R-CERM<br />
0201<br />
PLACE VBUS CAP NEAR EACH VBUS PIN<br />
BYPASS=JB500.58::2MM<br />
BYPASS=JB500.58::2MM<br />
1<br />
CRITICAL<br />
CB552<br />
0.01UF<br />
10%<br />
2<br />
25V<br />
X5R-CERM<br />
0201<br />
1<br />
2<br />
CRITICAL<br />
CB553<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
1<br />
CRITICAL<br />
CB562<br />
0.01UF<br />
10%<br />
10%<br />
2<br />
25V<br />
X5R-CERM 2<br />
25V<br />
X5R-CERM<br />
0201<br />
0201<br />
1<br />
CRITICAL<br />
CB555<br />
0.01UF<br />
D<br />
C<br />
B<br />
CC1<br />
TBT_R2D0<br />
TBT_D2R0<br />
SBU2<br />
USB2 BOT<br />
USB2 BOT<br />
SBU1<br />
TBT_R2D1<br />
TBT_D2R1<br />
CC2<br />
94<br />
104 96 94<br />
92<br />
92<br />
92<br />
92<br />
96<br />
96<br />
96<br />
95<br />
95<br />
95<br />
92<br />
92<br />
92<br />
92<br />
104 95 94<br />
BI<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
BI<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
BI<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=20V<br />
CRITICAL<br />
USBC_TB_CC1<br />
USBC_TB_R2D_C_P<br />
USBC_TB_D2R_N<br />
USBC_TB_D2R_P<br />
USBC_TB_SBU2<br />
USBC_TB_USB_BOT_N<br />
USBC_TB_USB_BOT_P<br />
USBC_TA_USB_BOT_N<br />
USBC_TA_USB_BOT_P<br />
USBC_TA_SBU1<br />
USBC_TA_R2D_C_P<br />
USBC_TA_R2D_C_N<br />
USBC_TA_D2R_P<br />
USBC_TA_D2R_N<br />
USBC_TA_CC2<br />
PP20V_USBC_TA_VBUS<br />
DB500<br />
DSN2<br />
NSR20F40NX_G<br />
K<br />
A<br />
USBC_TB_R2D_C_N<br />
DZB501<br />
0201-THICKSTNCL<br />
5.5V-6.2PF<br />
OMIT_TABLE<br />
CB504 1<br />
1UF<br />
2<br />
10%<br />
25V<br />
X5R<br />
402<br />
GND_VOID=TRUE<br />
2<br />
1<br />
DB554<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
DB527<br />
ESD8011<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
X3DFN2-THICKSTNCL<br />
K<br />
A<br />
2<br />
1<br />
GND_VOID=TRUE<br />
2<br />
1<br />
2<br />
1<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
CB591<br />
1 2<br />
GND_VOID=TRUE<br />
CB590<br />
1 2<br />
DB549<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
CB573<br />
1 2<br />
GND_VOID=TRUE<br />
CB572<br />
1 2<br />
2<br />
1<br />
DB526<br />
XWB500<br />
SM<br />
2 1<br />
ESD8011<br />
1610<br />
ESDA25P35-1U1M<br />
DB501<br />
DZB550<br />
0201-THICKSTNCL<br />
5.5V-6.2PF<br />
X3DFN2-THICKSTNCL<br />
DB525<br />
GND_VOID=TRUE<br />
0.22UF<br />
10% 6.3V X5R-CERM<br />
2<br />
1<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
2<br />
1<br />
USBC_TA_R2D_P<br />
USBC_TA_R2D_N<br />
2<br />
1<br />
DB553<br />
DB524<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
ESD8011<br />
0201<br />
GND_VOID=TRUE<br />
0.22UF<br />
10% 6.3V X5R-CERM 0201<br />
GND_VOID=TRUE<br />
0.22UF<br />
10% 6.3V X5R-CERM<br />
GND_VOID=TRUE<br />
10%<br />
0.22UF<br />
0201<br />
6.3V X5R-CERM 0201<br />
X3DFN2-THICKSTNCL<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=20V<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
DZB503<br />
0201-THICKSTNCL<br />
5.5V-6.2PF<br />
PP20V_USBC_TA_VBUS_CONN<br />
2<br />
1<br />
2<br />
1<br />
2<br />
1<br />
USBC_TB_R2D_N<br />
USBC_TB_R2D_P<br />
DB552<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
DB512<br />
DB551<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
BYPASS=JB500.59::2MM<br />
1<br />
2<br />
1<br />
2<br />
CRITICAL<br />
CB500<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
CRITICAL<br />
CB506<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
2<br />
1<br />
2<br />
1<br />
2<br />
1<br />
2<br />
1<br />
DB528<br />
CRITICAL<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
BYPASS=JB500.59::2MM<br />
1<br />
2<br />
1<br />
2<br />
CB501<br />
CRITICAL<br />
CB507<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
DB550<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
DZB552<br />
0201-THICKSTNCL<br />
5.5V-6.2PF<br />
BYPASS=JB500.59::2MM<br />
PLACE VBUS CAP NEAR EACH VBUS PIN<br />
BYPASS=JB500.59::2MM BYPASS=JB500.59::2MM<br />
BYPASS=JB500.59::2MM<br />
BYPASS=JB500.59::2MM<br />
BYPASS=JB500.59::2MM<br />
1<br />
2<br />
1<br />
2<br />
CRITICAL<br />
CB502<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
CRITICAL<br />
CB508<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
2<br />
1<br />
1<br />
2<br />
1<br />
CRITICAL<br />
CB503<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
BYPASS=JB500.59::2MM<br />
CRITICAL<br />
CB509<br />
0.01UF<br />
10%<br />
2<br />
25V<br />
X5R-CERM<br />
0201<br />
BYPASS=JB500.59::2MM<br />
1<br />
CRITICAL<br />
CB512<br />
0.01UF<br />
10%<br />
2<br />
25V<br />
X5R-CERM<br />
0201<br />
1<br />
CRITICAL<br />
CB505<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
JB500<br />
20759-056E-02<br />
F-ST-SM<br />
57 58<br />
PWR<br />
1<br />
SIGNAL<br />
2<br />
3 4<br />
5 6<br />
7 8<br />
9 10<br />
11 12<br />
13 14<br />
15 16<br />
17 18<br />
19 20<br />
21 22<br />
23 24<br />
25 26<br />
27 28<br />
29 30<br />
31 32<br />
33 34<br />
35 36<br />
37 38<br />
39 40<br />
41 42<br />
43 44<br />
45 46<br />
47 48<br />
49 50<br />
51 52<br />
53 54<br />
55 56<br />
PWR<br />
59 60<br />
61<br />
GND<br />
62<br />
63 64<br />
65 66<br />
67 68<br />
69 70<br />
71 72<br />
73 74<br />
75 76<br />
77 78<br />
79 80<br />
81 82<br />
83 84<br />
85 86<br />
TP_USBC_PP20V_TB<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
TP_USBC_PP20V_TA<br />
DZB500<br />
0201-THICKSTNCL<br />
5.5V-6.2PF<br />
104<br />
DZB551<br />
0201-THICKSTNCL<br />
5.5V-6.2PF<br />
104<br />
2<br />
1<br />
DB521<br />
2<br />
1<br />
DB555<br />
ESD8011<br />
CB566<br />
3.0PF<br />
PP20V_USBC_TA_VBUS_CONN<br />
1<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
X3DFN2-THICKSTNCL<br />
2<br />
1<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
2<br />
1<br />
1<br />
2<br />
CRITICAL<br />
CB556<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
BYPASS=JB500.58::2MM<br />
1<br />
2<br />
CB560<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
2<br />
1<br />
DB520<br />
BYPASS=JB500.58::2MM<br />
2<br />
1<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
1<br />
+/-0.1PF<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
DB556<br />
DB504<br />
CRITICAL<br />
CB557<br />
0.01UF<br />
10%<br />
2<br />
25V<br />
X5R-CERM<br />
0201<br />
BYPASS=JB500.58::2MM<br />
USBC_TB_R2D_N<br />
USBC_TB_R2D_P<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
DB558<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
USBC_TA_R2D_P<br />
USBC_TA_R2D_N<br />
2<br />
1<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
2<br />
97 104<br />
OUT<br />
OUT<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
2<br />
1<br />
1<br />
2<br />
2<br />
1<br />
1<br />
2<br />
CRITICAL<br />
CB561<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
DB529<br />
CB558<br />
0.01UF<br />
10%<br />
25V<br />
X5R-CERM<br />
0201<br />
BYPASS=JB500.58::2MM<br />
BYPASS=JB500.58::2MM<br />
2<br />
ESD8011<br />
BYPASS=JB500.58::2MM<br />
1<br />
X3DFN2-THICKSTNCL<br />
1<br />
2<br />
DB560<br />
DB523<br />
1<br />
CB563<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
DB559<br />
1<br />
2<br />
GND_VOID=TRUE<br />
CB564<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
CB592<br />
1 2<br />
GND_VOID=TRUE<br />
CB593<br />
1 2<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
GND_VOID=TRUE<br />
CB570<br />
1 2<br />
GND_VOID=TRUE<br />
2<br />
1<br />
GND_VOID=TRUE<br />
GND_VOID=TRUE<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
CRITICAL<br />
CB559<br />
0.01UF<br />
10%<br />
2<br />
25V<br />
X5R-CERM<br />
0201<br />
CB571<br />
1 2<br />
2<br />
1<br />
2<br />
1<br />
2<br />
1<br />
DB522<br />
1<br />
2<br />
DB557<br />
ESD8011<br />
X3DFN2-THICKSTNCL<br />
BYPASS=JB500.58::2MM<br />
ESD8011<br />
CB565<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
GND_VOID=TRUE<br />
6.3V X5R-CERM<br />
GND_VOID=TRUE<br />
0.22UF<br />
10% 6.3V X5R-CERM<br />
10% 0.22UF<br />
X3DFN2-THICKSTNCL<br />
DZB553<br />
0201-THICKSTNCL<br />
5.5V-6.2PF<br />
0.22UF<br />
DZB502<br />
0201-THICKSTNCL<br />
5.5V-6.2PF<br />
2<br />
1<br />
2<br />
1<br />
GND_VOID=TRUE<br />
10% 6.3V X5R-CERM 0201<br />
GND_VOID=TRUE<br />
0.22UF<br />
10% 6.3V X5R-CERM 0201<br />
USBC_TB_CC2<br />
USBC_TB_R2D_C_N<br />
0201<br />
USBC_TB_R2D_C_P<br />
0201<br />
USBC_TB_USB_TOP_P<br />
USBC_TB_USB_TOP_N<br />
USBC_TB_D2R_N<br />
USBC_TB_D2R_P<br />
USBC_TB_SBU1<br />
USBC_TA_SBU2<br />
USBC_TA_R2D_C_P<br />
USBC_TA_R2D_C_N<br />
USBC_TA_USB_TOP_P<br />
USBC_TA_USB_TOP_N<br />
USBC_TA_D2R_P<br />
USBC_TA_D2R_N<br />
USBC_TA_CC1<br />
BI<br />
IN<br />
IN<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
IN<br />
IN<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
BI<br />
92<br />
92<br />
92<br />
92<br />
94<br />
96<br />
96<br />
96<br />
92<br />
92<br />
92<br />
92<br />
95<br />
95<br />
95<br />
96<br />
104 94 95<br />
104<br />
CC2<br />
TBT_R2D1<br />
USB2 TOP<br />
TBT_D2R1<br />
SBU1<br />
SBU2<br />
TBT_R2D0<br />
USB2 BOT<br />
TBT_D2R0<br />
CC1<br />
D<br />
C<br />
B<br />
1<br />
2<br />
CB510<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CB516<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CB511<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CB513<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CB514<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CB515<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
PART NUMBER QTY DESCRIPTION<br />
REFERENCE DES CRITICAL BOM OPTION<br />
138S0683 2 CAP,CER,X5R,1UF,10%,25V,0402<br />
CB504, CB554 CRITICAL<br />
NOSTUFF<br />
A<br />
BOM_COST_GROUP=USB-C<br />
LAST CHANGE: Wed Apr 1 22:57:37 2015<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
USB-C CONNECTOR A<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
115 OF 145<br />
97 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
D<br />
MAKE_BASE=TRUE<br />
P3V3_TBT_T_SX_EN_R<br />
TBT T "POC" Power-up Reset<br />
NOSTUFF<br />
0<br />
402<br />
1 2<br />
MF-LF<br />
RB600<br />
5%<br />
1/16W<br />
C<br />
95<br />
96<br />
IN<br />
IN<br />
P3V3_TBT_T_SX_EN_R<br />
P3V3_TBT_T_SX_EN_R<br />
1<br />
RB605<br />
100K<br />
5%<br />
1/20W<br />
MF<br />
2<br />
201<br />
RB601<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
95<br />
P3V3_TBT_T_SX_EN<br />
IN<br />
USBC_T_RESET_L_R<br />
1<br />
ON<br />
CRITICAL<br />
UB600<br />
SLG5AP1449V<br />
STDFN<br />
GND<br />
4<br />
2<br />
3<br />
1<br />
RB602<br />
100K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
D<br />
S<br />
MAKE_BASE=TRUE<br />
USBC_T_RESET_L_R<br />
TBTTPOCRST_SNS<br />
PP3V3_S5 101<br />
1<br />
3<br />
CRITICAL<br />
ENABLE<br />
SENSE<br />
6<br />
VCC<br />
UB601<br />
TPS3895ADRY<br />
USON<br />
SENSE_OUT<br />
MAKE_BASE=TRUE<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
PP3V3_S5_TBT_T_SW<br />
PP3V3_S5_TBT_T_SW 93 94<br />
PP3V3_S5_TBT_T_SW 92<br />
CT<br />
4<br />
5<br />
Output<br />
Delay<br />
Vth<br />
UB601<br />
Push-pull<br />
USBC_T_RESET_L<br />
TBTTPOCRST_CT<br />
440us +/- 20us<br />
2.508V nominal<br />
OUT<br />
92<br />
94<br />
C<br />
1<br />
RB603<br />
24.9K<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
GND<br />
2<br />
CB600 1<br />
100PF<br />
2<br />
5%<br />
25V<br />
C0G<br />
0201<br />
NOSTUFF<br />
RB604<br />
0<br />
1 2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
B<br />
B<br />
A<br />
BOM_COST_GROUP=USB-C<br />
DESIGN: j130/dev_mlb_u<br />
LAST CHANGE: Wed Apr 1 22:57:37 2015<br />
SYNC_MASTER=J79_GREG<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
USB-C CONNECTOR B<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
.<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
116 OF 145<br />
98 OF 119<br />
SYNC_DATE=03/24/2016<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
99<br />
94<br />
PP5V_S4_T_USBC<br />
101<br />
PP5V_S4<br />
100<br />
33<br />
PPBUS_G3H<br />
D<br />
XWB701<br />
SM<br />
P5VUSBC_T_RTN_DIV_R<br />
RB703 1<br />
27.4K<br />
0.1%<br />
1/20W<br />
MF<br />
0201<br />
2<br />
NO_XNET_CONNECTION=1<br />
2<br />
1<br />
2<br />
1<br />
SM XWB702<br />
P5VUSBC_T_SENSE_DIV_R<br />
1<br />
RB731<br />
27.4K<br />
0.1%<br />
1/20W<br />
MF<br />
2<br />
0201<br />
NO_XNET_CONNECTION=1<br />
1<br />
RB717<br />
191K<br />
0.1%<br />
1/20W<br />
MF<br />
2<br />
0201<br />
1<br />
2<br />
CB717<br />
22PF<br />
5%<br />
50V<br />
C0G<br />
0201<br />
PP5V_USBC_T_VCC<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=5V<br />
1<br />
2<br />
CB722<br />
2.2UF<br />
10%<br />
10V<br />
X6S-CERM<br />
0402<br />
94<br />
IN<br />
UPC_T_5V_EN<br />
102<br />
P5VUSBC_T_SENSE_DIV<br />
P5VUSBC_T_SREF<br />
P5VUSBC_T_VO<br />
P5VUSBC_T_OCSET<br />
NC_P5VUSBC_T_PGOOD<br />
P5VUSBC_T_RTN_DIV<br />
P5VUSBC_T_FSEL<br />
15<br />
10<br />
7<br />
12<br />
11<br />
14<br />
4<br />
13<br />
EN<br />
FB<br />
RB701 1<br />
2.2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
SREF<br />
VO<br />
OCSET<br />
PGOOD<br />
RTN<br />
FSEL<br />
19<br />
VCC<br />
20<br />
UB700<br />
ISL95870AH<br />
UTQFN<br />
CRITICAL<br />
1<br />
RB706<br />
2.2<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
PVCC<br />
VOLTAGE=5V<br />
PP5V_USBC_T_PVCC<br />
BOOT<br />
UGATE<br />
PHASE<br />
LGATE<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
18<br />
17<br />
16<br />
1<br />
1<br />
2<br />
CB721<br />
10UF<br />
20%<br />
10V<br />
X5R-CERM<br />
0402-7<br />
RB709 1<br />
2.2<br />
5%<br />
1/20W<br />
201<br />
MF<br />
2<br />
P5VUSBC_T_VBST<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
P5VUSBC_T_DRVH_R<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
GATE_NODE=TRUE<br />
DIDT=TRUE<br />
P5VUSBC_T_LL<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
SWITCH_NODE=TRUE<br />
DIDT=TRUE<br />
P5VUSBC_T_DRVL<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
GATE_NODE=TRUE<br />
DIDT=TRUE<br />
P5VUSBC_T_BOOT_RC<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
DIDT=TRUE<br />
1<br />
2<br />
CB716<br />
0.1UF<br />
10%<br />
16V<br />
X7R-CERM<br />
0402<br />
2<br />
RB739<br />
0<br />
1<br />
5%<br />
1/20W<br />
MF<br />
0201 P5VUSBC_T_DRVH<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
GATE_NODE=TRUE<br />
DIDT=TRUE<br />
1<br />
2<br />
3<br />
4<br />
CB704 1<br />
33UF<br />
2<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
HSG<br />
QB701<br />
FDPC1012S<br />
LLP<br />
SW<br />
CB703 1<br />
33UF<br />
2<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
V+<br />
V+<br />
LSG<br />
8<br />
9<br />
7<br />
CB702 1<br />
33UF<br />
2<br />
20%<br />
16V<br />
TANT-POLY<br />
CASE-B3<br />
LB700<br />
1.5UH-20%-12.5A-0.017OHM<br />
1 2<br />
PIMB062D-SM<br />
1<br />
2<br />
CB700<br />
2.2UF<br />
20%<br />
25V<br />
X5R-CERM<br />
0402-1<br />
P5VUSBC_T_R<br />
MIN_LINE_WIDTH=0.6000<br />
MIN_NECK_WIDTH=0.2000<br />
1<br />
2<br />
P5VUSBC_T_POS<br />
CB701<br />
2.2UF<br />
20%<br />
25V<br />
X5R-CERM<br />
0402-1<br />
CRITICAL<br />
2<br />
4<br />
RB730<br />
0.002<br />
1%<br />
1/2W<br />
MF<br />
0306<br />
1<br />
3<br />
CB705 1<br />
2.2UF<br />
2<br />
20%<br />
25V<br />
X5R-CERM<br />
0402-1<br />
CB706 1<br />
2.2UF<br />
20%<br />
25V<br />
2<br />
X5R-CERM<br />
0402-1<br />
1<br />
2.4G DESENSE<br />
1<br />
2<br />
CRITICAL<br />
CB710<br />
12PF<br />
5%<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
CB709<br />
150UF<br />
20%<br />
6.3V<br />
TANT-POLY<br />
CASE-B1S-1<br />
PP5V_S4_T_USBC 94 99<br />
5G DESENSE<br />
1<br />
2<br />
CRITICAL<br />
CB711<br />
1<br />
3.0PF<br />
+/-0.1PF<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
CB708<br />
150UF<br />
20%<br />
6.3V<br />
TANT-POLY<br />
CASE-B1S-1<br />
1<br />
2<br />
CB707<br />
150UF<br />
20%<br />
6.3V<br />
TANT-POLY<br />
CASE-B1S-1<br />
D<br />
C<br />
1<br />
2<br />
CB726<br />
10PF<br />
5%<br />
50V<br />
C0G<br />
0201<br />
1<br />
RB704<br />
10K<br />
2<br />
0.1%<br />
1/20W<br />
MF<br />
0201-1<br />
1<br />
RB702<br />
10K<br />
2<br />
0.1%<br />
1/20W<br />
MF<br />
0201-1<br />
1<br />
2<br />
CB723 1<br />
0.1UF<br />
2<br />
10%<br />
16V<br />
X5R-CERM<br />
0201<br />
CB715<br />
10PF<br />
5%<br />
50V<br />
C0G<br />
0201<br />
1<br />
RB718<br />
95.3K<br />
0.1%<br />
1/20W<br />
MF<br />
2<br />
0201<br />
P5VUSBC_T_SET_R<br />
RB700<br />
11K<br />
1 2<br />
1%<br />
1/20W<br />
MF<br />
201<br />
NOSTUFF<br />
RB713 1<br />
0<br />
5%<br />
1/20W<br />
MF<br />
201<br />
2<br />
P5VUSBC_T_SET0<br />
P5VUSBC_T_SET1<br />
8<br />
9<br />
6<br />
5<br />
SET0<br />
SET1<br />
VID0<br />
VID1<br />
3<br />
GND<br />
PGND<br />
2<br />
GND<br />
GND<br />
GND<br />
5<br />
6<br />
10<br />
RB7211 2.55K<br />
1%<br />
1/20W<br />
MF<br />
201<br />
2<br />
CB770<br />
2200PF<br />
2<br />
1<br />
10%<br />
25V<br />
CER-X7R<br />
0201<br />
P5VUSBC_T_NEG<br />
1<br />
RB772<br />
2.55K<br />
1%<br />
1/20W<br />
MF<br />
2<br />
201<br />
Vout = 5.036V<br />
Freq = 500 kHz<br />
Max OCP = 13.05A<br />
Nom OCP = 10.84A<br />
Min OCP = 7.94A<br />
C<br />
P5VUSBC_T_AGND<br />
MIN_LINE_WIDTH=0.6000<br />
MIN_NECK_WIDTH=0.2000<br />
XWB700<br />
SM<br />
1 2<br />
PLACE_NEAR=UB700.2:1mm<br />
B<br />
B<br />
A<br />
BOM_COST_GROUP=USB-C<br />
SYNC_MASTER=J79_JSHAO<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
TBT 5V REGULATOR<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
117 OF 145<br />
99 OF 119<br />
SYNC_DATE=12/18/2015<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
C<br />
B<br />
A<br />
104<br />
57<br />
49<br />
52<br />
65<br />
74<br />
66<br />
52<br />
48<br />
52<br />
52<br />
PPBUS_G3H<br />
PPBUS_HS_CPU<br />
96<br />
PP3V3_G3H<br />
PBUS Rails<br />
PPBUS_HS_OTH5V<br />
PPBUS_HS_OTH3V3<br />
PPBUS_S4_HS_TPAD<br />
95<br />
94<br />
30<br />
29<br />
52<br />
PPDCIN_G3H<br />
PPDCIN_G3H<br />
3V3 G3H Rails<br />
PP3V3_G3H_SMC_ISNS<br />
PP3V0_G3H<br />
RTC Rails<br />
PPBUS_G3H<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=13.1V<br />
MAKE_BASE=TRUE<br />
PPBUS_G3H 52<br />
PPBUS_G3H 52<br />
PPBUS_G3H 52<br />
PPBUS_G3H 79<br />
PPBUS_G3H 52<br />
PPBUS_G3H 52<br />
PPBUS_G3H 74<br />
PPBUS_G3H 65<br />
PPBUS_G3H 76<br />
PPBUS_G3H 33 99<br />
PPBUS_G3H 76<br />
PPBUS_G3H 62 63<br />
PPBUS_G3H 91<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=13.1V<br />
PPBUS_HS_CPU 68<br />
PPBUS_HS_CPU 68<br />
PPBUS_HS_CPU 70<br />
PPBUS_HS_CPU 75<br />
PPBUS_HS_CPU 73<br />
PPBUS_HS_CPU 75<br />
PPBUS_HS_CPU 67<br />
PPBUS_HS_OTH5V<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=13.1V<br />
MAKE_BASE=TRUE<br />
PPBUS_HS_OTH5V 72<br />
PPBUS_HS_OTH3V3<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=13.1V<br />
MAKE_BASE=TRUE<br />
PPBUS_HS_OTH3V3 72<br />
PPBUS_S4_HS_TPAD<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=13.1V<br />
MAKE_BASE=TRUE<br />
PPBUS_S4_HS_TPAD 43<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=20V<br />
PP3V3_G3H<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
MAKE_BASE=TRUE<br />
PP3V3_G3H 59<br />
PP3V3_G3H 57 80<br />
PP3V3_G3H 50 100<br />
PP3V3_G3H 66<br />
PP3V3_G3H 43 50 104<br />
PP3V3_G3H 51<br />
PP3V3_G3H 49<br />
PP3V3_G3H 18<br />
PP3V3_G3H 51<br />
PP3V3_G3H 29<br />
PP3V3_G3H 30<br />
PP3V3_G3H 106<br />
PP3V3_G3H 77<br />
PP3V3_G3H 95<br />
PP3V3_G3H 96<br />
PP3V3_G3H 50 100<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
MAKE_BASE=TRUE<br />
PP3V0_G3H<br />
PPBUS_HS_CPU<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
PPDCIN_G3H<br />
PP3V3_G3H_SMC_ISNS<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.0V<br />
MAKE_BASE=TRUE<br />
PP3V0_G3H 8 12 14 15<br />
PP3V0_G3H 74<br />
66<br />
104<br />
76<br />
68<br />
68<br />
70<br />
75<br />
73<br />
78<br />
75<br />
53<br />
78<br />
IMVP Rails<br />
PPVCC_S0_CPU<br />
PPVCCSA_S0_CPU<br />
PPVCCGT_S0_CPU<br />
CPU VCCIO Rails<br />
PPVCCIO_S0_CPU<br />
CPU EDRAM Rails<br />
PPVCCEDRAM_S0_CPU<br />
PCH Prime Core Rails<br />
PPVCCPRIMCORE_SUS_PCH<br />
PP1V2_S3<br />
PP1V2_S3_CPUDDR<br />
PP1V2_S0SW<br />
1V2 Rails<br />
PPVCC_S0_CPU<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.5V<br />
MAKE_BASE=TRUE<br />
PPVCC_S0_CPU 8 54 104<br />
PPVCC_S0_CPU 10<br />
PPVCCSA_S0_CPU<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.5V<br />
MAKE_BASE=TRUE<br />
PPVCCSA_S0_CPU 8 55<br />
PPVCCSA_S0_CPU 10<br />
PPVCCGT_S0_CPU<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.5V<br />
MAKE_BASE=TRUE<br />
PPVCCGT_S0_CPU 8 54<br />
PPVCCGT_S0_CPU 11<br />
PPVCCGT_S0_CPU 8<br />
PPVCCGT_S0_CPU 11<br />
PPVCCIO_S0_CPU<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=0.95V<br />
MAKE_BASE=TRUE<br />
PPVCCIO_S0_CPU 5 8<br />
PPVCCIO_S0_CPU 10<br />
PPVCCEDRAM_S0_CPU<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.05V<br />
MAKE_BASE=TRUE<br />
PPVCCEDRAM_S0_CPU 8<br />
PPVCCEDRAM_S0_CPU 8<br />
PPVCCEDRAM_S0_CPU 8<br />
PPVCCEDRAM_S0_CPU 10<br />
PPVCCEDRAM_S0_CPU 8<br />
PPVCCEDRAM_S0_CPU 8<br />
PPVCCEDRAM_S0_CPU 10<br />
PPVCCPRIMCORE_SUS_PCH<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.0V<br />
MAKE_BASE=TRUE<br />
PPVCCPRIMCORE_SUS_PCH 8 12 55<br />
PP1V2_S3<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.2V<br />
MAKE_BASE=TRUE<br />
PP1V2_S3 21 22 23 24<br />
PP1V2_S3 75<br />
PP1V2_S3 20<br />
PP1V2_S3 21 22 23 24<br />
PP1V2_S3 21 22 23 24<br />
PP1V2_S3 53<br />
PP1V2_S3 78<br />
PP1V2_S3_CPUDDR<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.2V<br />
MAKE_BASE=TRUE<br />
PP1V2_S3_CPUDDR 8<br />
PP1V2_S3_CPUDDR 8<br />
PP1V2_S3_CPUDDR 10<br />
PP1V2_S3_CPUDDR 10<br />
PP1V2_S0SW<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.2V<br />
MAKE_BASE=TRUE<br />
PP1V2_S0SW 8 10<br />
75<br />
76<br />
78<br />
78<br />
78<br />
55<br />
100<br />
20<br />
20<br />
20<br />
PP1V8_S4<br />
0V6 Rails<br />
PP0V6_S0_DDRVTT<br />
100<br />
20<br />
PP1V8_SUS<br />
PP1V8_S3<br />
PP1V8_S0<br />
PP0V6_S3_MEM_VREFDQ_A<br />
PP0V6_S3_MEM_VREFCA_A<br />
PP0V6_S3_MEM_VREFDQ_B<br />
PP0V6_S3_MEM_VREFCA_A<br />
1V8 Rails<br />
PP1V8_S3_MEM<br />
PP0V6_S0_DDRVTT<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=0.6V<br />
MAKE_BASE=TRUE<br />
PP0V6_S0_DDRVTT 25<br />
PP0V6_S0_DDRVTT 25<br />
PP0V6_S3_MEM_VREFDQ_A<br />
MAKE_BASE=TRUE<br />
PP0V6_S3_MEM_VREFCA_A<br />
MAKE_BASE=TRUE<br />
PP0V6_S3_MEM_VREFDQ_B<br />
MAKE_BASE=TRUE<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.8V<br />
MAKE_BASE=TRUE<br />
PP1V8_SUS 78<br />
PP1V8_SUS 78<br />
PP1V8_SUS 8<br />
PP1V8_SUS 8<br />
PP1V8_SUS 12<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
MAKE_BASE=TRUE<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.8V<br />
MAKE_BASE=TRUE<br />
VOLTAGE=0.6V<br />
VOLTAGE=0.6V<br />
PP0V6_S3_MEM_VREFCA_A 23 24<br />
MAKE_BASE=TRUE<br />
PP1V8_SUS<br />
VOLTAGE=0.6V<br />
PP1V8_SUS 8 14 19<br />
PP1V8_SUS 8 12<br />
PP1V8_S4<br />
PP1V8_S4 38 42<br />
PP1V8_S4 18 19 35<br />
PP1V8_S3<br />
PP1V8_S3 55<br />
PP1V8_S3 74<br />
PP1V8_S3_MEM<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.8V<br />
MAKE_BASE=TRUE<br />
VOLTAGE=0.6V<br />
PP1V8_S3_MEM 21 22 23 24<br />
PP1V8_S0<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
MAKE_BASE=TRUE<br />
PP1V8_S0 12<br />
PP1V8_S0 60 62 63 104<br />
PP1V8_S0 19 106<br />
PP1V8_S0 37 38 42<br />
PP1V8_S0 74<br />
PP1V8_S0 18<br />
PP1V8_S0 37 42<br />
PP1V8_S0 37<br />
PP1V8_S0 19<br />
SYNC_MASTER=J79_ALFRED<br />
106<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
21<br />
21<br />
23<br />
22<br />
22<br />
24<br />
Power Aliases - 1<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
120 OF 145<br />
100 OF 119<br />
SYNC_DATE=06/17/2015<br />
SIZE<br />
D<br />
D<br />
C<br />
B<br />
A
SYNC_MASTER=J79_ALFRED<br />
SYNC_DATE=06/18/2015<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
76<br />
78<br />
1V0 Rails<br />
PP1V0_SUS<br />
PP1V0_SUSSW<br />
PP1V0_SUS<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1.0V<br />
MAKE_BASE=TRUE<br />
PP1V0_SUS 8 12<br />
PP1V0_SUS 8 12<br />
PP1V0_SUS 12 15<br />
PP1V0_SUS 8<br />
PP1V0_SUS 12<br />
PP1V0_SUS 8<br />
PP1V0_SUS 12<br />
PP1V0_SUS 12<br />
PP1V0_SUS 8<br />
PP1V0_SUS 17<br />
PP1V0_SUS 78<br />
PP1V0_SUS 78<br />
PP1V0_SUS 18 19<br />
PP1V0_SUS 78<br />
PP1V0_SUSSW<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1V<br />
MAKE_BASE=TRUE<br />
PP1V0_SUSSW 8 12<br />
PP1V0_SUSSW 12<br />
PP1V0_SUSSW 8 12<br />
PP1V0_SUSSW 8 12<br />
72<br />
104 72<br />
78<br />
PP5V_S5<br />
PP5V_S4<br />
PP5V_S4SW<br />
5V Rails<br />
PP5V_S5<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=5V<br />
MAKE_BASE=TRUE<br />
PP5V_S4<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=5V<br />
MAKE_BASE=TRUE<br />
PP5V_S4 43<br />
PP5V_S4 67<br />
PP5V_S4 78<br />
PP5V_S4 33<br />
PP5V_S4 99<br />
PP5V_S4 91<br />
PP5V_S4 78<br />
PP5V_S4 77<br />
PP5V_S4SW<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=5V<br />
MAKE_BASE=TRUE<br />
PP5V_S4SW 57<br />
72<br />
PP3V3_S5<br />
3V3 Rails<br />
PP3V3_S5<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
MAKE_BASE=TRUE<br />
PP3V3_S5 8 14<br />
PP3V3_S5 78<br />
PP3V3_S5 78<br />
PP3V3_S5 78<br />
PP3V3_S5 74<br />
PP3V3_S5 19<br />
PP3V3_S5 57 78<br />
PP3V3_S5 76<br />
PP3V3_S5 18<br />
PP3V3_S5 78<br />
PP3V3_S5 78<br />
PP3V3_S5 78<br />
PP3V3_S5 53<br />
PP3V3_S5 91<br />
PP3V3_S5 80<br />
PP3V3_S5 78<br />
PP3V3_S5 78<br />
PP3V3_S5 78<br />
PP3V3_S5 32<br />
PP3V3_S5 98<br />
78<br />
PP3V3_S0<br />
PP3V3_S0<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
MAKE_BASE=TRUE<br />
PP3V3_S0 55<br />
PP3V3_S0 58<br />
PP3V3_S0 54 56 106<br />
PP3V3_S0 73 74<br />
PP3V3_S0 5 13 14 16 19 94<br />
PP3V3_S0 19<br />
PP3V3_S0 38 42<br />
PP3V3_S0 51<br />
PP3V3_S0 51<br />
PP3V3_S0 51<br />
PP3V3_S0 51<br />
PP3V3_S0 54<br />
PP3V3_S0 52 53<br />
PP3V3_S0 53<br />
PP3V3_S0 34 106<br />
PP3V3_S0 37<br />
PP3V3_S0 56<br />
61<br />
D<br />
PP3V3_S0 56<br />
PP3V3_S0 49<br />
C<br />
78<br />
78<br />
PP1V0_S3<br />
PP1V0_S0SW<br />
PP1V0_S3<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1V<br />
MAKE_BASE=TRUE<br />
PP1V0_S3 6 8 10 14 19<br />
PP1V0_S3 67<br />
PP1V0_S3 8 10<br />
PP1V0_S3 78<br />
PP1V0_S3 49<br />
PP1V0_S3 73<br />
PP1V0_S0SW<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=1V<br />
MAKE_BASE=TRUE<br />
PP1V0_S0SW 6 8 10 17<br />
57<br />
78<br />
PP5V_S4SW_ISNS<br />
PP5V_S0<br />
PP5V_S4SW_ISNS<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=5V<br />
PP5V_S4SW_ISNS 51 55<br />
PP5V_S4SW_ISNS 53<br />
PP5V_S0<br />
MAKE_BASE=TRUE<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=5V<br />
MAKE_BASE=TRUE<br />
PP5V_S0 54 106<br />
PP5V_S0 67 68<br />
PP5V_S0 79<br />
PP5V_S0 43 58<br />
PP5V_S0 55<br />
38<br />
106<br />
78<br />
PP3V3_SUS<br />
PP3V3_SUS<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
MAKE_BASE=TRUE<br />
PP3V3_SUS 59<br />
PP3V3_SUS 5 8 12<br />
PP3V3_SUS 8 13<br />
PP3V3_SUS 8 12<br />
PP3V3_SUS 8 13 14 15 16<br />
PP3V3_SUS 8 12<br />
PP3V3_SUS 8 12<br />
PP3V3_SUS 8<br />
PP3V3_SUS 8 12<br />
PP3V3_SUS 8<br />
PP3V3_SUS 78<br />
PP3V3_SUS 74<br />
PP3V3_SUS 17 77<br />
PP3V3_SUS 78<br />
PP3V3_SUS 74<br />
PP3V3_S0 80<br />
PP3V3_S0 49<br />
PP3V3_S0 19<br />
PP3V3_S0 73<br />
PP3V3_S0 42<br />
PP3V3_S0 54<br />
PP3V3_S0 54<br />
PP3V3_S0 52<br />
PP3V3_S0 61 106<br />
PP3V3_S0 43<br />
C<br />
T208 Rails<br />
PP5V_S0 80<br />
PP5V_S0 73<br />
PP5V_S0 70<br />
78<br />
PP3V3_S4<br />
PP3V3_SUS 43<br />
PP3V3_S4<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
MAKE_BASE=TRUE<br />
PP3V3_S4 53 106<br />
PP3V3_S4 36 106<br />
106<br />
PP3V3_S4 54<br />
53<br />
PP3V3_S5_T139<br />
PP3V3_S5_T139<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
MAKE_BASE=TRUE<br />
PP3V3_S5_T139 42<br />
55<br />
PP5V_S0_KBD<br />
PP5V_S0_KBD<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=5V<br />
MAKE_BASE=TRUE<br />
PP5V_S0_KBD 43 104<br />
PP3V3_S4 43 104<br />
PP3V3_S4 51<br />
PP3V3_S4 14<br />
PP3V3_S4 84<br />
PP3V3_S4 54<br />
PP3V3_S4 57<br />
PP3V3_S4 49 50<br />
B<br />
54<br />
PP3V3_S4_SOC_PMU<br />
PP3V3_S4_SOC_PMU<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
MAKE_BASE=TRUE<br />
PP3V3_S4_SOC_PMU 38 42<br />
PP3V3_S4_SOC_PMU 40 41<br />
106<br />
54<br />
54<br />
53<br />
PP3V3_TBT_X_S0<br />
PP3V3_TBT_T_S0<br />
PP3V3_S4_BT<br />
PP3V3_TBT_X_S0 27 28<br />
PP3V3_TBT_T_S0 93 94<br />
PP3V3_S4_BT<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
MAKE_BASE=TRUE<br />
35<br />
B<br />
54<br />
PP5V_S0_T139<br />
PP5V_S0_T139<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=5V<br />
MAKE_BASE=TRUE<br />
54<br />
PP3V3_S4_TPAD<br />
PP3V3_S4_TPAD<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
MAKE_BASE=TRUE<br />
PP5V_S0_T139 42 104<br />
PP3V3_S4_TPAD 43 104<br />
PP3V3_S4_TPAD 104<br />
78<br />
PP3V3_S4SW_SNS<br />
PP3V3_S4SW_SNS<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
VOLTAGE=3.3V<br />
MAKE_BASE=TRUE<br />
PP3V3_S4SW_SNS 52<br />
PP3V3_S4SW_SNS 52 53 54 55 57<br />
A<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0700<br />
Digital Ground<br />
GND<br />
GND<br />
MIN_NECK_WIDTH=0.0700<br />
MIN_LINE_WIDTH=0.0900<br />
VOLTAGE=0V<br />
91<br />
57<br />
57<br />
89<br />
PP3V3_S5_SSD_LB<br />
PP3V3_S5_SSD<br />
PP3V3_S4_MESA<br />
PP3V3_2V7_NAND_VCC<br />
PP3V3_S5_SSD_LB<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
PP3V3_S4_MESA 47<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
MAKE_BASE=TRUE<br />
VOLTAGE=3.3V<br />
PP3V3_S5_SSD_LB 57<br />
PP3V3_S5_SSD<br />
MIN_LINE_WIDTH=0.0900<br />
MIN_NECK_WIDTH=0.0520<br />
MAKE_BASE=TRUE<br />
VOLTAGE=3.3V<br />
PP3V3_S5_SSD 84 88<br />
PP3V3_S4_MESA<br />
PP3V3_2V7_NAND_VCC<br />
VOLTAGE=3.3V<br />
MAKE_BASE=TRUE<br />
VOLTAGE=2.7V<br />
MAKE_BASE=TRUE<br />
86<br />
87<br />
88<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
Power Aliases - 2<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
121 OF 145<br />
101 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
UNUSED TP ALIASES<br />
UNUSED TP ALIASES<br />
UNUSED SIGNAL ALIAS<br />
D<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
NC_ANI0_NCE4<br />
NC_ANI0_NCE5<br />
NC_ANI0_NCE6<br />
NC_ANI0_NCE7<br />
NC_ANI1_NCE4<br />
NC_ANI1_NCE5<br />
NC_ANI1_NCE6<br />
NC_ANI1_NCE7<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NC_ANI0_NCE4<br />
NC_ANI0_NCE5<br />
NC_ANI0_NCE6<br />
NC_ANI0_NCE7<br />
NC_ANI1_NCE4<br />
NC_ANI1_NCE5<br />
NC_ANI1_NCE6<br />
NC_ANI1_NCE7<br />
D<br />
C<br />
B<br />
A<br />
83<br />
82<br />
81<br />
81<br />
81<br />
81<br />
81<br />
81<br />
74<br />
74<br />
74<br />
74<br />
74<br />
88<br />
14<br />
14<br />
14<br />
14<br />
14<br />
14<br />
16<br />
16<br />
16<br />
14<br />
14<br />
99<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
34<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
NC_S3X_VSS_S<br />
NC_S3X_VDD_S<br />
NC_S3X_PMIC_CTRL_2<br />
NC_S3X_PCIE_ATB1<br />
NC_S3X_PCIE_ATB0<br />
NC_S3X_DT1<br />
NC_S3X_DT0<br />
NC_S3X_DDR_ATO<br />
NC_PMIC_PGG<br />
NC_PMIC_PGF<br />
NC_PMIC_PGE<br />
NC_PMIC_PGD<br />
NC_PMIC_PGC<br />
NC_PICCOLO_24M_CLK_REQ<br />
NC_PCH_SLP_A_L<br />
NC_PCH_PME_L<br />
NC_PCH_LANPHYPC<br />
NC_PCH_GPP_F9<br />
NC_PCH_GPP_F8<br />
NC_PCH_GPP_F10<br />
NC_PCH_GPP_D4<br />
NC_PCH_GPP_D3<br />
NC_PCH_GPP_D1<br />
NC_PCH_GPP_D0<br />
NC_PCH_GPD7<br />
NC_P5VUSBC_T_PGOOD<br />
NC_DPMUX_SAK_20<br />
NC_DPMUX_SAK_19<br />
NC_DPMUX_SAK_18<br />
NC_DPMUX_SAK_17<br />
NC_DPMUX_SAK_16<br />
NC_DPMUX_SAK_15<br />
NC_DPMUX_SAK_14<br />
NC_S3X_VSS_S<br />
MAKE_BASE=TRUE NC_S3X_VDD_S<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NO_TEST=1<br />
NC_S3X_PMIC_CTRL_2<br />
MAKE_BASE=TRUE NC_S3X_PCIE_ATB1<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NC_S3X_PCIE_ATB0<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NO_TEST=1<br />
NC_S3X_DT1<br />
MAKE_BASE=TRUE<br />
NC_S3X_DT0<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NC_S3X_DDR_ATO<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NC_PMIC_PGG<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NC_PMIC_PGF<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NC_PMIC_PGE<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NC_PMIC_PGD<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NC_PMIC_PGC<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NO_TEST=1<br />
NC_ANI2_NCE4<br />
NC_ANI2_NCE5<br />
NC_ANI2_NCE6<br />
NC_ANI2_NCE7<br />
NC_ANI3_NCE4<br />
NC_ANI3_NCE5<br />
NC_ANI3_NCE6<br />
NC_ANI3_NCE7<br />
NC_ANI4_NCE4<br />
NC_ANI4_NCE5<br />
NC_ANI4_NCE6<br />
NC_ANI4_NCE7<br />
NC_ANI5_NCE4<br />
NC_ANI5_NCE5<br />
NC_ANI5_NCE6<br />
NC_ANI5_NCE7<br />
NC_ANI6_NCE4<br />
NC_ANI6_NCE5<br />
NC_ANI6_NCE6<br />
NC_ANI6_NCE7<br />
NC_ANI7_NCE4<br />
NC_ANI7_NCE5<br />
NC_ANI7_NCE6<br />
NC_ANI7_NCE7<br />
NC_CPU_NCTFVSS_B71<br />
MAKE_BASE=TRUE NC_PICCOLO_24M_CLK_REQ<br />
87<br />
NC_ANI7_RNB<br />
IN<br />
MAKE_BASE=TRUE NO_TEST=1<br />
MAKE_BASE=TRUE NC_PCH_SLP_A_L<br />
NO_TEST=1<br />
UNUSED SIGNALS<br />
MAKE_BASE=TRUE NC_PCH_PME_L<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NC_PCH_LANPHYPC<br />
NO_TEST=1<br />
14 NC_PCH_SLP_WLAN_L<br />
TRUE<br />
NC_PCH_SLP_WLAN_L<br />
105<br />
MAKE_BASE=TRUE NC_PCH_GPP_F9<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NC_PCH_GPP_F8<br />
NO_TEST=1<br />
102 13 NC_SPI_CS1_L<br />
TRUE<br />
NC_SPI_CS1_L<br />
102 105<br />
81 NC_S3X_GPIO1<br />
NC_S3X_GPIO1<br />
MAKE_BASE=TRUE NO_TEST=1<br />
102 13 NC_SPI_CS2_L<br />
TRUE<br />
NC_SPI_CS2_L<br />
102 105<br />
81 NC_S3X_BOOTSTRAP6<br />
MAKE_BASE=TRUE NC_PCH_GPP_F10<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NO_TEST=1<br />
MAKE_BASE=TRUE NC_PCH_GPP_D4<br />
NO_TEST=1<br />
81 NC_S3X_BOOTSTRAP1<br />
MAKE_BASE=TRUE NO_TEST=1<br />
MAKE_BASE=TRUE NC_PCH_GPP_D3<br />
NO_TEST=1<br />
102 13 NC_SPI_CS1_L<br />
TRUE<br />
NC_SPI_CS1_L<br />
102 105<br />
102 13 NC_SPI_CS2_L<br />
TRUE<br />
NC_SPI_CS2_L<br />
102 105<br />
MAKE_BASE=TRUE NC_PCH_GPP_D1<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NO_TEST=1<br />
TRUE<br />
NC_PCIE_CAMERA_D2R_N<br />
S3X Aliasing<br />
NC_PCH_GPP_D0<br />
15<br />
NC_PCIE_CAMERA_D2R_N 105<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
15 NC_PCIE_CAMERA_D2R_P<br />
NC_PCIE_CAMERA_D2R_P TRUE<br />
MAKE_BASE=TRUE NC_PCH_GPD7<br />
105<br />
SSD_CLKREQ_L 91<br />
19 SSD_CLKREQ_L<br />
MAKE_BASE=TRUE NC_P5VUSBC_T_PGOOD<br />
NO_TEST=1<br />
15 NC_PCIE_CAMERA_R2D_C_N<br />
NC_PCIE_CAMERA_R2D_C_N<br />
TRUE 105<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE NC_DPMUX_SAK_20<br />
NO_TEST=1<br />
15 NC_PCIE_CAMERA_R2D_C_P<br />
NC_PCIE_CAMERA_R2D_C_P<br />
TRUE 105<br />
14 SSD_SR_EN_L<br />
SSD_SR_EN_L 91 104<br />
MAKE_BASE=TRUE NC_DPMUX_SAK_19<br />
NO_TEST=1<br />
15 NC_PCIE_CLK100M_CAMERA_N NC_PCIE_CLK100M_CAMERA_N<br />
105 TRUE<br />
MAKE_BASE=TRUE NC_DPMUX_SAK_18 NO_TEST=1<br />
15 NC_PCIE_CLK100M_CAMERA_P NC_PCIE_CLK100M_CAMERA_P<br />
105 TRUE<br />
EPD PANEL<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
NC_DPMUX_SAK_17<br />
MAKE_BASE=TRUE NC_DPMUX_SAK_16<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NO_TEST=1<br />
NC_DPMUX_SAK_15<br />
MAKE_BASE=TRUE<br />
NC_DPMUX_SAK_14<br />
NO_TEST=1<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
6<br />
6<br />
6<br />
6<br />
6<br />
6<br />
6<br />
6<br />
9<br />
9<br />
9<br />
9<br />
9<br />
9<br />
9<br />
9<br />
6<br />
6<br />
6<br />
6<br />
6<br />
73<br />
28<br />
94<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
15<br />
15<br />
15<br />
15<br />
6<br />
6<br />
6<br />
15<br />
15<br />
15<br />
15<br />
NC_CPU_RSVD_BB69<br />
NC_CPU_RSVD_BB68<br />
NC_CPU_RSVD_BA70<br />
NC_CPU_RSVD_BA68<br />
NC_CPU_RSVD_AW71<br />
NC_CPU_RSVD_AW70<br />
NC_CPU_RSVD_AK13<br />
NC_CPU_RSVD_AK12<br />
NC_CPU_NCTFVSS_C1<br />
NC_CPU_NCTFVSS_BB70<br />
NC_CPU_NCTFVSS_BA71<br />
NC_CPU_NCTFVSS_BA1<br />
NC_CPU_NCTFVSS_B71<br />
NC_CPU_NCTFVSS_AV1<br />
NC_CPU_NCTFVSS_A70<br />
NC_CPU_NCTFVSS_A5<br />
NC_CPU_BB5<br />
NC_CPU_BB3<br />
NC_CPU_AY4<br />
NC_CPU_AU5<br />
NC_CPU_AT5<br />
NC_CPU_MSM_L<br />
NC_USBC_XA_RESET_L<br />
NC_USBC_TB_RESET_L<br />
NC_USB_EXTA_N<br />
NC_USB_EXTA_P<br />
NC_USB_EXTB_N<br />
NC_USB_EXTB_P<br />
NC_XDP_BPM_L<br />
NC_XDP_BPM_L<br />
NC_XDP_BPM_L<br />
NC_USB3_EXTB_D2R_N<br />
NC_USB3_EXTB_D2R_P<br />
NC_USB3_EXTB_R2D_C_N<br />
NC_USB3_EXTB_R2D_C_P<br />
NC_USB_EXTA_N<br />
NC_USB_EXTA_P<br />
NC_USB_EXTB_N<br />
NC_USB_EXTB_P<br />
NC_XDP_BPM_L<br />
NC_XDP_BPM_L<br />
NC_XDP_BPM_L<br />
NC_USB3_EXTB_D2R_N<br />
NC_USB3_EXTB_D2R_P<br />
NC_USB3_EXTB_R2D_C_N<br />
NC_USB3_EXTB_R2D_C_P<br />
NC_CPU_RSVD_BB69<br />
MAKE_BASE=TRUE NC_CPU_RSVD_BB68<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NC_CPU_RSVD_BA70<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NC_CPU_RSVD_BA68<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NC_CPU_RSVD_AW71<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NO_TEST=1<br />
NC_CPU_RSVD_AW70<br />
MAKE_BASE=TRUE<br />
NC_CPU_RSVD_AK13<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NC_CPU_RSVD_AK12<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NO_TEST=1<br />
NC_CPU_NCTFVSS_C1<br />
MAKE_BASE=TRUE NO_TEST=1<br />
NC_CPU_NCTFVSS_BB70<br />
MAKE_BASE=TRUE<br />
NC_CPU_NCTFVSS_BA71<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NO_TEST=1<br />
NC_CPU_NCTFVSS_BA1<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NC_CPU_NCTFVSS_AV1<br />
MAKE_BASE=TRUE NC_CPU_NCTFVSS_A70<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NO_TEST=1<br />
NC_CPU_NCTFVSS_A5<br />
MAKE_BASE=TRUE<br />
NC_CPU_BB5<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NC_CPU_BB3<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NC_CPU_AY4<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NC_CPU_AU5<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NC_CPU_AT5<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NC_CPU_MSM_L<br />
NO_TEST=1<br />
MAKE_BASE=TRUE NO_TEST=1<br />
NC_USBC_XA_RESET_L<br />
MAKE_BASE=TRUE NC_USBC_TB_RESET_L<br />
NO_TEST=1<br />
MAKE_BASE=TRUE<br />
NO_TEST=1<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
86<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
87<br />
86<br />
86<br />
87<br />
79<br />
79<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
NC_ANI1_RNB<br />
NC_ANI3_RNB<br />
NC_ANI5_RNB<br />
NC_ANI7_RNB<br />
I2C_BKLT_SCL<br />
I2C_BKLT_SDA<br />
MAKE_BASE<br />
TRUE<br />
TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
I2C_BKLT_SCL<br />
I2C_BKLT_SDA<br />
SYNC_MASTER=SHART_J44<br />
PAGE TITLE<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
R<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
80<br />
80<br />
104<br />
104<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
NC_ANI2_NCE4<br />
NC_ANI2_NCE5<br />
NC_ANI2_NCE6<br />
NC_ANI2_NCE7<br />
NC_ANI3_NCE4<br />
NC_ANI3_NCE5<br />
NC_ANI3_NCE6<br />
NC_ANI3_NCE7<br />
NC_ANI4_NCE4<br />
NC_ANI4_NCE5<br />
NC_ANI4_NCE6<br />
NC_ANI4_NCE7<br />
NC_ANI5_NCE4<br />
NC_ANI5_NCE5<br />
NC_ANI5_NCE6<br />
NC_ANI5_NCE7<br />
NC_ANI6_NCE4<br />
NC_ANI6_NCE5<br />
NC_ANI6_NCE6<br />
NC_ANI6_NCE7<br />
NC_ANI7_NCE4<br />
NC_ANI7_NCE5<br />
NC_ANI7_NCE6<br />
NC_ANI7_NCE7<br />
NC_ANI1_RNB<br />
NC_ANI3_RNB<br />
NC_ANI5_RNB<br />
NC_S3X_BOOTSTRAP6<br />
NC_S3X_BOOTSTRAP1<br />
Signal Aliases<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
IV ALL RIGHTS RESERVED<br />
Apple Inc.<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
SYNC_DATE=11/19/2012<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
122 OF 145<br />
102 OF 119<br />
SIZE<br />
D<br />
C<br />
B<br />
A<br />
8 7 6<br />
5 4 3<br />
2 1
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
Memory Bit & Byte Swizzle<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
D<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
D<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
C<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 21<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 23<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
C<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
B<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
MEM_A_DQ 22<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
MEM_B_DQ 24<br />
B<br />
MAKE_BASE=TRUE<br />
MAKE_BASE=TRUE<br />
7<br />
7<br />
MEM_A_DQS_P<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P 21<br />
MEM_A_DQS_N 21<br />
7<br />
7<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P 23<br />
MEM_B_DQS_N 23<br />
7<br />
7<br />
MEM_A_DQS_P<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P 21<br />
MEM_A_DQS_N 21<br />
7<br />
7<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P 23<br />
MEM_B_DQS_N 23<br />
7<br />
7<br />
MEM_A_DQS_P<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P 21<br />
MEM_A_DQS_N 21<br />
7<br />
7<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P 23<br />
MEM_B_DQS_N 23<br />
7<br />
7<br />
MEM_A_DQS_P<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P 21<br />
MEM_A_DQS_N 21<br />
7<br />
7<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P 23<br />
MEM_B_DQS_N 23<br />
A<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
MEM_A_DQS_P<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P<br />
MEM_A_DQS_N<br />
MEM_A_DQS_P 22<br />
MEM_A_DQS_N 22<br />
MEM_A_DQS_P 22<br />
MEM_A_DQS_N 22<br />
MEM_A_DQS_P 22<br />
MEM_A_DQS_N 22<br />
MEM_A_DQS_P 22<br />
MEM_A_DQS_N 22<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
7<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P<br />
MEM_B_DQS_N<br />
MEM_B_DQS_P 24<br />
MEM_B_DQS_N 24<br />
MEM_B_DQS_P 24<br />
MEM_B_DQS_N 24<br />
MEM_B_DQS_P 24<br />
MEM_B_DQS_N 24<br />
MEM_B_DQS_P 24<br />
MEM_B_DQS_N 24<br />
SYNC_MASTER=AHARTMAN_J52<br />
LPDDR3 Bit & Byte Swizzle<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
SYNC_DATE=10/29/2013<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
123 OF 145<br />
103 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
C<br />
B<br />
A<br />
104 42 38<br />
42 38<br />
42 38<br />
42<br />
42<br />
105 42<br />
105 42<br />
105 42<br />
105 42<br />
106 104 42 37<br />
42 38 37<br />
42 38 37<br />
104 42<br />
104 42<br />
42 37<br />
42<br />
42 38 37<br />
42 38 37<br />
42 37<br />
106 104 42 37<br />
101 42<br />
42 38<br />
104 42 38<br />
42<br />
42<br />
42 38<br />
42 38<br />
42 38<br />
106 104 42 37<br />
43<br />
43<br />
58 43<br />
58 43<br />
58 43<br />
58 43<br />
101 43<br />
100 50 43<br />
104 43<br />
104 43<br />
101 43<br />
104 43<br />
104 43<br />
104 43<br />
104 43<br />
104 43<br />
50 43<br />
104 43<br />
104 43<br />
104 43<br />
104 43<br />
51 43<br />
51 43<br />
101 43<br />
101<br />
43<br />
43<br />
43<br />
43<br />
43<br />
43<br />
43<br />
43<br />
43<br />
50 43<br />
50 43<br />
49 43 42<br />
50<br />
104 43<br />
104 43<br />
104 43<br />
104 43<br />
104 43<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
Functional Test Points<br />
J4401 - DFR Display Connector<br />
6 TPs<br />
J4402 - DFR Touch Connector<br />
DFR_TOUCH_LID<br />
DFR_TOUCH_LID<br />
DFR_TOUCH_SPI_CS_L<br />
DFR_TOUCH_SPI_MOSI_R<br />
DFR_TOUCH_ROM_I2C_SCL<br />
DFR_TOUCH_ROM_I2C_SDA<br />
DFR_TOUCH_RESET_L<br />
PP1V8_S0SW_DFR<br />
PP5V_S0_T139<br />
DFR_TOUCH_PANEL_DETECT<br />
DFR_DISP_VSYNC<br />
DFR_TOUCH_SPI_MISO_R<br />
DFR_TOUCH_SPI_CLK_R<br />
DFR_TOUCH_INT_L<br />
DFR_CLKIN_RESET_L<br />
DFR_TOUCH_ROM_WC<br />
PP1V8_S0SW_DFR<br />
GND<br />
6 TPs<br />
J4500 - Keyboard Connector<br />
PP5V_S0_FAN_CONN<br />
GND_FAN<br />
FAN_LT_TACH<br />
FAN_LT_PWM<br />
FAN_RT_TACH<br />
FAN_RT_PWM<br />
PP5V_S0_KBD<br />
PP3V3_G3H<br />
KBD_BLC_GSSOUT<br />
KBD_BLC_GSLAT<br />
PP3V3_S4<br />
KBD_BLC_GSSIN<br />
KBD_BLC_XBLANK<br />
KBD_I2C_SDA<br />
KBD_INT_L<br />
KBD_I2C_SCL<br />
SMC_LSOC_RST_L<br />
KBD_BLC_GSSCK<br />
GND<br />
6 TPs<br />
J4501 - Trackpad Connector<br />
KBD_I2C_SCL<br />
KBD_I2C_SDA<br />
KBD_INT_L<br />
SMBUS_SMC_3_SDA<br />
SMBUS_SMC_3_SCL<br />
PP3V3_S4_TPAD<br />
PP3V3_S4_TPAD<br />
PP5V_S4_TPAD_CONN<br />
ACT_GND<br />
PPVIN_S4_TPAD_FUSE<br />
TPAD_SPI_CLK_R<br />
TPAD_SPI_IF_EN_CONN<br />
TPAD_SPI_MISO_R<br />
TPAD_SPI_CS_CONN_R_L<br />
TPAD_SPI_MOSI_R<br />
TPAD_SPI_INT_CONN_L<br />
SMC_ACTUATOR_DISABLE_L<br />
SMC_PME_S4_WAKE_L<br />
SMC_LID<br />
KBD_BLC_GSLAT<br />
KBD_BLC_GSSCK<br />
KBD_BLC_GSSOUT<br />
KBD_BLC_GSSIN<br />
KBD_BLC_XBLANK<br />
GND<br />
6 TPs<br />
DFR_DISP_VSYNC<br />
DFR_DISP_TE<br />
DFR_DISP_INT<br />
DFR_DISP_RESET_L<br />
PP3V3_S0SW_DFR<br />
MIPID_CLK_CONN_P<br />
MIPID_CLK_CONN_N<br />
MIPID_DATA_CONN_P<br />
MIPID_DATA_CONN_N<br />
PP1V8_S0SW_DFR<br />
DFRDRV_I2C_SCL<br />
DFRDRV_I2C_SDA<br />
GND<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
3 TPs<br />
2 TPs<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
2 TPs<br />
1 TPs<br />
8 TPs<br />
8 TPs<br />
3 TPs<br />
1 TPs<br />
1 TPs<br />
2 TPs<br />
1 TPs<br />
1 TPs<br />
8 TPs<br />
8 TPs<br />
47<br />
47<br />
47<br />
47 37<br />
47 37<br />
47<br />
47<br />
47<br />
47<br />
47<br />
47<br />
60<br />
60<br />
60<br />
60<br />
62<br />
62<br />
62 60<br />
62<br />
62<br />
63<br />
63<br />
63<br />
63<br />
104 64<br />
104 64<br />
104 64<br />
104 64<br />
64<br />
64<br />
64<br />
64<br />
104 64<br />
104 64<br />
104 64<br />
104 64<br />
66 65<br />
65<br />
65 51<br />
65 51<br />
65 54<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
J4900 - Mesa Connector<br />
PP3V0_MESA<br />
MESA_SPI_MISO_CONN<br />
MESA_SNSR_INT_CONN<br />
MESA_BOOST_EN_CONN<br />
MESA_I2C_SDA<br />
MESA_I2C_SCL<br />
ESD_GND<br />
PP1V8_MESA<br />
MESA_SPI_MOSI_CONN<br />
MENU_KEY_L<br />
MESA_SPI_CLK_CONN<br />
PP16V0_MESA<br />
GND<br />
2 TPs<br />
J6200 - MIC Connector<br />
DMIC1_DATA<br />
DMIC1_CLK<br />
PP1V8_S0<br />
DMIC2_DATA<br />
DMIC2_CLK<br />
GND<br />
2 TPs<br />
J6410 - Left Tweeter Connector<br />
2 TPs<br />
J6430 - Left Woofer Connector<br />
2 TPs<br />
J6500 - Right Tweeter Connector<br />
2 TPs<br />
J6550 - Right Woofer Connector<br />
2 TPs<br />
J6600 - Audio Jack Connector<br />
4 TPs<br />
J6950 - Battery Connector<br />
8 TPs<br />
1 TPs<br />
1 TPs<br />
J6951 - Battery Sense Connector<br />
SYS_DETECT_L<br />
SMBUS_SMC_5_G3_SCL<br />
SMBUS_SMC_5_G3_SDA<br />
BMON_IOUT<br />
GND<br />
1 TPs<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
SPKRCONN_TL_OUT_P<br />
SPKRCONN_TL_OUT_N<br />
8409_SPKR_ID0<br />
GND<br />
FUNC_TEST=TRUE<br />
SPKRCONN_WL_OUT_P<br />
SPKRCONN_WL_OUT_N<br />
GND<br />
FUNC_TEST=TRUE<br />
SPKRCONN_TR_OUT_P<br />
SPKRCONN_TR_OUT_N<br />
GND<br />
FUNC_TEST=TRUE<br />
SPKRCONN_WR_OUT_P<br />
SPKRCONN_WR_OUT_N<br />
GND<br />
FUNC_TEST=TRUE<br />
AUD_CONN_HP_LEFT<br />
AUD_CONN_HP_RIGHT<br />
AUD_CONN_RING2<br />
AUD_CONN_SLEEVE<br />
AUD_CONN_HP_SENSE_L<br />
AUD_CONN_HP_SENSE_R<br />
AUD_CONN_TIP_SENSE<br />
AUD_CONN_SLEEVE_XW<br />
AUD_CONN_RING2_XW<br />
AUD_CONN_HP_LEFT<br />
AUD_CONN_HP_RIGHT<br />
AUD_CONN_RING2<br />
AUD_CONN_SLEEVE<br />
GND<br />
PPVBAT_G3H_CONN<br />
GND<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
2 TPs<br />
1 TPs<br />
1 TPs<br />
4 TPs<br />
4 TPs<br />
104 92 80 77 74 73 48 26 19 14<br />
8 TPs<br />
80 79<br />
80 38 37<br />
80 38 37<br />
80 42<br />
80 42<br />
80 51<br />
80 51<br />
102 80<br />
102 80<br />
80 5<br />
80 48<br />
80 16<br />
80 5<br />
80<br />
106 80<br />
106 80<br />
106 80 38<br />
105 80 38<br />
105 80 38<br />
105 80 38<br />
105 80 38<br />
80<br />
80<br />
80<br />
80<br />
80<br />
80<br />
80<br />
80<br />
80<br />
15<br />
15<br />
15<br />
15<br />
15<br />
15<br />
49 48 28<br />
91 19 16<br />
91 84<br />
102 91<br />
91 14<br />
88 84<br />
88 84 19<br />
84 81<br />
94 84 81<br />
84 81<br />
84 81<br />
94 84 81<br />
84 81<br />
88 87 86 85 84 82 81 19<br />
66<br />
100 54 8<br />
88 82<br />
50 49 48 47<br />
50<br />
73 48 14<br />
101 72<br />
100 66<br />
35 19 14<br />
100 65<br />
66<br />
80 66 59 50<br />
77 48 19 14<br />
77 74 48 43 19 14<br />
104 92 80 77 74 73 48 26 19 14<br />
74 48 19 14<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
J8500 - eDP Connector<br />
PPVOUT_S0_LCDBKLT<br />
I2C_CAM_SDA<br />
I2C_CAM_SCL<br />
I2C_ALS_SCL<br />
I2C_ALS_SDA<br />
SMBUS_SMC_0_S0_SCL<br />
SMBUS_SMC_0_S0_SDA<br />
I2C_BKLT_SCL<br />
I2C_BKLT_SDA<br />
BKLT_PWM_MLB2TCON<br />
BKLT_PWM_TCON2MLB<br />
LCD_IRQ_L<br />
DP_INT_HPD<br />
BUF_EDP_PANEL_PWR_EN<br />
PP3V3_S0SW_LCD<br />
PP5V_S0SW_LCD<br />
PP5V_S0_ALSCAM_F<br />
MIPI_CLK_CONN_P<br />
MIPI_CLK_CONN_N<br />
MIPI_DATA_CONN_P<br />
MIPI_DATA_CONN_N<br />
EDP_INT_ML_P<br />
EDP_INT_ML_N<br />
EDP_INT_ML_P<br />
EDP_INT_ML_N<br />
EDP_INT_ML_P<br />
EDP_INT_ML_N<br />
EDP_INT_ML_P<br />
EDP_INT_ML_N<br />
EDP_INT_AUX_P<br />
EDP_INT_AUX_N<br />
GND<br />
8 TPs<br />
FUNC_TEST=TRUE<br />
Probe Block Grid - WiPass and NAND Rack<br />
TP_USB_TESTERN<br />
Debug LEDs<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
TP_USB_TESTERP<br />
FUNC_TEST=TRUE<br />
TP_USB3_03_D2RN<br />
FUNC_TEST=TRUE<br />
TP_USB3_03_D2RP<br />
FUNC_TEST=TRUE<br />
TP_USB3_03_R2DN<br />
FUNC_TEST=TRUE<br />
TP_USB3_03_R2DP<br />
FUNC_TEST=TRUE<br />
SMC_DEBUGPRT_RX_L<br />
FUNC_TEST=TRUE<br />
SMC_DEBUGPRT_TX_L<br />
FUNC_TEST=TRUE<br />
SSD_RESET_L<br />
FUNC_TEST=TRUE<br />
STORAGE_EN<br />
FUNC_TEST=TRUE<br />
SSD_SR_EN_L<br />
FUNC_TEST=TRUE<br />
SSD_BOOT_L<br />
FUNC_TEST=TRUE<br />
SSD_DBG_UART_R2D<br />
FUNC_TEST=TRUE<br />
SSD_DBG_UART_D2R<br />
FUNC_TEST=TRUE<br />
SSD_PWR_EN_L<br />
FUNC_TEST=TRUE<br />
S3X_JTAG_SEL<br />
FUNC_TEST=TRUE<br />
S3X_JTAG_TCK<br />
FUNC_TEST=TRUE<br />
S3X_JTAG_TDI<br />
FUNC_TEST=TRUE<br />
S3X_JTAG_TDO<br />
FUNC_TEST=TRUE<br />
S3X_JTAG_TMS<br />
FUNC_TEST=TRUE<br />
S3X_JTAG_TRST_L<br />
FUNC_TEST=TRUE<br />
PP1V8_SSD_COLD<br />
FUNC_TEST=TRUE<br />
PPDCIN_G3H_CHGR<br />
FUNC_TEST=TRUE<br />
PPVBAT_G3H_CHGR_REG<br />
FUNC_TEST=TRUE<br />
PPVCC_S0_CPU<br />
FUNC_TEST=TRUE<br />
PP0V9_SSD_REG<br />
FUNC_TEST=TRUE<br />
SMC_ONOFF_L<br />
FUNC_TEST=TRUE<br />
TP_SMC_DEV_SUPPLY_L<br />
FUNC_TEST=TRUE<br />
PM_PCH_SYS_PWROK<br />
FUNC_TEST=TRUE<br />
PP5V_S4<br />
FUNC_TEST=TRUE<br />
PPDCIN_G3H<br />
FUNC_TEST=TRUE<br />
PM_SLP_S3_L<br />
FUNC_TEST=TRUE<br />
PLT_RST_L<br />
FUNC_TEST=TRUE<br />
PP3V3_G3H<br />
FUNC_TEST=TRUE<br />
HPWR_EN_L<br />
FUNC_TEST=TRUE<br />
SMC_RESET_L<br />
FUNC_TEST=TRUE<br />
GND<br />
FUNC_TEST=TRUE<br />
3 TPs; 1x for USB2 pair, 1x for USB3 R2D, 1x for USB3 D2R<br />
PM_SLP_S5_L<br />
PM_SLP_S4_L<br />
PM_SLP_S3_L<br />
PM_SLP_S0_L<br />
PM_SLP_SUS_L<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
7 TPs<br />
1 TPs<br />
31<br />
31<br />
31 29 28<br />
31 29 28<br />
31 30 28<br />
31 30 28<br />
31<br />
97<br />
97<br />
97 95 94<br />
97 95 94<br />
97 96 94<br />
97 96 94<br />
97<br />
97<br />
J3300 - Left USB-C Connector<br />
PP20V_USBC_XA_VBUS_CONN<br />
4 TPs<br />
PP20V_USBC_XB_VBUS_CONN<br />
4 TPs<br />
USBC_XA_CC1<br />
USBC_XA_CC2<br />
USBC_XB_CC1<br />
USBC_XB_CC2<br />
TP_USBC_PP20V_XB<br />
GND<br />
4 TPs<br />
JB500 - Right USB-C Connector<br />
4 TPs<br />
4 TPs<br />
4 TPs<br />
FUNC_TEST=TRUE<br />
PP20V_USBC_TA_VBUS_CONN<br />
PP20V_USBC_TB_VBUS_CONN<br />
USBC_TA_CC1<br />
USBC_TA_CC2<br />
USBC_TB_CC1<br />
USBC_TB_CC2<br />
TP_USBC_PP20V_TB<br />
TP_USBC_PP20V_TA<br />
GND<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
FUNC_TEST=TRUE<br />
SYNC_MASTER=YHARTANTO_J44<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
ICT FCT 1<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
IN<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
SYNC_DATE=12/18/2012<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
124 OF 145<br />
104 OF 119<br />
SIZE<br />
D<br />
D<br />
C<br />
B<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
105 91 15<br />
105 91 15<br />
34 5<br />
34 5<br />
34 5<br />
34 5<br />
49 48<br />
IN<br />
IN<br />
IN<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
DP_DDI1_ML_C_N<br />
DP_DDI1_ML_C_P<br />
DP_DDI2_ML_C_N<br />
DP_DDI2_ML_C_P<br />
SMC_PECI_L<br />
PCIE_SSD_D2R_N<br />
PCIE_SSD_D2R_P<br />
P2MM<br />
SM<br />
1<br />
PP<br />
P2MM<br />
SM<br />
1<br />
PP<br />
P2MM<br />
SM<br />
1<br />
PP<br />
P2MM<br />
SM<br />
1<br />
PP<br />
P2MM<br />
SM<br />
1<br />
PP<br />
P2MM<br />
SM<br />
1P2MM<br />
PP<br />
SM<br />
1<br />
PP<br />
PP9901<br />
PP9902<br />
PP9903<br />
PP9904<br />
PP9918<br />
PP9910<br />
PP9911<br />
38<br />
38<br />
38<br />
38<br />
MIPIC_DATA_P<br />
MIPIC_DATA_N<br />
MIPIC_CLK_P<br />
MIPIC_CLK_N<br />
P2MM<br />
SM<br />
1<br />
PP<br />
P2MM<br />
SM<br />
1<br />
PP<br />
P2MM<br />
SM<br />
1<br />
PP<br />
P2MM<br />
SM<br />
1<br />
PP<br />
PP9949<br />
PP9950<br />
PP9951<br />
PP9952<br />
I241<br />
I240<br />
I239<br />
I238<br />
I237<br />
NO_TESTs<br />
NC_PCH_SLP_WLAN_L<br />
NC_SPI_CS1_L<br />
NC_SPI_CS2_L<br />
NC_SPI_CS1_L<br />
NC_SPI_CS2_L<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
102<br />
102<br />
102<br />
102<br />
102<br />
105<br />
105<br />
105<br />
105<br />
D<br />
C<br />
PP9933<br />
PP9934<br />
28 15<br />
28 15<br />
94 15<br />
94 15<br />
P2MM<br />
SM<br />
1<br />
PP<br />
P2MM<br />
SM<br />
1<br />
PP<br />
IN<br />
IN<br />
IN<br />
IN<br />
PCIE_TBT_X_D2R_N<br />
PCIE_TBT_X_D2R_P<br />
PCIE_TBT_T_D2R_N<br />
PCIE_TBT_T_D2R_P<br />
USB_CAMERA_DFR_N<br />
USB_CAMERA_DFR_P<br />
BI<br />
BI<br />
15<br />
15<br />
P2MM<br />
SM<br />
1P2MM<br />
PP<br />
SM<br />
1<br />
P2MM<br />
SM<br />
1P2MM<br />
PP<br />
SM<br />
1<br />
38<br />
38<br />
PP<br />
PP<br />
PP9919<br />
PP9920<br />
PP9927<br />
PP9928<br />
I110<br />
I109<br />
I88<br />
I87<br />
I86<br />
I85<br />
I84<br />
I83<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
TRUE<br />
MIPID_DATA_CONN_P<br />
MIPID_DATA_CONN_N<br />
MIPID_CLK_CONN_P<br />
MIPID_CLK_CONN_N<br />
MIPI_DATA_CONN_P<br />
MIPI_DATA_CONN_N<br />
MIPI_CLK_CONN_P<br />
MIPI_CLK_CONN_N<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
BI<br />
BI<br />
OUT<br />
OUT<br />
42 104<br />
42 104<br />
42 104<br />
42 104<br />
38 80 104<br />
38 80 104<br />
38 80 104<br />
38 80 104<br />
I236<br />
I235<br />
I234<br />
I233<br />
I232<br />
I231<br />
I230<br />
I229<br />
I228<br />
I227<br />
I226<br />
I225<br />
I224<br />
I223<br />
I222<br />
I267<br />
I266<br />
I265<br />
I264<br />
High Speed NO_TEST<br />
NC_PCIE_CAMERA_D2R_N<br />
NC_PCIE_CAMERA_D2R_P<br />
NC_PCIE_CAMERA_R2D_C_N<br />
NC_PCIE_CAMERA_R2D_C_P<br />
NC_PCIE_CLK100M_CAMERA_N<br />
NC_PCIE_CLK100M_CAMERA_P<br />
NC_PICCOLO_VEN2<br />
NO_TEST=1<br />
NC_PCIE_TBT_T_D2R_C_P<br />
NC_PCIE_TBT_T_D2R_C_N<br />
NC_PCIE_TBT_T_D2R_C_P<br />
NC_PCIE_TBT_T_D2R_C_N<br />
NC_PCIE_TBT_T_R2D_P<br />
NC_PCIE_TBT_T_R2D_N<br />
NC_PCIE_TBT_T_R2D_P<br />
NC_PCIE_TBT_T_R2D_N<br />
Unused nets with offpage<br />
NO_TEST=1<br />
NO_TEST=1<br />
PCIE_SSD_R2D_C_P 15 84 91<br />
PCIE_SSD_R2D_C_N<br />
TRUE<br />
15 84 91<br />
PCIE_SSD_D2R_P<br />
TRUE<br />
15 81 91 105<br />
PCIE_SSD_D2R_N<br />
TRUE<br />
15 81 91 105<br />
88<br />
TRUE<br />
102<br />
102<br />
102<br />
102<br />
102<br />
102<br />
94<br />
94<br />
94<br />
94<br />
94<br />
94<br />
94<br />
94<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
NO_TEST=1<br />
C<br />
(Nets with offpages not used on this project)<br />
I249<br />
BT_PWRRST_L<br />
6<br />
13<br />
B<br />
91 81<br />
91 81<br />
26 15<br />
26 15<br />
92 15<br />
92 15<br />
35 15<br />
35 15<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
OUT<br />
PCIE_CLK100M_SSD_LB_N<br />
PCIE_CLK100M_SSD_LB_P<br />
PCIE_CLK100M_TBT_X_N<br />
PCIE_CLK100M_TBT_X_P<br />
PCIE_CLK100M_TBT_T_N<br />
PCIE_CLK100M_TBT_T_P<br />
PCIE_CLK100M_AP_N<br />
PCIE_CLK100M_AP_P<br />
P2MM<br />
SM<br />
1P2MM<br />
PP<br />
SM<br />
1<br />
PP<br />
P2MM<br />
SM<br />
1P2MM<br />
PP<br />
SM<br />
1<br />
PP<br />
P2MM<br />
SM<br />
1<br />
PP<br />
P2MM<br />
SM<br />
1<br />
PP<br />
P2MM<br />
SM<br />
1<br />
PP<br />
P2MM<br />
SM<br />
1<br />
PP<br />
PP9941<br />
PP9942<br />
PP9943<br />
PP9944<br />
PP9945<br />
PP9946<br />
PP9947<br />
PP9948<br />
B<br />
I274<br />
I273<br />
I272<br />
I271<br />
60 13<br />
I269<br />
I270<br />
48<br />
13<br />
17<br />
17<br />
17<br />
17<br />
HDA_SDIN0<br />
LPC_CLK24M_SMC<br />
XDP_USB_EXTA_OC_L<br />
XDP_USB_EXTB_OC_L<br />
XDP_USB_EXTC_OC_L<br />
XDP_USB_EXTD_OC_L<br />
P2MM<br />
1<br />
SM<br />
PP<br />
P2MM<br />
1<br />
PP<br />
P2MM<br />
1<br />
SM<br />
SM<br />
PP<br />
P2MM<br />
1<br />
SM<br />
P2MM<br />
1<br />
SM<br />
PP9801<br />
PP9802<br />
PP9803<br />
PP9804<br />
PP9808<br />
PLACE_NEAR=U0500.BA21:6MM<br />
P2MM<br />
1<br />
PP<br />
PP<br />
SM<br />
PP<br />
PP9819<br />
A<br />
I268<br />
6<br />
XDP_BPM_L<br />
TP9<strong>820</strong><br />
1<br />
A<br />
TP-P5<br />
SYNC_MASTER=YHARTANTO_J44<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
ICT FCT 2<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
SYNC_DATE=12/18/2012<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
125 OF 145<br />
105 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
101<br />
54<br />
PP5V_S0<br />
104 80<br />
PP3V3_S0SW_LCD<br />
1<br />
2<br />
CC700<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC701<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC702<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC703<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC728<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
D<br />
PP1V8_S0SW_DFR<br />
104 42 37 104 80<br />
1<br />
2<br />
CC704<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC705<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC706<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
PP5V_S0SW_LCD<br />
1<br />
2<br />
CC729<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
D<br />
100<br />
PP3V3_G3H<br />
101<br />
PP3V3_S4<br />
1<br />
2<br />
CC707<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC730<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC731<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC732<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC733<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC734<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
101<br />
53<br />
PP3V3_S4<br />
1<br />
2<br />
CC708<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC709<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC710<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
101 38<br />
PP5V_S0<br />
1<br />
2<br />
CC735<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC736<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC737<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC738<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC739<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
C<br />
101<br />
53<br />
PP3V3_S4_BT<br />
1<br />
2<br />
CC711<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
100<br />
PP1V8_S0<br />
1<br />
2<br />
CC740<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC741<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC742<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
C<br />
101<br />
36<br />
PP3V3_S4<br />
53 36 35<br />
PP3V3_S4_WLAN_SW<br />
1<br />
2<br />
CC712<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC713<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC743<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC744<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
100<br />
19<br />
PP1V8_S0<br />
1<br />
2<br />
CC714<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
34<br />
TP_DPMUX_SAK_6<br />
1<br />
2<br />
CC749<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
101<br />
34<br />
PP3V3_S0<br />
B<br />
1<br />
2<br />
CC715<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC716<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC717<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC718<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
34<br />
TP_DPMUX_SAK_13<br />
1<br />
2<br />
CC750<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
B<br />
101<br />
56<br />
54<br />
PP3V3_S0<br />
1<br />
CC745<br />
12PF<br />
CC746<br />
12PF<br />
5%<br />
5%<br />
2<br />
25V<br />
NP0-C0G<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
0201<br />
1<br />
1<br />
2<br />
CC747<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC748<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
34 28<br />
DDI1_MUX_SEL<br />
1<br />
2<br />
CC751<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC752<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC753<br />
12PF<br />
5%<br />
25V<br />
NP0-C0G<br />
0201<br />
101<br />
61<br />
PP3V3_S0<br />
1<br />
2<br />
1<br />
2<br />
CC719<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
CC724<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
1<br />
2<br />
CC720<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
CC725<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
1<br />
2<br />
CC721<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
CC726<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC722<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
1<br />
2<br />
CC723<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
34 28<br />
DDI2_MUX_SEL<br />
1<br />
CC754<br />
12PF<br />
CC755<br />
12PF<br />
5%<br />
5%<br />
2<br />
25V<br />
NP0-C0G<br />
2<br />
25V<br />
NP0-C0G<br />
0201<br />
0201<br />
1<br />
A<br />
104 80 38<br />
PP5V_S0_ALSCAM_F<br />
1<br />
2<br />
CC727<br />
3.0PF<br />
+/-0.1PF<br />
25V<br />
NP0-C0G<br />
0201<br />
BOM_COST_GROUP=WIRELESS<br />
SYNC_MASTER=YHARTANTO_J44<br />
PAGE TITLE<br />
R<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
Desense Capacitors<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
IV ALL RIGHTS RESERVED<br />
Apple Inc.<br />
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8 7 6<br />
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8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
D<br />
D<br />
C<br />
C<br />
B<br />
B<br />
A<br />
SYNC_MASTER=J79_RIO<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
Empty<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
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8<br />
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6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
J79 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS<br />
D<br />
D<br />
C<br />
C<br />
B<br />
B<br />
A<br />
SYNC_MASTER=YHARTANTO_J44<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
PCB Rule Definitions<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
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TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
CPU Signal Constraints<br />
CPU Signal Properties<br />
PHYSICAL_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH<br />
MINIMUM NECK WIDTH<br />
MAXIMUM NECK LENGTH<br />
DIFFPAIR PRIMARY GAP<br />
CPU_45S * =45_OHM_SE =45_OHM_SE<br />
=45_OHM_SE<br />
=45_OHM_SE<br />
=STANDARD<br />
DIFFPAIR NECK GAP<br />
=STANDARD<br />
ELECTRICAL CONST SET<br />
NET TYPE<br />
PHYSICAL<br />
SPACING<br />
CPU_27P4S<br />
* =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE<br />
7 MIL<br />
7 MIL<br />
D<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
CPU_VCCSENSE * 25 MIL<br />
?<br />
CPU_08MIL<br />
*<br />
0.203 MM ?<br />
CPU_12MIL * 0.305 MM<br />
?<br />
CPU_18MIL * 0.457 MM<br />
?<br />
CPU_25MIL<br />
WEIGHT<br />
* 0.635 MM<br />
?<br />
D<br />
C<br />
C<br />
B<br />
B<br />
A<br />
SYNC_MASTER=YHARTANTO_J44<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
CPU Constraints<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
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5 4 3<br />
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TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
LPC Bus Constraints<br />
PHYSICAL_RULE_SET<br />
8<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH<br />
LPC_45S * =45_OHM_SE =45_OHM_SE<br />
=45_OHM_SE =45_OHM_SE<br />
=STANDARD<br />
CLK_LPC_45S * =45_OHM_SE =45_OHM_SE =45_OHM_SE<br />
=45_OHM_SE =STANDARD<br />
7<br />
MINIMUM NECK WIDTH<br />
MAXIMUM NECK LENGTH<br />
6<br />
DIFFPAIR PRIMARY GAP<br />
DIFFPAIR NECK GAP<br />
=STANDARD<br />
=STANDARD<br />
<br />
5<br />
PCH Net Properties<br />
ELECTRICAL CONST SET<br />
4<br />
NET TYPE<br />
PHYSICAL<br />
SPACING<br />
3<br />
2 1<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
LPC * 6 MIL ?<br />
D<br />
CLK_LPC * 8 MIL ?<br />
SMBus Interface Constraints<br />
D<br />
PHYSICAL_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH<br />
MINIMUM NECK WIDTH<br />
SMB_45S *<br />
=45_OHM_SE =45_OHM_SE =45_OHM_SE<br />
MAXIMUM NECK LENGTH<br />
=45_OHM_SE<br />
DIFFPAIR PRIMARY GAP<br />
=STANDARD<br />
DIFFPAIR NECK GAP<br />
=STANDARD<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
SMB * =2x_DIELECTRIC ?<br />
HD Audio Interface Constraints<br />
PHYSICAL_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH<br />
MINIMUM NECK WIDTH<br />
HDA_45S * =45_OHM_SE =45_OHM_SE<br />
=45_OHM_SE<br />
MAXIMUM NECK LENGTH<br />
=45_OHM_SE<br />
DIFFPAIR PRIMARY GAP<br />
=STANDARD<br />
DIFFPAIR NECK GAP<br />
=STANDARD<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
HDA * =2x_DIELECTRIC<br />
?<br />
SPI Interface Constraints<br />
C<br />
PHYSICAL_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
SPI_45S * =45_OHM_SE =45_OHM_SE<br />
=45_OHM_SE =45_OHM_SE<br />
=STANDARD<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
MINIMUM LINE WIDTH<br />
WEIGHT<br />
MINIMUM NECK WIDTH<br />
MAXIMUM NECK LENGTH<br />
DIFFPAIR PRIMARY GAP<br />
DIFFPAIR NECK GAP<br />
=STANDARD<br />
C<br />
SPI<br />
* 8 MIL<br />
?<br />
PCH Single Net Constraints<br />
PHYSICAL_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH<br />
MINIMUM NECK WIDTH<br />
PCH_45S * =45_OHM_SE =45_OHM_SE =45_OHM_SE<br />
MAXIMUM NECK LENGTH<br />
=45_OHM_SE<br />
DIFFPAIR PRIMARY GAP<br />
=STANDARD<br />
DIFFPAIR NECK GAP<br />
=STANDARD<br />
PCH_27P4S<br />
* =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE<br />
7 MIL<br />
7 MIL<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
PCH_12MIL<br />
PCH_15MIL<br />
* 0.381 MM<br />
PCH_18MIL *<br />
0.457 MM ?<br />
PCH_20MIL<br />
* 0.305 MM<br />
?<br />
* 0.508 MM<br />
?<br />
?<br />
B<br />
B<br />
A<br />
SYNC_MASTER=YHARTANTO_J44<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
PCH Constraints<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
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Apple Inc.<br />
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REVISION<br />
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PAGE<br />
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TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_ASSIGNMENT_HEAD<br />
TABLE_PHYSICAL_ASSIGNMENT_ITEM<br />
TABLE_PHYSICAL_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
Memory Bus Constraints<br />
Memory Net Properties<br />
Memory to Power Spacing<br />
PHYSICAL_RULE_SET<br />
MEM_40S<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH<br />
* =40_OHM_SE =40_OHM_SE<br />
MINIMUM NECK WIDTH<br />
=40_OHM_SE<br />
MAXIMUM NECK LENGTH<br />
=40_OHM_SE<br />
DIFFPAIR PRIMARY GAP<br />
=40_OHM_SE<br />
DIFFPAIR NECK GAP<br />
=40_OHM_SE<br />
ELECTRICAL CONST SET<br />
NET TYPE<br />
PHYSICAL<br />
SPACING<br />
NET_SPACING_TYPE1<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
SPACING_RULE_SET<br />
MEM_PWR MEM_* *<br />
MEM_2PWR<br />
MEM_45S *<br />
=45_OHM_SE<br />
=45_OHM_SE<br />
=45_OHM_SE<br />
=45_OHM_SE<br />
=45_OHM_SE<br />
=45_OHM_SE<br />
MEM_PWR *<br />
* DEFAULT<br />
D<br />
MEM_70D * =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF<br />
MEM_75D * =75_OHM_DIFF =75_OHM_DIFF =75_OHM_DIFF =75_OHM_DIFF =75_OHM_DIFF =75_OHM_DIFF<br />
MEM_80D * =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF<br />
Spacing Rule Sets<br />
=80_OHM_DIFF<br />
Memory to GND Spacing<br />
NET_SPACING_TYPE1<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
SPACING_RULE_SET<br />
GND MEM_* *<br />
MEM_2GND<br />
D<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
MEM_DATA2SELF<br />
MEM_DQS2OWNDATA<br />
* =4x_DIELECTRIC ?<br />
* =6x_DIELECTRIC ?<br />
MEM_CMD2CMD * =6x_DIELECTRIC ?<br />
MEM_CMD2CTL * =6x_DIELECTRIC ?<br />
MEM_DATA2SELF<br />
MEM_DQS2OWNDATA<br />
TOP,BOTTOM<br />
TOP,BOTTOM<br />
=10x_DIELECTRIC ?<br />
=10x_DIELECTRIC ?<br />
MEM_CMD2CMD TOP,BOTTOM =10x_DIELECTRIC ?<br />
MEM_CMD2CTL TOP,BOTTOM =10x_DIELECTRIC ?<br />
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET<br />
MEM_70D<br />
MEM_40S<br />
BGA_MEM<br />
BGA_MEM<br />
MEM_80D<br />
MEM_45S<br />
MEM_CTL2CTL * =6x_DIELECTRIC ?<br />
MEM_CTL2CTL<br />
TOP,BOTTOM =10x_DIELECTRIC ?<br />
MEM_CLK2CLK * =12x_DIELECTRIC ?<br />
MEM_CLK2CLK TOP,BOTTOM =16x_DIELECTRIC ?<br />
MEM_DATA2OTHERMEM<br />
* =16x_DIELECTRIC<br />
?<br />
MEM_2OTHERMEM<br />
TOP,BOTTOM<br />
=16x_DIELECTRIC ?<br />
MEM_2OTHERMEM *<br />
=8x_DIELECTRIC ?<br />
MEM_2PWR<br />
TOP,BOTTOM<br />
=8x_DIELECTRIC<br />
?<br />
MEM_2PWR * =4x_DIELECTRIC ?<br />
MEM_2GND TOP,BOTTOM =8x_DIELECTRIC ?<br />
MEM_2GND * =4x_DIELECTRIC ?<br />
MEM_2OTHER TOP,BOTTOM =20x_DIELECTRIC ?<br />
MEM_2OTHER * =12x_DIELECTRIC ?<br />
MEM_12MIL<br />
*<br />
0.305 MM<br />
?<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
C<br />
MEM_DATA2SELF_B<br />
MEM_DQS2OWNDATA_B<br />
MEM_CMD2CMD_B<br />
* =1.5x_DIELECTRIC<br />
*<br />
=1.5x_DIELECTRIC<br />
* =1.5x_DIELECTRIC<br />
?<br />
?<br />
?<br />
MEM_DATA2OTHERMEM_B<br />
MEM_2OTHERMEM_B<br />
MEM_2OTHER_B<br />
* =1.5x_DIELECTRIC ?<br />
*<br />
=1.5x_DIELECTRIC<br />
* =1.5x_DIELECTRIC<br />
?<br />
?<br />
C<br />
MEM_CMD2CTL_B<br />
* =1.5x_DIELECTRIC<br />
?<br />
MEM_CTL2CTL_B<br />
* =1.5x_DIELECTRIC<br />
?<br />
MEM_CLK2CLK_B<br />
* =1.5x_DIELECTRIC<br />
?<br />
Memory Bus Spacing Group Assignments<br />
NET_SPACING_TYPE1<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
SPACING_RULE_SET<br />
NET_SPACING_TYPE1<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
SPACING_RULE_SET<br />
MEM_*_DQBYTE_*<br />
*<br />
* MEM_2OTHER<br />
MEM_*_DQBYTE_* *<br />
BGA_MEM MEM_2OTHER_B<br />
MEM_*_DQS_*<br />
*<br />
*<br />
MEM_2OTHER<br />
MEM_*_DQS_* *<br />
BGA_MEM MEM_2OTHER_B<br />
MEM_CMD<br />
*<br />
*<br />
MEM_2OTHER<br />
MEM_CMD * BGA_MEM MEM_2OTHER_B<br />
MEM_CTL *<br />
*<br />
MEM_2OTHER<br />
MEM_CTL * BGA_MEM MEM_2OTHER_B<br />
MEM_CLK<br />
*<br />
*<br />
MEM_2OTHER<br />
MEM_CLK *<br />
BGA_MEM MEM_2OTHER_B<br />
MEM_*<br />
MEM_*<br />
*<br />
MEM_2OTHERMEM<br />
MEM_*<br />
MEM_* BGA_MEM MEM_2OTHERMEM_B<br />
NET_SPACING_TYPE1<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
SPACING_RULE_SET<br />
NET_SPACING_TYPE1<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
SPACING_RULE_SET<br />
B<br />
MEM_*_DQBYTE_* =SAME * MEM_DATA2SELF<br />
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET<br />
MEM_*_DQBYTE_* =SAME BGA_MEM MEM_DATA2SELF_B<br />
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET<br />
B<br />
MEM_*_DQBYTE_* MEM_* * MEM_DATA2OTHERMEM<br />
MEM_*_DQBYTE_* MEM_* BGA_MEM MEM_DATA2OTHERMEM_B<br />
NET_SPACING_TYPE1<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
SPACING_RULE_SET<br />
NET_SPACING_TYPE1<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
SPACING_RULE_SET<br />
MEM_CMD<br />
MEM_CMD<br />
*<br />
MEM_CMD2CMD<br />
MEM_CMD<br />
MEM_CMD<br />
BGA_MEM<br />
MEM_CMD2CMD_B<br />
MEM_CMD<br />
MEM_CTL<br />
*<br />
MEM_CMD2CTL<br />
MEM_CMD MEM_CTL<br />
BGA_MEM MEM_CMD2CTL_B<br />
MEM_CTL MEM_CTL<br />
*<br />
MEM_CTL2CTL<br />
MEM_CTL MEM_CTL<br />
BGA_MEM MEM_CTL2CTL_B<br />
MEM_CLK<br />
MEM_CLK *<br />
MEM_CLK2CLK<br />
MEM_CLK MEM_CLK BGA_MEM MEM_CLK2CLK_B<br />
NET_SPACING_TYPE1<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
SPACING_RULE_SET<br />
NET_SPACING_TYPE1<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
SPACING_RULE_SET<br />
MEM_A_DQS_0 MEM_A_DQBYTE_0 * MEM_DQS2OWNDATA<br />
MEM_A_DQS_0 MEM_A_DQBYTE_0 BGA_MEM<br />
MEM_DQS2OWNDATA_B<br />
MEM_A_DQS_1 MEM_A_DQBYTE_1 *<br />
MEM_DQS2OWNDATA<br />
MEM_A_DQS_1<br />
MEM_A_DQBYTE_1<br />
BGA_MEM<br />
MEM_DQS2OWNDATA_B<br />
MEM_A_DQS_2<br />
MEM_A_DQBYTE_2<br />
*<br />
MEM_DQS2OWNDATA<br />
MEM_A_DQS_2 MEM_A_DQBYTE_2 BGA_MEM MEM_DQS2OWNDATA_B<br />
MEM_A_DQS_3 MEM_A_DQBYTE_3 *<br />
MEM_DQS2OWNDATA<br />
MEM_A_DQS_3 MEM_A_DQBYTE_3 BGA_MEM<br />
MEM_DQS2OWNDATA_B<br />
MEM_A_DQS_4<br />
MEM_A_DQBYTE_4<br />
* MEM_DQS2OWNDATA<br />
MEM_A_DQS_4 MEM_A_DQBYTE_4 BGA_MEM<br />
MEM_DQS2OWNDATA_B<br />
MEM_A_DQS_5<br />
MEM_A_DQBYTE_5<br />
* MEM_DQS2OWNDATA<br />
MEM_A_DQS_5 MEM_A_DQBYTE_5 BGA_MEM MEM_DQS2OWNDATA_B<br />
A<br />
MEM_A_DQS_6 MEM_A_DQBYTE_6 *<br />
MEM_A_DQS_7 MEM_A_DQBYTE_7 *<br />
MEM_B_DQS_0<br />
MEM_B_DQS_1<br />
MEM_B_DQS_2<br />
MEM_B_DQBYTE_2 *<br />
MEM_DQS2OWNDATA<br />
MEM_DQS2OWNDATA<br />
MEM_DQS2OWNDATA<br />
MEM_B_DQS_3 MEM_B_DQBYTE_3 *<br />
MEM_DQS2OWNDATA<br />
MEM_B_DQS_4<br />
MEM_B_DQBYTE_0<br />
MEM_B_DQBYTE_1<br />
MEM_B_DQBYTE_4 *<br />
MEM_DQS2OWNDATA<br />
MEM_B_DQS_5 MEM_B_DQBYTE_5 * MEM_DQS2OWNDATA<br />
MEM_B_DQS_7 MEM_B_DQBYTE_7 * MEM_DQS2OWNDATA<br />
*<br />
*<br />
MEM_DQS2OWNDATA<br />
MEM_DQS2OWNDATA<br />
MEM_B_DQS_6 MEM_B_DQBYTE_6 * MEM_DQS2OWNDATA<br />
MEM_A_DQS_6 MEM_A_DQBYTE_6 BGA_MEM MEM_DQS2OWNDATA_B<br />
MEM_A_DQS_7 MEM_A_DQBYTE_7 BGA_MEM MEM_DQS2OWNDATA_B<br />
MEM_B_DQS_0 MEM_B_DQBYTE_0 BGA_MEM MEM_DQS2OWNDATA_B<br />
MEM_B_DQS_1 MEM_B_DQBYTE_1 BGA_MEM MEM_DQS2OWNDATA_B<br />
MEM_B_DQS_2 MEM_B_DQBYTE_2 BGA_MEM MEM_DQS2OWNDATA_B<br />
MEM_B_DQS_3 MEM_B_DQBYTE_3 BGA_MEM MEM_DQS2OWNDATA_B<br />
MEM_B_DQS_4 MEM_B_DQBYTE_4 BGA_MEM MEM_DQS2OWNDATA_B<br />
MEM_B_DQS_5 MEM_B_DQBYTE_5 BGA_MEM MEM_DQS2OWNDATA_B<br />
MEM_B_DQS_6 MEM_B_DQBYTE_6 BGA_MEM MEM_DQS2OWNDATA_B<br />
MEM_B_DQS_7 MEM_B_DQBYTE_7 BGA_MEM MEM_DQS2OWNDATA_B<br />
SYNC_MASTER=YHARTANTO_J44<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
Memory Constraints<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
SYNC_DATE=01/02/2013<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
133 OF 145<br />
111 OF 119<br />
SIZE<br />
D<br />
A
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
8<br />
7<br />
Thunderbolt, DP, HDMI Constraints<br />
Thunderbolt SPI Signal Constraints<br />
6<br />
<br />
5<br />
Thunderbolt, DP, HDMI Net Properties<br />
ELECTRICAL CONST SET<br />
4<br />
NET TYPE<br />
PHYSICAL<br />
SPACING<br />
3<br />
2 1<br />
PHYSICAL_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH<br />
MINIMUM NECK WIDTH<br />
MAXIMUM NECK LENGTH<br />
DIFFPAIR PRIMARY GAP<br />
DIFFPAIR NECK GAP<br />
TBT_SPI_45S<br />
* =45_OHM_SE<br />
=45_OHM_SE<br />
=45_OHM_SE<br />
=45_OHM_SE<br />
=STANDARD<br />
=STANDARD<br />
D<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
TBT_SPI * =2x_DIELECTRIC ?<br />
Thunderbolt & DisplayPort Constraints<br />
D<br />
PHYSICAL_RULE_SET<br />
TBTDP_85D<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH<br />
MINIMUM NECK WIDTH<br />
MAXIMUM NECK LENGTH<br />
DIFFPAIR PRIMARY GAP<br />
* =85_OHM_DIFF =85_OHM_DIFF<br />
=85_OHM_DIFF<br />
=85_OHM_DIFF<br />
=85_OHM_DIFF<br />
DIFFPAIR NECK GAP<br />
=85_OHM_DIFF<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
TBTDP_2SAME * =3X_DIELECTRIC ?<br />
TBTDP_2SAME TOP,BOTTOM =4x_DIELECTRIC<br />
?<br />
TBTDP_TXRX * =6X_DIELECTRIC ?<br />
TBTDP_TXRX TOP,BOTTOM =10X_DIELECTRIC<br />
?<br />
TBTDP_2OTHER * =4X_DIELECTRIC ?<br />
TBTDP_2OTHER TOP,BOTTOM =6X_DIELECTRIC<br />
?<br />
NET_SPACING_TYPE1<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
SPACING_RULE_SET<br />
TBTDP_*<br />
*<br />
*<br />
TBTDP_2OTHER<br />
TBTDP_*<br />
=SAME<br />
*<br />
TBTDP_2SAME<br />
TBTDP_TX<br />
*_RX<br />
*<br />
TBTDP_TXRX<br />
TBTDP_RX<br />
*_TX<br />
*<br />
TBTDP_TXRX<br />
C<br />
DisplayPort & HDMI Constraints<br />
PHYSICAL_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH<br />
MINIMUM NECK WIDTH<br />
MAXIMUM NECK LENGTH<br />
DIFFPAIR PRIMARY GAP<br />
DIFFPAIR NECK GAP<br />
C<br />
DP_85D<br />
*<br />
=85_OHM_DIFF<br />
=85_OHM_DIFF<br />
=85_OHM_DIFF<br />
=85_OHM_DIFF<br />
=85_OHM_DIFF<br />
=85_OHM_DIFF<br />
HDMI_85D<br />
*<br />
=85_OHM_DIFF<br />
=85_OHM_DIFF<br />
=85_OHM_DIFF<br />
=85_OHM_DIFF<br />
=85_OHM_DIFF<br />
=85_OHM_DIFF<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
DP_2SAME<br />
*<br />
=3x_DIELECTRIC<br />
?<br />
DP_2SAME TOP,BOTTOM =4x_DIELECTRIC<br />
?<br />
DP_2OTHER *<br />
=4x_DIELECTRIC ?<br />
DP_2OTHER TOP,BOTTOM =6x_DIELECTRIC<br />
?<br />
HDMICLK_2OTHER *<br />
=7x_DIELECTRIC<br />
?<br />
HDMICLK_2OTHER TOP,BOTTOM =10x_DIELECTRIC<br />
?<br />
HDMICLK_2DPHDMI *<br />
=4x_DIELECTRIC<br />
?<br />
HDMICLK_2DPHDMI TOP,BOTTOM =6x_DIELECTRIC<br />
?<br />
HDMIDATA_2SAME *<br />
=3x_DIELECTRIC<br />
?<br />
HDMIDATA_2SAME TOP,BOTTOM =4x_DIELECTRIC<br />
?<br />
HDMIDATA_2OTHER *<br />
=4x_DIELECTRIC<br />
?<br />
HDMIDATA_2OTHER TOP,BOTTOM =6x_DIELECTRIC<br />
?<br />
NET_SPACING_TYPE1<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
SPACING_RULE_SET<br />
NET_SPACING_TYPE1<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
SPACING_RULE_SET<br />
HDMI_DATA<br />
*<br />
*<br />
HDMIDATA_2OTHER<br />
DISPLAYPORT *<br />
*<br />
DP_2OTHER<br />
HDMI_DATA<br />
=SAME<br />
*<br />
HDMIDATA_2SAME<br />
DISPLAYPORT =SAME * DP_2SAME<br />
HDMI_DATA<br />
TBTDP_TX<br />
*<br />
HDMIDATA_2SAME<br />
DISPLAYPORT<br />
HDMI_DATA<br />
*<br />
DP_2SAME<br />
HDMI_DATA<br />
TBTDP_RX<br />
*<br />
TBTDP_TXRX<br />
DISPLAYPORT TBTDP_TX * DP_2SAME<br />
B<br />
HDMI_CLK<br />
HDMI_CLK<br />
*<br />
HDMI_DATA<br />
*<br />
*<br />
HDMICLK_2OTHER<br />
HDMICLK_2DPHDMI<br />
DISPLAYPORT TBTDP_RX * TBTDP_TXRX<br />
B<br />
HDMI_CLK<br />
DISPLAYPORT<br />
*<br />
HDMICLK_2DPHDMI<br />
HDMI_CLK<br />
TBTDP_TX<br />
*<br />
HDMICLK_2DPHDMI<br />
A<br />
SYNC_MASTER=J79_JACK<br />
TBT DP HDMI Constraints<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
SYNC_DATE=05/19/2015<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
134 OF 145<br />
112 OF 119<br />
SIZE<br />
D<br />
A
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
PCI Express Constraints<br />
PHYSICAL_RULE_SET<br />
PCIE_85D<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH<br />
MINIMUM NECK WIDTH<br />
MAXIMUM NECK LENGTH<br />
DIFFPAIR PRIMARY GAP<br />
* =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF<br />
DIFFPAIR NECK GAP<br />
=85_OHM_DIFF<br />
PCI Express Properties<br />
ELECTRICAL CONST SET<br />
NET TYPE<br />
PHYSICAL<br />
SPACING<br />
CLK_PCIE_85D<br />
* =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF<br />
D<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
PCIE_2SAME * =3X_DIELECTRIC ?<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
PCIE_2SAME TOP,BOTTOM =4X_DIELECTRIC ?<br />
D<br />
PCIE_TXRX * =6X_DIELECTRIC ?<br />
PCIE_TXRX TOP,BOTTOM =10X_DIELECTRIC ?<br />
PCIE_2OTHER<br />
*<br />
=4X_DIELECTRIC ?<br />
PCIE_2OTHER<br />
TOP,BOTTOM<br />
=6X_DIELECTRIC<br />
?<br />
PCIE_2CLK * =7X_DIELECTRIC ?<br />
PCIE_2CLK TOP,BOTTOM =10X_DIELECTRIC ?<br />
PCIECLK_2OTHER<br />
*<br />
=7X_DIELECTRIC ?<br />
PCIECLK_2OTHER TOP,BOTTOM =10X_DIELECTRIC ?<br />
NET_SPACING_TYPE1<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
SPACING_RULE_SET<br />
PCIE_* *<br />
PCIE_*<br />
=SAME<br />
PCIE_*<br />
CLK_*<br />
CLK_PCIE *<br />
PCIE_TX<br />
*_RX<br />
PCIE_RX<br />
*_TX<br />
*<br />
*<br />
*<br />
*<br />
PCIE_2OTHER<br />
PCIE_2SAME<br />
PCIE_2CLK<br />
PCIECLK_2OTHER<br />
* PCIE_TXRX<br />
* PCIE_TXRX<br />
C<br />
C<br />
B<br />
B<br />
A<br />
SYNC_MASTER=J79_JACK<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
PCIe Constraints<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
SYNC_DATE=05/19/2015<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
135 OF 145<br />
113 OF 119<br />
SIZE<br />
D<br />
A
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
USB 2 Interface Constraints<br />
USB Constraints<br />
PHYSICAL_RULE_SET<br />
PCH_USB_RBIAS<br />
LAYER<br />
*<br />
ALLOW ROUTE<br />
ON LAYER?<br />
=STANDARD<br />
MINIMUM LINE WIDTH<br />
=STANDARD<br />
MINIMUM NECK WIDTH<br />
=STANDARD<br />
MAXIMUM NECK LENGTH<br />
=STANDARD<br />
DIFFPAIR PRIMARY GAP<br />
=STANDARD<br />
DIFFPAIR NECK GAP<br />
=STANDARD<br />
ELECTRICAL CONST SET<br />
NET TYPE<br />
PHYSICAL<br />
SPACING<br />
USB_85D<br />
*<br />
=85_OHM_DIFF<br />
=85_OHM_DIFF<br />
=85_OHM_DIFF<br />
=85_OHM_DIFF<br />
=85_OHM_DIFF<br />
=85_OHM_DIFF<br />
D<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
USB * =4X_DIELECTRIC ?<br />
USB_RBIAS * =6X_DIELECTRIC ?<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
USB TOP,BOTTOM =6X_DIELECTRIC ?<br />
USB_RBIAS TOP,BOTTOM =10X_DIELECTRIC ?<br />
D<br />
USB 3 Interface Constraints<br />
PHYSICAL_RULE_SET<br />
USB3_85D<br />
LAYER<br />
*<br />
ALLOW ROUTE<br />
ON LAYER?<br />
=85_OHM_DIFF<br />
MINIMUM LINE WIDTH<br />
=85_OHM_DIFF<br />
MINIMUM NECK WIDTH<br />
=85_OHM_DIFF<br />
MAXIMUM NECK LENGTH<br />
=85_OHM_DIFF<br />
DIFFPAIR PRIMARY GAP<br />
=85_OHM_DIFF<br />
DIFFPAIR NECK GAP<br />
=85_OHM_DIFF<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
USB3_2SAME<br />
*<br />
=3X_DIELECTRIC<br />
?<br />
USB3_2SAME TOP,BOTTOM =4x_DIELECTRIC ?<br />
USB3_TXRX<br />
*<br />
=6X_DIELECTRIC<br />
?<br />
USB3_TXRX TOP,BOTTOM =10X_DIELECTRIC ?<br />
USB3_2OTHER * =4X_DIELECTRIC ?<br />
USB3_2OTHER TOP,BOTTOM =6X_DIELECTRIC ?<br />
NET_SPACING_TYPE1<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
SPACING_RULE_SET<br />
C<br />
USB3_*<br />
USB3_*<br />
* * USB3_2OTHER<br />
=SAME<br />
* USB3_2SAME<br />
C<br />
USB3_TX<br />
*_RX<br />
* USB3_TXRX<br />
USB3_RX<br />
*_TX<br />
* USB3_TXRX<br />
System Clock Signal Constraints<br />
PHYSICAL_RULE_SET<br />
LAYER<br />
ALLOW ROUTE<br />
ON LAYER?<br />
MINIMUM LINE WIDTH<br />
MINIMUM NECK WIDTH<br />
MAXIMUM NECK LENGTH<br />
DIFFPAIR PRIMARY GAP<br />
CLK_25M_45S * =45_OHM_SE =45_OHM_SE<br />
=45_OHM_SE =45_OHM_SE =STANDARD<br />
DIFFPAIR NECK GAP<br />
=STANDARD<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
CLK_25M * =5x_DIELECTRIC ?<br />
B<br />
B<br />
SATA Interface Constraints (Not Used)<br />
PHYSICAL_RULE_SET<br />
SATA_85D<br />
LAYER<br />
*<br />
ALLOW ROUTE<br />
ON LAYER?<br />
=85_OHM_DIFF<br />
MINIMUM LINE WIDTH<br />
=85_OHM_DIFF<br />
MINIMUM NECK WIDTH<br />
=85_OHM_DIFF<br />
MAXIMUM NECK LENGTH<br />
=85_OHM_DIFF<br />
DIFFPAIR PRIMARY GAP<br />
=85_OHM_DIFF<br />
DIFFPAIR NECK GAP<br />
=85_OHM_DIFF<br />
SATA_45SE<br />
*<br />
=45_OHM_SE<br />
=45_OHM_SE<br />
=45_OHM_SE<br />
=45_OHM_SE<br />
=45_OHM_SE<br />
=45_OHM_SE<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
SATA_2SAME<br />
*<br />
=3X_DIELECTRIC ?<br />
SATA_2SAME<br />
TOP,BOTTOM<br />
=4x_DIELECTRIC<br />
?<br />
SATA_TXRX<br />
*<br />
=6X_DIELECTRIC ?<br />
SATA_TXRX<br />
TOP,BOTTOM<br />
=10X_DIELECTRIC<br />
?<br />
SATA_2OTHER<br />
*<br />
=4X_DIELECTRIC ?<br />
SATA_2OTHER<br />
TOP,BOTTOM<br />
=6X_DIELECTRIC<br />
?<br />
NET_SPACING_TYPE1<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
SPACING_RULE_SET<br />
A<br />
SATA_* * * SATA_2OTHER<br />
SATA_* =SAME * SATA_2SAME<br />
SATA_TX<br />
SATA_RX<br />
*_RX * SATA_TXRX<br />
*_TX * SATA_TXRX<br />
SYNC_MASTER=J79_JACK<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
USB Constraints<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
SYNC_DATE=05/21/2015<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
136 OF 145<br />
114 OF 119<br />
SIZE<br />
D<br />
A
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
SMC SMBus & Charger Net Properties<br />
ELECTRICAL CONST SET<br />
NET TYPE<br />
PHYSICAL<br />
SPACING<br />
D<br />
D<br />
C<br />
C<br />
B<br />
B<br />
A<br />
SYNC_MASTER=YHARTANTO_J44<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
SMC Constraints<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
SYNC_DATE=01/02/2013<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
137 OF 145<br />
115 OF 119<br />
SIZE<br />
D<br />
A
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
Camera Net Properties<br />
3<br />
2 1<br />
ELECTRICAL CONST SET<br />
NET TYPE<br />
PHYSICAL<br />
SPACING<br />
MIPI Interface Constraints<br />
D<br />
PHYSICAL_RULE_SET<br />
MIPI_85D<br />
LAYER<br />
*<br />
ALLOW ROUTE<br />
ON LAYER?<br />
=85_OHM_DIFF<br />
MINIMUM LINE WIDTH<br />
=85_OHM_DIFF<br />
MINIMUM NECK WIDTH<br />
=85_OHM_DIFF<br />
MAXIMUM NECK LENGTH<br />
=85_OHM_DIFF<br />
DIFFPAIR PRIMARY GAP<br />
=85_OHM_DIFF<br />
DIFFPAIR NECK GAP<br />
=85_OHM_DIFF<br />
D<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
MIPI_2OTHER * =4X_DIELECTRIC ?<br />
MIPI_2OTHER TOP,BOTTOM =6X_DIELECTRIC ?<br />
MIPI_2CLK * =6X_DIELECTRIC ?<br />
MIPI_2CLK TOP,BOTTOM =8X_DIELECTRIC ?<br />
MIPICLK_2OTHER * =7X_DIELECTRIC ?<br />
MIPICLK_2OTHER TOP,BOTTOM =10X_DIELECTRIC ?<br />
NET_SPACING_TYPE1<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
SPACING_RULE_SET<br />
MIPI_DATA<br />
*<br />
*<br />
MIPI_2OTHER<br />
MIPI_DATA<br />
CLK_MIPI<br />
*<br />
MIPI_2CLK<br />
CLK_MIPI<br />
*<br />
*<br />
MIPICLK_2OTHER<br />
Memory Bus Constraints<br />
PHYSICAL_RULE_SET<br />
S2_MEM_45S<br />
S2_MEM_85D<br />
LAYER<br />
*<br />
*<br />
ALLOW ROUTE<br />
ON LAYER?<br />
=45_OHM_SE =45_OHM_SE<br />
=45_OHM_SE<br />
=45_OHM_SE<br />
=STANDARD =STANDARD<br />
=85_OHM_DIFF<br />
MINIMUM LINE WIDTH<br />
=85_OHM_DIFF<br />
MINIMUM NECK WIDTH<br />
=85_OHM_DIFF<br />
MAXIMUM NECK LENGTH<br />
=85_OHM_DIFF<br />
DIFFPAIR PRIMARY GAP<br />
=85_OHM_DIFF<br />
DIFFPAIR NECK GAP<br />
=85_OHM_DIFF<br />
C<br />
Spacing Rule Sets<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
C<br />
S2_DATA2SELF<br />
*<br />
=2x_DIELECTRIC<br />
?<br />
S2_DATA2SELF<br />
TOP,BOTTOM<br />
=4x_DIELECTRIC<br />
?<br />
S2_DQS2OWNDATA * =2x_DIELECTRIC ?<br />
S2_DQS2OWNDATA TOP,BOTTOM =4x_DIELECTRIC ?<br />
S2_CMD2CMD<br />
*<br />
=2x_DIELECTRIC<br />
?<br />
S2_CMD2CMD<br />
TOP,BOTTOM<br />
=4x_DIELECTRIC<br />
?<br />
S2_CMD2CTRL<br />
*<br />
=2x_DIELECTRIC<br />
?<br />
S2_CMD2CTRL<br />
TOP,BOTTOM<br />
=4x_DIELECTRIC<br />
?<br />
S2_CTRL2CTRL<br />
*<br />
=2x_DIELECTRIC<br />
?<br />
S2_CTRL2CTRL<br />
TOP,BOTTOM<br />
=4x_DIELECTRIC ?<br />
S2_2OTHERMEM<br />
*<br />
=4x_DIELECTRIC<br />
?<br />
S2_2OTHERMEM<br />
TOP,BOTTOM<br />
=6x_DIELECTRIC<br />
?<br />
S2MEM_2PWR<br />
*<br />
=2x_DIELECTRIC<br />
?<br />
S2MEM_2PWR<br />
TOP,BOTTOM<br />
=4x_DIELECTRIC<br />
?<br />
S2MEM_2GND<br />
*<br />
=2x_DIELECTRIC<br />
?<br />
S2MEM_2GND<br />
TOP,BOTTOM<br />
=4x_DIELECTRIC<br />
?<br />
S2MEM_2OTHER<br />
*<br />
=6x_DIELECTRIC<br />
?<br />
S2MEM_2OTHER<br />
TOP,BOTTOM<br />
=10x_DIELECTRIC<br />
?<br />
Memory Bus Spacing Group Assignments<br />
NET_SPACING_TYPE1<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
SPACING_RULE_SET<br />
NET_SPACING_TYPE1<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
SPACING_RULE_SET<br />
S2_MEM_DATA*<br />
*<br />
*<br />
S2MEM_2OTHER<br />
S2_MEM_DQS1<br />
S2_MEM_DATA1<br />
*<br />
S2_DQS2OWNDATA<br />
S2_MEM_DQS*<br />
*<br />
*<br />
S2MEM_2OTHER<br />
S2_MEM_DQS0<br />
S2_MEM_DATA0<br />
*<br />
S2_DQS2OWNDATA<br />
B<br />
S2_MEM_CMD<br />
S2_MEM_CTRL<br />
*<br />
*<br />
*<br />
*<br />
S2MEM_2OTHER<br />
S2MEM_2OTHER<br />
B<br />
S2_MEM_CLK<br />
S2_MEM_DATA*<br />
S2_MEM_CMD<br />
*<br />
=SAME<br />
S2_MEM_CMD<br />
*<br />
*<br />
*<br />
S2MEM_2OTHER<br />
S2_DATA2SELF<br />
S2_CMD2CMD<br />
Memory to Power Spacing<br />
S2_MEM_CMD<br />
S2_MEM_CTRL<br />
S2_MEM_*<br />
S2_MEM_CTRL<br />
S2_MEM_CTRL<br />
S2_MEM_*<br />
*<br />
*<br />
*<br />
S2_CMD2CTRL<br />
S2_CTRL2CTRL<br />
S2_2OTHERMEM<br />
NET_SPACING_TYPE1<br />
S2_MEM_PWR<br />
S2_MEM_PWR<br />
NET_SPACING_TYPE2<br />
S2_MEM_*<br />
*<br />
AREA_TYPE<br />
*<br />
*<br />
SPACING_RULE_SET<br />
S2MEM_2PWR<br />
DEFAULT<br />
Memory to GND Spacing<br />
NET_SPACING_TYPE1<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
SPACING_RULE_SET<br />
GND S2_MEM_* * S2MEM_2GND<br />
A<br />
SYNC_MASTER=YHARTANTO_J44<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
Camera Constraints<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
SYNC_DATE=01/09/2013<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
138 OF 145<br />
116 OF 119<br />
SIZE<br />
D<br />
A
TABLE_PHYSICAL_ASSIGNMENT_HEAD<br />
TABLE_PHYSICAL_ASSIGNMENT_ITEM<br />
TABLE_PHYSICAL_ASSIGNMENT_ITEM<br />
TABLE_PHYSICAL_ASSIGNMENT_ITEM<br />
TABLE_PHYSICAL_ASSIGNMENT_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_HEAD<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_SPACING_RULE_ITEM<br />
TABLE_PHYSICAL_ASSIGNMENT_HEAD<br />
TABLE_PHYSICAL_ASSIGNMENT_ITEM<br />
TABLE_PHYSICAL_ASSIGNMENT_ITEM<br />
TABLE_PHYSICAL_ASSIGNMENT_ITEM<br />
TABLE_PHYSICAL_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_HEAD<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_SPACING_ASSIGNMENT_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_HEAD<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
TABLE_PHYSICAL_RULE_ITEM<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
PHYSICAL_RULE_SET<br />
SENSE_45S<br />
DIG_AUDIO<br />
ANL_AUDIO<br />
LAYER<br />
*<br />
*<br />
ALLOW ROUTE<br />
ON LAYER?<br />
=1TO1_DIFFPAIR<br />
=1TO1_DIFFPAIR<br />
MINIMUM LINE WIDTH<br />
=1TO1_DIFFPAIR<br />
0.1 MM<br />
MINIMUM NECK WIDTH<br />
=1TO1_DIFFPAIR<br />
ANL_AUDIO_WIDE * =1TO1_DIFFPAIR 0.3 MM 0.3 MM 10 MM<br />
0.1 MM<br />
0.1 MM<br />
0.1 MM<br />
MAXIMUM NECK LENGTH<br />
THERM_45S * =1TO1_DIFFPAIR =45_OHM_SE<br />
=45_OHM_SE<br />
=45_OHM_SE<br />
=1TO1_DIFFPAIR<br />
10 MM<br />
DIFFPAIR PRIMARY GAP<br />
DIFFPAIR NECK GAP<br />
* =1TO1_DIFFPAIR =45_OHM_SE<br />
=45_OHM_SE<br />
=45_OHM_SE<br />
0.1 MM<br />
0.1 MM<br />
0.1 MM 0.1 MM<br />
0.1 MM 0.1 MM<br />
0.1 MM 0.1 MM<br />
J79 Specific Net Properties<br />
NET TYPE<br />
ELECTRICAL CONST SET<br />
PHYSICAL<br />
SPACING<br />
J79 Specific Net Properties<br />
ELECTRICAL CONST SET<br />
NET TYPE<br />
PHYSICAL<br />
SPACING<br />
D<br />
D<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
WEIGHT<br />
NET_SPACING_TYPE1<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
SPACING_RULE_SET<br />
SENSE<br />
* =2X_DIELECTRIC ?<br />
CPU_VCCSENSE<br />
GND *<br />
GND_P2MM<br />
THERM *<br />
=2X_DIELECTRIC<br />
?<br />
AUDIO<br />
*<br />
=2X_DIELECTRIC ?<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
GND *<br />
=STANDARD ?<br />
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING<br />
GND_P2MM<br />
PWR_P2MM<br />
*<br />
*<br />
0.20 MM<br />
0.20 MM<br />
WEIGHT<br />
WEIGHT<br />
1000<br />
1000<br />
NET_SPACING_TYPE1<br />
NET_SPACING_TYPE2<br />
AREA_TYPE<br />
CLK_PCIE GND<br />
*<br />
GND PCIE_*<br />
*<br />
GND_P2MM<br />
USB GND<br />
* GND_P2MM<br />
CLK_PCIE SB_POWER *<br />
SB_POWER SATA_*<br />
*<br />
USB SB_POWER<br />
*<br />
SPACING_RULE_SET<br />
GND_P2MM<br />
GND SATA_*<br />
* GND_P2MM<br />
PWR_P2MM<br />
PWR_P2MM<br />
PWR_P2MM<br />
C<br />
PHYSICAL_RULE_SET<br />
MEM_45S<br />
OVERRIDE<br />
MEM_40S<br />
OVERRIDE<br />
MEM_72D<br />
OVERRIDE<br />
MEM_85D<br />
OVERRIDE<br />
PCIE_85D<br />
OVERRIDE<br />
USB_85D<br />
LAYER<br />
*<br />
OVERRIDE<br />
*<br />
OVERRIDE<br />
*<br />
OVERRIDE<br />
*<br />
OVERRIDE<br />
*<br />
OVERRIDE<br />
TOP<br />
ALLOW ROUTE<br />
ON LAYER?<br />
OVERRIDE<br />
OVERRIDE<br />
OVERRIDE<br />
OVERRIDE<br />
OVERRIDE<br />
MINIMUM LINE WIDTH<br />
OVERRIDE<br />
OVERRIDE<br />
OVERRIDE<br />
OVERRIDE<br />
OVERRIDE<br />
MINIMUM NECK WIDTH MAXIMUM NECK LENGTH<br />
0.070 MM<br />
100 MIL<br />
OVERRIDE<br />
OVERRIDE<br />
0.090 MM<br />
100 MIL<br />
OVERRIDE<br />
OVERRIDE<br />
0.090 MM 100 MIL<br />
OVERRIDE<br />
OVERRIDE<br />
0.090 MM<br />
100 MIL<br />
OVERRIDE<br />
OVERRIDE<br />
0.090 MM<br />
10 MM<br />
OVERRIDE<br />
OVERRIDE<br />
0.100 MM<br />
500 MIL<br />
DIFFPAIR PRIMARY GAP<br />
OVERRIDE<br />
OVERRIDE<br />
OVERRIDE<br />
OVERRIDE<br />
OVERRIDE<br />
DIFFPAIR NECK GAP<br />
OVERRIDE<br />
OVERRIDE<br />
OVERRIDE<br />
OVERRIDE<br />
OVERRIDE<br />
C<br />
CPU_27P4S<br />
BOTTOM<br />
0.230 MM<br />
100 MIL<br />
USB3_85D<br />
TOP<br />
0.100 MM<br />
500 MIL<br />
USB3_85D<br />
ISL10<br />
0.075 MM<br />
0.090 MM<br />
DP_85D<br />
ISL9<br />
0.075 MM<br />
0.090 MM<br />
PCIE_85D<br />
ISL10<br />
0.075 MM<br />
0.090 MM<br />
B<br />
B<br />
DP, SATA, HDMI, PCIE CONSTRAINT RELAXATIONS<br />
Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)<br />
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET<br />
DP_85D<br />
BGA<br />
P65_BGA<br />
PCIE_85D<br />
BGA<br />
P65_BGA<br />
A<br />
CLK_PCIE_85D<br />
HDMI_85D<br />
BGA<br />
BGA<br />
P65_BGA<br />
P65_BGA<br />
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET<br />
SENSE_45S<br />
THERM_45S<br />
DIG_AUDIO<br />
ANL_AUDIO *<br />
*<br />
*<br />
*<br />
SENSE_45S<br />
THERM_45S<br />
DIG_AUDIO<br />
ANL_AUDIO<br />
SYNC_MASTER=YHARTANTO_J44<br />
PAGE TITLE<br />
Sensors & Audio Constraints<br />
R<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
IV ALL RIGHTS RESERVED<br />
Apple Inc.<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
SYNC_DATE=01/04/2013<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
139 OF 145<br />
117 OF 119<br />
SIZE<br />
D<br />
A<br />
8 7 6<br />
5 4 3<br />
2 1
8<br />
7<br />
6<br />
5<br />
4<br />
3<br />
2 1<br />
Change List:<br />
LOHWILL SCHEMATIC | PROTO 1A<br />
D<br />
Kismet:<br />
AFP://KISMET.APPLE.COM/KISMET-PROJECTS/LOHWILL<br />
D<br />
Useful Wiki Links:<br />
Schematic Conventions - https://hmts.ecs.apple.com/wiki/index.php/User:Wferry/SchConventions<br />
Schematic Design Wiki - https://hmts.ecs.apple.com/wiki/index.php/Schematic_Design<br />
C<br />
MobileMac HW Radar:<br />
MobileMac HW | Task<br />
MobileMac HW | Schematic<br />
MobileMac HW | New Bugs<br />
MobileMac HW | Layout<br />
MobileMac HW | Investigation<br />
MobileMac HW | Architecture<br />
Other Info:<br />
Page Allocations - 2015 Schematic Page Allocations<br />
Page Allocations - 2015 Schematic Page Allocations<br />
Page Allocations - 2015 Schematic Page Allocations<br />
Page Allocations - 2015 Schematic Page Allocations<br />
C<br />
B<br />
B<br />
A<br />
SYNC_MASTER=J79_RUENJOU_CONSTRAINTS<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
References<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
140 OF 145<br />
118 OF 119<br />
SYNC_DATE=06/11/2015<br />
SIZE<br />
D<br />
A
TABLE_ALT_HEAD<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_HEAD<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_HEAD<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
TABLE_ALT_ITEM<br />
8<br />
7<br />
6<br />
<br />
5<br />
4<br />
3<br />
2 1<br />
Alternate Parts<br />
D<br />
PART NUMBER<br />
107S00033 107S00034 ALL<br />
138S0738<br />
138S0846<br />
152S00359<br />
371S0704<br />
376S1053<br />
ALTERNATE FOR<br />
PART NUMBER<br />
138S1101<br />
138S0811<br />
152S00253<br />
371S00077<br />
376S0604<br />
BOM OPTION<br />
REF DES<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
COMMENTS:<br />
Samsung alt to Murata<br />
Samsung alt to Murata<br />
Chilisin alt to Cyntec<br />
NXP alt to Diodes<br />
Diodes alt to Fairchild<br />
BLC<br />
PART NUMBER<br />
197S00046<br />
197S00055<br />
197S00036<br />
197S00050<br />
ALL<br />
Epson w/ TXC<br />
197S00047 197S00036 ALL<br />
Kyocera w/ TXC<br />
197S00048<br />
197S00036<br />
ALL<br />
Murata w/ TXC<br />
197S00053 197S00050 ALL<br />
Kyocera w/ TXC<br />
197S00054<br />
ALTERNATE FOR<br />
PART NUMBER<br />
197S00050<br />
BOM OPTION<br />
REF DES<br />
ALL<br />
ALL<br />
COMMENTS:<br />
NDK w/ TXC<br />
Murata w/ TXC<br />
PART NUMBER<br />
138S00104<br />
311S00072<br />
353S00854<br />
377S0077<br />
ALTERNATE FOR<br />
PART NUMBER<br />
138S0978<br />
311S0657<br />
353S4342<br />
377S0183<br />
BOM OPTION<br />
REF DES<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
COMMENTS:<br />
Murata w/ Taiyo<br />
NXP w/ On Semi<br />
311S00090 311S00028<br />
ALL On Semi w/ TI<br />
TI w/ ST<br />
Infineon w/ ST<br />
D<br />
376S1106<br />
740S00027<br />
107S0249<br />
107S00015<br />
376S0678<br />
740S0159<br />
107S0251<br />
107S00011<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
107S00071 107S00053 ALL<br />
Fairchild alt to Vishay<br />
Bourns alt to Little Fuse<br />
311S0596 311S0593 ALL NXP w/ Diodes<br />
107S0276 107S00020 ALL Cyntec w/ TFT<br />
107S00021<br />
152S00343<br />
107S00087<br />
107S0284<br />
152S1682<br />
107S00029<br />
ALL<br />
ALL<br />
ALL<br />
TFT w/ Yageo<br />
NXP w/ Diodes<br />
TFT w/ Yageo<br />
138S0700 138S0641<br />
ALL Murata w/ SS&Taiyo<br />
152S00363<br />
376S00146<br />
152S00048 ALL Cyntec w/ Vishay<br />
155S0659 155S0382 ALL<br />
Murata w/ TDK<br />
376S1061 ALL NXP w/ Diodes<br />
128S0364<br />
128S0264<br />
ALL<br />
Kemet w/ Panasonic<br />
128S00058<br />
128S00018<br />
ALL<br />
NEC w/ Rohm<br />
128S0325<br />
128S0397<br />
ALL<br />
138S0706<br />
138S0739<br />
ALL<br />
NEC w/ Vishay<br />
128S00009<br />
128S00007<br />
ALL<br />
138S0945<br />
138S0739<br />
ALL<br />
NEC w/ Rohm<br />
C<br />
128S00029<br />
128S00070<br />
128S00010<br />
128S00031<br />
128S00026<br />
132S00064<br />
138S0863<br />
138S00084<br />
152S00369<br />
155S00188<br />
155S0694<br />
155S0660<br />
155S00007<br />
128S00007<br />
128S00007<br />
128S00011<br />
128S00011<br />
128S00011<br />
132S0409<br />
138S0853<br />
138S00060<br />
152S00268<br />
155S0275<br />
155S0387<br />
155S0513<br />
155S00018 155S0664 ALL<br />
Murata w/ Taiyo<br />
155S0667<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
138S0614 138S0578 ALL<br />
138S0703<br />
138S00032<br />
138S0648<br />
138S0831<br />
ALL<br />
ALL<br />
138S00049 138S0831 ALL<br />
ALL<br />
138S0775 138S0860 ALL<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
Cyntec w/ NEC<br />
Murata w/ Taiyo<br />
152S00358<br />
152S00400<br />
152S1872<br />
107S00086<br />
152S2052<br />
152S2015<br />
107S00101<br />
152S00361<br />
107S00056<br />
152S1954<br />
152S1958<br />
107S00005<br />
ALL<br />
ALL<br />
ALL<br />
TFT w/ Cyntec<br />
Taiyo w/ Cyntec<br />
Taiyo w/ Cyntec<br />
138S0789 138S0941 ALL<br />
Murata w/ SS<br />
ALL<br />
ALL<br />
Murata w/ Cyntec<br />
155S00034 155S0706<br />
ALL Taiyo w/ Murata<br />
353S00711<br />
740S00019<br />
155S00189<br />
138S0714<br />
138S0715<br />
138S0875<br />
138S0786<br />
107S00102<br />
152S00208<br />
152S00361<br />
353S2073<br />
740S00007<br />
155S0342<br />
138S0713<br />
138S0732<br />
138S0678<br />
138S0705<br />
107S00017<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
Murata w/ Chillisin<br />
Murata w/ Cyntec<br />
On Semi w/ TI<br />
Bourns w/ Polytronics<br />
Murata w/ Taiyo<br />
Murata w/ Samsung<br />
Murata w/ Samsung<br />
Taiyo w/ Mur&SS<br />
Murata w/ Samsung<br />
Cyntec w/ Yageo<br />
Cyntec w/ Yageo<br />
128S00062<br />
132S00012<br />
138S1103<br />
155S00203<br />
197S00082<br />
311S00060<br />
311S0271<br />
311S00104<br />
311S0437<br />
335S00213<br />
343S00136<br />
343S00137<br />
343S00138<br />
353S00880<br />
128S00067<br />
132S0401<br />
197S00081<br />
311S0273<br />
311S00008<br />
311S00091<br />
311S00112<br />
335S0888<br />
343S00135<br />
343S00135<br />
343S00135<br />
353S3452<br />
ALL<br />
128S00069 128S00067 ALL<br />
138S0660<br />
138S0684<br />
ALL<br />
ALL<br />
138S00097 138S0750 ALL<br />
138S00111<br />
138S0719<br />
138S00036<br />
155S0894<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
311S00118 311S0489 ALL<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
C<br />
155S0914<br />
155S00190<br />
311S00004<br />
311S00013<br />
353S00107<br />
155S0897<br />
155S0897<br />
311S0370<br />
311S0508<br />
353S3239<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
ALL<br />
NXP w/ Diodes<br />
107S00100<br />
107S00103<br />
107S00104<br />
107S00105<br />
152S00403<br />
107S00057<br />
ALL<br />
Cyntec w/ TFT<br />
107S00058<br />
ALL<br />
Cyntec w/ Yageo<br />
107S00061<br />
ALL<br />
Cyntec w/ Yageo<br />
107S00062<br />
ALL<br />
Cyntec w/ Yageo<br />
152S00322 ALL Murata w/ Chillisin<br />
353S00878 353S00599<br />
ALL<br />
353S00879 353S00754 ALL<br />
353S00750 353S00877 ALL<br />
371S00089 371S00085<br />
ALL<br />
377S0178<br />
377S00031<br />
ALL<br />
B<br />
353S00525<br />
372S0186<br />
353S4471<br />
372S0185<br />
ALL<br />
ALL<br />
B<br />
376S00014 376S0761 ALL<br />
376S00086<br />
376S0761<br />
ALL<br />
376S1080<br />
376S0<strong>820</strong><br />
ALL<br />
376S00074<br />
376S0855<br />
ALL<br />
376S1089<br />
376S1128<br />
ALL<br />
740S0144<br />
740S0118<br />
ALL<br />
740S00028<br />
740S0118<br />
ALL<br />
740S00003<br />
740S0135<br />
ALL<br />
998-04070 998-04071<br />
ALL<br />
Hynix alt to SS<br />
T208<br />
A<br />
SYNC_MASTER=J80_MLB<br />
Alternates BOM Table<br />
THE INFORMATION CONTAINED HEREIN IS THE<br />
PROPRIETARY PROPERTY OF APPLE INC.<br />
THE POSESSOR AGREES TO THE FOLLOWING:<br />
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE<br />
II NOT TO REPRODUCE OR COPY IT<br />
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART<br />
8 7 6<br />
5 4 3<br />
2 1<br />
PAGE TITLE<br />
IV ALL RIGHTS RESERVED<br />
R<br />
Apple Inc.<br />
NOTICE OF PROPRIETARY PROPERTY:<br />
DRAWING NUMBER<br />
REVISION<br />
BRANCH<br />
PAGE<br />
SHEET<br />
051-00777<br />
9.0.0<br />
dvt-fab09-0<br />
145 OF 145<br />
119 OF 119<br />
SYNC_DATE=12/12/2015<br />
SIZE<br />
D<br />
A
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