2.Digital Design with CPLD Applications _ VHDL - Dueck

Recommendations

Info

Answers to Selected Odd-Numbered Problems 7793.9 a. T U V W X0 0 0 0 10 0 0 1 10 0 1 0 10 0 1 1 10 1 0 0 10 1 0 1 10 1 1 0 10 1 1 1 11 0 0 0 11 0 0 1 11 0 1 0 11 0 1 1 11 1 0 0 11 1 0 1 01 1 1 0 11 1 1 1 1j.A B C D Y0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 00 1 0 0 00 1 0 1 00 1 1 0 00 1 1 1 01 0 0 0 01 0 0 1 01 0 1 0 01 0 1 1 01 1 0 0 11 1 0 1 01 1 1 0 11 1 1 1 0h.A B C Y0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 01 0 1 01 1 0 11 1 1 03.11 SOP: Y A B C A B C A B C A B CPOS: Y (A B C)(A B C)(A B C)(A B C)See Figure ANS3.11ABCi.A B C Y0 0 0 10 0 1 10 1 0 10 1 1 11 0 0 11 0 1 11 1 0 11 1 1 1Y (SOP)Y (POS)FIGURE ANS3.11
780 Answers to Selected Odd-Numbered Problems3.13 SOP: Y A B C A B C A B C A B C A B CPOS: Y (A B C)(A B C)(A B C)See Figure ANS3.133.29 Y A B C D A B C D BC3.31 Y A B C A B C A B D A DSee Figure ANS3.31.3.33 Y A B CD See Figure ANS3.33.ABCABCD00ABC0111ABD10001110010 0 0 0Y11ABC101 1 0 11 0 0 1ADFIGURE ANS3.31FIGURE ANS3.133.15 Y (A B)(A B) See Figure ANS3.15.3.35 Y AD BC See Figure ANS3.35.CDCDAB 00 01 11 10AB00010 0 1 01 1 1 1AB110010100 0 1 0Y (A B)(A B)FIGURE ANS3.333.37 Y AB C D AD CD. See Figure ANS3.37.FIGURE ANS3.15ABCD00011110BC3.17 Y (A B C)D AD BD CD3.19 a. Y AB C; b. Y C;c. J K; d. S 0;e. S T; f. Y B C D A B F C F3.21 a. Y A B;b. Y C D C D A B;c. K MN ML3.23 SOP: Y A C B C; POS: Y (A B)C3.25 Y AD BC3.27 Y AD CD BCD00011110FIGURE ANS3.350 0 1 10 0 0 0X X X X0 1 X XAD
Page 2 and 3:
CHAPTER1❘❙❚❘❙❚❘❙❚
Page 4 and 5:
1.2 • Digital Logic Levels 3FIGUR
Page 6 and 7:
1.3 • The Binary Number System 5t
Page 8 and 9:
1.3 • The Binary Number System 7S
Page 10 and 11:
1.3 • The Binary Number System 9
Page 12 and 13:
1.3 • The Binary Number System 11
Page 14 and 15:
1.4 • Hexadecimal Numbers 13❘
Page 16 and 17:
1.5 • Digital Waveforms 15❘❙
Page 18 and 19:
1.5 • Digital Waveforms 17Figure
Page 20 and 21:
1.5 • Digital Waveforms 19of the
Page 22 and 23:
Problems 21Continuous Smoothly conn
Page 24:
Answers To Section Review Problems
Page 27 and 28:
26 CHAPTER 2 • Logic Functions an
Page 29 and 30:
Page 31 and 32:
Page 33 and 34:
Page 35 and 36:
Page 37 and 38:
Page 39 and 40:
Page 41 and 42:
Page 43 and 44:
Page 45 and 46:
Page 47 and 48:
Page 49 and 50:
Page 51 and 52:
Page 53 and 54:
Page 55 and 56:
Page 58 and 59:
Page 60 and 61:
3.1 • Boolean Expressions, Logic
Page 62 and 63:
Page 64 and 65:
Page 66 and 67:
Page 68 and 69:
3.2 • Sum-of-Products and Product
Page 70 and 71:
Page 72 and 73:
Page 74 and 75:
3.3 • Theorems of Boolean Algebra
Page 76 and 77:
Page 78 and 79:
Page 80 and 81:
Page 82 and 83:
Page 84 and 85:
Page 86 and 87:
19. x x DeMorgan’s Theorems3.3
Page 88 and 89:
3.4 • Simplifying SOP and POS Exp
Page 90 and 91:
3.4 • Simplifying SOP and POS Exp
Page 92 and 93:
3.5 • Simplification by the Karna
Page 94 and 95:
Page 96 and 97:
Page 98 and 99:
Page 100 and 101:
Page 102 and 103:
Page 104 and 105:
Page 106 and 107:
Glossary 105For example, addition i
Page 108 and 109:
Problems 107bubble-to-bubble conven
Page 110 and 111:
Problems 1093.15 Write the POS form
Page 112 and 113:
Problems 1113.30 Use the rules of B
Page 114 and 115:
Problems 113A B C D Y0 0 0 0 10 0 0
Page 116 and 117:
Page 118 and 119:
4.1 • What Is a PLD? 117Let’s l
Page 120 and 121:
4.2 • Programming PLDs Using MAX+
Page 122 and 123:
4.3 • Graphic Design File 121In p
Page 124 and 125:
4.3 • Graphic Design File 123FIGU
Page 126 and 127:
4.3 • Graphic Design File 125FIGU
Page 128 and 129:
4.4 • Compiling MAX+PLUS II Files
Page 130 and 131:
4.5 • Hierarchial Design 129FIGUR
Page 132 and 133:
4.5 • Hierarchical Design 131FIGU
Page 134 and 135:
4.6 • Text Design File (VHDL) 133
Page 136 and 137:
Page 138 and 139:
Page 140 and 141:
Page 142 and 143:
4.7 • Creating a Physical Design
Page 144 and 145:
Page 146 and 147:
Page 148 and 149:
Page 150 and 151:
Glossary 149ote\maj_vote.sof. Click
Page 152 and 153:
Problems 151JTAG Chain Multiple JTA
Page 154:
Problems 153formation after the pow
Page 157 and 158:
156 CHAPTER 5 • Combinational Log
Page 159 and 160:
Page 161 and 162:
Page 163 and 164:
Page 165 and 166:
Page 167 and 168:
Page 169 and 170:
Page 171 and 172:
Page 173 and 174:
Page 175 and 176:
Page 177 and 178:
Page 179 and 180:
Page 181 and 182:
Page 183 and 184:
Page 185 and 186:
Page 187 and 188:
Page 189 and 190:
Page 191 and 192:
Page 193 and 194:
Page 195 and 196:
Page 197 and 198:
Page 199 and 200:
S 1D198 CHAPTER 5 • Combinational
Page 201 and 202:
Page 203 and 204:
Page 205 and 206:
Page 207 and 208:
Page 209 and 210:
Page 211 and 212:
Page 213 and 214:
Page 215 and 216:
Page 217 and 218:
Page 219 and 220:
Page 222 and 223:
Page 224 and 225:
6.1 • Digital Arithmetic 223Sum b
Page 226 and 227:
6.2 • Representing Signed Binary
Page 228 and 229:
6.3 • Signed Binary Arithmetic 22
Page 230 and 231:
Page 232 and 233:
Page 234 and 235:
6.4 • Hexadecimal Arithmetic 233M
Page 236 and 237:
6.5 • Numeric and Alphanumeric Co
Page 238 and 239:
6.5 • Numeric and Alphanumeric Co
Page 240 and 241:
6.6 • Binary Adders and Subtracto
Page 242 and 243:
Page 244 and 245:
Page 246 and 247:
Page 248 and 249:
Page 250 and 251:
Page 252 and 253:
Page 254 and 255:
Page 256 and 257:
Page 258 and 259:
Page 260 and 261:
6.7 • BCD Adders 259❘❙❚ SEC
Page 262 and 263:
6.7 • BCD Adders 261C 4 4 3 C 4
Page 264 and 265:
6.8 • Carry Generation in MAXPLUS
Page 266 and 267:
6.8 • Carry Generation in MAXPLUS
Page 268 and 269:
Summary 267❘❙❚❘❙❚❘❙
Page 270 and 271:
Glossary 269GLOSSARY1’s complemen
Page 272 and 273:
Problems 2716.10 Subtract the follo
Page 274:
Answers to Section Review Problems
Page 277 and 278:
276 CHAPTER 7 • Introduction to S
Page 279 and 280:
Page 281 and 282:
Page 283 and 284:
Page 285 and 286:
Page 287 and 288:
Page 289 and 290:
Page 291 and 292:
Page 293 and 294:
Page 295 and 296:
Page 297 and 298:
Page 299 and 300:
Page 301 and 302:
Page 303 and 304:
Page 305 and 306:
Page 307 and 308:
Page 309 and 310:
Page 311 and 312:
Page 313 and 314:
Page 315 and 316:
Page 317 and 318:
Page 319 and 320:
Page 321 and 322:
Page 323 and 324:
Page 325 and 326:
Page 327 and 328:
Page 330 and 331:
Page 332 and 333:
8.1 • Programmable Sum-of-Product
Page 334 and 335:
8.2 • PAL Fuse Matrix and Combina
Page 336 and 337:
8.2 • PAL Fuse Matrix and Combina
Page 338 and 339:
8.3 • PAL Outputs With Programmab
Page 340 and 341:
8.3 • PAL Outputs With Programmab
Page 342 and 343:
8.4 • PAL Devices With Registered
Page 344 and 345:
8.4 • PAL Devices With Registered
Page 346 and 347:
8.5 • Universal PAL and Generic A
Page 348 and 349:
Page 350 and 351:
Page 352 and 353:
8.6 • MAX7000S CPLD 351FIGURE 8.1
Page 354 and 355:
8.6 • MAX7000S CPLD 353The main s
Page 356 and 357:
8.7 • FLEX10K CPLD 355Table 8.2 T
Page 358 and 359:
8.7 • FLEX10K CPLD 357FIGURE 8.25
Page 360 and 361:
Summary 359Embedded Array Block (EA
Page 362 and 363:
Problems 361In-system programmabili
Page 364 and 365:
Page 366 and 367:
9.1 • Basic Concepts of Digital C
Page 368 and 369:
9.1 • Basic Concepts of Digital C
Page 370 and 371:
9.2 • Synchronous Counters 369Tab
Page 372 and 373:
9.2 • Synchronous Counters 371VCC
Page 374 and 375:
9.2 • Synchronous Counters 373K 0
Page 376 and 377:
9.2 • Synchronous Counters 375The
Page 378 and 379:
9.3 • Design of Synchronous Count
Page 380 and 381:
FIGURE 9.15K-Map Simplification of
Page 382 and 383:
Page 384 and 385:
Page 386 and 387:
9.4 • Programming Binary Counters
Page 388 and 389:
9.4 • Programming Binary Counters
Page 390 and 391:
9.5 • Control Options for Synchro
Page 392 and 393:
Page 394 and 395:
Page 396 and 397:
Page 398 and 399:
Page 400 and 401:
Page 402 and 403:
Page 404 and 405:
9.6 • Programming Presettable and
Page 406 and 407:
Page 408 and 409:
Page 410 and 411:
Page 412 and 413:
Page 414 and 415:
9.7 • Shift Registers 4139.7 Shif
Page 416 and 417:
9.7 • Shift Registers 415FIGURE 9
Page 418 and 419:
9.7 • Shift Registers 4171, above
Page 420 and 421:
9.7 • Shift Registers 419Data in0
Page 422 and 423:
9.7 • Shift Registers 421AND2OR2O
Page 424 and 425:
9.7 • Shift Registers 423AND2OR2O
Page 426 and 427:
S 1INPUTNOTINPUTS 0NOTPINPUT0PINPUT
Page 428 and 429:
9.8 • Programming Shift Registers
Page 430 and 431:
Page 432 and 433:
Page 434 and 435:
Page 436 and 437:
Page 438 and 439:
Page 440 and 441:
9.9 • Shift Register Counters 439
Page 442 and 443:
Page 444 and 445:
0 0 0 0Q 3 Q 2 Q 1 Q 0D Q D Q D Q D
Page 446 and 447:
Page 448 and 449:
Page 450 and 451:
Glossary 449e. Output decoding, whi
Page 452 and 453:
Problems 451CLKthe counter.)CTR DIV
Page 454 and 455:
Problems 453Table 9.20SequenceQ 3 Q
Page 456 and 457:
Problems 455FIGURE 9.91Problem 9.46
Page 458 and 459:
CHAPTER10❘❙❚❘❙❚❘❙
Page 460 and 461:
10.2 • State Machines with No Con
Page 462 and 463:
Page 464 and 465:
Page 466 and 467:
10.3 • State Machines with Contro
Page 468 and 469:
Page 470 and 471:
Page 472 and 473:
Page 474 and 475:
Page 476 and 477:
10.4 • Switch Debouncer for a Nor
Page 478 and 479:
Page 480 and 481:
4792digit_1@682digit_1@792digit_1@5
Page 482 and 483:
Page 484 and 485:
4832digit@682digit@792digit@582digi
Page 486 and 487:
10.5 • Unused States in State Mac
Page 488 and 489:
in1INPUTclkINPUTq 2 q 1 q 0AND3d 2D
Page 490 and 491:
10.6 • Unused States in State Mac
Page 492 and 493:
Traffic Light Controller 491Figure
Page 494 and 495:
Problems 493Moore machine A state m
Page 496 and 497:
Problems 495a. In the idle state, t
Page 498 and 499:
Page 500 and 501:
11.1 • Electrical Characteristics
Page 502 and 503:
11.1 • Electrical Characteristics
Page 504 and 505:
11.2 • Propagation Delay 503NOTEP
Page 506 and 507:
11.3 • Fanout 50511.3 FanoutKEY T
Page 508 and 509:
11.3 • Fanout 507Solution Since t
Page 510 and 511:
11.3 • Fanout 509www.electronicte
Page 512 and 513:
11.4 • Power Dissipation 511Power
Page 514 and 515:
11.4 • Power Dissipation 513Solut
Page 516 and 517:
11.5 • Noise Margin 515AAA 1 25 V
Page 518 and 519:
11.6 • Interfacing TTL and CMOS G
Page 520 and 521:
11.7 • Internal Circuitry of TTL
Page 522 and 523:
Page 524 and 525:
Page 526 and 527:
Page 528 and 529:
Page 530 and 531:
Page 532 and 533:
Page 534 and 535:
Page 536 and 537:
Page 538 and 539:
Page 540 and 541:
11.8 • Internal Circuitry of MOS
Page 542 and 543:
Page 544 and 545:
Page 546 and 547:
Page 548 and 549:
Page 550 and 551:
Page 552 and 553:
11.9 • TTL and CMOS Variations 55
Page 554 and 555:
Page 556 and 557:
Page 558 and 559:
Summary 557Devices from earlier CMO
Page 560 and 561:
Glossary 559p-channel enhancement-m
Page 562 and 563:
Problems 561Section 11.4 Power Diss
Page 564 and 565:
Answers to Section Review Problems
Page 566 and 567:
Page 568 and 569:
12.1 • Analog and Digital Signals
Page 570 and 571:
12.1 • Analog and Digital Signals
Page 572 and 573:
12.2 • Digital-to-Analog Conversi
Page 574 and 575:
Page 576 and 577:
Page 578 and 579:
Page 580 and 581:
Page 582 and 583:
Page 584 and 585:
Page 586 and 587:
Page 588 and 589:
Page 590 and 591:
Page 592 and 593:
12.3 • Analog-to-Digital Conversi
Page 594 and 595:
Page 596 and 597:
Page 598 and 599:
Page 600 and 601:
Page 602 and 603:
Page 604 and 605:
Page 606 and 607:
12.4 • Data Acquisition 605Anti-a
Page 608 and 609:
12.4 • Data Acquisition 607ADC080
Page 610 and 611:
12.4 • Data Acquisition 609FIGURE
Page 612 and 613:
12.4 • Data Acquisition 611Tfss=7
Page 614 and 615:
Summary 613FIGURE 12.46Simulation o
Page 616 and 617:
Problems 615GLOSSARYAliasing A phen
Page 618 and 619:
Problems 61712.20 Refer to the bipo
Page 620:
Answers 619ANSWERS TO SECTION REVIE
Page 623 and 624:
622 CHAPTER 13 • Memory Devices a
Page 625 and 626:
Page 627 and 628:
Page 629 and 630:
Page 631 and 632:
Page 633 and 634:
Page 635 and 636:
Page 637 and 638:
Page 639 and 640:
Page 641 and 642:
Page 643 and 644:
Page 645 and 646:
Page 647 and 648:
Page 649 and 650:
Page 651 and 652:
Page 653 and 654:
Page 655 and 656:
Page 658 and 659:
APPENDIX AAltera UP-1 User Guide❘
Page 660 and 661:
APPENDIX A • Altera UP-1 User Gui
Page 662 and 663:
Page 664 and 665:
Page 666 and 667:
Page 668 and 669:
Page 670 and 671:
Page 672 and 673:
Page 674 and 675:
Page 676 and 677:
Page 678 and 679:
Page 680 and 681:
Page 682 and 683:
Page 684 and 685:
Page 686 and 687:
Page 688 and 689:
Page 690 and 691:
APPENDIX B❘❙❚❘❙❚❘❙
Page 692 and 693:
APPENDIX B • VHDL Language Refere
Page 694 and 695:
Page 696 and 697:
Page 698 and 699:
Page 700 and 701:
Page 702:
Page 705 and 706:
APPENDIX C • Manufacturers’ Dat
Page 707 and 708:
Page 709 and 710:
Page 711 and 712:
Page 713 and 714:
Page 715 and 716:
Page 717 and 718:
Page 719 and 720:
Page 721 and 722:
Page 723 and 724:
Page 725 and 726:
Page 727 and 728:
Page 729 and 730:
Page 731 and 732: APPENDIX C • Manufacturers’ Dat
Page 769 and 770: APPENDIX D • Handling Precautions
Page 771 and 772: APPENDIX E • EPROM Data for a Dig
Page 778 and 779: Answersto Selected Odd-Numbered Pro
Page 780 and 781: Answers to Selected Odd-Numbered Pr
Page 816 and 817: DFFAND2CLOCKINPUTDPRNQNOTAND3OR2CLR
Page 824 and 825: FIGURE ANS9.47821
Page 832 and 833:
Answers to Selected Odd-Numbered Pr
Page 834 and 835:
Page 836 and 837:
Page 838 and 839:
Page 840:
show all

2.Digital Design with CPLD Applications _ VHDL - Dueck

Create successful ePaper yourself

Delete template?

Save as template?