082-Engineering-Mathematics-Anthony-Croft-Robert-Davison-Martin-Hargreaves-James-Flint-Edisi-5-2017

5.4 Boolean algebra 193
V DD
PMOS
Q1
D
D
PMOS
Q2
A
G
S
D
S
G
Y
G
S
D
NMOS
Q3
B
G
S
NMOS
Q4
0 V
Figure5.19
Internal construction ofasingle
CMOS NAND gate.
ThediagramshowstwoPMOStransistors,labelledQ1andQ2,connectedinparallel.
These are connected in series with two NMOS transistors, Q3 and Q4. There
arefoursourceterminalsalllabelledS,togetherwithfourdrainterminalslabelledD.
ThevoltageV DD
isthepositivevoltagesupplywhichisconnectedtothedrainonthe
fieldeffecttransistors.ThelabellingV DD
isaconventionoftenadoptedinthistypeof
circuit.Logiclevelsinacircuitlikethisarerepresentedbytakingalowvoltage,close
to 0V, to be a logic 0 and a high voltage, close toV DD
, to be a logic 1. The PMOS
transistors Q1 and Q2 each carry current between their source and drain terminals
only when a low voltage (logic 0) is connected at their gate terminal (labelled G).
The NMOS transistors Q3 and Q4 are a complementary type where current flows,
whichonlyoccurswhenahighvoltage,correspondingtologic1,ispresentedattheir
gates.ThuswhenbothAandBareatlogic0,Q1andQ2areswitchedonandQ3and
Q4 are switched off, hence the output isV DD
, which represents logic 1. This output
is still the same if either A or B, but not both, are at logic 1 because although Q3 or
Q4 will be turned on they are connected in series and individually have no effect. If
both A and B are at logic 1, then Q1 and Q2 are switched off, and Q3 and Q4 are
switched on, hence the output will be approximately 0V, which represents logic 0.
This behaviour isconsistentwith the truthtable given inTable 5.7.
All modern VLSI chips are designed using high-level design languages such as
VHDL(aspecializedcomputerlanguageforhardware)andthetransistordesignand
layoutisfullyautomated.Itisnowrarelynecessaryforthemicroprocessordesigner
toconsider individual transistors or even individual gates.
EXERCISES5.4
1 WriteBoolean expressionsforthe output,F,from the
electronic devices shown in Figure 5.20.
2 WriteBoolean expressionsforthe output from the
devices shown in Figure5.21.
3 Design electronic devices which produce the
following outputs:
(a) A +B (b) A·(B·C)
(d) A +B
(e)A·B+A ·B+B·C
(c) (C+D)·(A+B)