Acer Emachines E627 COMPAL LA-5481P HCWG0_H0 Rev1.0
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A
B
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D
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1 1
Compal Confidential
2 2
NCWG0/H0 Schematics Document
AMD S1g1 / RS780MN/ SB710
2009 / 06 / 24
LA-5481
3 3
Rev:1.0
4 4
A
B
Security Classification
Compal Secret Data
Issued Date
2005/03/08 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
C
401743
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 1 of
47
C
D
E
5
4
3
2
1
D
Compal confidential
Project Code: NCWG0/H0
File Name : LA-5481P
Thermal Sensor
Clock Generator
ADM1032ARM SLG8SP626
ICS9LPRS488BKLFT
page 8 page 17
AMD S1g1 CPU
638P PGA
page 6,7,8,9
DDRII
H_A#(3..31)
H_D#(0..63)
HT 16x16 1000MHZ
533/667/800
Dual Channel
DDRII-SO-DIMM X2
page 10,11
D
CRT
page 24
LCD CONN
page 25
ATI-RS780MN
465 BGA
page 12,13,14,15,16
PCIE X1
A-Link Express
4 x PCIE
USB 2.0
C
Mini card
WLAN
page 31
10/100 LAN
AR8114 / AR8132
page 26
RJ45 CONN
page 27
LPC BUS
ATI-SB710
549 BGA
page 18,19,20,21,22
HD Audio
SATA0
HDA Codec
ALC272
page 39
MDC Conn.
page 41
HDD Conn.
Camera
page 23
USB conn
X2
AMP & Audio Jack
page 40
TPA6017
CardReader
RTS5159
HeadPhone
Out
MIC In
C
B
Power On/Off CKT / LID switch / Power OK CKT
DC/DC Interface CKT. CIR/LED RTC CKT.
Power Circuit DC/DC
page 37
page 41 page 38
page 18
page 42~48
Touch Pad
CONN.
ENE KB926
Ver:D3
page 29
page 28
Int. KBD
page 29
SPI BIOS
page 30
SATA2
ODD Conn.
page 23
SATA1
SATA3
Second HDD/ODD
HDD Conn.
ODD Conn.
B
A
A
WWW.AliSaler.Com
5
4
Security Classification
Compal Secret Data
Issued Date
2009/03/08 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
401743 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 2 of
47
3
2
1
5
4
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2
1
Voltage Rails
STATE
Full ON
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
HIGH HIGH HIGH HIGH ON ON ON ON
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
D
C
VIN
B+
+CPU_CORE
+0.9V
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
0.9V switched power rail for DDR terminator
+1.2V_HT
1.2V switched power rail ON OFF
+1.5VS
1.5V switched power rail
ON OFF OFF
+1.8V 1.8V power rail for DDR ON
ON*
+1.8VS
1.8V switched power rail
OFF
+2.5VS
2.5V switched power rail
ON OFF OFF
+3VALW
3.3V always on power rail
ON ON ON*
+3VS
3.3V switched power rail
ON OFF OFF
+5VALW
5V always on power rail
ON ON ON*
+5VS
5V switched power rail
ON OFF OFF
+VSB
VSB always on power rail
ON ON ON*
+RTCVCC
RTC power
ON ON ON
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
LOW
LOW
LOW
LOW
LOW LOW LOW LOW
Board ID / SKU ID Table for AD channel
Vcc 3.3V +/- 5%
Ra/Rc/Re 100K +/- 5%
Board ID Rb / Rd / Rf VAD_BID min VAD_BID
typ VAD_BID max
0
0
0 V
0 V 0 V
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
2
3
4
18K +/- 5%
33K +/- 5%
56K +/- 5%
0.436 V
0.712 V
1.036 V
0.503 V
0.819 V
1.185 V
0.538 V
0.875 V
1.264 V
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
6
7
200K +/- 5%
NC
1.935 V
2.500 V
2.200 V
3.300 V
2.341 V
3.300 V
HIGH
LOW
HIGH
HIGH
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
D
C
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
BOARD ID Table
Board ID
0
1
2
3
4
5
6
7
PCB Revision
No Support VaryBright
Support VaryBright
BTO Option Table
BTO Item
BOM Structure
10/100 Lan 8114@
GIGA Lan 8132@
17" ID 17@
15" ID 15@
Support VaryBright
VARY@
B
B
EC SM Bus1 address
EC SM Bus2 address
PROJECT ID Table
Device
Address
Smart Battery 0001 011X b
SB600 SM Bus 1 address
Device
Address
Device
Address
ADM1032
1001 100X b
SB600 SM Bus 2 address
Device
Address
SKU ID
0
1
2
3
4
5
6
7
SKU
NCWG0
NAL00
NCWH0
Clock Generator
1101 001Xb
New Card
A
DDR DIMM0
1001 000Xb
A
DDR DIMM2
1001 010Xb
Wireless Lan
5
4
Security Classification
Compal Secret Data
Issued Date
2009/03/08 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
401743 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 3 of
47
3
2
1
5
4
3
2
1
DDR_A_CLK[1..2]
DIMMA
D
D
CPU CLK
200MHZ
CPU
S1G1
SOCKET
DDR_B_CLK[1..2]
DIMMB
H_CLKI[1:0]
Host Bus
H_CLKO[1:0]
C
SBLINK_CLK
100MHZ
C
14.31818MHz
EXTERNAL
CLK GEN.
SLG8SP626 / ICS9LPRS488
NBSRC_CLK
100MHZ
HTREFCLK
66MHZ
ATI
NB
RS780MN
NB_OSC
14.318MHZ
B
CLK_14M_SB
14.318MHZ
B
SB_OSCIN
100MHZ
CLK_PCIE_MINI
100MHZ
CLK_PCIE_LAN
14.318MHZ
SBSRC_CLKP
100MHZ
CLK_48M_USB
48MHZ
RTC
ATI
SB
SB710
SATA
CLK_PCI_LPC
33MHZ
EC
ENE
KB926D3
A
Mini PCI Socket
Mini card
LAN
Atheros
AR8114/AR8132
32.768K Hz
25M Hz
32.768K Hz
A
WWW.AliSaler.Com
5
4
Security Classification
Compal Secret Data
Issued Date
2005/10/10 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
401743 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 4 of
47
3
2
1
5
4
3
2
1
D
AC ADAPTOR
19V 65W
BATTERY
11.1V
2.2Ah/6-cell
VIN
BATT+
PU17
BATTERY CHARGER
BQ24751ARHDR
B+
PU12
ISL6264CRZ-T
PU18
ISL6228HRTZ-T
AMD CPU
S1G1 socket
+2.5VS
PU21
APL5915KAI
VDDA 2.5V
+CPU_CORE 0.9V
VDD 0.95V
+NB_CORE
+1.2VALW
+1.2VALW
U46
AO4430
+1.2V_HT
+1.8V
+0.9V
PU22
APL5331KAC
VDDIO
VTT
VLDT
1.8V
0.9V
1.2V
DDRII SODIMMX2
VDD_MEM
VTT_MEM
1.8V
0.9V
250 mA
24.5 A
3.6 A
1.75 A
500 mA
6.08 A
500 mA
D
C
PU19
TPS51117RGYR
PU16
ISL6237IRZ-T
+5VALW
+1.8V
+3VALW
+3VS
U41
AO4468
+3VS
+1.2VALW
+1.8V
PU20
APL5912
KAC-TRL
U37
AO4430
PU23
APL5915KAI
+1.5VS
+1.1VS
+1.8VS
+1.2VALW
NB
VDDC
RS780MN
1.0-1.1V
VDD_HT
PLLVDD
1.1V
VDDPCIE
VDDHTRX
VDDHTTX 1.2V
AVDDQ
AVDDDI
PLLVDD18
VDDA18HTPLL
VDDA18PCIE 1.8V
VDDA18PCIEPLL
VDD18
VDDLT18
VDDLTP18
AVDD
3.3V
VDD33
10 A
680 mA
65 mA
2.5 A
C 680 mA
400 mA
4 mA
20 mA
20 mA
20 mA
700 mA
120 mA
10 mA
300 mA
15 mA
110 mA
60 mA
B
A
LCD panel
15.6"
B+ 300mA
+3.3 350mA
U4
TPS2061DRG4
+USB_VCCA
USB X2
+5V
Dual
1.5A
5
Audio AMP
TPA6017A2
+5V 25mA
+5VS
FAN Control
APL5607
+5VS 500mA
Audio Codec
ALC272
+3VS
+5V 45mA
+3.3VS 25mA
U7
AO4468
Realtek
RTS5159
+3.3VS 300mA
4
+5VS
SATA
+5V 3A
+3.3V
EC
ENE KB926
+3.3VALW 30mA
+3.3VS 3mA
LAN
Atheros AR8114
+3.3VALW 201mA
Security Classification
Issued Date
Mini Card
+1.5VS 500mA
+3.3VS 1A
+3.3VALW 330mA
ICS9LPRS488B
+3.3V 400mA
+1.2V
+1.2V_HT
RTC
Bettary
Compal Secret Data
2009/3/8 Deciphered Date
2010/03/12
Title
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
401743 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 5 of
47
3
2
1
SB
VDD
S5_1.2V
AVDDCK_1.2V
CKVDD_1.2
PCIE_PVDD
PCIE_VDDR
AVDD_SATA
PLLVDD_SATA_1
AVDDC
AVDD TX/RX
VDDQ
VDD33_18
SB710
USB_PHY_1.2V
S5_3.3V
AVDDCK_3.3V
XTLVDD_SATA
VBAT
1.2V
3.3V
Compal Electronics, Inc.
3V
510mA
113 mA
197 mA
62 mA
43 mA
600 mA
567 mA
93 mA
32 mA
17 mA
658 mA
131 mA
71 mA
47 mA
6 mA
B
A
5
4
3
2
1
D
<12> H_CADIP[0..15]
<12> H_CADIN[0..15]
H_CADIP[0..15]
H_CADIN[0..15]
H_CADOP[0..15]
H_CADON[0..15]
H_CADOP[0..15] <12>
H_CADON[0..15] <12>
D
+1.2V_HT
D4
VLDT=500mA D3
D2
D1
VLDT_A3
VLDT_A2
VLDT_A1
VLDT_A0
JCPU1A
VLDT_B3
VLDT_B2
VLDT_B1
VLDT_B0
AE5
AE4
AE3
AE2
1 2
C84
4.7U_0805_10V4Z
C
B
check AMD
<12> H_CLKIP1
<12> H_CLKIN1
<12> H_CLKIP0
<12> H_CLKIN0
H_CADIP15 N5
H_CADIN15
L0_CADIN_H15
P5
H_CADIP14
L0_CADIN_L15
M3
H_CADIN14
L0_CADIN_H14
M4
H_CADIP13
L0_CADIN_L14
L5
H_CADIN13
L0_CADIN_H13
M5
H_CADIP12
L0_CADIN_L13
K3
H_CADIN12
L0_CADIN_H12
K4
H_CADIP11
L0_CADIN_L12
H3
H_CADIN11
L0_CADIN_H11
H4
H_CADIP10
L0_CADIN_L11
G5
H_CADIN10
L0_CADIN_H10
H5
H_CADIP9
L0_CADIN_L10
F3
H_CADIN9
L0_CADIN_H9
F4
H_CADIP8
L0_CADIN_L9
E5
H_CADIN8
L0_CADIN_H8
F5
H_CADIP7
L0_CADIN_L8
N3
H_CADIN7
L0_CADIN_H7
N2
H_CADIP6
L0_CADIN_L7
L1
H_CADIN6
L0_CADIN_H6
M1
H_CADIP5
L0_CADIN_L6
L3
H_CADIN5
L0_CADIN_H5
L2
H_CADIP4
L0_CADIN_L5
J1
H_CADIN4
L0_CADIN_H4
K1
H_CADIP3
L0_CADIN_L4
G1
H_CADIN3
L0_CADIN_H3
H1
H_CADIP2
L0_CADIN_L3
G3
H_CADIN2
L0_CADIN_H2
G2
H_CADIP1
L0_CADIN_L2
E1
H_CADIN1
L0_CADIN_H1
F1
H_CADIP0
L0_CADIN_L1
E3
H_CADIN0
L0_CADIN_H0
E2
L0_CADIN_L0
J5
L0_CLKIN_H1
K5
L0_CLKIN_L1
J3
L0_CLKIN_H0
J2
L0_CLKIN_L0
H_CADOP15
L0_CADOUT_H15
T4
H_CADON15
L0_CADOUT_L15
T3
H_CADOP14
L0_CADOUT_H14
V5
H_CADON14
L0_CADOUT_L14
U5
H_CADOP13
L0_CADOUT_H13
V4
H_CADON13
L0_CADOUT_L13
V3
H_CADOP12
L0_CADOUT_H12
Y5
H_CADON12
L0_CADOUT_L12
W5
H_CADOP11
L0_CADOUT_H11
AB5
H_CADON11
L0_CADOUT_L11
AA5
H_CADOP10
L0_CADOUT_H10
AB4
H_CADON10
L0_CADOUT_L10
AB3
H_CADOP9
L0_CADOUT_H9
AD5
H_CADON9
L0_CADOUT_L9
AC5
H_CADOP8
L0_CADOUT_H8
AD4
H_CADON8
L0_CADOUT_L8
AD3
H_CADOP7
L0_CADOUT_H7
T1
H_CADON7
L0_CADOUT_L7
R1
H_CADOP6
L0_CADOUT_H6
U2
H_CADON6
L0_CADOUT_L6
U3
H_CADOP5
L0_CADOUT_H5
V1
H_CADON5
L0_CADOUT_L5
U1
H_CADOP4
L0_CADOUT_H4
W2
H_CADON4
L0_CADOUT_L4
W3
H_CADOP3
L0_CADOUT_H3
AA2
H_CADON3
L0_CADOUT_L3
AA3
H_CADOP2
L0_CADOUT_H2
AB1
H_CADON2
L0_CADOUT_L2
AA1
H_CADOP1
L0_CADOUT_H1
AC2
H_CADON1
L0_CADOUT_L1
AC3
H_CADOP0
L0_CADOUT_H0
AD1
H_CADON0
L0_CADOUT_L0
AC1
L0_CLKOUT_H1
Y4
L0_CLKOUT_L1
Y3
L0_CLKOUT_H0
Y1
L0_CLKOUT_L0
W1
H_CLKOP1 <12>
H_CLKON1 <12>
H_CLKOP0 <12>
H_CLKON0 <12>
H_CTLIP1_R
H_CTLOP1_R
<12> H_CTLIP1
1 2
P3
H_CTLIN1_R
L0_CTLIN_H1 L0_CTLOUT_H1
T5
1 2
H_CTLOP1 <12>
R45
H_CTLON1_R
<12> H_CTLIN1
1 2
0_0402_5%
P4
L0_CTLIN_L1 L0_CTLOUT_L1
R5
R41 1 2
0_0402_5%
H_CTLON1 <12>
R46
0_0402_5%
R44
0_0402_5%
H_CTLIP0
H_CTLOP0
<12> H_CTLIP0
N1
H_CTLOP0 <12>
H_CTLIN0
L0_CTLIN_H0 L0_CTLOUT_H0
R2
H_CTLON0
<12> H_CTLIN0
P1
L0_CTLIN_L0 L0_CTLOUT_L0
R3
H_CTLON0 <12>
FOX_PZ63823-284S-41F
CONN@
Athlon 64 S1
Processor Socket
1 2
+5VS
R247
0_0603_5%
@
U1
1
EN GND 8
2
+VCC_FAN1
VIN GND 7
3
VOUT GND 6
<28> EN_DFAN1
1 2
4
R733
0_0402_5%
VSET GND 5
1
C760
APL5607KI-TRG_SO8
@
0.01U_0402_25V4Z
+3VS
2
<28> FANPWM
<28> FAN_SPEED1
C92
10U_0805_10V4Z
1 2
<BOM Structure>
+3VS
1
2
FAN1 Conn
1
2
R37
10K_0402_5%
1
C91
1000P_0402_50V7K
2
R40
10K_0402_5%
@
FANPWN
40mil
+VCC_FAN1
+VCC_FAN1
@
+5VS
1
2
Reserve when PVT
for cos down
D13
1SS355_SOD323-2
@D4
BAS16_SOT23-3
1 2
C97
10U_0805_10V4Z
1 2
C96
1000P_0402_50V7K
1 2
<BOM Structure>
JP12
1
2
3
CONN@
ACES_85205-03001
LDO FAN
JP38
1
1
2
2
3
3
4
4
CONN@
ACES_85205-0400
PWM FAN
C
B
+1.2V_HT
R2
R3
2
2
@ 1
51_0402_1%
@ 1
51_0402_1%
H_CTLIP1_R
H_CTLIN1_R
AMD : 49.9 1%
ATI : 51 1%
250 mil
+1.2V_HT
VLDT CAP.
1
C86
4.7U_0805_10V4Z
1
C82
4.7U_0805_10V4Z
1
C90
0.22U_0603_16V4Z
1
C89
0.22U_0603_16V4Z
1
C83
180P_0402_50V8J
1
C85
180P_0402_50V8J
2
2
2
2
2
<BOM Structure>
2
<BOM Structure>
<BOM Structure>
<BOM Structure>
Near CPU Socket
A
A
WWW.AliSaler.Com
5
4
Security Classification
Compal Secret Data
Issued Date
2007/5/18 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Document Number Rev
R&D
Custom
401743 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 6 of
46
3
2
1
A
B
C
D
E
<11> DDR_B_D[63..0]
JCPU1C
DDR_A_D[63..0] <10>
+1.8V
DDR_B_D63 AD11
DDR_A_D63
4 DDR_B_D62
MB_DATA63
MA_DATA63
AA12
4
AF11
DDR_A_D62
DDR_B_D61
MB_DATA62
MA_DATA62
AB12
AF14
DDR_A_D61
DDR_B_D60
MB_DATA61
MA_DATA61
AA14
AE14
DDR_A_D60
DDR_B_D59
MA_DATA60
AB14
R4
MB_DATA60
Y11
DDR_A_D59
DDR_B_D58
MA_DATA59
W11
1K_0402_1%
MB_DATA59
AB11
DDR_A_D58
+CPU_M_VREF
DDR_B_D57
MB_DATA58
MA_DATA58
Y12
AC12
DDR_A_D57
DDR_B_D56
MB_DATA57
MA_DATA57
AD13
AF13
DDR_A_D56
DDR_B_D55
MB_DATA56
MA_DATA56
AB13
(15/20, <6")
AF15
DDR_A_D55
DDR_B_D54
MB_DATA55
MA_DATA55
AD15
AF16
DDR_A_D54
DDR_B_D53
MB_DATA54
MA_DATA54
AB15
1
1
AC18
DDR_A_D53
DDR_B_D52
MA_DATA53
AB17
R5
MB_DATA53
AF19
DDR_A_D52
DDR_B_D51
MA_DATA52
Y17
1K_0402_1%
MB_DATA52
AD14
DDR_A_D51
DDR_B_D50
MB_DATA51
MA_DATA51
Y14
AC14
DDR_A_D50
DDR_B_D49
MA_DATA50
W14
2
2
MB_DATA50
AE18
DDR_A_D49
DDR_B_D48
MB_DATA49
MA_DATA49
W16
AD18
DDR_A_D48
DDR_B_D47
MB_DATA48
MA_DATA48
AD17
AD20
DDR_A_D47
DDR_B_D46
MB_DATA47
MA_DATA47
Y18
AC20
DDR_A_D46
+CPU_M_VREF
DDR_B_D45
MB_DATA46
MA_DATA46
AD19
AF23
DDR_A_D45
JCPU1B
+0.9V
DDR_B_D44
MB_DATA45
MA_DATA45
AD21
AF24
DDR_A_D44
DDR_B_D43
MB_DATA44
MA_DATA44
AB21
AF20
DDR_A_D43
DDR_B_D42
MB_DATA43
MA_DATA43
AB18
W17
DDR_A_D42
M_VREF
VTT1
D10
AE20
DDR_B_D41
MB_DATA42
MA_DATA42
AA18
DDR_A_D41
VTT_SENSE
VTT2
C10
AD22
DDR_B_D40
MA_DATA41
AA20
TP1
MB_DATA41
Y10
DDR_A_D40
VTT_SENSE
VTT3
B10
AC22
DDR_B_D39
MB_DATA40
MA_DATA40
Y20
DDR_A_D39
VTT4
AD10
AE25
DDR_B_D38
MB_DATA39
MA_DATA39
AA22
(10/10, <1")
DDR_A_D38
+1.8V
R7
M_ZN
VTT5
W10
AD26
DDR_B_D37
MB_DATA38
MA_DATA38
Y22
1 2
AE10
DDR_A_D37
39.2_0402_1% M_ZP
M_ZN
VTT6
AC10
AA25
R6
DDR_B_D36
MB_DATA37
MA_DATA37
W21
2 1
AF10
DDR_A_D36
M_ZP
VTT7
AB10
AA26
39.2_0402_1%
DDR_B_D35
MB_DATA36
MA_DATA36
W22
DDR_A_D35
VTT8
AA10
AE24
DDR_B_D34
MB_DATA35
MA_DATA35
AA21
DDR_A_D34
VTT9
A10
AD24
DDR_B_D33
MB_DATA34
MA_DATA34
AB22
AA23
DDR_A_D33
DDR_CS3_DIMMA#
DDR_A_CLK2
DDR_B_D32
MB_DATA33
MA_DATA33
AB24
DDR_A_D32
<10> DDR_CS3_DIMMA#
V19
DDR_A_CLK2 <10>
DDR_CS2_DIMMA#
MA0_CS_L3
MA0_CLK_H2
Y16
AA24
DDR_A_CLK#2
DDR_B_D31
MB_DATA32
MA_DATA32
Y24
DDR_A_D31
3 <10> DDR_CS2_DIMMA#
J22
DDR_A_CLK#2 <10>
DDR_CS1_DIMMA#
MA0_CS_L2
MA0_CLK_L2
AA16
G24
DDR_A_CLK1
DDR_B_D30
MB_DATA31
MA_DATA31
H22
DDR_A_D30
3
<10> DDR_CS1_DIMMA#
V22
DDR_A_CLK1 <10>
DDR_CS0_DIMMA#
MA0_CS_L1
MA0_CLK_H1
E16
G23
DDR_A_CLK#1
DDR_B_D29
MB_DATA30
MA_DATA30
H20
DDR_A_D29
<10> DDR_CS0_DIMMA#
T19
MA0_CS_L0
MA0_CLK_L1
F16
DDR_A_CLK#1 <10>
D26
DDR_B_D28
MB_DATA29
MA_DATA29
E22
C26
DDR_A_D28
DDR_CS3_DIMMB#
DDR_B_CLK2
DDR_B_D27
MB_DATA28
MA_DATA28
E21
DDR_A_D27
<11> DDR_CS3_DIMMB#
Y26
DDR_B_CLK2 <11>
DDR_CS2_DIMMB#
MB0_CS_L3
MB0_CLK_H2
AF18
G26
DDR_B_CLK#2
DDR_B_D26
MB_DATA27
MA_DATA27
J19
DDR_A_D26
<11> DDR_CS2_DIMMB#
J24
DDR_B_CLK#2 <11>
DDR_CS1_DIMMB#
MB0_CS_L2
MB0_CLK_L2
AF17
G25
DDR_B_CLK1
DDR_B_D25
MB_DATA26
MA_DATA26
H24
DDR_A_D25
<11> DDR_CS1_DIMMB#
W24
DDR_B_CLK1 <11>
DDR_CS0_DIMMB#
MB0_CS_L1
MB0_CLK_H1
A17
E24
DDR_B_CLK#1
DDR_B_D24
MB_DATA25
MA_DATA25
F22
DDR_A_D24
<11> DDR_CS0_DIMMB#
U23
MB0_CS_L0
MB0_CLK_L1
A18
DDR_B_CLK#1 <11>
E23
DDR_B_D23
MB_DATA24
MA_DATA24
F20
C24
DDR_A_D23
DDR_CKE1_DIMMB
DDR_B_ODT1
DDR_B_D22
MB_DATA23
MA_DATA23
C23
DDR_A_D22
<11> DDR_CKE1_DIMMB
H26
DDR_B_ODT1 <11>
DDR_CKE0_DIMMB
MB_CKE1
MB0_ODT1
W23
B24
DDR_B_ODT0
DDR_B_D21
MB_DATA22
MA_DATA22
B22
DDR_A_D21
<11> DDR_CKE0_DIMMB
J23
DDR_B_ODT0 <11>
DDR_CKE1_DIMMA
MB_CKE0
MB0_ODT0
W26
C20
DDR_A_ODT1
DDR_B_D20
MB_DATA21
MA_DATA21
F18
DDR_A_D20
<10> DDR_CKE1_DIMMA
J20
DDR_A_ODT1 <10>
DDR_CKE0_DIMMA
MA_CKE1
MA0_ODT1
V20
B20
DDR_A_ODT0
DDR_B_D19
MB_DATA20
MA_DATA20
E18
DDR_A_D19
<10> DDR_CKE0_DIMMA
J21
MA_CKE0
MA0_ODT0
U19
DDR_A_ODT0 <10>
C25
DDR_B_D18
MB_DATA19
MA_DATA19
E20
DDR_A_D18
<10> DDR_A_MA[15..0]
DDR_B_MA[15..0] <11>
D24
DDR_A_MA15 K19
DDR_B_MA15
DDR_B_D17
MB_DATA18
MA_DATA18
D22
DDR_A_D17
DDR_A_MA14
MA_ADD15
MB_ADD15
J25
A21
K20
DDR_B_MA14
DDR_B_D16
MB_DATA17
MA_DATA17
C19
DDR_A_D16
DDR_A_MA13
MA_ADD14
MB_ADD14
J26
D20
V24
DDR_B_MA13
DDR_B_D15
MB_DATA16
MA_DATA16
G18
DDR_A_D15
DDR_A_MA12
MA_ADD13
MB_ADD13
W25
D18
K24
DDR_B_MA12
DDR_B_D14
MB_DATA15
MA_DATA15
G17
DDR_A_D14
DDR_A_MA11
MA_ADD12
MB_ADD12
L23
C18
L20
DDR_B_MA11
DDR_B_D13
MB_DATA14
MA_DATA14
C17
DDR_A_D13
DDR_A_MA10
MA_ADD11
MB_ADD11
L25
D14
R19
DDR_B_MA10
DDR_B_D12
MB_DATA13
MA_DATA13
F14
DDR_A_D12
DDR_A_MA9
MA_ADD10
MB_ADD10
U25
C14
L19
DDR_B_MA9
DDR_B_D11
MB_DATA12
MA_DATA12
E14
DDR_A_D11
DDR_A_MA8
MA_ADD9
MB_ADD9
L24
A20
L22
DDR_B_MA8
DDR_B_D10
MB_DATA11
MA_DATA11
H17
DDR_A_D10
DDR_A_MA7
MA_ADD8
MB_ADD8
M26
A19
L21
DDR_B_MA7
DDR_B_D9
MB_DATA10
MA_DATA10
E17
DDR_A_D9
DDR_A_MA6
MA_ADD7
MB_ADD7
L26
A16
M19
DDR_B_MA6
DDR_B_D8
MB_DATA9
MA_DATA9
E15
DDR_A_D8
DDR_A_MA5
MA_ADD6
MB_ADD6
N23
A15
M20
DDR_B_MA5
DDR_B_D7
MB_DATA8
MA_DATA8
H15
DDR_A_D7
DDR_A_MA4
MA_ADD5
MB_ADD5
N24
A13
M24
DDR_B_MA4
DDR_B_D6
MB_DATA7
MA_DATA7
E13
DDR_A_D6
DDR_A_MA3
MA_ADD4
MB_ADD4
N25
D12
M22
DDR_B_MA3
DDR_B_D5
MB_DATA6
MA_DATA6
C13
DDR_A_D5
DDR_A_MA2
MA_ADD3
MB_ADD3
N26
E11
N22
DDR_B_MA2
DDR_B_D4
MB_DATA5
MA_DATA5
H12
DDR_A_D4
DDR_A_MA1
MA_ADD2
MB_ADD2
P24
G11
N21
DDR_B_MA1
DDR_B_D3
MB_DATA4
MA_DATA4
H11
DDR_A_D3
DDR_A_MA0
MA_ADD1
MB_ADD1
P26
B14
R21
DDR_B_MA0
DDR_B_D2
MB_DATA3
MA_DATA3
G14
DDR_A_D2
MA_ADD0
MB_ADD0
T24
A14
DDR_B_D1
MB_DATA2
MA_DATA2
H14
A11
DDR_A_D1
DDR_A_BS#2
DDR_B_BS#2
DDR_B_D0
MB_DATA1
MA_DATA1
F12
DDR_A_D0
<10> DDR_A_BS#2
K22
DDR_B_BS#2 <11>
DDR_A_BS#1
MA_BANK2
MB_BANK2
K26
C11
DDR_B_BS#1
MB_DATA0
MA_DATA0
G12
2 <10> DDR_A_BS#1
R20
DDR_B_BS#1 <11>
<11> DDR_B_DM[7..0]
DDR_A_DM[7..0] <10>
DDR_A_BS#0
MA_BANK1
MB_BANK1
T26
DDR_B_BS#0
DDR_B_DM7
DDR_A_DM7
2
<10> DDR_A_BS#0
T22
MA_BANK0
MB_BANK0
U26
DDR_B_BS#0 <11>
AD12
DDR_B_DM6
MB_DM7
MA_DM7
Y13
AC16
DDR_A_DM6
DDR_A_RAS#
DDR_B_RAS#
DDR_B_DM5
MB_DM6
MA_DM6
AB16
DDR_A_DM5
<10> DDR_A_RAS#
T20
DDR_B_RAS# <11>
DDR_A_CAS#
MA_RAS_L
MB_RAS_L
U24
AE22
DDR_B_CAS#
DDR_B_DM4
MB_DM5
MA_DM5
Y19
DDR_A_DM4
<10> DDR_A_CAS#
U20
DDR_B_CAS# <11>
DDR_A_WE#
MA_CAS_L
MB_CAS_L
V26
AB26
DDR_B_WE#
DDR_B_DM3
MB_DM4
MA_DM4
AC24
DDR_A_DM3
<10> DDR_A_WE#
U21
MA_WE_L
MB_WE_L
U22
DDR_B_WE# <11>
E25
DDR_B_DM2
MB_DM3
MA_DM3
F24
A22
DDR_A_DM2
CONN@ FOX_PZ63823-284S-41F
DDR_B_DM1
MB_DM2
MA_DM2
E19
B16
DDR_A_DM1
DDR_B_DM0
MB_DM1
MA_DM1
C15
A12
DDR_A_DM0
MB_DM0
MA_DM0
E12
1 2
1 2
C16
0.1U_0402_16V4Z
C100
1000P_0402_50V7K
PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH
DDR_A_CLK2
DDR_A_CLK#2
1
C102
1.5P_0402_50V8C
2
Athlon 64 S1
Processor
Socket
DDR_B_CLK2
DDR_B_CLK#2
1
C17
1.5P_0402_50V8C
2
<11> DDR_B_DQS7
<11> DDR_B_DQS#7
<11> DDR_B_DQS6
<11> DDR_B_DQS#6
<11> DDR_B_DQS5
<11> DDR_B_DQS#5
<11> DDR_B_DQS4
<11> DDR_B_DQS#4
<11> DDR_B_DQS3
<11> DDR_B_DQS#3
<11> DDR_B_DQS2
<11> DDR_B_DQS#2
<11> DDR_B_DQS1
<11> DDR_B_DQS#1
<11> DDR_B_DQS0
<11> DDR_B_DQS#0
Processor DDR2 Memory Interface
DDR_B_DQS7 AF12
DDR_B_DQS#7
MB_DQS_H7
AE12
DDR_B_DQS6
MB_DQS_L7
AE16
DDR_B_DQS#6
MB_DQS_H6
AD16
DDR_B_DQS5
MB_DQS_L6
AF21
DDR_B_DQS#5
MB_DQS_H5
AF22
DDR_B_DQS4
MB_DQS_L5
AC25
DDR_B_DQS#4
MB_DQS_H4
AC26
DDR_B_DQS3
MB_DQS_L4
F26
DDR_B_DQS#3
MB_DQS_H3
E26
DDR_B_DQS2
MB_DQS_L3
A24
DDR_B_DQS#2
MB_DQS_H2
A23
DDR_B_DQS1
MB_DQS_L2
D16
DDR_B_DQS#1
MB_DQS_H1
C16
DDR_B_DQS0
MB_DQS_L1
C12
DDR_B_DQS#0
MB_DQS_H0
B12
MB_DQS_L0
DDR_A_CLK1
DDR_B_CLK1
CONN@ FOX_PZ63823-284S-41F
1
1
Athlon 64 S1
Processor Socket
C104
C105
1.5P_0402_50V8C
1.5P_0402_50V8C
DDR_A_CLK#1 2
DDR_B_CLK#1 2
1 1
MA_DQS_H7
W12
MA_DQS_L7
W13
MA_DQS_H6
Y15
MA_DQS_L6
W15
MA_DQS_H5
AB19
MA_DQS_L5
AB20
MA_DQS_H4
AD23
MA_DQS_L4
AC23
MA_DQS_H3
G22
MA_DQS_L3
G21
MA_DQS_H2
C22
MA_DQS_L2
C21
MA_DQS_H1
G16
MA_DQS_L1
G15
MA_DQS_H0
G13
MA_DQS_L0
H13
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS7 <10>
DDR_A_DQS#7 <10>
DDR_A_DQS6 <10>
DDR_A_DQS#6 <10>
DDR_A_DQS5 <10>
DDR_A_DQS#5 <10>
DDR_A_DQS4 <10>
DDR_A_DQS#4 <10>
DDR_A_DQS3 <10>
DDR_A_DQS#3 <10>
DDR_A_DQS2 <10>
DDR_A_DQS#2 <10>
DDR_A_DQS1 <10>
DDR_A_DQS#1 <10>
DDR_A_DQS0 <10>
DDR_A_DQS#0 <10>
A
B
Security Classification
Compal Secret Data
Issued Date
2007/5/18 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 7 of
46
C
D
E
0.1
401743
5
4
3
2
1
+1.8VS
D
C
<17>
LDT_RST#
<17> H_PWRGD
<13,17> LDT_STOP#
1 2
+1.8VS
1 2
+1.8VS
1 2
R344
300_0402_5%
LDT_RST#
1
C721
0.01U_0402_25V4Z
@
2
R346
300_0402_5%
H_PWRGD
1
C720
0.01U_0402_25V4Z
@
2
R342
300_0402_5%
LDT_STOP#
1
C719
0.01U_0402_25V4Z
@
2
+3VS
C119
0.1U_0402_16V4Z
1 2
+2.5VS
C113
150U_D2_6.3VM
<16> CLK_CPU_BCLK
<16> CLK_CPU_BCLK#
1
+
2
+2.5VDDA VDDA=300mA
L4
<15/20>
1 2
3300P_0402_50V7K
FCM2012CF-800T06_2P
1
1
1
C116
C118
C22
0.22U_0603_16V4Z
2
2
2
4.7U_0805_10V4Z
<BOM Structure>
<BOM Structure>
LDT_RST#
H_PWRGD
LDT_STOP#
(10/5/5/5/10)
+1.2V_HT
1 2
3900P_0402_50V7K
C109
1
2
R22
169_0402_1%
1 2
C23
3900P_0402_50V7K
R61
R16
2
R13
<45> CPU_VCC_SENSE
<45> CPU_VSS_SENSE
1 2
44.2_0402_1% CPU_HTREF1 P6
1 2
44.2_0402_1% CPU_HTREF0 R6
(5/10, >1")
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
1 CPU_SIC
300_0402_5%
CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
(10/10)
TP26
TP3
TP5
TP30
TP8
TP28
TP31
CPU_THERMDC
CPU_THERMDA
F8
F9
B7
A7
F10
AF4
AF5
F6
E6
W9
Y9
A9
A8
G10
AA9
AC9
AD9
AF9
E9
E8
G9
H10
AA7
C2
D7
E7
F7
C7
AC8
C3
AA6
W7
W8
Y6
AB6
VDDA2
VDDA1
RESET_L
PWROK
LDTSTOP_L
SIC
SID
HTREF1
HTREF0
VDDIO_FB_H
VDDIO_FB_L
CLKIN_H
CLKIN_L
DBRDY
TMS
TCK
TRST_L
TDI
JCPU1D
THERMTRIP_L
PROCHOT_L
VID5
VID4
VID3
VID2
VID1
VID0
CPU_PRESENT_L
VDD_FB_H
VDD_FB_L
PSI_L
TEST25_H
TEST25_L
TEST19
TEST18
TEST13
TEST9
TEST17
TEST16
TEST15
TEST14
TEST12
TEST7
TEST6
THERMDC
THERMDA
TEST3
TEST2
DBREQ_L
TDO
TEST29_H
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
TEST8
AF6
AC7
A5
C6
A6
A4
C5
B5
CPU_THERMTRIP#_R
CPU_PROCHOT#_1.8
AC6 CPU_PRESENT#
A3
E10
CPU_DBREQ#
TP6
TP7
TP9
CPU_TEST21_SCANEN
TP29
CPU_TEST26_BURNIN#
CPU_VID5 <45>
CPU_VID4 <45>
CPU_VID3 <45>
CPU_VID2 <45>
CPU_VID1 <45>
CPU_VID0 <45>
PSI_L <45>
AE9 CPU_TDO
R53
80.6_0402_1%
C9 CPU_TEST29_H_FBCLKOUT_P 1 2
C8 CPU_TEST29_L_FBCLKOUT_N
<BOM Structure>
ROUTE AS 80 Ohm DIFFERENTIAL PAIR
PLACE IT CLOSE TO CPU WITHIN 1"
AE7
AD7
AE8
AB8
AF7
J7
H8
AF8
AE6
K8
C4
+1.8V
CPU_VID1
CPU_PRESENT#
CPU_TEST26_BURNIN#
CPU_TEST21_SCANEN
2
R65
2
R68
2
R69
2
R66
+1.8V
1 2
VID1: For compatibility
with future processors
R24
300_0402_5%
<BOM Structure>
1 2
R64
1K_0402_5%
<BOM Structure>
1 2
R27
300_0402_5%
1 2
R47
300_0402_5%
1 CPU_TEST25_H_BYPASSCLK_H
510_0402_5%
1 CPU_TEST25_L_BYPASSCLK_L
510_0402_5%
1
CPU_TEST19_PLLTEST0
300_0402_5%
1
CPU_TEST18_PLLTEST1
300_0402_5%
D
C
B
CPU_THERMDA
1 2 CPU_THERMDC
C120
2200P_0402_50V7K
U3
1
VDD
2
3
4
D+
D-
THERM#
SCLK 8
SDATA
ALERT#
ADM1032ARMZ-2REEL_MSOP8
<BOM Structure>
F75383M_MSOP8
SMBus Address: 1001110X (b)
7
6
GND 5
EC_SMB_CK2 <28>
EC_SMB_DA2 <28>
P20
RSVD0
P19
RSVD1
N20
RSVD2
N19
RSVD3
R26
RSVD4
R25
RSVD5
P22
RSVD6
R22
RSVD7
FOX_PZ63823-284S-41F
CONN@
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
H16
B18
B3
C1
H6
G6
D5
R24
W18
R23
AA8
H18
H19
R8
CPU_THERMTRIP#_R
+1.8V
1
300_0402_5%
2
+1.8V
Q3
3 1H_THERMTRIP#
E
1
2
B
2
R18
1K_0402_5%
C
MMBT3904_NL_SOT23-3
+3VALW
1
2
R17
+3VALW
10K_0402_5%
Q2
MMBT3904_NL_SOT23-3
3 1
MAINPWON <39,41>
@
E
1
2
B
2
R25
@1K_0402_5%
C
B
H_THERMTRIP# <18>
+1.8V
AMD: suggest DBREQ need pull high
A
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO
@ 220_0402_5%
R33
@ 220_0402_5%
R38
1
2
@ 220_0402_5%
R34
R36
220_0402_5% R36
220_0402_5% 2 1
NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY.
1
1
2
2
1
2
@ 220_0402_5%
R35
HDT Connector
WWW.AliSaler.Com
5
JP3
1 2
3 4
5 6
7 8
9 10
11 12
+3VS
13 14
15 16
17 18
19 20
21 22
HDT_RST#
B
2
23 24
4
Y
26
U51
A
1
NC7SZ08P5X_NL_SC70-5
@SAMTEC_ASP-68200-07
<BOM Structure>
4
5
P
G
3
LDT_RST#
CPU_PROCHOT#_1.8
1 2
H_PROCHOT_R# <17>
R52
0_0402_5%
SB_PWRGD <18,33>
Security Classification
Compal Secret Data
Issued Date
2007/5/18 Deciphered Date
2010/03/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Document Number Rev
R&D
Custom
401743 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 8 of
46
3
2
1
+1.8V
1
R20
300_0402_5%
2
Compal Electronics, Inc.
SCHEMATIC, MB A5481
A
5
4
3
2
1
D
C
B
VDD(+CPU_CORE) decoupling.
+CPU_CORE
1
1
1
1
1
2
+CPU_CORE
+ C26
330U_D2E_2.5VM_R9M
+ C32
330U_D2E_2.5VM_R9M
@
2
Near CPU Socket
1
1
1
1
1
C33
22U_0805_6.3V6M
C36
22U_0805_6.3V6M
C34
22U_0805_6.3V6M
C35
22U_0805_6.3V6M
C178
22U_0805_6.3V6M
2
2
2
<BOM Structure>
2
2
2
2
2
2
+CPU_CORE
+CPU_CORE
+CPU_CORE
VDDIO decoupling.
+ C27
330U_D2E_2.5VM_R9M
2
2
<BOM Structure>
1
1
1
1
C129
0.22U_0603_16V4Z
C151
0.22U_0603_16V4Z
C122
0.01U_0402_25V7K
C47
180P_0402_50V8J
2
2
2
2
+ C28
+ C29
330U_D2E_2.5VM_R9M
330U_D2E_2.5VM_R9M
2
1
1
1
1
C41
22U_0805_6.3V6M
C190
22U_0805_6.3V6M
C39
22U_0805_6.3V6M
C128
22U_0805_6.3V6M
Under CPU Socket
+CPU_CORE
+CPU_CORE
JCPU1E
AC4
VDD1
VDD43
V12
AD2
VDD2
VDD44
V14
G4
VDD3
VDD45
W4
H2
VDD4
VDD46
Y2
J9
VDD5
VDD47
J15
J11
VDD6
VDD48
K16
J13
VDD7
VDD49
L15
K6
VDD8
VDD50
M16
K10
VDD9
VDD51
P16
K12
VDD10
VDD52
T16
K14
VDD11
VDD53
U15
L4
VDD12
VDD54
V16
L7
+1.8V
VDD13
L9
VDD14
L11
VDD15
VDDIO1
H25
L13
VDD16
VDDIO2
J17
M2
VDD17
VDDIO3
K18
M6
VDD18
VDDIO4
K21
M8
VDD19
VDDIO5
K23
M10
VDD20
VDDIO6
K25
N7
VDD21
VDDIO7
L17
N9
VDD22
VDDIO8
M18
N11
VDD23
VDDIO9
M21
P8
VDD24 VDDIO10
M23
P10
VDD25 VDDIO11
M25
R4
VDD26 VDDIO12
N17
R7
VDD27 VDDIO13
P18
R9
VDD28 VDDIO14
P21
R11
VDD29 VDDIO15
P23
T2
VDD30 VDDIO16
P25
T6
VDD31 VDDIO17
R17
T8
VDD32 VDDIO18
T18
T10
VDD33 VDDIO19
T21
T12
VDD34 VDDIO20
T23
T14
VDD35 VDDIO21
T25
U7
VDD36 VDDIO22
U17
U9
VDD37 VDDIO23
V18
U11
VDD38 VDDIO24
V21
U13
VDD39 VDDIO25
V23
V6
VDD40 VDDIO26
V25
V8
VDD41 VDDIO27
Y25
V10
VDD42
FOX_PZ63823-284S-41F
CONN@
Athlon 64 S1
Processor Socket
+1.8V
+1.8V
1
1
1
1
C170
C181
C124
C147
22U_0805_6.3V6M
22U_0805_6.3V6M
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
2
2
2
<BOM Structure>
Under CPU Socket
+0.9V
Near Power Supply
VTT decoupling. 1
C: Change to NBO CAP
C66
+
Between CPU Socket and DIMM
+1.8V
150U_D2_6.3VM
2
JCPU1F
AA4
VSS1
VSS66
AA11
VSS2
VSS67
AA13
VSS3
VSS68
AA15
VSS4
VSS69
AA17
VSS5
VSS70
AA19
VSS6
VSS71
AB2
VSS7
VSS72
AB7
VSS8
VSS73
AB9
VSS9
VSS74
AB23
VSS10
VSS75
AB25
VSS11
VSS76
AC11
VSS12
VSS77
AC13
VSS13
VSS78
AC15
VSS14
VSS79
AC17
VSS15
VSS80
AC19
VSS16
VSS81
AC21
VSS17
VSS82
AD6
VSS18
VSS83
AD8
VSS19
VSS84
AD25
VSS20
VSS85
AE11
VSS21
VSS86
AE13
VSS22
VSS87
AE15
VSS23
VSS88
AE17
VSS24
VSS89
AE19
VSS25
VSS90
AE21
VSS26
VSS91
AE23
VSS27
VSS92
B4
VSS28
VSS93
B6
VSS29
VSS94
B8
VSS30
VSS95
B9
VSS31
VSS96
B11
VSS32
VSS97
B13
VSS33
VSS98
B15
VSS34
VSS99
B17
VSS35
VSS100
B19
VSS36
VSS101
B21
VSS37
VSS102
B23
VSS38
VSS103
B25
VSS39
VSS104
D6
VSS40
VSS105
D8
VSS41
VSS106
D9
VSS42
VSS107
D11
VSS43
VSS108
D13
VSS44
VSS109
D15
VSS45
VSS110
D17
VSS46
VSS111
D19
VSS47
VSS112
D21
VSS48
VSS113
D23
VSS49
VSS114
D25
VSS50
VSS115
E4
VSS51
VSS116
F2
VSS52
VSS117
F11
VSS53
VSS118
F13
VSS54
VSS119
F15
VSS55
VSS120
F17
VSS56
VSS121
F19
VSS57
VSS122
F21
VSS58
VSS123
F23
VSS59
VSS124
F25
VSS60
VSS125
H7
VSS61
VSS126
H9
VSS62
VSS127
H21
VSS63
VSS128
H23
VSS64
VSS129
J4
VSS65
FOX_PZ63823-284S-41F
CONN@
Athlon 64 S1
Processor Socket
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
M11
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
D
C
B
1
C157
0.22U_0603_16V4Z
1
C182
0.22U_0603_16V4Z
1
C68
0.22U_0603_16V4Z
1
C188
0.22U_0603_16V4Z
+0.9V
2
2
2
2
+1.8V
1
C175
0.01U_0402_25V7K
2
1
C159
0.01U_0402_25V7K
2
<BOM Structure>
+1.8V
<BOM Structure>
180PF Qt'y follow the distance between
CPU socket and DIMM0. <2.5inch>
1
1
C189
180P_0402_50V8J
C136
180P_0402_50V8J
2
<BOM Structure>
2
1
C156
180P_0402_50V8J
2
<BOM Structure>
1
C158
180P_0402_50V8J
2
<BOM Structure>
1
C155
4.7U_0805_10V4Z
2
<BOM Structure>
+0.9V
1
1
1
1
1
1
C146
4.7U_0805_10V4Z
C184
0.22U_0603_16V4Z
C173
0.22U_0603_16V4Z
C72
1000P_0402_50V7K
C145
1000P_0402_50V7K
C180
180P_0402_50V8J
2
2
2
2
2
2
<BOM Structure>
<BOM Structure>
Near CPU Socket Right side.
<BOM Structure>
<BOM Structure>
1
C121
180P_0402_50V8J
2
<BOM Structure>
A
+1.8V
1
1
C76
4.7U_0805_10V4Z
2
<BOM Structure>
2
1
C167
4.7U_0805_10V4Z
2
1
C187
4.7U_0805_10V4Z
2
1
+ C162
C132
4.7U_0805_10V4Z
220U_D2_4VM_R15
<BOM Structure>
2
1
1
C73
C70
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
2
<BOM Structure>
1
1
C127
C185
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
2
<BOM Structure>
<BOM Structure>
Near CPU Socket Left side.
1
1
1
C164
1000P_0402_50V7K
C163
1000P_0402_50V7K
C152
180P_0402_50V8J
2
2
2
1
C179
180P_0402_50V8J
2
A
5
4
Security Classification
Compal Secret Data
Issued Date
2007/5/18 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Document Number Rev
R&D
Custom
401743 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 9 of
46
3
2
1
5
WWW.AliSaler.Com
4
3
2
1
+1.8V
+1.8V
+DIMM_VREF
+1.8V
D
C
B
A
<7> DDR_CKE0_DIMMA
<7> DDR_CS2_DIMMA#
<7> DDR_A_BS#2
<7> DDR_A_BS#0
<7> DDR_A_WE#
<7> DDR_A_CAS#
<7> DDR_CS1_DIMMA#
<7> DDR_A_ODT1
<11,16,18,31> SB_CK_SDAT
<11,16,18,31> SB_CK_SCLK
5
DDR_A_D0
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
DDR_CS2_DIMMA#
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
DDR_A_ODT1
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
SB_CK_SDAT
SB_CK_SCLK
+3VS
1
C448
0.1U_0402_16V4Z
2
+0.9V
+1.8V
R398
RP1
JDIMM2
C507
DDR_A_MA11
8 1
1 2
1
DDR_A_MA7
VREF
VSS 2
1
1
7 2
C81
0.1U_0402_16V4Z
3
DDR_A_D4
1K_0402_1%
DDR_A_MA6
VSS
DQ4
4
6 3
1 2
5
DDR_A_D5
DDR_A_MA2
C139
0.1U_0402_16V4Z
DQ0
DQ5
6
5 4
7
DQ1
VSS 8
DDR_A_DM0
2
2
9
47_0804_8P4R_5%
VSS
DM0
10
11
RP2
DQS0#
VSS 12
13
DDR_A_D6
DDR_CKE0_DIMMA
DQS0
DQ6
14
8 1
1 2
15
DDR_A_D7
R397
DDR_CS2_DIMMA#
C192
0.1U_0402_16V4Z
VSS
DQ7
16
7 2
17
DDR_A_BS#2
DQ2
VSS 18
6 3
1 2
19
DDR_A_D12
DDR_A_MA12
DQ3
DQ12
20
5 4
C88
0.1U_0402_16V4Z
21
DDR_A_D13
1K_0402_1%
VSS
DQ13
22
23
47_0804_8P4R_5%
DQ8
VSS 24
25
DDR_A_DM1
DQ9
DM1
26
RP3
27
DDR_A_MA4
VSS
VSS 28
8 1
1 2
29
DDR_A_CLK1
DDR_A_MA0
C117
0.1U_0402_16V4Z
DQS1#
CK0
30
DDR_A_CLK1 <7>
7 2
31
DDR_A_CLK#1
DDR_A_BS#1
DQS1
CK0#
32
DDR_A_CLK#1 <7>
6 3
1 2
33
DDR_CS0_DIMMA#
C144
0.1U_0402_16V4Z
VSS
VSS 34
5 4
35
DDR_A_D14
<BOM Structure>
DQ10
DQ14
36
37
DDR_A_D15
DQ11
DQ15
38
47_0804_8P4R_5%
39
VSS
VSS 40
<BOM Structure>
RP4
DDR_A_MA9
8 1
1 2
DDR_A_MA8
7 2
C114
0.1U_0402_16V4Z
41
DDR_A_MA5
VSS
VSS 42
6 3
1 2
43
DDR_A_D20
DDR_A_MA3
C95
0.1U_0402_16V4Z
DQ16
DQ20
44
5 4
45
DDR_A_D21
DDR_A_D[0..63]
DQ17
DQ21
46
<7> DDR_A_D[0..63]
47
VSS
VSS 48
47_0804_8P4R_5%
<BOM Structure>
49
DDR_A_DM[0..7]
<7> DDR_A_DM[0..7]
RP5
DQS2#
NC 50
51
DDR_A_DM2
DQS2
DM2
52
8 1
1 2
53
DDR_A_DQS[0..7]
DDR_A_MA1
VSS
VSS 54
DDR_A_D22
<7> DDR_A_DQS[0..7]
7 2
C193
0.1U_0402_16V4Z
55
DDR_A_MA10
DQ18
DQ22
56
6 3
1 2
57
DDR_A_D23
DDR_A_MA[0..15]
<7> DDR_A_MA[0..15]
DDR_A_BS#0
DQ19
DQ23
58
5 4
C125
0.1U_0402_16V4Z
59
VSS
VSS 60
61
DDR_A_D28
DDR_A_DQS#[0..7]
47_0804_8P4R_5%
DQ24
DQ28
62
DDR_A_D29
<7> DDR_A_DQS#[0..7]
<BOM Structure>
63
DQ25
DQ29
64
RP6
65
DDR_A_WE#
VSS
VSS 66
8 1
1 2
67
DDR_A_DQS#3
DDR_A_CAS#
C103
0.1U_0402_16V4Z
DM3
DQS3#
68
7 2
69
DDR_A_DQS3
DDR_CS1_DIMMA#
NC
DQS3
70
6 3
1 2
71
DDR_A_ODT1
C99
0.1U_0402_16V4Z
VSS
VSS 72
5 4
73
DDR_A_D30
<BOM Structure>
DQ26
DQ30
74
75
DDR_A_D31
DQ27
DQ31
76
47_0804_8P4R_5%
77
RP7
VSS
VSS 78
<BOM Structure>
79
DDR_CKE1_DIMMA
DDR_A_RAS#
CKE0 NC/CKE1
80
DDR_CKE1_DIMMA <7>
8 1
1 2
81
DDR_A_ODT0
VDD
VDD 82
7 2
C107
0.1U_0402_16V4Z
83
DDR_A_MA15
DDR_A_MA13
NC
NC/A15
84
6 3
1 2
85
DDR_A_MA14
DDR_CS3_DIMMA#
C98
0.1U_0402_16V4Z
BA2
NC/A14
86
5 4
87
VDD
VDD 88
<BOM Structure>
89
DDR_A_MA11
47_0804_8P4R_5%
A12
A11
90
<BOM Structure>
91
DDR_A_MA7
A9
A7
92
RP8
93
DDR_A_MA6
DDR_CKE1_DIMMA
A8
A6
94
8 1
1 2
95
DDR_A_MA15
C101
0.1U_0402_16V4Z
VDD
VDD 96
7 2
97
DDR_A_MA4
DDR_A_MA14
A5
A4
98
6 3
1 2
99
DDR_A_MA2
C191
0.1U_0402_16V4Z
A3
A2
100
5 4
101
DDR_A_MA0
A1
A0
102
103
VDD
VDD 104
47_0804_8P4R_5%
<BOM Structure>
105
DDR_A_BS#1
A10/AP
BA1
106
DDR_A_BS#1 <7>
107
DDR_A_RAS#
BA0
RAS#
108
DDR_A_RAS# <7>
109
DDR_CS0_DIMMA#
WE#
S0#
110
DDR_CS0_DIMMA# <7>
111
VDD
VDD 112
113
DDR_A_ODT0
CAS#
ODT0
114
DDR_A_ODT0 <7>
115
DDR_A_MA13
NC/S1# NC/A13
116
117
VDD
VDD 118
<BOM Structure>
119
DDR_CS3_DIMMA#
NC/ODT1
NC 120
DDR_CS3_DIMMA# <7>
121
VSS
VSS 122
123
DDR_A_D36
DQ32
DQ36
124
125
DDR_A_D37
DQ33
DQ37
126
127
VSS
VSS 128
129
DDR_A_DM4
DQS4#
DM4
130
131
DQS4
VSS 132
133
DDR_A_D38
VSS
DQ38
134
135
DDR_A_D39
DQ34
DQ39
136
137
DQ35
VSS 138
139
DDR_A_D44
VSS
DQ44
140
141
DDR_A_D45
DQ40
DQ45
142
143
DQ41
VSS 144
145
DDR_A_DQS#5
VSS
DQS5#
146
147
DDR_A_DQS5
DM5
DQS5
148
149
VSS
VSS 150
151
DDR_A_D46
DQ42
DQ46
152
153
DDR_A_D47
DQ43
DQ47
154
155
VSS
VSS 156
157
DDR_A_D52
DQ48
DQ52
158
159
DDR_A_D53
DQ49
DQ53
160
161
VSS
VSS 162
163
DDR_A_CLK2
NC,TEST CK1
164
DDR_A_CLK2 <7>
165
DDR_A_CLK#2
VSS
CK1#
166
DDR_A_CLK#2 <7>
167
DQS6#
VSS 168
169
DDR_A_DM6
DQS6
DM6
170
171
VSS
VSS 172
173
DDR_A_D54
DQ50
DQ54
174
175
DDR_A_D55
DQ51
DQ55
176
177
VSS
VSS 178
179
DDR_A_D60
DQ56
DQ60
180
181
DDR_A_D61
DQ57
DQ61
182
183
VSS
VSS 184
185
DDR_A_DQS#7
DM7
DQS7#
186
187
DDR_A_DQS7
VSS
DQS7
188
189
DQ58
VSS 190
191
DDR_A_D62
DQ59
DQ62
192
193
DDR_A_D63
VSS
DQ63
194
195
SDA
VSS 196
197
R12 1 2
10K_0402_5%
SCL
SAO 198
199
R10 1 2
10K_0402_5%
VDDSPD
SA1
200
Security Classification
Compal Secret Data
203
Compal Electronics, Inc.
GND
GND 204 Issued Date
2005/10/11 Title
Deciphered Date 2010/03/12
FOX_AS0A426-M2RN-7F
CONN@
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
C
DIMM2 REV H:5.2mm (BOT)
401743 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 10 of
46
4
3
2
1
4.7U_0805_10V4Z
0.1U_0402_16V4Z
C503
1
2
1
2
D
C
B
A
5
4
3
2
1
+1.8V
+1.8V
+DIMM_VREF
D
C
B
A
<7> DDR_CKE0_DIMMB
<7> DDR_CS2_DIMMB#
<7> DDR_B_BS#2
<7> DDR_B_BS#0
<7> DDR_B_WE#
<7> DDR_B_CAS#
<7> DDR_CS1_DIMMB#
<7> DDR_B_ODT1
<10,16,18,31> SB_CK_SDAT
<10,16,18,31> SB_CK_SCLK
5
DDR_B_D0
DDR_B_D1
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_CKE0_DIMMB
DDR_CS2_DIMMB#
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS1_DIMMB#
DDR_B_ODT1
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
SB_CK_SDAT
SB_CK_SCLK
+3VS
1
C21
0.1U_0402_16V4Z
2
JDIMM1
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
VSS 2
DQ4
4
DQ5
6
VSS 8
DM0
10
VSS 12
DQ6
14
DQ7
16
VSS 18
DQ12
20
DQ13
22
VSS 24
DM1
26
VSS 28
CK0
30
CK0#
32
VSS 34
DQ14
36
DQ15
38
VSS 40
DDR_B_D4
DDR_B_D5
DDR_B_DM0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR_B_DM1
DDR_B_CLK1
DDR_B_CLK#1
DDR_B_D14
DDR_B_D15
4.7U_0805_10V4Z
1
2
C202
0.1U_0402_16V4Z
DDR_B_CLK1 <7>
DDR_B_CLK#1 <7>
1
2
C198
DDR_CS2_DIMMB#
DDR_B_BS#2
DDR_CKE0_DIMMB
RP12
41
DDR_B_MA5
VSS
VSS 42
8 1
2 1
43
DDR_B_D20
DDR_B_MA8
C199
0.1U_0402_16V4Z
DQ16
DQ20
44
7 2
45
DDR_B_D21
DDR_B_MA9
DQ17
DQ21
46
6 3
1 2
47
DDR_B_MA12
C200
0.1U_0402_16V4Z
VSS
VSS 48
5 4
49
DQS2#
NC 50
51
DDR_B_DM2
DDR_B_D[0..63]
47_0804_8P4R_5%
DQS2
DM2
52
<7> DDR_B_D[0..63]
53
VSS
VSS 54
55
DDR_B_D22
DDR_B_DM[0..7]
<7> DDR_B_DM[0..7]
RP13
DQ18
DQ22
56
57
DDR_B_D23
DDR_B_BS#0
DQ19
DQ23
58
8 1
2 1
59
DDR_B_DQS[0..7]
DDR_B_MA10
C206
0.1U_0402_16V4Z
VSS
VSS 60
DDR_B_D28
<7> DDR_B_DQS[0..7]
7 2
61
DDR_B_MA1
DQ24
DQ28
62
6 3
1 2
63
DDR_B_D29
DDR_B_MA[0..15]
<7> DDR_B_MA[0..15]
DDR_B_MA3
C201
0.1U_0402_16V4Z
DQ25
DQ29
64
5 4
65
VSS
VSS 66
67
DDR_B_DQS#3
DDR_B_DQS#[0..7]
47_0804_8P4R_5%
DM3
DQS3#
68
DDR_B_DQS3
<7> DDR_B_DQS#[0..7]
69
NC
DQS3
70
71
VSS
VSS 72
RP14
73
DDR_B_D30
DDR_B_ODT1
DQ26
DQ30
74
8 1
2 1
75
DDR_B_D31
DDR_CS1_DIMMB#
C210
0.1U_0402_16V4Z
DQ27
DQ31
76
7 2
77
DDR_B_CAS#
VSS
VSS 78
6 3
1 2
79
DDR_CKE1_DIMMB
DDR_B_WE#
C208
0.1U_0402_16V4Z
CKE0 NC/CKE1
80
DDR_CKE1_DIMMB <7>
5 4
81
VDD
VDD 82
83
DDR_B_MA15
NC
NC/A15
84
47_0804_8P4R_5%
85
DDR_B_MA14
BA2
NC/A14
86
87
RP15
VDD
VDD 88
89
DDR_B_MA11
DDR_CS0_DIMMB#
A12
A11
90
8 1
2 1
91
DDR_B_MA7
DDR_B_ODT0 7 2
C194
0.1U_0402_16V4Z
A9
A7
92
93
DDR_B_MA6
DDR_B_MA13
A8
A6
94
6 3
1 2
95
DDR_CS3_DIMMB# 5 4
C207
0.1U_0402_16V4Z
VDD
VDD 96
97
DDR_B_MA4
A5
A4
98
99
DDR_B_MA2
47_0804_8P4R_5%
A3
A2
100
101
DDR_B_MA0
A1
A0
102
103
RP16
VDD
VDD 104
105
DDR_B_BS#1
A10/AP
BA1
106
DDR_B_BS#1 <7>
8 1
2 1
107
DDR_B_RAS#
DDR_CKE1_DIMMB
C212
0.1U_0402_16V4Z
BA0
RAS#
108
DDR_B_RAS# <7>
7 2
109
DDR_CS0_DIMMB#
DDR_B_MA15
WE#
S0#
110
DDR_CS0_DIMMB# <7>
6 3
1 2
111
DDR_B_MA14 5 4
C195
0.1U_0402_16V4Z
VDD
VDD 112
113
DDR_B_ODT0
CAS#
ODT0
114
DDR_B_ODT0 <7>
115
DDR_B_MA13
47_0804_8P4R_5%
NC/S1# NC/A13
116
117
VDD
VDD 118
119
DDR_CS3_DIMMB#
NC/ODT1
NC 120
DDR_CS3_DIMMB# <7>
121
VSS
VSS 122
123
DDR_B_D36
DQ32
DQ36
124
125
DDR_B_D37
DQ33
DQ37
126
127
VSS
VSS 128
129
DDR_B_DM4
DQS4#
DM4
130
131
DQS4
VSS 132
133
DDR_B_D38
VSS
DQ38
134
135
DDR_B_D39
DQ34
DQ39
136
137
DQ35
VSS 138
139
DDR_B_D44
VSS
DQ44
140
141
DDR_B_D45
DQ40
DQ45
142
143
DQ41
VSS 144
145
DDR_B_DQS#5
VSS
DQS5#
146
147
DDR_B_DQS5
DM5
DQS5
148
149
VSS
VSS 150
151
DDR_B_D46
DQ42
DQ46
152
153
DDR_B_D47
DQ43
DQ47
154
155
VSS
VSS 156
157
DDR_B_D52
DQ48
DQ52
158
159
DDR_B_D53
DQ49
DQ53
160
161
VSS
VSS 162
163
DDR_B_CLK2
NC,TEST CK1
164
DDR_B_CLK2 <7>
165
DDR_B_CLK#2
VSS
CK1#
166
DDR_B_CLK#2 <7>
167
DQS6#
VSS 168
169
DDR_B_DM6
DQS6
DM6
170
171
VSS
VSS 172
173
DDR_B_D54
DQ50
DQ54
174
175
DDR_B_D55
DQ51
DQ55
176
177
VSS
VSS 178
179
DDR_B_D60
DQ56
DQ60
180
181
DDR_B_D61
DQ57
DQ61
182
183
VSS
VSS 184
185
DDR_B_DQS#7
DM7
DQS7#
186
187
DDR_B_DQS7
VSS
DQS7
188
189
DQ58
VSS 190
191
DDR_B_D62
DQ59
DQ62
192
193
DDR_B_D63
VSS
DQ63
194
195
SDA
VSS 196
197
R11 1 2
10K_0402_5%
SCL
SAO 198
+3VS
199
R9 1 2
10K_0402_5%
VDDSPD
SA1
200
Security Classification
Compal Secret Data
201
Compal Electronics, Inc.
GND
GND 202 Issued Date
2005/10/11 Title
Deciphered Date 2010/03/12
FOX_AS0A426-MARG-7F
CONN@
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
C
DIMM1 REV H:9.2mm (BOT)
401743 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 11 of
46
4
3
2
1
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
RP9
8
7
6
5
47_0804_8P4R_5%
RP10
8
7
6
5
RP11
8
7
6
5
1
2
3
4
1
2
3
4
47_0804_8P4R_5%
1
2
3
4
47_0804_8P4R_5%
+0.9V
2 1
C196
0.1U_0402_16V4Z
1 2
C209
0.1U_0402_16V4Z
2 1
C197
0.1U_0402_16V4Z
1 2
C211
0.1U_0402_16V4Z
2 1
C205
0.1U_0402_16V4Z
1 2
C213
0.1U_0402_16V4Z
+1.8V
D
C
B
A
5
4
3
2
1
D
C
B
<31> PCIE_PTX_C_IRX_P0
<31> PCIE_PTX_C_IRX_N0
<25> PCIE_PTX_C_IRX_P1
<25> PCIE_PTX_C_IRX_N1
<17> SB_RX0P
<17> SB_RX0N
<17> SB_RX1P
<17> SB_RX1N
<17> SB_RX2P
<17> SB_RX2N
<17> SB_RX3P
<17> SB_RX3N
U22B
D4
GFX_RX0P
GFX_TX0P
PART 2 OF 6
A5
C4
GFX_RX0N
GFX_TX0N
B5
A3
GFX_RX1P
GFX_TX1P
A4
B3
GFX_RX1N
GFX_TX1N
B4
C2
GFX_RX2P
GFX_TX2P
C3
C1
GFX_RX2N
GFX_TX2N
B2
E5
GFX_RX3P
GFX_TX3P
D1
F5
GFX_RX3N
GFX_TX3N
D2
G5
GFX_RX4P
GFX_TX4P
E2
G6
GFX_RX4N
GFX_TX4N
E1
H5
GFX_RX5P
GFX_TX5P
F4
H6
GFX_RX5N
GFX_TX5N
F3
J6
GFX_RX6P
GFX_TX6P
F1
J5
GFX_RX6N
GFX_TX6N
F2
J7
GFX_RX7P
GFX_TX7P
H4
J8
GFX_RX7N
GFX_TX7N
H3
L5
GFX_RX8P
GFX_TX8P
H1
L6
GFX_RX8N
GFX_TX8N
H2
M8
GFX_RX9P
GFX_TX9P
J2
L8
GFX_RX9N
GFX_TX9N
J1
P7
GFX_RX10P
GFX_TX10P
K4
M7
GFX_RX10N
GFX_TX10N
K3
P5
GFX_RX11P
GFX_TX11P
K1
M5
GFX_RX11N
GFX_TX11N
K2
R8
GFX_RX12P
GFX_TX12P
M4
P8
GFX_RX12N
GFX_TX12N
M3
R6
GFX_RX13P
GFX_TX13P
M1
R5
GFX_RX13N
GFX_TX13N
M2
P4
GFX_RX14P
GFX_TX14P
N2
P3
GFX_RX14N
GFX_TX14N
N1
T4
GFX_RX15P
GFX_TX15P
P1
T3
GFX_RX15N
GFX_TX15N
P2
AE3
PCIE_ITX_PRX_P0
C600 1 2
0.1U_0402_16V7K
GPP_RX0P
GPP_TX0P
AC1
AD4
PCIE_ITX_PRX_N0
C601 1 2
0.1U_0402_16V7K
GPP_RX0N
GPP_TX0N
AC2
AE2
PCIE_ITX_PRX_P1
C602 1 2
0.1U_0402_16V7K
GPP_RX1P
GPP_TX1P
AB4
AD3
PCIE_ITX_PRX_N1
GPP_RX1N
GPP_TX1N
AB3
C605 1 2
0.1U_0402_16V7K
AD1
GPP_RX2P
GPP_TX2P
PCIE I/F GPP
AA2
AD2
GPP_RX2N
GPP_TX2N
AA1
V5
GPP_RX3P
GPP_TX3P
Y1
W6
GPP_RX3N
GPP_TX3N
Y2
U5
GPP_RX4P
GPP_TX4P
Y4
U6
GPP_RX4N
GPP_TX4N
Y3
U8
GPP_RX5P
GPP_TX5P
V1
U7
GPP_RX5N
GPP_TX5N
V2
AA8
SB_TX0P_C
SB_RX0P
SB_TX0P
AD7
C259 1 2
0.1U_0402_16V7K
Y8
SB_TX0N_C
SB_RX0N
SB_TX0N
AE7
C272 1 2
0.1U_0402_16V7K
AA7
SB_TX1P_C
SB_RX1P
SB_TX1P
AE6
C254 1 2
0.1U_0402_16V7K
Y7
SB_TX1N_C
SB_RX1N
SB_TX1N
PCIE I/F SB
AD6
C252 1 2
0.1U_0402_16V7K
AA5
SB_TX2P_C
SB_RX2P
SB_TX2P
AB6
C168 1 2
0.1U_0402_16V7K
AA6
SB_TX2N_C
SB_RX2N
SB_TX2N
AC6
C261 1 2
0.1U_0402_16V7K
W5
SB_TX3P_C
SB_RX3P
SB_TX3P
AD5
C248 1 2
0.1U_0402_16V7K
Y5
SB_TX3N_C
SB_RX3N
SB_TX3N
AE5
C275 1 2
0.1U_0402_16V7K
R29 1 2
1.27K_0402_1%
PCE_CALRP(PCE_BCALRP)
AC8
PCE_CALRN(PCE_BCALRN)
AB8
R32 1 2
2K_0402_1%
+1.1VS
RS780M_FCBGA528
RS780MN-SA00002DR30 Ver:A13
RS780M Display Port Support (muxed on GFX)
DP0
DP1
PCIE I/F GFX
GFX_TX0,TX1,TX2 and TX3
AUX0 and HPD0
GFX_TX4,TX5,TX6 and TX7
AUX1 and HPD1
Check SW Routing
AN_RS780MN1, Only suggest pair0~3 can
usage for power save.
PCIE_ITX_C_PRX_P0 <31>
PCIE_ITX_C_PRX_N0 <31>
PCIE_ITX_C_PRX_P1 <25>
PCIE_ITX_C_PRX_N1 <25>
WLAN
LAN
<6> H_CADOP[0..15]
H_CADOP[0..15]
H_CADIP[0..15]
H_CADIP[0..15] <6>
H_CADON[0..15]
H_CADIN[0..15]
<6> H_CADON[0..15]
H_CADIN[0..15] <6>
SB_TX0P <17>
SB_TX0N <17>
SB_TX1P <17>
U22A
SB_TX1N <17>
H_CADOP0
H_CADIP0
SB_TX2P <17>
Y25
H_CADON0
HT_RXCAD0P
HT_TXCAD0P
H_CADIN0
SB_TX2N <17>
PART 1 OF 6
D24
Y24
H_CADOP1
HT_RXCAD0N
HT_TXCAD0N
D25
H_CADIP1
SB_TX3P <17>
V22
H_CADON1
HT_RXCAD1P
HT_TXCAD1P
E24
H_CADIN1
SB_TX3N <17>
V23
H_CADOP2
HT_RXCAD1N
HT_TXCAD1N
E25
V25
H_CADIP2
H_CADON2
HT_RXCAD2P
HT_TXCAD2P
F24
V24
H_CADIN2
H_CADOP3
HT_RXCAD2N
HT_TXCAD2N
F25
U24
H_CADIP3
H_CADON3
HT_RXCAD3P
HT_TXCAD3P
F23
U25
H_CADIN3
H_CADOP4
HT_RXCAD3N
HT_TXCAD3N
F22
T25
H_CADIP4
H_CADON4
HT_RXCAD4P
HT_TXCAD4P
H23
T24
H_CADIN4
H_CADOP5
HT_RXCAD4N
HT_TXCAD4N
H22
P22
H_CADIP5
H_CADON5
HT_RXCAD5P
HT_TXCAD5P
J25
P23
H_CADIN5
H_CADOP6
HT_RXCAD5N
HT_TXCAD5N
J24
P25
H_CADIP6
H_CADON6
HT_RXCAD6P
HT_TXCAD6P
K24
P24
H_CADIN6
H_CADOP7
HT_RXCAD6N
HT_TXCAD6N
K25
N24
H_CADIP7
H_CADON7
HT_RXCAD7P
HT_TXCAD7P
K23
N25
H_CADIN7
HT_RXCAD7N
HT_TXCAD7N
K22
H_CADOP8 AC24
H_CADIP8
H_CADON8
HT_RXCAD8P
HT_TXCAD8P
HT Link
F21
AC25
H_CADIN8
H_CADOP9
HT_RXCAD8N
HT_TXCAD8N
G21
H_CADIP9
When tune trace length, must
AB25
H_CADON9
HT_RXCAD9P
HT_TXCAD9P
G20
AB24
H_CADIN9
keep 1:4 on self-trace
H_CADOP10
HT_RXCAD9N
HT_TXCAD9N
H21
AA24
H_CADIP10
H_CADON10
HT_RXCAD10P
HT_TXCAD10P
J20
AA25
H_CADIN10
H_CADOP11
HT_RXCAD10N
HT_TXCAD10N
J21
Y22
H_CADIP11
H_CADON11
HT_RXCAD11P
HT_TXCAD11P
J18
Y23
H_CADIN11
H_CADOP12
HT_RXCAD11N
HT_TXCAD11N
K17
W21
H_CADIP12
H_CADON12
HT_RXCAD12P
HT_TXCAD12P
L19
W20
H_CADIN12
H_CADOP13
HT_RXCAD12N
HT_TXCAD12N
J19
V21
H_CADIP13
H_CADON13
HT_RXCAD13P
HT_TXCAD13P
M19
V20
H_CADIN13
H_CADOP14
HT_RXCAD13N
HT_TXCAD13N
L18
U20
H_CADIP14
H_CADON14
HT_RXCAD14P
HT_TXCAD14P
M21
U21
H_CADIN14
H_CADOP15
HT_RXCAD14N
HT_TXCAD14N
P21
U19
H_CADIP15
H_CADON15
HT_RXCAD15P
HT_TXCAD15P
P18
U18
H_CADIN15
HT_RXCAD15N
HT_TXCAD15N
M18
<6> H_CLKOP0
T22
HT_RXCLK0P
HT_TXCLK0P
H24
H_CLKIP0 <6>
<6> H_CLKON0
T23
HT_RXCLK0N
HT_TXCLK0N
H25
H_CLKIN0 <6>
<6> H_CLKOP1
AB23
HT_RXCLK1P
HT_TXCLK1P
L21
H_CLKIP1 <6>
<6> H_CLKON1
AA22
HT_RXCLK1N
HT_TXCLK1N
L20
H_CLKIN1 <6>
H_CTLOP0
H_CTLIP0
<6> H_CTLOP0
M22
H_CTLIP0 <6>
H_CTLON0
HT_RXCTL0P
HT_TXCTL0P
M24
H_CTLIN0
<6> H_CTLON0
M23
H_CTLIN0 <6>
H_CTLOP1
HT_RXCTL0N
HT_TXCTL0N
M25
H_CTLIP1
<6> H_CTLOP1
R21
H_CTLIP1 <6>
Check AMD
H_CTLON1
HT_RXCTL1P
HT_TXCTL1P
P19
H_CTLIN1
<6> H_CTLON1
R20
HT_RXCTL1N
HT_TXCTL1N
R18
H_CTLIN1 <6>
1 R67 2
C23
1 R79
HT_RXCALP
HT_TXCALP
B24
2
A24
301_0402_1%~D
HT_RXCALN
HT_TXCALN
B25
301_0402_1%~D
Place within 1"
RS780M_FCBGA528
Place within 1"
layout 4/8
RS780MN-SA00002DR30 Ver:A13 layout 4/8
HYPER TRANSPORT CPU I/F
D
C
B
A
A
WWW.AliSaler.Com
5
4
Security Classification
Compal Secret Data
Issued Date
2005/03/08 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
401743 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 12 of
47
3
2
1
5
4
3
2
1
D
C
B
+1.8VS
+NB_HTPVDD
L10
1 2 <65mA>
MBK2012221YZF 0805 1
+1.8VS
+VDDA18PCIEPLL
L5
1 2 <20mA>
MBK2012221YZF 0805 1
+1.1VS
L50 +NB_PLLVDD
1 2 <120mA>
MBK2012221YZF 0805 1
<16> CLK_NB_14.318M
+3VS
C78
2.2U_0603_6.3V4Z
2
+1.8VS
+VDDA18HTPLL
L24
1 2 <20mA>
MBK2012221YZF 0805 1
C266
2.2U_0603_6.3V4Z
2
C31
2.2U_0603_6.3V4Z
2
C400
2.2U_0603_6.3V4Z
2
@
1 2
C691
22P_0402_50V8J
CLK_NB_14.318M
@
1 2
For EMI
R323 1 2
4.7K_0402_5%
R322 1 2
4.7K_0402_5%
R488 1 2
4.7K_0402_5%
R493 1 2
4.7K_0402_5%
R637
10_0402_5%
GMCH_LCD_CLK
GMCH_LCD_DATA
GMCH_CRT_CLK
GMCH_CRT_DATA
+1.8VS
1 2 GMCH_CRT_R
R55
140_0402_1%
1 2 GMCH_CRT_G
R60
150_0402_1%
1 2 GMCH_CRT_B
R62
150_0402_1%
Close to U22 Ball
+1.1VS
<15,17,25,28,31> PLT_RST#
<18> NB_PWRGD
NB_PGRGD (SB)
Output, OD
1 2
R58
4.7K_0402_5%
<42> POWER_SEL
LOW
L25
1 2
MBK2012170YZF_0805
+3VS
+3VS
L8
1 2 +AVDD1 <110mA>
MBK2012170YZF_0805
C40 1
+1.8VS
22U_0805_6.3V6M
L23
+AVDD2 2
1 2
MBK2012170YZF_0805 1
C267
2.2U_0603_6.3V4Z
2
1 2
R43
4.7K_0402_5%
POWER_SEL
+AVDDQ
<23> GMCH_CRT_R
<23> GMCH_CRT_G
<23> GMCH_CRT_B
<15,23> GMCH_CRT_HSYNC
<15,23> GMCH_CRT_VSYNC
<23> GMCH_CRT_CLK
<23> GMCH_CRT_DATA
+1.8VS
<16> CLK_NBHT
<16> CLK_NBHT#
<16> CLK_NBGFX
<16> CLK_NBGFX#
<16> CLK_SBLINK_BCLK
<16> CLK_SBLINK_BCLK#
POWER_SEL
1.1V
HIGH 1.0V
1
C265
2.2U_0603_6.3V4Z
2
<4mA>
+NB_PLLVDD
+NB_HTPVDD
+VDDA18HTPLL
+VDDA18PCIEPLL
R319
0_0402_5%
1 2
1 2
R326
300_0402_5%
<24> GMCH_LCD_CLK
<24> GMCH_LCD_DATA
2
@ 1
R327
10K_0402_5%
<15>
AUX_CAL
Strap pin
<20mA>
GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B
+NB_PLLVDD
+NB_HTPVDD
NB_RESET#
NB_LDTSTOP#
NB_ALLOW_LDTSTOP
CLK_NB_14.318M
GMCH_LCD_CLK
GMCH_LCD_DATA
U22C
F12
AVDD1(NC)
E12
AVDD2(NC)
F14
AVDDDI(NC)
G15
AVSSDI(NC)
H15
AVDDQ(NC)
H14
AVSSQ(NC)
E17
C_Pr(DFT_GPIO5)
F17
Y(DFT_GPIO2)
F15
COMP_Pb(DFT_GPIO4)
G18
RED(DFT_GPIO0)
G17
REDb(NC)
E18
GREEN(DFT_GPIO1)
F18
GREENb(NC)
E19
BLUE(DFT_GPIO3)
F19
BLUEb(NC)
GMCH_CRT_HSYNC A11
GMCH_CRT_VSYNC
DAC_HSYNC(PWM_GPIO4)
B11
GMCH_CRT_CLK
DAC_VSYNC(PWM_GPIO6)
F8
GMCH_CRT_DATA
DAC_SCL(PCE_RCALRN)
E8
DAC_SDA(PCE_TCALRN)
R59 1 2
715_0402_1% G14
DAC_RSET(PWM_GPIO1)
1 2
R552
2K_0402_1%
1 2
R320
@
0_0402_5%
A12
PLLVDD(NC)
D14
PLLVDD18(NC)
B12
PLLVSS(NC)
H17
VDDA18HTPLL
D7
VDDA18PCIEPLL1
E7
VDDA18PCIEPLL2
D8
SYSRESETb
A10
POWERGOOD
C10
LDTSTOPb
C12
ALLOW_LDTSTOP
C25
HT_REFCLKP
C24
HT_REFCLKN
E11
REFCLK_P/OSCIN(OSCIN)
F11
REFCLK_N(PWM_GPIO3)
T2
GFX_REFCLKP
T1
GFX_REFCLKN
U1
GPP_REFCLKP
U2
GPP_REFCLKN
B9
I2C_CLK
A9
I2C_DATA
B8
DDC_DATA0/AUX0N(NC)
A8
DDC_CLK0/AUX0P(NC)
B7
DDC_CLK1/AUX1P(NC)
A7
DDC_DATA1/AUX1N(NC)
B10
STRP_DATA
C8
AUX_CAL(NC)
RS780M_FCBGA528
PART 3 OF 6
CRT/TVOUT
CLOCKs PM
PLL PWR
LVTM
V4
GPPSB_REFCLKP(SB_REFCLKP)
V3
GPPSB_REFCLKN(SB_REFCLKN)
G11
RSVD
MIS.
RS780MN-SA00002DR30 Ver:A13
TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)
TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3P(PCIE_RESET_GPIO5)
TXOUT_U3N(NC)
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)
VDDLTP18(NC)
VSSLTP18(NC)
VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)
VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
TMDS_HPD(NC)
HPD(NC)
SUS_STAT#(PWM_GPIO5)
THERMALDIODE_P
THERMALDIODE_N
TESTMODE
A22
B22
A21
B21
B20
A20
A19
B19
B18
A18
A17
B17
D20
D21
D18
D19
B16
A16
D16
D17
A13 <15mA>
B13
+VDDLTP18
A15 <300mA> +VDDLT18
B15
A14
B14
C14
D15
C16
C18
C20
E20
C22
E9
F7
G12
D9
D10
D12
AE8
AD8
1
2
4.7K_0402_5%
R15
1
2
4.7K_0402_5%
D13 1 2
R343
1.8K_0402_5%
VARY_ENBKL
2 VARY@ 1
4.7K_0402_5%
R54
R56
2
@ 1
R328
10K_0402_5%
1 2
R48
0_0402_5%
GMCH_TXOUT0+ <24>
GMCH_TXOUT0- <24>
GMCH_TXOUT1+ <24>
GMCH_TXOUT1- <24>
GMCH_TXOUT2+ <24>
GMCH_TXOUT2- <24>
GMCH_TZOUT0+ <24>
GMCH_TZOUT0- <24>
GMCH_TZOUT1+ <24>
GMCH_TZOUT1- <24>
GMCH_TZOUT2+ <24>
GMCH_TZOUT2- <24>
GMCH_TXCLK+ <24>
GMCH_TXCLK- <24>
GMCH_TZCLK+ <24>
GMCH_TZCLK- <24>
+VDDLTP18
+VDDLT18
C115
0.1U_0402_16V4Z
R49 1 2
0_0402_5%
R50 1 2
0_0402_5%
R57 1 VARY@ 2
0_0402_5%
R51 1 VARY@ 2
0_0402_5%
SUS_STAT# <18>
SUS_STAT_R# <15> Strap Pin
1
2
L51
1 2
1
MBC1608121YZF_0603
C449
2.2U_0603_6.3V4Z
2
1
L49
1 2
MBC1608121YZF_0603
C455
4.7U_0805_10V4Z
2
GMCH_ENVDD <24>
ENBKL <28>
+1.8VS
GMCH_INVT_PWM <24>
+1.8VS
D
C
B
+1.8VS
<8,17> LDT_STOP#
LDT_STP# (SB)
Output, OD
R85
0_0402_5%
1 2
NB_LDTSTOP#
LDTSTOP# (NB)
In Lagcy mode: Input, 1.8V signal can be used
In CLMC mode: Output, OD
<17> ALLOW_LDTSTOP
SB: I/ OD
1 2
R28
300_0402_5%
R553
0_0402_5%
1 2 NB_ALLOW_LDTSTOP
ALLOW_LDTSTOP (NB)
In Lagcy mode: Output,OD
In CLMC mode: Input, 1.8Vsignal can be used
A
A
5
4
Security Classification
Compal Secret Data
Issued Date
2005/03/08 Deciphered Date
2010/03/12
Title
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
401743
C
Date: Wednesday, June 24, 2009
Sheet 13 of
47
3
2
1
Compal Electronics, Inc.
5
4
3
2
1
U22F
D
C
B
A
+1.8VS
L14
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.1VS
2
1
+VDDHT
FBMA-L11-201209-221LMA30T_0805
1 1 1 1 1
L16
C108
C131
C249
C253
C126
2
1
+1.1VS
FBMA-L11-201209-221LMA30T_0805
2 2 2 2 2
U22E
<1.1A>
22U_0805_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
J17
+VDDA11PCIE
VDDHT_1
VDDPCIE_1
A6
1 2
K16
VDDHT_2
PART 5/6 VDDPCIE_2
B6
C19 1 2
22U_0805_6.3V6M
L16
C15
22U_0805_6.3V6M
L22
VDDHT_3
VDDPCIE_3
C6
M16
2
1
0.1U_0402_16V4Z
+VDDHTRX
VDDHT_4
VDDPCIE_4
D6
0.1U_0402_16V4Z
P16
VDDHT_5
VDDPCIE_5
E6
C42 1 2
1U_0402_6.3V4Z
0.68A
R16
C59 1 2
1U_0402_6.3V4Z
FBMA-L11-201209-221LMA30T_0805
VDDHT_6
VDDPCIE_6
F6
1 1 1 1 1
T16
VDDHT_7
VDDPCIE_7
G7
C44 1 2
1U_0402_6.3V4Z
<680mA>
C38 1 2
1U_0402_6.3V4Z
C257
VDDPCIE_8
H8
C154
C219
C264
C273
H18
VDDHTRX_1
VDDPCIE_9
J9
G19
2
VDDHTRX_2
VDDPCIE_10
K9
1 2
2
2 2 2
F20
VDDHTRX_3
VDDPCIE_11
M9
C51 1 2
0.1U_0402_16V4Z
22U_0805_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
E21
VDDHTRX_4
VDDPCIE_12
L9
C43
0.1U_0402_16V4Z
D22
VDDHTRX_5
VDDPCIE_13
P9
B23
VDDHTRX_6
VDDPCIE_14
R9
A23
L21
VDDHTRX_7
VDDPCIE_15
T9
+1.2V_HT 2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z +VDDHTTX
VDDPCIE_16
V9
<680mA> AE25
VDDHTTX_1
VDDPCIE_17
U9
AD24
@
L7
FBMA-L11-201209-221LMA30T_0805
VDDHTTX_2
1 1 1 1 1
AC23
VDDHTTX_3
VDDC_1
K12
+1.1VS
2
1
AB22
C130
C171
VDDHTTX_4
VDDC_2
J14
FBMA-L11-201209-221LMA30T_0805
C262
C258
C255
AA21
VDDHTTX_5
VDDC_3
U16
2
1
Y20
FBMA-L11-201209-221LMA30T_0805
2
2
VDDHTTX_6
VDDC_4
J11
2
2
2
W19
@L6
VDDHTTX_7
VDDC_5
K15
22U_0805_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
V18
VDDHTTX_8
VDDC_6
M12
U17
VDDHTTX_9
VDDC_7
L14
<7.6A>
T17
VDDHTTX_10
VDDC_8
L11
R17
VDDHTTX_11
VDDC_9
M13
P17
VDDHTTX_12
VDDC_10
M15
M17
L9
VDDHTTX_13
VDDC_11
N12
2
1
+VDDA18PCIE
VDDC_12
N14
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
<700mA> J10
1 1
2
FBMA-L11-201209-221LMA30T_0805
VDDA18PCIE_1
VDDC_13
P11
1 1 1 1 1 1 1 2
P10
VDDA18PCIE_2
VDDC_14
P13
+
1
1 1 1 1 1 1
K10
VDDA18PCIE_3
VDDC_15
P14
C52
M10
C37
C58
VDDA18PCIE_4
VDDC_16
R12
22U_0805_6.3V6M
C53
C55
C56
C62
2 2 2 2 2 2 2 2 2 1 1 2
L10
VDDA18PCIE_5
VDDC_17
R15
W9
2
2
VDDA18PCIE_6
VDDC_18
T11
2
22U_0805_6.3V6M 2
2
2 2
H9
4.7U_0805_10V4Z
0.1U_0402_16V4Z
VDDA18PCIE_7
VDDC_19
T15
0.1U_0402_16V4Z
T10
VDDA18PCIE_8
VDDC_20
U12
R10
VDDA18PCIE_9
VDDC_21
T14
Y9
VDDA18PCIE_10
VDDC_22
J16
AA9
VDDA18PCIE_11
AB9
VDDA18PCIE_12 VDD_MEM1(NC)
AE10
AD9
VDDA18PCIE_13 VDD_MEM2(NC)
AA11
AE9
VDDA18PCIE_14 VDD_MEM3(NC)
Y11
U10
VDDA18PCIE_15 VDD_MEM4(NC)
AD10
VDD_MEM5(NC)
AB10
+1.8VS
<10mA> F9
VDD18_1
VDD_MEM6(NC)
AC10
G9
VDD18_2
1
+1.8VS <25mA> AE11
<60mA>
+3VS
C398
VDD18_MEM1(NC) VDD33_1(NC)
H11
AD11
1U_0402_6.3V4Z
VDD18_MEM2(NC) VDD33_2(NC)
H12
1
1
RS780M_FCBGA528
2
RS780MN-SA00002DR30 Ver:A13
C93
C61
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
POWER
0.1U_0402_16V4Z
C110
0.1U_0402_16V4Z
C112
0.1U_0402_16V4Z
C57
0.1U_0402_16V4Z
C123
0.1U_0402_16V4Z
C215
0.1U_0402_16V4Z
C256
0.1U_0402_16V4Z
C80
0.1U_0402_16V4Z
C218
0.1U_0402_16V4Z
C251
22U_0805_6.3V6M
C18
22U_0805_6.3V6M
C20
C10
330U_D2E_2.5VM_R9M
+NB_CORE
A25
VSSAHT1
VSSAPCIE1
A2
D23
VSSAHT2
PART 6/6 VSSAPCIE2
B1
E22
VSSAHT3
VSSAPCIE3
D3
G22
VSSAHT4
VSSAPCIE4
D5
G24
VSSAHT5
VSSAPCIE5
E4
G25
VSSAHT6
VSSAPCIE6
G1
H19
VSSAHT7
VSSAPCIE7
G2
J22
VSSAHT8
VSSAPCIE8
G4
L17
VSSAHT9
VSSAPCIE9
H7
L22
VSSAHT10
VSSAPCIE10
J4
L24
VSSAHT11
VSSAPCIE11
R7
L25
VSSAHT12
VSSAPCIE12
L1
M20
VSSAHT13
VSSAPCIE13
L2
N22
VSSAHT14
VSSAPCIE14
L4
P20
VSSAHT15
VSSAPCIE15
L7
R19
VSSAHT16
VSSAPCIE16
M6
R22
VSSAHT17
VSSAPCIE17
N4
R24
VSSAHT18
VSSAPCIE18
P6
R25
VSSAHT19
VSSAPCIE19
R1
H20
VSSAHT20
VSSAPCIE20
R2
U22
VSSAHT21
VSSAPCIE21
R4
V19
VSSAHT22
VSSAPCIE22
V7
W22
VSSAHT23
VSSAPCIE23
U4
W24
VSSAHT24
VSSAPCIE24
V8
W25
VSSAHT25
VSSAPCIE25
V6
Y21
VSSAHT26
VSSAPCIE26
W1
AD25
VSSAHT27
VSSAPCIE27
W2
VSSAPCIE28
W4
L12
VSS11
VSSAPCIE29
W7
M14
VSS12
VSSAPCIE30
W8
N13
VSS13
VSSAPCIE31
Y6
P12
VSS14
VSSAPCIE32
AA4
P15
VSS15
VSSAPCIE33
AB5
R11
VSS16
VSSAPCIE34
AB1
R14
VSS17
VSSAPCIE35
AB7
T12
VSS18
VSSAPCIE36
AC3
U14
VSS19
VSSAPCIE37
AC4
U11
VSS20
VSSAPCIE38
AE1
U15
VSS21
VSSAPCIE39
AE4
V12
VSS22
VSSAPCIE40
AB2
W11
VSS23
W15
VSS24
AC12
VSS25
VSS1
AE14
AA14
VSS26
VSS2
D11
Y18
VSS27
VSS3
G8
AB11
VSS28
VSS4
E14
AB15
VSS29
VSS5
E15
AB17
VSS30
VSS6
J15
AB19
VSS31
VSS7
J12
AE20
VSS32
VSS8
K14
AB21
VSS33
VSS9
M11
K11
VSS34
VSS10
L15
GROUND
RS780M_FCBGA528
RS780MN-SA00002DR30 Ver:A13
U22D
PAR 4 OF 6
AB12
MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC)
AE16
MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC)
V11
MEM_A2(NC)
MEM_DQ2/DVO_DE(NC)
AE15
MEM_A3(NC)
MEM_DQ3/DVO_D0(NC)
AA12
MEM_A4(NC)
MEM_DQ4(NC)
AB16
MEM_A5(NC)
MEM_DQ5/DVO_D1(NC)
AB14
MEM_A6(NC)
MEM_DQ6/DVO_D2(NC)
AD14
MEM_A7(NC)
MEM_DQ7/DVO_D4(NC)
AD13
MEM_A8(NC)
MEM_DQ8/DVO_D3(NC)
AD15
MEM_A9(NC)
MEM_DQ9/DVO_D5(NC)
AC16
MEM_A10(NC)
MEM_DQ10/DVO_D6(NC)
AE13
MEM_A11(NC)
MEM_DQ11/DVO_D7(NC)
AC14
MEM_A12(NC)
MEM_DQ12(NC)
Y14
MEM_A13(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
AD16
MEM_BA0(NC) MEM_DQ15/DVO_D11(NC)
AE17
MEM_BA1(NC)
AD17
MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
W12
MEM_RASb(NC)
MEM_DQS1P(NC)
Y12
MEM_CASb(NC)
MEM_DQS1N(NC)
AD18
MEM_WEb(NC)
AB13
MEM_CSb(NC)
MEM_DM0(NC)
AB18
MEM_CKE(NC)
MEM_DM1/DVO_D8(NC)
V14
MEM_ODT(NC)
IOPLLVDD18(NC)
V15
MEM_CKP(NC)
IOPLLVDD(NC)
W14
MEM_CKN(NC)
IOPLLVSS(NC)
AE12
MEM_COMPP(NC)
AD12
MEM_COMPN(NC)
MEM_VREF(NC)
SBD_MEM/DVO_I/F
RS780M_FCBGA528
RS780MN-SA00002DR30 Ver:A13
AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21
Y17
W18
AD20
AE21
W17
AE19
AE23
AE24
AD23
+1.8VS
+1.1VS
AE18 1 2
R351
0_0402_5%
D
C
B
A
WWW.AliSaler.Com
5
4
Security Classification
Compal Secret Data
Issued Date
2005/03/08 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
401743 C
Date: Wednesday, June 24, 2009
Sheet 14 of
47
3
2
1
5
4
3
2
1
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
D
<13,23> GMCH_CRT_VSYNC
2
R341
R337
2
1
3K_0402_5%
@ 3K_0402_5%
1
+3VS
Enables the Test Debug Bus using GPIO. (VSYNC)
1 : Disable (RS780)
0 : Enable (Rs780)
D
DFT_GPIO1: LOAD_EEPROM_STRAPS
RS780 DFT_GPIO1
<13> AUX_CAL
@R315
1 150_0402_1%
2
@
<13> SUS_STAT_R#
2 1
PLT_RST# <13,17,25,28,31>
D22
CH751H-40PT_SOD323-2
Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT
C
C
RS780 use HSYNC to enable SIDE PORT
<13,23> GMCH_CRT_HSYNC
2
R332
1
3K_0402_5%
2
@ 1
R331
3K_0402_5%
+3VS
RS780 use HSYNC to enable SIDE PORT
RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)
0. Enable (RS780)
1 : Disable(RS780)
B
B
A
A
5
4
Security Classification
Compal Secret Data
Issued Date
2005/10/10 Deciphered Date
2010/03/12
Title
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
401743
C
Date: Wednesday, June 24, 2009
Sheet 15 of
47
3
2
1
Compal Electronics, Inc.
5
4
3
2
1
+1.2V_HT
+VDDCLK_IO
L30
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
1
1
FBMA-L11-201209-221LMA30T_0805
C260
C142
C298
C293
C280
C135
2
2
2
2
2
2
22U_0805_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C263
2
+3VS
+3VS_CLK
L31
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
1
FBMA-L11-201209-221LMA30T_0805
C367
C138
C278
C404
C295
22U_0805_6.3V6M
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
C274
C160
C140
C268
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C294
2
0.1U_0402_16V4Z
1
C297
1U_0402_6.3V4Z
2
D
+3VS_CLK
L36
1 2
+3VS_CLKVDDA
1U CLOSE PIN 69
D
+3VS_CLK
FBMA-L11-201209-221LMA30T_0805
22U_0805_6.3V6M
1
C161
2
1
2
C141
0.1U_0402_16V4Z
49
48
U15
VDDA
GNDA
ICS 9LPRS488
SMBCLK 1
SMBDAT
2
SB_CK_SCLK <10,11,18,31>
SB_CK_SDAT <10,11,18,31>
C
1 2
R112
8.2K_0402_5%
@
R182
8.2K_0402_5%
1 2
1 2
1 2
R187
@
8.2K_0402_5%
SEL_SATA
SEL_HT66
R188
@
8.2K_0402_5%
LAN request <25> LAN_CLKREQ#
MiniCard1 request <31> MINI1_CLKREQ#
R495 8.2K_0402_5%
1 2
+3VS_CLK
+3VS_CLK
R490 8.2K_0402_5%
1 2
C277 2 1
0.1U_0402_16V4Z
+VDDCLK_IO
+3VS_CLK
+3VS
L35
1 2
FBM-L11-160808-800LMT_0603
1 2
C282
@
2.2U_0603_6.3V4Z
1 2
C281
0.1U_0402_16V4Z
62
66
12
18
28
37
53
3
17
29
38
44
54
61
69
24
51
50
43
42
VDDREF
GNDREF
VDDSRC_IO
VDDSRC_IO
VDDATIG_IO
VDDSB_SRC_IO
VDDCPU_IO
VDDDOT
VDDSRC
VDDATIG
VDDSB_SRC
VDDSATA
VDDCPU
VDDHTT
VDD48
CLKREQ0 #
CLKREQ1#
CLKREQ2#
CLKREQ3#
CLKREQ4#
SB_SRC_SLOW#
41
CPUKG0T_LPRS 56
CPUKG0C_LPRS 55
HTT0T_LPRS / 66 M 60
HTT0C_LPRS / 66 M 59
SB_SRC0T_LPRS 40
SB_SRC0C_LPRS 39
SB_SRC1T_LPRS 35
SB_SRC1C_LPRS 34
ATIG0T_LPRS 33
ATIG0C_LPRS 32
ATIG1T_LPRS 31
ATIG1C_LPRS 30
ATIG2T_LPRS 26
ATIG2C_LPRS 25
SRC0T_LPRS 23
SRC0C_LPRS 22
SRC_SLOW
CLK_CPU
CLK_CPU#
CLK_HTT
CLK_HTT#
CLK_ATIG0
CLK_ATIG0#
CLK_SRC0
CLK_SRC0#
1 2
R170 1 2
47.5_0402_1%
R168
47.5_0402_1%
1 2
R175 1 2
0_0402_5%
R172
0_0402_5%
1 2
R174 1 2
0_0402_5%
R176
0_0402_5%
1 2
R189 1 2
0_0402_5%
R190
0_0402_5%
1 2
R169
261_0402_1%
CLK_NBHT <13>
CLK_NBHT# <13>
CLK_NBGFX <13>
CLK_NBGFX# <13>
CLK_PCIE_LAN <25>
CLK_PCIE_LAN# <25>
CLK_CPU_BCLK <8>
CLK_CPU_BCLK# <8>
NB HTT
NB GFX
LAN
CPU
SRC_SLOW
+3VS_CLK
@
1 2 1
2
R161
8.2K_0402_5%
R111
8.2K_0402_5%
C
B
External 14MHz CLK
for SB710
CLK_XTAL_OUT
<17> CLK_14M_SB
R109
33_0402_5%
1 2
SEL_SATA
<13> CLK_NB_14.318M
1 2 SEL_HT66
R179
158_0402_1%
1 2
R178
90.9_0402_1%
<27> CLK_48M_SD
2 1 CLK_48M_0
R194
33_0402_5%
<18> CLK_48M_USB
2 1 CLK_48M_1
R193
33_0402_5%
CLK_XTAL_IN
CLK_XTAL_OUT
63
64
65
71
70
67
68
REF2/SEL_27
REF1/SEL_SATA
REF0/SEL_HTT66
48MHz_0
48MHz_1
X1
X2
SRC1T_LPRS 21
SRC1C_LPRS 20
SRC2T_LPRS 16
SRC2C_LPRS 15
SRC3T_LPRS 14
SRC3C_LPRS 13
SRC4T_LPRS 10
SRC4C_LPRS 9
SRC5T_LPRS 8
SRC5C_LPRS 7
CLK_SRC2
CLK_SRC2#
CLK_SRC4
CLK_SRC4#
1 2
R197 1 2
0_0402_5%
R196
0_0402_5%
1 2
R200 1 2
0_0402_5%
R199
0_0402_5%
CLK_PCIE_MINI1 <31>
CLK_PCIE_MINI1# <31>
CLK_SBLINK_BCLK <13>
CLK_SBLINK_BCLK# <13>
MiniCard
NB A LINK
SRC 0
SRC 1
SRC 2
SRC 3
SRC 4
LAN
MINI1 (WLAN)
NEW CARD
NB-Alink
B
CLK_XTAL_IN
Y4
2 1 FUJICOM
14.31818MHZ_20P_6X1430004201
1
1
C290
C288
33P_0402_50V8J
33P_0402_50V8J
2
2
6
GNDDOT
11
GNDSRC
19
GNDSRC
27
GNDATIG
36
GNDSB_SRC
47
GNDSATA
52
GNDCPU
58
GNDHTT
72
GND48
73
GNDPAD
SRC7T_LPRS/27MHz_SS 5
SRC7C_LPRS/27MHz_NS 4
ICS9LPRS488AKLFT_MLF72_10x10
SRC6T/SATAT_LPRS 46
SRC6C/SATAC_LPRS 45
Main--SLG8SP626VTR-SA00001Z310
Second--ICS9LPRS488CKLFT-SA000023H10
PD#
57
@
CLK_SRC6
CLK_SRC6#
2 1
R173
8.2K_0402_5%
1
C299
1U_0402_6.3V4Z
2
1 2
R163 1 2
0_0402_5%
R164
0_0402_5%
+3VS_CLK
CLK_SBSRC_BCLK <17>
CLK_SBSRC_BCLK# <17>
SB RCLK
HT_REFCLKP
SRC 5
SRC 6
SB-Alink
NB CLOCK INPUT TABLE
NB CLOCKS RS740 RX780 RS780
HT_REFCLKN
REFCLK_P
REFCLK_N
GFX_REFCLK
66M SE(SINGLE END) 100M DIFF
NC
100M DIFF
100M DIFF
100M DIFF
14M SE (3.3V) 14M SE (1.8V) 14M SE (1.1V)
NC NC vref
100M DIFF
100M DIFF
100M DIFF(IN/OUT)*
A
GPP_REFCLK
NC
100M DIFF
GPPSB_REFCLK 100M DIFF
100M DIFF 100M DIFF
NC
A
1 configure as single-ended 66MHz output
SEL_27M 1 configure as 27M and 27M_SS output
SEL_HTT66
No used
0* configure as differential 100MHz output
0 configure as SRC_7 output
1* SS 100M SATA SRC6 output
SEL_SATA
0 SS 100M SATA SRC6 output
* default
WWW.AliSaler.Com
5
4
Security Classification
Compal Secret Data
Issued Date
2005/03/08 Deciphered Date
2010/03/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
401743
C
Date: Wednesday, June 24, 2009
Sheet 16 of
47
3
2
1
Compal Electronics, Inc.
SCHEMATIC, MB A5481
5
4
3
2
1
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
C172
C246
C402
C176
C183
C186
C204
C214
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
A_RST#
0.1U_0402_16V7K SB_RX0P_C
0.1U_0402_16V7K SB_RX0N_C
0.1U_0402_16V7K SB_RX1P_C
0.1U_0402_16V7K SB_RX1N_C
0.1U_0402_16V7K SB_RX2P_C
0.1U_0402_16V7K SB_RX2N_C
0.1U_0402_16V7K SB_RX3P_C
0.1U_0402_16V7K SB_RX3N_C
U10A
N2
A_RST#
V23
PCIE_TX0P
V22
PCIE_TX0N
V24
PCIE_TX1P
V25
PCIE_TX1N
U25
PCIE_TX2P
U24
PCIE_TX2N
T23
PCIE_TX3P
T22
PCIE_TX3N
SB700
Part 1 of 5
PCI CLKS
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5/GPIO41
PCIRST#
P4
P3
P1
P2
T4
T3
N1
PCI_CLK2 <21>
PCI_CLK3 <21>
PCI_CLK4 <21> Strap pin
PCI_CLK5 <21>
D
C
B
<12> SB_TX0P
U22
<12> SB_TX0N
U21
<12> SB_TX1P
U19
<12> SB_TX1N
V19
<12> SB_TX2P
R20
<12> SB_TX2N
R21
<12> SB_TX3P
R18
<12> SB_TX3N
R17
R127 2 1
562_0402_1% T25
+PCIE_VDDR
R131 2 1
2.05K_0402_1% T24
+1.2V_HT 1 2
+SB_PCIEVDD <43mA> P24
L59
2 1
MBC1608121YZF_0603
C468
C472
P25
1 2 A_RST#
2.2U_0402_6.3V6M 1
1U_0402_6.3V4Z
R135
@
8.2K_0402_5%
2
+3VALW
C177
2 1
0.1U_0402_16V4Z
U11
<16> CLK_SBSRC_BCLK
N25
2
B
<16> CLK_SBSRC_BCLK#
N24
PLT_RST#
PLT_RST# <13,15,25,28,31>
A_RST#
Y
4
1
A
K23
K22
NC7SZ08P5X_NL_SC70-5
R293
@
M24
M25
100K_0402_5%
2 1
P17
R134
@
33_0402_5%
M18
M23
M22
J19
J18
L20
L19
M19
External 14MHz for SB710
M20
N22
@R101
20M_0402_5%
P22
1 2
<16> CLK_14M_SB
L18
C203
1 2
SB_32KHI
R635
J21
@ Y2
10_0402_5%
18P_0402_50V8J
4
R91
OUT NC 3
1
J20
20M_0603_5%
1
IN NC 2 C690
@ C403
32.768KHZ_12.5P_MC-306
22P_0402_50V8J
2
1 2
SB_32KHO
SB_32KHI A3
18P_0402_50V8J
Close to SB
SB_32KHO B3
1
2
5
P
G
3
1
2
1
2
PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_CALRP
PCIE_CALRN
PCIE_PVDD
PCIE_PVSS
RTC XTAL
PCI EXPRESS INTERFACE
PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN
NB_DISP_CLKP
NB_DISP_CLKN
NB_HT_CLKP
NB_HT_CLKN
CPU_HT_CLKP
CPU_HT_CLKN
SLT_GFX_CLKP
SLT_GFX_CLKN
GPP_CLK0P
GPP_CLK0N
GPP_CLK1P
GPP_CLK1N
GPP_CLK2P
GPP_CLK2N
GPP_CLK3P
GPP_CLK3N
25M_48M_66M_OSC
25M_X1
25M_X2
X1
X2
LPC
CLOCK GENERATOR
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#
REQ3#/GPIO70
REQ4#/GPIO71
GNT0#
GNT1#
GNT2#
GNT3#/GPIO72
GNT4#/GPIO73
CLKRUN#
LOCK#
INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/GNT5#/GPIO68
BMREQ#/REQ5#/GPIO65
SERIRQ
PCI INTERFACE
U2
P7
V4
T1
V3
U1
V1
V2
T2
W1
T9
R6
R7
R5
U8
U5
Y7
W8
V9
Y8
AA8
Y4
Y3
Y2 PCI_AD23
PCI_AD23 <21>
AA2 PCI_AD24
PCI_AD24 <21>
AB4 PCI_AD25
PCI_AD25 <21>
AA1 PCI_AD26
PCI_AD26 <21>
AB3 PCI_AD27
PCI_AD27 <21>
AB2 PCI_AD28
PCI_AD28 <21>
AC1
AC2
AD1
W2
U7
AA7
Y1
AA6
W5
AA5
Y5
U6
W6
W4
V7
AC3
AD4
AB7
AE6
AB6
AD2
AE4
AD5
AC6
AE5
AD6
1 2
PM_CLKRUN# <28>
V5
R149
0_0402_5%
AD3
AC4
AE2
AE3
G22 CLK_LPC_EC
R108 1 2
22_0402_5% CLK_PCI_EC
E22
H24
LPC_AD0 <28>
H23
LPC_AD1 <28>
J25
LPC_AD2 <28>
J24
LPC_AD3 <28>
H25
LPC_FRAME# <28>
H22
AB8
AD7
V15
SERIRQ <28>
CLK_PCI_EC <21,28>
LPCCLK1 <21>
STRAP PIN
D
C
B
<13> ALLOW_LDTSTOP
<8> H_PROCHOT_R#
<8> H_PWRGD
<8,13> LDT_STOP#
<8> LDT_RST#
F23
F24
F22
G25
G24
ALLOW_LDTSTP
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#
CPU
RTCCLK
INTRUDER_ALERT#
VBAT
C3
C2
B2
1 @ 2
R107
1M_0402_5%
RTC_CLK <21>
+RTCVCC
STRAP PIN
+RTCVCC
+RTCBATT
A
LDT_PG: OD pin
RTC
218S7EALA11FG_BGA528_SB700
SB710 Ver:A14 <SA000030740>
C405
0.1U_0402_16V4Z
1
2
1
2
1 2
R385
510_0402_5%
C134 W=20mils
1U_0402_6.3V4Z
@
for Clear CMOS
R556
1K_0402_5%
2 1
1
R379
C339
0_0603_5%
2
0.1U_0402_16V4Z
D5
3
1
2
BAS40-04_SOT23-3
+CHGRTC
A
5
4
Security Classification
Compal Secret Data
Issued Date
2005/03/08 Deciphered Date
2010/03/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
401743
Wednesday, June 24, 2009
Date: Sheet of
17 47
3
2
1
Compal Electronics, Inc.
SCHEMATIC, MB A5481
5
4
3
2
1
D
C
B
+3VS
+3VS
1 2 SUS_STAT#_L
R395
4.7K_0402_5%
1 2
RSMRST#
R389
2.2K_0402_5%
<35> HDA_BITCLK_AUDIO
<34> HDA_BITCLK_MDC
<34> HDA_SDOUT_MDC
<35> HDA_SDOUT_AUDIO
<35> HDA_SDIN0
<34> HDA_SDIN1
+3VALW
R409
R399
MDC: option
R525
1 2
2.2K_0402_5%
1 2
2.2K_0402_5%
R393 2
R391 2
R116 2
SB_CK_SCLK
SB_CK_SDAT
<34> HDA_SYNC_MDC
<35> HDA_SYNC_AUDIO
<35> HDA_RST_AUDIO#
<34> HDA_RST_MDC#
STRAP PIN<21>
HDARST#
@ 10K_0402_5%
1
@ 10K_0402_5%
1
@ 10K_0402_5%
1
1 @ 2
100K_0402_5%
HDA_SDIN0
HDA_SDIN1
HDA_BITCLK
EC_LID_OUT#
<13> SUS_STAT#
HDA_BITCLK
HDA_SDOUT
HDA_SDIN0
HDA_SDIN1
CRT_DET_R
<28> PM_SLP_S3#
<28> PM_SLP_S5#
<28> PBTN_OUT#
SUS_STAT#
<8,33> SB_PWRGD
1 2
SUS_STAT#_L
R555
0_0402_5%
TP10
TP11
TP12
<31> SB_PCIE_WAKE#
<8> H_THERMTRIP#
<13> NB_PWRGD
+3VS
SKU ID: UMA
Combine NAL00 SW code
R119 33_0402_5% 1 2
R118 33_0402_5% 1 @ 2
R121 33_0402_5% 1 2
R120 33_0402_5% 1 2
<28>
<28>
EC_SWI#
<28> EC_GA20
<28> EC_KBRST#
<28> EC_SCI#
<28> EC_SMI#
RSMRST#
<35> SB_SPKR
<10,11,16,31> SB_CK_SCLK
CLK Gen, WLAN, DDR <10,11,16,31> SB_CK_SDAT
R123 33_0402_5% 1 2
R125 33_0402_5% 1 2
<28> EC_LID_OUT#
R117 33_0402_5% 1 2
R122 33_0402_5% 1 2
1 2
R404
@
2.2K_0402_5%
1 2
R410
2.2K_0402_5%
<32> USB_OC#1
<32> USB_OC#0
+3VS
H_THERMTRIP#
NB_PWRGD
RSMRST#
HDA_SYNC
HDARST#
SKUID
SB_CK_SCLK
SB_CK_SDAT
USB_OC#1
USB_OC#0
1 @ 2
R126
2.2K_0402_5%
U10D
E1
PCI_PME#/GEVENT4#
E2
RI#/EXTEVNT0#
H7
SLP_S2/GPM9#
F5
SLP_S3#
G1
SLP_S5#
H2
PWR_BTN#
H1
PWR_GOOD
K3
SUS_STAT#
H5
TEST2
H4
TEST1
H3
TEST0
Y15
GA20IN/GEVENT0#
W15
KBRST#/GEVENT1#
K4
LPC_PME#/GEVENT3#
K24
LPC_SMI#/EXTEVNT1#
F1
S3_STATE/GEVENT5#
J2
SYS_RESET#/GPM7#
H6
WAKE#/GEVENT8#
F2
BLINK/GPM6#
J6
SMBALERT#/THRMTRIP#/GEVENT2#
W14
NB_PWRGD
D3
RSMRST#
B9
USB_OC6#/IR_TX1/GEVENT6#
B8
USB_OC5#/IR_TX0/GPM5#
A8
USB_OC4#/IR_RX0/GPM4#
A9
USB_OC3#/IR_RX1/GPM3#
E5
USB_OC2#/GPM2#
F8
USB_OC1#/GPM1#
E4
USB_OC0#/GPM0#
HD AUDIO
218S7EALA11FG_BGA528_SB700
USB OC
INTEGRATED uC
SB700
ACPI / WAKE UP EVENTS
AE18
SATA_IS0#/GPIO10
AD18
CLK_REQ3#/SATA_IS1#/GPIO6
AA19
SMARTVOLT1/SATA_IS2#/GPIO4
W17
CLK_REQ0#/SATA_IS3#/GPIO0
V17
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39
W20
CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
W21
SPKR/GPIO2
AA18
SCL0/GPOC0#
W18
SDA0/GPOC1#
K1
SCL1/GPOC2#
K2
SDA1/GPOC3#
AA20
DDC1_SCL/GPIO9
Y18
DDC1_SDA/GPIO8
C1
LLB#/GPIO66
Y19
SMARTVOLT2/SHUTDOWN#/GPIO5
G5
DDR3_RST#/GEVENT7#
M1
AZ_BITCLK
M2
AZ_SDOUT
J7
AZ_SDIN0/GPIO42
J8
AZ_SDIN1/GPIO43
L8
AZ_SDIN2/GPIO44
M3
AZ_SDIN3/GPIO46
L6
AZ_SYNC
M4
AZ_RST#
L5
AZ_DOCK_RST#/GPM8#
H19
IMC_GPIO0
H20
IMC_GPIO1
H21
SPI_CS2#/IMC_GPIO2
F25
IDE_RST#/F_RST#/IMC_GPO3
D22
IMC_GPIO4
E24
IMC_GPIO5
E25
IMC_GPIO6
D23
IMC_GPIO7
INTEGRATED uC
USB MISC
GPIO
USB 1.1
USB 2.0
Part 4 of 5
USBCLK/14M_25M_48M_OSC
USB_RCOMP
USB_FSD13P
USB_FSD13N
USB_FSD12P
USB_FSD12N
USB_HSD11P
USB_HSD11N
USB_HSD10P
USB_HSD10N
USB_HSD9P
USB_HSD9N
USB_HSD8P
USB_HSD8N
USB_HSD7P
USB_HSD7N
USB_HSD6P
USB_HSD6N
USB_HSD5P
USB_HSD5N
USB_HSD4P
USB_HSD4N
USB_HSD3P
USB_HSD3N
USB_HSD2P
USB_HSD2N
USB_HSD1P
USB_HSD1N
USB_HSD0P
USB_HSD0N
IMC_GPIO8
IMC_GPIO9
IMC_PWM0/IMC_GPIO10
SCL2/IMC_GPIO11
SDA2/IMC_GPIO12
SCL3_LV/IMC_GPIO13
SDA3_LV/IMC_GPIO14
IMC_PWM1/IMC_GPIO15
IMC_PWM2/IMC_GPO16
IMC_PWM3/IMC_GPO17
IMC_GPIO18
IMC_GPIO19
IMC_GPIO20
IMC_GPIO21
IMC_GPIO22
IMC_GPIO23
IMC_GPIO24
IMC_GPIO25
IMC_GPIO26
IMC_GPIO27
IMC_GPIO28
IMC_GPIO29
IMC_GPIO30
IMC_GPIO31
IMC_GPIO32
IMC_GPIO33
IMC_GPIO34
IMC_GPIO35
IMC_GPIO36
IMC_GPIO37
IMC_GPIO38
IMC_GPIO39
IMC_GPIO40
IMC_GPIO41
C8
G8
E6
E7
F7
E8
H11
J10
E11
F11
A11
B11
C10
D10
G11
H12
E12
E14
C12
D12
B12
A12
G12
G14
H14
H15
A13
B13
B14
A14
A18
B18
F21
D21
F19
E20
E21
E19
D19
E18
G20
G21
D25
D24
C25
C24
B25
C23
B24
B23
A23
C22
A22
B22
B21
A21
D20
C20
A20
B20
B19
A19
D18
C18
USB_RCOMP 1 2
R390
11.8K_0402_1%
USB20_P5
USB20_N5
USB20_P4
USB20_N4
USB20_P3
USB20_N3
USB20_P1
USB20_N1
USB20_P0
USB20_N0
OHCI4 Disable
EHCI1 Disable
1 @ 2
R124
33_0402_5%
USB20_P5 <31>
USB20_N5 <31>
USB20_P4 <27>
USB20_N4 <27>
USB20_P3 <24>
USB20_N3 <24>
USB20_P1 <32>
USB20_N1 <32>
USB20_P0 <32>
USB20_N0 <32>
GPIO16 <21>
GPIO17 <21>
<23> CRT_DET#
STRAP PIN
STRAP PIN
@
1 2
C269
22P_0402_50V8J
CLK_48M_USB <16>
MiniCard1(WLAN)
Card Reader
Camera
M/B conn
M/B conn
2
Q40
G
2N7002_SOT23
1
3
CRT_DET
D
S
S3 Wake Up
S3 Power off
+3VALW
SB Power Domain :S5
High: CRT Plugged
R413
100K_0402_5%
1 2
1 @ 2 CRT_DET_R
R558
0_0402_5%
D
C
B
R415
1 2
10K_0402_5%
SB_PCIE_WAKE#
SB710 Ver:A14 <SA000030740>
A
A
WWW.AliSaler.Com
5
4
Security Classification
Compal Secret Data
Issued Date
2005/03/08 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
401743 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 18 of
47
3
2
1
5
4
3
2
1
Port Number
Pri/SEC,Mas/Slave assignment
SATA drive controlled by
Port 0
Primary master
SATA controler
D
Port 1
Secondary master
SATA controler
D
Port 2
Primary slave
SATA controler
C
B
27P_0402_50V8J 1 2
C276
25MHZ_20P
27P_0402_50V8J 1 2
C279
1
2
Y3
1
2
+3VS
R150
10M_0402_5%
Main
HDD
2nd
HDD
Main
ODD
2nd
ODD
SATA_X1
SATA_X2
<22> SATA_STX_DRX_P0
<22> SATA_STX_DRX_N0
<22> SATA_DTX_C_SRX_N0
<22> SATA_DTX_C_SRX_P0
<22> SATA_STX_DRX_P1
<22> SATA_STX_DRX_N1
<22> SATA_DTX_C_SRX_N1
<22> SATA_DTX_C_SRX_P1
<22> SATA_STX_DRX_P2
<22> SATA_STX_DRX_N2
<22> SATA_DTX_C_SRX_N2
<22> SATA_DTX_C_SRX_P2
<22> SATA_STX_DRX_P3
<22> SATA_STX_DRX_N3
<22> SATA_DTX_C_SRX_N3
<22> SATA_DTX_C_SRX_P3
+XTLVDD_SATA
C496
1 SATA_CAL
1K_0402_1%
SATA_X1
SATA_X2 AA12
+3VS
R401 1 2
10K_0402_5%
SATA_X2
+1.2V_HT
<34> SATA_LED#
W11
SATA_ACT#/GPIO67
L64
2
1
+PLLVDD_SATA
BLM18PG121SN1D_0603
<93mA> AA11
PLLVDD_SATA
1
C530
C497
1 <6mA> W12
XTLVDD_SATA
2.2U_0603_6.3V4Z
0.1U_0402_16V4Z
2
2
L62
2
1
BLM18PG121SN1D_0603 2
C493
1U_0402_6.3V4Z 1
2
R400
1
0.1U_0402_16V4Z
2
U10B
AD9
SATA_TX0P
AE9
SATA_TX0N
AB10
SATA_RX0N
AC10
SATA_RX0P
AE10
SATA_TX1P
AD10
SATA_TX1N
AD11
SATA_RX1N
AE11
SATA_RX1P
AB12
SATA_TX2P
AC12
SATA_TX2N
AE12
SATA_RX2N
AD12
SATA_RX2P
AD13
SATA_TX3P
AE13
SATA_TX3N
AB14
SATA_RX3N
AC14
SATA_RX3P
AE14
SATA_TX4P
AD14
SATA_TX4N
AD15
SATA_RX4N
AE15
SATA_RX4P
AB16
SATA_TX5P
AC16
SATA_TX5N
AE16
SATA_RX5N
AD16
SATA_RX5P
V12
Y12
SATA_CAL
SATA_X1
SATA PWR SERIAL ATA
SA00001S570 Ver:A12
SB700
Part 2 of 5
HW MONITOR
SPI ROM
218S7EALA11FG_BGA528_SB700
ATA 66/100/133
IDE_IORDY
AA24
IDE_IRQ
AA25
IDE_A0
Y22
IDE_A1
AB23
IDE_A2
Y23
IDE_DACK#
AB24
IDE_DRQ
AD25
IDE_IOR#
AC25
IDE_IOW#
AC24
IDE_CS1#
Y25
IDE_CS3#
Y24
IDE_D0/GPIO15
AD24
IDE_D1/GPIO16
AD23
IDE_D2/GPIO17
AE22
IDE_D3/GPIO18
AC22
IDE_D4/GPIO19
AD21
IDE_D5/GPIO20
AE20
IDE_D6/GPIO21
AB20
IDE_D7/GPIO22
AD19
IDE_D8/GPIO23
AE19
IDE_D9/GPIO24
AC20
IDE_D10/GPIO25
AD20
IDE_D11/GPIO26
AE21
IDE_D12/GPIO27
AB22
IDE_D13/GPIO28
AD22
IDE_D14/GPIO29
AE23
IDE_D15/GPIO30
AC23
SPI_DI/GPIO12
G6
SPI_DO/GPIO11
D2
SPI_CLK/GPIO47
D1
SPI_HOLD#/GPIO31
F4
SPI_CS1#/GPIO32
F3
LAN_RST#/GPIO13
U15
ROM_RST#/GPIO14
J1
FANOUT0/GPIO3
M8
FANOUT1/GPIO48
M5
FANOUT2/GPIO49
M7
FANIN0/GPIO50
P5
FANIN1/GPIO51
P8
FANIN2/GPIO52
R8
TEMP_COMM
C6
TEMPIN0/GPIO61
B6
TEMPIN1/GPIO62
A6
TEMPIN2/GPIO63
A5
TEMPIN3/TALERT#/GPIO64
B5
SB_SI_SPI_SO
SB_SO_SPI_SI
SB_SPICLK
SB_HOLD#
SB_SPICS#
Port 3
Port 4
Port 5
EC_THERM# <28>
Secondary slave
VIN0/GPIO53
A4
2 1
D25
CH751H-40PT_SOD323-2
VIN1/GPIO54
B4
VIN2/GPIO55
C4
R377 1 2
100K_0402_5%
VIN3/GPIO56
D4
VIN4/GPIO57
D5
R378 1 @ 2
100K_0402_5%
VIN5/GPIO58
D6
VIN6/GPIO59
A7
VIN7/GPIO60
B7
+3VALW
L55
AVDD
F6 <5mA> +SB_AVDD 2
1
1 1
BLM18PG121SN1D_0603
AVSS
G7
C457
2.2U_0603_6.3V4Z
2 2
C456
0.1U_0402_16V4Z
Primary (Secondary) master
Primary (Secondary) slave
+3VALW
+3VALW
+3VS
ACIN <28,37,38,40>
+3VALW
1 2
SATA controler
PATA controler
PATA controler
D36
CH751H-40PT_SOD323-2
2 1
@
@R557
2 1
0_0603_5%
1 2
R549
1K_0402_5%
@
R554
R559
@
@
10K_0402_5%
10K_0402_5%
U40
SB_SPICS#
1
CE#
3
SB_HOLD#
WP#
1 @ 2
7
R551
0_0402_5%
HOLD#
4
VSS
1 2
C677
@
0.1U_0402_16V4Z
1 2
for ACIN level issue
+SB_SPI_VCC
VDD 8
SCK 6
SI
5
SO 2
MX25L8005M2C-15G_SOP8
@
SB_SPICLK
SB_SO_SPI_SI
SB_SI_SPI_SO
Reserve For Debug
C
B
A
A
5
4
Security Classification
Compal Secret Data
Issued Date
2005/03/08 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
401743 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 19 of
47
3
2
1
5
4
3
2
1
D
C
B
U10C
<131mA>
SB700
+3VS
L9
VDDQ_1
VDD_1
M9
C524
22U_0805_6.3V6M
VDDQ_2
Part 3 of 5 VDD_2
1 2
T15
VDDQ_3
VDD_3
U9
C604 1 2
1U_0402_6.3V4Z
VDDQ_4
VDD_4
U16
C603
1U_0402_6.3V4Z
VDDQ_5
VDD_5
1 2
U17
C508
1U_0402_6.3V4Z
VDDQ_6
VDD_6
1 2
V8
C489
1U_0402_6.3V4Z
VDDQ_7
VDD_7
1 2
W7
C512
VDDQ_8
VDD_8
1 2
1U_0402_6.3V4Z
Y6
C529
0.1U_0402_16V4Z
VDDQ_9
VDD_9
1 2
AA4
C490
0.1U_0402_16V4Z
VDDQ_10
1 2
AB5
C465
0.1U_0402_16V4Z
VDDQ_11
1 2
AB21
VDDQ_12
<71mA>
+3VS
Y20
VDD33_18_1
CKVDD_1.2V_1
AA21
@
VDD33_18_2
CKVDD_1.2V_2
1 2
AA22
C516
22U_0805_6.3V6M
VDD33_18_3
CKVDD_1.2V_3
AE25
C495 1 @ 2
0.1U_0402_16V4Z
VDD33_18_4
CKVDD_1.2V_4
C518 1 @ 2
0.1U_0402_16V4Z
C522 1 2
0.1U_0402_16V4Z
@
+PCIE_VDDR
L65
POWER
+1.2V_HT
2
1
<600mA>
FBMA-L11-201209-221LMA30T_0805
P18
PCIE_VDDR_1
1 2
P19
C250
22U_0805_6.3V6M
PCIE_VDDR_2
P20
PCIE_VDDR_3
1 2
P21
C520
4.7U_0805_10V4Z
PCIE_VDDR_4
S5_3.3V_1
R22
C467 1 2
1U_0402_6.3V4Z
PCIE_VDDR_5
S5_3.3V_2
R24
PCIE_VDDR_6
S5_3.3V_3
R25
C247 1 2
0.1U_0402_16V4Z
PCIE_VDDR_7
S5_3.3V_4
C514 1 2
0.1U_0402_16V4Z
S5_3.3V_5
S5_3.3V_6
+1.2V_SATA
S5_3.3V_7
L63
<567mA>
+1.2V_HT
2
1
AA14
FBMA-L11-201209-221LMA30T_0805
AVDD_SATA_1
AB18
AVDD_SATA_4
AA15
AVDD_SATA_2
1 2
AA17
C526
22U_0805_6.3V6M
AVDD_SATA_3
S5_1.2V_1
AC18
C517
AVDD_SATA_5
S5_1.2V_2
1 2
1U_0402_6.3V4Z
AD17
C527 1 2
1U_0402_6.3V4Z
AVDD_SATA_6
AE17
C509 1 2
0.1U_0402_16V4Z
AVDD_SATA_7
C511 1 2
0.1U_0402_16V4Z
USB_PHY_1.2V_1
USB_PHY_1.2V_2
+AVDD_USB
L26
<658mA>
+3VALW
2
1
A16
FBMA-L11-201209-221LMA30T_0805
AVDDTX_0
V5_VREF
B16
AVDDTX_1
C16
C217 1 2
10U_0805_10V4Z
AVDDTX_2
AVDDCK_3.3V
D16
C216 1 2
10U_0805_10V4Z
AVDDTX_3
D17
C458 1 2
1U_0402_6.3V4Z
AVDDTX_4
AVDDCK_1.2V
E17
C459 1 2
1U_0402_6.3V4Z
AVDDTX_5
F15
C466 1 2
0.1U_0402_16V4Z
AVDDRX_0
AVDDC
F17
C494 1 2
0.1U_0402_16V4Z
AVDDRX_1
F18
C469
0.1U_0402_16V4Z
AVDDRX_2
1 2
G15
AVDDRX_3
G17
AVDDRX_4
G18
AVDDRX_5
PCI/GPIO I/O
IDE/FLSH I/O
A-LINK I/O
SATA I/O
PLL CLKGEN I/O
CORE S5
3.3V_S5 I/O
USB I/O
CORE S0
<510mA>
L15
+SB_VDD
M12
1 R418
2
0_0805_5%
+1.2V_HT
M14
1 2
N13
C528
22U_0805_6.3V6M
P12
C484 2 1
1U_0402_6.3V4Z
P14
C487 2 1
1U_0402_6.3V4Z
R11
C475 2 1
1U_0402_6.3V4Z
R15
C471 2 1
1U_0402_6.3V4Z
T16
C492 2 1
0.1U_0402_16V4Z
C485 2 1
0.1U_0402_16V4Z
L21
+1.2V_CKVDD
L22
L24
L25
+3VALW
<32mA>
A17
+S5_3V 1 2
A24
R416
0_0805_5%
B17
1 2
J4
C481
22U_0805_6.3V6M
J5
1 2
L1
C483
2.2U_0603_6.3V4Z
L2
1 2
C525 2 1
2.2U_0603_6.3V4Z
C510 2 1
0.1U_0402_16V4Z
C470 2 1
0.1U_0402_16V4Z
C504
0.1U_0402_16V4Z
+1.2VALW
<113mA>
G2
+S5_1.2V
R528
0_0603_5%
G4
+1.2VALW
2 1
<197mA>
L29
C460 2 1
1U_0402_6.3V4Z
+1.2_USB 2
1
C461
1U_0402_6.3V4Z
A10
FBMA-L11-160808-221LMT 0603
B10
1 2
C271
22U_0805_6.3V6M
C286 2 1
0.1U_0402_16V4Z
C270 2 1
0.1U_0402_16V4Z
R419 2 1
1K_0402_5% Reserve for SB700 leakage voltage issue
AE7 <1mA> +V5_VREF
J16
2
<47mA> +AVDDCK_3.3V
C513
K17 <62mA> +AVDDCK_1.2V
0.1U_0402_16V4Z 1
E9 <17mA> +AVDDC
L28
2
1
FBMA-L11-160808-221LMT 0603
+1.2V_HT
C515 1 2
1U_0402_6.3V4Z
C285 1 2
1U_0402_6.3V4Z
C521 2 1
0.1U_0402_16V4Z
C523 2 1
0.1U_0402_16V4Z
C284 1 2
10U_0805_10V4Z
R417 2 1
1K_0402_5%
+5VS
2
C519
1 2
+3VS
1U_0603_10V4Z
D27
CH751H-40PT_SOD323-2
1
L54
2
1
+3VALW
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z 2 1
C463
U10E
SB700
VSS_1
VSS_2
VSS_3
VSS_4
T10
AVSS_SATA_1
VSS_5
U10
AVSS_SATA_2
VSS_6
U11
AVSS_SATA_3
VSS_7
U12
AVSS_SATA_4
VSS_8
V11
AVSS_SATA_5
VSS_9
V14
AVSS_SATA_6
VSS_10
W9
AVSS_SATA_7
VSS_11
Y9
AVSS_SATA_8
VSS_12
Y11
AVSS_SATA_9
VSS_13
Y14
AVSS_SATA_10
VSS_14
Y17
AVSS_SATA_11
VSS_15
AA9
AVSS_SATA_12
VSS_16
AB9
AVSS_SATA_13
VSS_17
AB11
AVSS_SATA_14
VSS_18
AB13
AVSS_SATA_15
VSS_19
AB15
AVSS_SATA_16
VSS_20
AB17
AVSS_SATA_17
VSS_21
AC8
AVSS_SATA_18
VSS_22
AD8
AVSS_SATA_19
VSS_23
AE8
AVSS_SATA_20
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
A15
AVSS_USB_1
VSS_29
B15
AVSS_USB_2
VSS_30
C14
AVSS_USB_3
VSS_31
D8
AVSS_USB_4
VSS_32
D9
AVSS_USB_5
VSS_33
D11
AVSS_USB_6
VSS_34
D13
AVSS_USB_7
VSS_35
D14
AVSS_USB_8
VSS_36
D15
AVSS_USB_9
VSS_37
E15
AVSS_USB_10
VSS_38
F12
AVSS_USB_11
VSS_39
F14
AVSS_USB_12
VSS_40
G9
AVSS_USB_13
VSS_41
H9
AVSS_USB_14
VSS_42
H17
AVSS_USB_15
VSS_43
J9
AVSS_USB_16
VSS_44
J11
AVSS_USB_17
VSS_45
J12
AVSS_USB_18
VSS_46
J14
AVSS_USB_19
VSS_47
J15
AVSS_USB_20
VSS_48
K10
AVSS_USB_21
VSS_49
K12
AVSS_USB_22
VSS_50
K14
AVSS_USB_23
K15
AVSS_USB_24
PCIE_CK_VSS_9
PCIE_CK_VSS_10
PCIE_CK_VSS_11
PCIE_CK_VSS_12
PCIE_CK_VSS_13
H18
PCIE_CK_VSS_1 PCIE_CK_VSS_14
J17
PCIE_CK_VSS_2 PCIE_CK_VSS_15
J22
PCIE_CK_VSS_3 PCIE_CK_VSS_16
K25
PCIE_CK_VSS_4 PCIE_CK_VSS_17
M16
PCIE_CK_VSS_5 PCIE_CK_VSS_18
M17
PCIE_CK_VSS_6 PCIE_CK_VSS_19
M21
PCIE_CK_VSS_7 PCIE_CK_VSS_20
P16
PCIE_CK_VSS_8 PCIE_CK_VSS_21
GROUND
F9
AVSSC
AVSSCK
Part 5 of 5
218S7EALA11FG_BGA528_SB700
A2
A25
B1
D7
F20
G19
H8
K9
K11
K16
L4
L7
L10
L11
L12
L14
L16
M6
M10
M11
M13
M15
N4
N12
N14
P6
P9
P10
P11
P13
P15
R1
R2
R4
R9
R10
R12
R14
T11
T12
T14
U4
U14
V6
Y21
AB1
AB19
AB25
AE1
AE24
P23
R16
R19
T17
U18
U20
V18
V20
V21
W19
W22
W24
W25
L17
D
C
B
218S7EALA11FG_BGA528_SB700
0.1U_0402_16V4Z 2 1
C462
SB710 Ver:A14 <SA000030740>
SB710 Ver:A14 <SA000030740>
+AVDDCK_1.2V
L56
2
1
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z 2 1
0.1U_0402_16V4Z 2 1
+1.2V_HT
C464
C491
+AVDDCK_3.3V
L58
2
1
BLM18PG121SN1D_0603
+3VS
A
2.2U_0603_6.3V4Z 2 1
C498
0.1U_0402_16V4Z 2 1
C499
A
WWW.AliSaler.Com
5
4
Security Classification
Compal Secret Data
Issued Date
2005/03/08 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
401743 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 20 of
47
3
2
1
5
4
3
2
1
REQUIRED STRAPS
NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK
D
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLK5
LPC_CLK0
CLK_PCI_EC
LPC_CLK1
RTC_CLK AZ_RST_CD#
GP17
GP16
D
PULL
HIGH
PULL
LOW
BOOTFAIL
TIMER
ENABLED
BOOTFAIL
TIMER
DISABLED
DEFAULT
USE
DEBUG
STRAPS
IGNORE
DEBUG
STRAPS
DEFAULT
RESERVED
RESERVED
ENABLE PCI
MEM BOOT
DISABLE PCI
MEM BOOT
DEFAULT
CLKGEN
ENABLED
CLKGEN
DISABLED
DEFAULT
INTERNAL
RTC
DEFAULT
EXT. RTC
(PD on X1,
apply
32KHz to
RTC_CLK)
EC
ENABLED
EC
DISABLED
DEFAULT
Internal pull up
H,H = Reserved
H,L = SPI ROM
L,H = LPC ROM (Default L,NC)
L,L = FWH ROM
+3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW
C
<17> PCI_CLK2
<17> PCI_CLK3
<17> PCI_CLK4
<17> PCI_CLK5
<17,28> CLK_PCI_EC
<17> LPCCLK1
<17> RTC_CLK
<18> HDARST#
<18> GPIO17
<18> GPIO16
R145
10K_0402_5%
2
@
R138
10K_0402_5%
2
@
DEBUG STRAPS
SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]
C
PULL
HIGH
PCI_AD28
USE
LONG
RESET
DEFAULT
PCI_AD27
USE PCI
PLL
DEFAULT
PCI_AD26
USE ACPI
BCLK
DEFAULT
PCI_AD25
USE IDE
PLL
DEFAULT
PCI_AD24
USE DEFAULT
PCIE STRAPS
DEFAULT
PCI_AD23
RESERVED
DEBUG STRAPS
PULL
LOW
USE
SHORT
RESET
BYPASS
PCI PLL
BYPASS
ACPI
BCLK
BYPASS IDE
PLL
USE EEPROM
PCIE STRAPS
B
B
<17>
<17>
<17>
<17>
<17>
<17>
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
R158
2.2K_0402_5%
2
@
1
1
R144
10K_0402_5%
2
@
1
R146
10K_0402_5%
2
@
1
R136
10K_0402_5%
2
@
1
R89
10K_0402_5%
2
@
1
R394
10K_0402_5%
2
@
R142
10K_0402_5%
2
@
1
R87
2.2K_0402_5%
2
@
R143
10K_0402_5%
2 1
R133
10K_0402_5%
2 1
R132
10K_0402_5%
2 1
1
@
R129
10K_0402_5%
2 1
R130
10K_0402_5%
2 1
@
R148
2.2K_0402_5%
2
@
1
R157
2.2K_0402_5%
2
@
1
R141
10K_0402_5%
2 1
R94
2.2K_0402_5%
2 1
R159
2.2K_0402_5%
2
1
@
1
1
@
R386
2.2K_0402_5%
2 1
@
R137
2.2K_0402_5%
2 1
R156
2.2K_0402_5%
2
@
1
R147
2.2K_0402_5%
2
@
1
1
R494
2.2K_0402_5%
2
R96
10K_0402_5%
2 1
A
A
5
4
Security Classification
Compal Secret Data
Issued Date
2005/03/08 Deciphered Date
2010/03/12
Title
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
401743
C
Date: Wednesday, June 24, 2009
Sheet 21 of
47
3
2
1
Compal Electronics, Inc.
5
4
3
2
1
D
+5VS
1
C360
10U_0805_10V4Z
2
+3VS
0.1U_0402_16V4Z
1
1
1
1
C351
C363
C366
C368
10U_0805_10V4Z
2
2
2
2
0.1U_0402_16V4Z
1000P_0402_50V7K
0.1U_0402_16V4Z
1
1
1
C349
C347
C346
2
2
2
0.1U_0402_16V4Z
1000P_0402_50V7K
+5VS
1
C153
10U_0805_10V4Z
2
Placea caps. near ODD CONN.
1
C150
2
1U_0402_6.3V4Z
0.1U_0402_16V4Z
1
C148
2
1
C149
2
1000P_0402_50V7K
D
SATA HDD CONN
SATA ODD CONN
C
<19> SATA_STX_DRX_P0
<19> SATA_STX_DRX_N0
<19> SATA_DTX_C_SRX_N0
<19> SATA_DTX_C_SRX_P0
C289 1 2
0.01U_0402_25V7K SATA_STX_C_DRX_P0
C291 1 2
0.01U_0402_25V7K SATA_STX_C_DRX_N0
C302 1 2
0.01U_0402_25V7K
C305 1 2
0.01U_0402_25V7K
+3VS
+5VS
R544
1 2
0_0805_5%
R545
1 2
0_0805_5%
SATA_DTX_SRX_N0
SATA_DTX_SRX_P0
JSATA2
1
GND
2
HTX+
3
HTX-
4
GND
5
HRX-
6
HRX+
7
GND
8
VCC3.3
9
VCC3.3
10
VCC3.3
11
GND
12
GND
13
GND
14
VCC5
15
VCC5
16
VCC5
17
GND
18
RESERVED
19
GND
20
VCC12
21
VCC12 GND 24
22
VCC12 GND 23
+5VS
1
C370
+
@
150U_D2_6.3VM 2
Close to SATA HDD
<19> SATA_STX_DRX_P2
<19> SATA_STX_DRX_N2
<19> SATA_DTX_C_SRX_N2
<19> SATA_DTX_C_SRX_P2
C308 1 2
0.01U_0402_25V7K
C307 1 2
0.01U_0402_25V7K
C311 1 2
0.01U_0402_25V7K
C312 1 2
0.01U_0402_25V7K
SATA_STX_C_DRX_P2
SATA_STX_C_DRX_N2
SATA_DTX_SRX_N2
SATA_DTX_SRX_P2
1 2
R617
@
1K_0402_1%
+5VS
JSATA1
1
GND
2
A+
3
A-
4
GND
5
B-
6
B+
7
GND
8
DP
9
+5V
10
+5V
11
MD
12
GND
13
GND
SANTA_206401-1_13P
CONN@
KALA0 used
GND 15
GND 14
C
OCTEK_SAT-22SU1G_NR
CONN@
KALA0 used
B
Second HDD
Second ODD
<19> SATA_STX_DRX_P1
<19> SATA_STX_DRX_N1
<19> SATA_DTX_C_SRX_N1
<19> SATA_DTX_C_SRX_P1
<19> SATA_STX_DRX_P3
<19> SATA_STX_DRX_N3
<19> SATA_DTX_C_SRX_N3
<19> SATA_DTX_C_SRX_P3
C314 1 2
0.01U_0402_25V7K
C313 1 2
0.01U_0402_25V7K
C316 1 2
0.01U_0402_25V7K
C315 1 2
0.01U_0402_25V7K
C318 1 2
0.01U_0402_25V7K
C317 1 2
0.01U_0402_25V7K
C320 1 2
0.01U_0402_25V7K
C319 1 2
0.01U_0402_25V7K
SATA_STX_C_DRX_P1
SATA_STX_C_DRX_N1
SATA_DTX_SRX_N1
SATA_DTX_SRX_P1
SATA_STX_C_DRX_P3
SATA_STX_C_DRX_N3
SATA_DTX_SRX_N3
SATA_DTX_SRX_P3
JP2
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
GND
GND
GND
GND
GND
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
+5VS
+3VS
B
31
32
33
34
35
36
ACES_88018-304G
CONN@
+5VS
+3VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C574
1
C577
1
C579
1
C580
1
C572
1
C573
1
C571
2
2
2
2
2
2
2
A
1000P_0402_50V7K
10U_0805_10V4Z
1000P_0402_50V7K
10U_0805_10V4Z
A
WWW.AliSaler.Com
5
4
Security Classification
Compal Secret Data
Issued Date
2005/03/08 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
C
401743 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 22 of
47
3
2
1
A
B
C
D
E
CRT Connector
D18
D19
D20
@
@
@
DAN217_SC59
DAN217_SC59
DAN217_SC59
1
1
1
+5VS
+R_CRT_VCC
W=40mils
D17
F1
2 1 1 2
W=40mils
+CRT_VCC
RB491D_SC59-3
1.1A_6VDC_FUSE
1
+5VS
2
3
2
3
2
3
C407
0.1U_0402_16V4Z
2
1 1
<13> GMCH_CRT_R
<13> GMCH_CRT_G
<13> GMCH_CRT_B
R339
140_0402_1%
1 2
1
2
CRT_R
CRT_G
CRT_B
1
C408
1
C412
L32
1 2 CRT_R_L
FCM2012CF-800T06_2P
L34
1 2 CRT_G_L
FCM2012CF-800T06_2P
L33
1 2 CRT_B_L
FCM2012CF-800T06_2P
150_0402_1% 2
8P_0402_50V8D 2
8P_0402_50V8D 2
8P_0402_50V8D
+CRT_VCC
1 2
HSYNC_L
L38
MBC1608121YZF_0603
1 2
2 1
D_DDC_DATA
C434
0.1U_0402_16V4Z
R360
10K_0402_5%
1 2
VSYNC_L
L37
MBC1608121YZF_0603
1
U36
C411
<13,15> GMCH_CRT_HSYNC
1
1
CRT_DET# <18>
1 2
CRT_HSYNC 2
D_CRT_HSYNC
68P_0402_50V8J
R354
0_0402_5%
A Y
4
C424
C423
2
D_DDC_CLK
74AHCT1G125GW_SOT353-5
2
2
+CRT_VCC
1
R636
C422
100K_0402_5%
2 2
1 2
68P_0402_50V8J
C433
0.1U_0402_16V4Z
2
U35
1
C414
1
C410
6P_0402_50V8D
2
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
JCRT1
16
17
KAW60 used
SUYIN_070549FR015S208CR
CONN@
<13,15> GMCH_CRT_VSYNC
1 2
R356
0_0402_5%
CRT_VSYNC
D_CRT_VSYNC
+CRT_VCC
Close to Conn side
+CRT_VCC
+3VS
1
R338
150_0402_1%
1
2
P
A
G
3
1
2
R340
5
P
G
3
1
OE#
5
1
C409
6P_0402_50V8D
2
10P_0402_50V8J
10P_0402_50V8J
C406
100P_0402_50V8J
1 2
OE#
Y
4
74AHCT1G125GW_SOT353-5
1
1
C413
6P_0402_50V8D
2
R77
6.8K_0402_5%
2
R72
6.8K_0402_5%
2
2
G
D_DDC_DATA
1 3
GMCH_CRT_DATA <13>
Q50
3 BSH111 1N_SOT23-3
3
D
S
2
G
D_DDC_CLK
1 3
Q51
BSH111 1N_SOT23-3
D
S
GMCH_CRT_CLK <13>
4 4
A
B
Security Classification
Compal Secret Data
Issued Date
2005/03/08 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
401743 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 23 of
47
C
D
E
5
4
3
2
1
+3VS
INVT_PWM
D
LCD POWER CIRCUIT
1
C426
@0.1U_0402_16V4Z
2
D21
BAS16_SOT23-3
@
1
2
1
C416
1U_0402_6.3V4Z
@
2
D
+3VS
+LCDVDD
+3VALW
1
C77
C
<13> GMCH_ENVDD
2N7002DW-T/R7_SOT363-6
Q22A
1
6 2 1
R274
300_0603_5%
2
GMCH_ENVDD 5
R345
10K_0402_5%
1
2
1 2
4
3
R348
100K_0402_5%
Q22B
2N7002DW-T/R7_SOT363-6
1 2
2 1
R278
1K_0402_5%
1
R347
C431
2
0.047U_0402_16V7K
@100K_0402_5%
2
G
1 3
D
S
W=60mils
Q23
AO3413_SOT23-3
@4.7U_0805_10V4Z
2
W=60mils
+LCDVDD
1
C415
4.7U_0805_10V4Z
2
+LCDVDD
1
C420
0.1U_0402_16V4Z
2
<18> USB20_N3
<18> USB20_P3
LCD/PANEL CONN.
JLVDS1
42
GND GND 41
+INVPWR_B+
40
DAC_BRIG
40 39
39
DAC_BRIG <28>
38
INVT_PWM
38 37
37
+3VS
36
DISPOFF#
<13> GMCH_LCD_CLK
EDID_LCD_CLK
36 35
35
34
<13> GMCH_LCD_DATA
EDID_LCD_DAT
34 33
33
+LCDVDD
32
32 31
31
30
30 29
29
<13> GMCH_TZOUT0-
28
28 27
27
<13> GMCH_TZOUT0+
26
26 25
25
GMCH_TXOUT0- <13>
24
24 23
23
GMCH_TXOUT0+ <13>
<13> GMCH_TZOUT1+
22
22 21
21
<13> GMCH_TZOUT1-
20
20 19
19
GMCH_TXOUT1- <13>
18
18 17
17
GMCH_TXOUT1+ <13>
<13> GMCH_TZOUT2+
16
16 15
15
<13> GMCH_TZOUT2-
14
14 13
13
GMCH_TXOUT2+ <13>
12
12 11
11
GMCH_TXOUT2- <13>
<13> GMCH_TZCLK-
10
10 9
9
<13> GMCH_TZCLK+
8
8 7
7
GMCH_TXCLK- <13>
6
GMCH_TXCLK+ <13>
R759 1 2
0_0402_5% USB20_CMOS_N3
6 5
5
4
R760 1 2
0_0402_5% USB20_CMOS_P3
4 3
3
2
R761 1 2
0_0603_5%
2 1
1
+3VS
R762 1 2
0_0603_5%
+3VALW
L77
ACES_88242-4001
@
4
4
3
3
CONN@
1
KALA0 used
C
1
1
2
2
@
WCM2012F2S-900T04_0805
C768
0.1U_0402_16V4Z
2
<28> EC_INVT_PWM
EC_INVT_PWM
1 2
R764
0_0402_5%
INVT_PWM
<13> GMCH_INVT_PWM
GMCH_INVT_PWM
1 VARY@ 2
R767
0_0402_5%
B
VARYBRIGHT FUNCTION
R769
0_0402_5%
EC_INVT_PWM 2
1 @ 1
2
R21
4.7K_0402_5%
R770
0_0402_5%
GMCH_INVT_PWM 2
@ 1
1
6
+3VS
2
2
Q52A
2N7002DW-T/R7_SOT363-6
5
1
1 2
R23
4.7K_0402_5% 4
3
Q52B
2N7002DW-T/R7_SOT363-6
R30
@
4.7K_0402_5%
2
G
+3VS
1
R39
@
4.7K_0402_5%
1 @ 2 INVT_PWM
R768
0_0402_5%
2
1
3
D
S
Q69
2N7002_SOT23-3
<28>
BKOFF#
DAC_BRIG
INVT_PWM
DISPOFF#
1 2
R763
0_0402_5%
BKOFF# 1 2
D2
RB751V_SOD323
@
C371 1 2
220P_0402_50V7K
C372 1 2
220P_0402_50V7K
C377 1 2
220P_0402_50V7K
+3VS
1
R1
@
4.7K_0402_5%
DISPOFF#
2
1 2
R414
@
100K_0402_5%
W=40mils
+INVPWR_B+
L20 2
1
FBMA-L11-201209-221LMA30T_0805
L15 2
1
FBMA-L11-201209-221LMA30T_0805
1 1
C379
C362
680P_0402_50V7K
68P_0402_50V8J
2 2
+LCDVDD
1
1
C383
C382
@
10U_0805_10V4Z
0.1U_0402_16V4Z
2
2
B+
B
A
A
WWW.AliSaler.Com
5
4
Security Classification
Compal Secret Data
Issued Date
2005/03/08 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
C
401743 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 24 of
47
3
2
1
5
4
3
2
1
+3V_LAN
+3V_LAN
+AVDD_CEN
1 8114@ 2
+1.8_VDD/LX
R820
0_0603_5%
1 2
L88
8132@
4.7UH_1008HC-472EJFS-A_5%_1008
1
C932
0.1U_0402_16V4Z
2
1
R821
4.7K_0402_5%
2
1
2
R822
4.7K_0402_5%
Place Close to Chip
LAN_MIDI0+
R843 2 1
49.9_0402_1%
C978 1 2
0.1U_0402_16V4Z
D
R8441 2
0_0603_5%
C933
4.7U_0805_10V4Z
8132@
1 2
+2.5V_VDDH/VDD17 1 2
+2.5V_VDDH
1
R824
8132@
0_0603_5%
R825
8114@
0_0603_5%
C934
0.1U_0402_16V4Z
2
8132@
U84
1
A0 VCC 8
2
A1 WP
7
3
A2 SCL
6
4
GND
AT24C02BN-SH-T_SO8
@
TWSI_SCL
TWSI_SDA
LAN_MIDI0-
R845 2
LAN_MIDI1+
R846 2
LAN_MIDI1-
R847 2
1
49.9_0402_1%
1
49.9_0402_1%
1
49.9_0402_1%
C979 1 2
0.1U_0402_16V4Z
D
U85
C
B
2 1
+1.8_VDD/LX 1
TWSI_SCL
C936
8114@
1U_0603_10V4Z
VDD18O
TWSI_CLK 29
TWSI_SDA
TWSI_DATA 30
+3V_LAN
2
8114@
VDD33
LAN_ACTIVITY#
+2.5V_VDDH/VDD17
LED_ACTn
47
LAN_ACTIVITY# <26>
WAKEn
C935 2 1
1U_0603_10V4Z
6
LAN_LINK#
VDDHO
LED_10_100n
48
LAN_LINK# <26>
8114: Internal PU
C982 2 1
0.1U_0402_16V7K
CTR12
5
8132: OD
CTR12
LED_DUPLEXn
27 1 2
LAN_CLKREQ# <16>
8132@
R261
0_0402_5%
LAN_MIDI0+
<13,15,17,28,31> PLT_RST#
3
PERSTn
TRXP0
13
LAN_MIDI0+ <26>
<28> EC_PME#
4
LAN_MIDI0-
WAKEn
TRXN0
14
LAN_MIDI0- <26>
8114@
LAN_MIDI1+
TRXP1
17
LAN_MIDI1+ <26>
+3V_LAN 1 2
2 1
7
LAN_MIDI1-
VBG1P18V
TRXN1
18
LAN_MIDI1- <26>
R829
4.7K_0402_5%
C937
1000P_0402_50V7K
<16> CLK_PCIE_LAN
2 1
41
AVDDVCO1
C938
0.1U_0402_16V7K
REFCLKP
AVDDL_REG 11
AVDDVCO2
AVDDL/AVDDL_REG 42
<16> CLK_PCIE_LAN#
2 1
40
C939
0.1U_0402_16V7K
REFCLKN
<12> PCIE_ITX_C_PRX_P1
43
RX_P
+1.2_DVDDL
DVDDL0
28
<12> PCIE_ITX_C_PRX_N1
44
RX_N
DVDDL1
32
<12> PCIE_PTX_C_IRX_P1
PCIE_PTX_IRX_P1
DVDDL2
45
2 1
38
TX_P
AR8114A 10/100 LAN DVDDL3
46
C940
0.1U_0402_16V7K
<12> PCIE_PTX_C_IRX_N1
2 1
PCIE_PTX_IRX_N1 37
+1.2_AVDDL
TX_N
AVDDL0
8
C943
0.1U_0402_16V7K
AVDDL1
16
Place Close to Chip
LAN_X1
AVDDL2
22
9
LAN_X2
XTLO
AVDDL3
36
10
XTLI
AVDDL4
39
1
2
LAN_X1
+1.2_AVDDL
Y8
1 2
25MHZ_20P
C946
27P_0402_50V8J
LAN_X2
C947
27P_0402_50V8J
L89
FBMA-L11-201209-221LMA30T_0805
1 2
8114@
1
2
2 1
R831
2.37K_0402_1%
+1.2_DVDDL
31
SMCLK
33
SMDATA
12
RBIAS
34
TESTMODE
49
GND
AR8114-AL1E_QFN48_6X6
change to AR8132L-AL1E
+1.2_DVDDL
AVDDH0
15
AVDDH1
19
AVDDH2
25
NC_0
20
NC_1
21
NC_2
23
NC_3
24
NC_4
26
NC_5
35
SDA 5 R832
+2.5V_VDDH
Place Close to Pin 28324546
C953
C955
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 1 1
+3VALW
Layout Notice : Close to chip
+3V_LAN
1 2
0.1U_0402_16V4Z
R830
0_1206_5%
1
+3V_LAN
1
C948
R832
1 8132@ 2+2.5V_VDDH
0.1U_0402_16V4Z
10K_0402_1%
R833
0_0402_5%
8114@ 2
Q73
8114@
1
CTR12
1
C949
NJT4030PT1G_SOT223
0.1U_0402_16V4Z
8114@
8132@
+1.2_AVDDL 2
1 1
C950
C951
10U_0805_10V4Z
0.1U_0402_16V4Z
8114@
8114@
2 2
4
2 3
C944
4.7U_0805_10V4Z
2
1 1 1
C941
C942
C945
2 2 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C
B
A
R835
0_0603_5%
1 2 1 2
R834
@ 1
1
0_0603_5%
C956
1000P_0402_50V7K
C957
1U_0603_10V4Z
2
2
R546 1 2
0_0805_5%
1
8114: R546 need change to bead
C958
0.1U_0402_16V4Z
2
AVDDVCO1
AVDDVCO2
8132@
8114@
2 2 2 2
C983
C954
1U_0603_10V4Z
0.1U_0402_16V4Z
Place Close to Pin151925
C960
+2.5V_VDDH
0.1U_0402_16V4Z
1 1 1
C961
0.1U_0402_16V4Z
2 2 2
C959
1U_0603_10V4Z
C952
0.1U_0402_16V4Z
2
Place Close to Pin816223639
C984
C963
C965
+1.2_AVDDL
1U_0603_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 1 1 1
C966
8132@
8114@
0.1U_0402_16V4Z
2 2 2 2 2 2
C962
C964
0.1U_0402_16V4Z
0.1U_0402_16V4Z
A
5
4
Security Classification
Compal Secret Data
Issued Date
2005/07/29 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
C
401743 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 25 of
47
3
2
1
5
4
3
2
1
+AVDD_CEN
C967
1 2
D
<25>
<25>
<25>
<25>
LAN_MIDI0+
LAN_MIDI0-
LAN_MIDI1+
LAN_MIDI1-
1 2
R836
0_0603_5%
T1
LAN_MIDI0+
LAN_MIDI0-
LAN_MIDI1+
LAN_MIDI1-
1
RD+
2
RD-
3
CT
4
NC
5
NC
6
CT
7
TD+
8
TD-
LAN_ACTIVITY#_R
<25> LAN_ACTIVITY#
2 1
R837
510_0402_5%
2 1
RJ45_MIDI0+
RX+
16
R14
5.11K_0402_1%
RJ45_MIDI0-
RX-
15
CT
14
NC 13
NC 12 RJ45_MIDI1-
CT
11
RJ45_MIDI1+
TX+
10
RJ45_MIDI1-
TX-
9
220P_0402_50V7K
JRJ1
12
Amber LED+
11
Amber LED-
8
PR4-
7
PR4+
6
PR2-
5
PR3-
SHLD2
SHLD1
16
15
D
LAN_TCT
1
C969
2
1
C970
0.1U_0402_16V4Z
2
350uH_NS0013LF
1
R839
75_0402_1%
2
1
2
R840
75_0402_1%
RJ45_GND
+3V_LAN
2
R838
<25> LAN_LINK#
1
510_0402_5%
1
RJ45_MIDI1+
RJ45_MIDI0-
RJ45_MIDI0+
LAN_LINK#
4
3
2
1
10
9
PR3+
PR2+
PR1-
PR1+
Green LED-
Green LED+
SHLD2
SHLD1
FOX_JM36113-L2R8-7F
CONN@
14
13
0.1U_0402_16V4Z
2
C968
220P_0402_50V7K
C
C
RJ45_GND
1 2
C973
1000P_1206_2KV7K
1
2
C974
LANGND
1
C975
4.7U_0805_10V4Z
2
0.1U_0402_16V4Z
LAN_LINK#
H1
H_3P4
H14
H_3P4
H19
H_3P4
H26
H_3P4
H25
H_3P4
H24
H_3P4
H23
H_3P4
H17
H_3P4
LAN_ACTIVITY#_R
C976
1 2
@68P_0402_50V8J
LAN_LINK#
1 2
C977
@68P_0402_50V8J
3
2
LAN_ACTIVITY#_R
D16
@
PJDLC05_SOT23-3
1
@
1
@
1
@
1
@
1
@
1
@
1
@
1
@
1
B
H7
H_3P4
H9
H_3P4
H4
H_3P4
H18
H_3P4
H16
H_4P2
B
1
@
1
@
1
@
1
@
1
@
H11
H_4P2
H10
H_4P2
H20
H_3P4
H6
H_2P8
1
@
1
@
1
@
1
@
H5
H_2P8
H8
H_4P0N
H2
H_3P3
H3
H_3P3
H12
H_3P3
H22
H_3P3
H27
H_2P3
1
@
1
@
1
@
1
@
1
@
1
@
1
@
H15
H_4P2
H21
H_4P6X4P0N
A
1
@
1
@
A
FD1
FD2
FD3
FD4
@
@
@
@
FIDUCIAL_C40M80
FIDUCIAL_C40M80
FIDUCIAL_C40M80
FIDUCIAL_C40M80
WWW.AliSaler.Com
5
1
1
1
1
4
Security Classification
Compal Secret Data
Issued Date
2005/03/08 Deciphered Date
2010/03/12
Title
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
401743
C
Date: Wednesday, June 24, 2009
Sheet 26 of
47
3
2
1
Compal Electronics, Inc.
5
4
3
2
1
2
R675
1
0_0402_5%
D
C
+3VS
1 2
1
2
<16> CLK_48M_SD
@
R674
100K_0402_5%
+3VALW
1 2 RST#
R335
0_0402_5%
C854
1U_0402_6.3V4Z
@C855
47P_0402_50V8J
2
1
+3VS
MODE_SEL
+3V_CARD
<18> USB20_N4
<18> USB20_P4
<34> 5IN1_LED#
XTLI
+XDPWR_SDPWR_MSPWR
RST#
MODE_SEL
XTLO
XTLI
USB20_N4
USB20_P4
XTAL_CTR 2
R681
SD_CMD
+3VS
1 SDCLK_XDD1_MSCLK
0_0402_5%
XTAL_CTR
If Open , use 12MHz. crystal
If Pull high , use CLKGEN 48MHz.
D
C
R673
10_0402_5%
1
@Y7
12MHZ_16PF_6X12000012
EMI
2
1
1
2
R680
0_0402_5%
1 @ 2
R548
0_0805_5%
1 2
R547
0_0805_5%
1
C852
@
4.7U_0603_6.3V6K
2
1 2
R676
0_0402_5%
@
1 2
C856
6P_0402_50V8D
1
C853
0.1U_0402_16V4Z
2
2
C851
1
0.1U_0402_16V4Z
1 2
R678
6.19K_0402_1%
1 2
U77
1
AV_PLL
3
NC
7
NC
9
CARD_3V3
11
D3V3
33
D3V3
8
3V3_IN
44
RST#
45
MODE_SEL
47
XTLO
48
XTLI
4
DM
5
DP
14
GPIO0
2
RREF
12
DGND
32
DGND
6
AGND
46
AGND
RTS5159-GR_LQFP48_7X7
R672
0_0402_5%
VREG 10
MS_D4
22
NC 30
XD_CLE_SP19
43
XD_CE#_SP18
42
XD_ALE_SP17
41
SD_DAT2/XD_RE#_SP16
40
SD_DAT3/XD_WE#_SP15
39
XD_RDY_SP14
38
SD_DAT4/XD_WP#/MS_D7_SP13
37
SD_DAT5/XD_D0/MS_D6_SP12 35
SD_CLK/XD_D1/MS_CLK_SP11 34
SD_DAT6/XD_D7/MS_D3_SP10 31
MS_INS#_SP9
29
SD_DAT7/XD_D2/MS_D2_SP8 28
SD_DAT0/XD_D6/MS_D0_SP7 27
SD_DAT1/XD_D3/MS_D1_SP6 26
XD_D5_SP5
25
XD_D4/SD_DAT1_SP4
23
SD_CD#_SP3
21
SD_WP_SP2
20
XD_CD#_SP1
19
EEDI
18
XTAL_CTR 13
MS_D5
24
EEDO 15
EECS 16
EESK 17
SD_CMD 36
1 2
C860
1U_0402_6.3V4Z
XDCLE
XDCE#
XDALE
SDDAT2_XDRE#
SDDAT3_XDWE#
XD_RDY
SDDAT4_XDWP#_MSD7
SDDAT5_XDD0_MSD6
SDCLK_XDD1_MSCLK_L 2
SDDAT6_XDD7_MSD3
R671
MS_INS#
SDDAT7_XDD2_MSD2
SDDAT0_XDD6_MSD0
SDDAT1_XDD3_MSD1
XDD5_MSBS
XDD4_SDDAT1
SDCD
SDWP
XDCD
1
0_0603_5%
2
1
C858
10P_0402_50V8J
2
@
1 2
C857
6P_0402_50V8D
XTLO
+CARDPWR
+CARDPWR
B
A
Close to CLK_SD_48M via
+5VS
1
C859
0.1U_0402_16V4Z
2
EMI
+CARDPWR
1 1 1
C477
C342
C480
0.1U_0402_16V4Z
2 2 2
10U_0805_10V4Z
0.1U_0402_16V4Z
+XDPWR_SDPWR_MSPWR
+CARDPWR
1 2
R318
0_0603_5%
1 2
R295
100K_0402_5%
1
C348
0.1U_0402_16V4Z
2
SDDAT5_XDD0_MSD6
SDCLK_XDD1_MSCLK
SDDAT7_XDD2_MSD2
SDDAT1_XDD3_MSD1
XDD4_SDDAT1
XDD5_MSBS
SDDAT0_XDD6_MSD0
SDDAT6_XDD7_MSD3
SDDAT3_XDWE#
SDDAT4_XDWP#_MSD7
XDALE
XDCD
XD_RDY
SDDAT2_XDRE#
XDCE#
XDCLE
JREAD1
3
XD-VCC
SD-VCC 21
MS-VCC 28
32
XD-D0
10
XD-D1
7 IN 1 CONN SD_CLK 20
9
XD-D2
SD-DAT0
14
8
XD-D3
SD-DAT1
12
7
XD-D4
SD-DAT2
30
6
XD-D5
SD-DAT3
29
5
XD-D6
SD-DAT4
27
4
XD-D7
SD-DAT5
23
SD-DAT6
18
34
XD-WE
SD-DAT7
16
33
XD-WP
SD-CMD 25
35
XD-ALE
SD-CD-SW 1
40
XD-CD
39
XD-R/B
SD-WP-SW 2
38
XD-RE
37
XD-CE
36
XD-CLE
MS-SCLK 26
MS-DATA0
17
11
7IN1 GND
MS-DATA1
15
31
7IN1 GND
MS-DATA2
19
MS-DATA3
24
MS-INS 22
MS-BS 13
41
7IN1 GND
42
7IN1 GND
TAITW_R015-B10-LM
CONN@
JAWD0 used
SDCLK_XDD1_MSCLK
SDDAT0_XDD6_MSD0
XDD4_SDDAT1
SDDAT2_XDRE#
SDDAT3_XDWE#
SDDAT4_XDWP#_MSD7
SDDAT5_XDD0_MSD6
SDDAT6_XDD7_MSD3
SDDAT7_XDD2_MSD2
SD_CMD
SDCD
SDWP
SDCLK_XDD1_MSCLK
SDDAT0_XDD6_MSD0
SDDAT1_XDD3_MSD1
SDDAT7_XDD2_MSD2
SDDAT6_XDD7_MSD3
MS_INS#
XDD5_MSBS
1
C862
@
22P_0402_50V8J
2
B
A
5
4
Security Classification
Compal Secret Data
Issued Date
2005/07/29 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
C
401743 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 27 of
47
3
2
1
5
4
3
2
1
CLK_PCI_EC
+3VALW
D
C
B
A
R633
@ 10_0402_5%
C689
@ 22P_0402_50V8J
<19> EC_THERM#
+3VALW
R632
47K_0402_5%
2 1 ECRST#
2 1
C549
0.1U_0402_16V4Z
+3VALW
+3VS
+5VS
R514 2
R731
2.2K_0402_5%
1 2 EC_SMB_CK2
1 2 EC_SMB_DA2
R732
2.2K_0402_5%
EC_CRY1
1 TP_CLK
R208
1 TP_DATA
R207
ENBKL
EC_PME#
R729 1 2
2.2K_0402_5% EC_SMB_CK1
R730 1 2
2.2K_0402_5% EC_SMB_DA1
R19 1 2
100K_0402_5% LID_SW#
R634 2
R639 2
1
2
1
2
2
4.7K_0402_5%
2
4.7K_0402_5%
@ 1
10K_0402_5%
1
47K_0402_5%
1
47K_0402_5%
1 @ 2
R519
10K_0402_5%
1
C344
15P_0402_50V8J
2
EC_CRY2
KSO1
KSO2
R460
0_0402_5%
1 2 EC_THERM#_R
@
4
IN 1
OUT
NC
NC
L48
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2 +EC_VCCA
1 1
C567 1 1 2
2
FBMA-L11-160808-800LMT_0603
C569
1
C476
C557
C568
C561
1000P_0402_50V7K
1000P_0402_50V7K
2 2 2 2 1
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
<29,34> KSI[0..7]
<29,34> KSO[0..17]
<18> EC_GA20
<18> EC_KBRST#
<17> SERIRQ
<17> LPC_FRAME#
<17> LPC_AD3
<17> LPC_AD2
<17> LPC_AD1
<17> LPC_AD0
<17,21> CLK_PCI_EC
<13,15,17,25,31> PLT_RST#
EC test-mode issue
1
C343
15P_0402_50V8J
2
<18> EC_SCI#
<17> PM_CLKRUN#
<41> EC_SMB_CK1
<41> EC_SMB_DA1
<8> EC_SMB_CK2
<8> EC_SMB_DA2
<18> PM_SLP_S3#
<18> PM_SLP_S5#
<18> EC_SMI#
<6> FAN_SPEED1
<33> ON/OFF
<34> PWR_SUSP_LED
<34> NUM_LED#
KSI[0..7]
KSO[0..17]
ECRST#
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
U27
Chagne to D3 version
VCC 9
VCC 22
VCC 33
VCC 96
VCC 111
VCC 125
20mil
ECAGND
C566
0.1U_0402_16V4Z
1
GA20/GPIO00
INVT_PWM/PWM1/GPIO0F 21
2
KBRST#/GPIO01
BEEP#/PWM2/GPIO10
23
3
SERIRQ#
FANPWM1/GPIO12
26
4
LFRAME#
ACOFF/FANPWM2/GPIO13
27
5
LAD3
7
LAD2
PWM Output
8
LAD1
BATT_TEMP/AD0/GPIO38
63
10
LAD0
LPC & MISC
BATT_OVP/AD1/GPIO39
64
ADP_I/AD2/GPIO3A AD Input
65
12
PCICLK
AD3/GPIO3B 66
13
PCIRST#/GPIO05
AD4/GPIO42
75
37
ECRST#
SELIO2#/AD5/GPIO43
76
20
SCI#/GPIO0E
38
CLKRUN#/GPIO1D
DAC_BRIG/DA0/GPIO3C 68
EN_DFAN1/DA1/GPIO3D DA Output
70
IREF/DA2/GPIO3E 71
55
KSI0/GPIO30
DA3/GPIO3F
72
56
KSI1/GPIO31
57
KSI2/GPIO32
58
KSI3/GPIO33
PSCLK1/GPIO4A 83
59
KSI4/GPIO34
PSDAT1/GPIO4B 84
60
KSI5/GPIO35
PSCLK2/GPIO4C PS2 Interface
85
61
KSI6/GPIO36
PSDAT2/GPIO4D 86
62
KSI7/GPIO37
TP_CLK/PSCLK3/GPIO4E 87
39
KSO0/GPIO20
TP_DATA/PSDAT3/GPIO4F 88
40
KSO1/GPIO21
41
KSO2/GPIO22
42
KSO3/GPIO23
SDICS#/GPXOA00
97
43
KSO4/GPIO24
SDICLK/GPXOA01
98
44
KSO5/GPIO25
Int. K/B
SDIDO/GPXOA02
99
45
KSO6/GPIO26
Matrix
SDIDI/GPXID0
109
46
KSO7/GPIO27
SPI Device Interface
47
KSO8/GPIO28
48
KSO9/GPIO29
SPIDI/RD#
119
49
KSO10/GPIO2A
SPIDO/WR#
120
50
KSO11/GPIO2B
SPI Flash ROM SPICLK/GPIO58
126
51
KSO12/GPIO2C
SPICS#
128
52
KSO13/GPIO2D
53
KSO14/GPIO2E
54
KSO15/GPIO2F
CIR_RX/GPIO40
73
81
KSO16/GPIO48
CIR_RLC_TX/GPIO41
74
82
KSO17/GPIO49
FSTCHG/SELIO#/GPIO50
89
BATT_CHGI_LED#/GPIO52
90
CAPS_LED#/GPIO53
91
77
SCL1/GPIO44
GPIO BATT_LOW_LED#/GPIO54
92
78
SDA1/GPIO45
SUSP_LED#/GPIO55
93
79
SCL2/GPIO46
SM Bus
SYSON/GPIO56
95
80
SDA2/GPIO47
VR_ON/XCLK32K/GPIO57
121
AC_IN/GPIO59
127
6
PM_SLP_S3#/GPIO04
EC_RSMRST#/GPXO03
100
14
PM_SLP_S5#/GPIO07
EC_LID_OUT#/GPXO04
101
15
EC_SMI#/GPIO08
EC_ON/GPXO05
102
16
LID_SW#/GPIO0A
EC_SWI#/GPXO06
103
17
SUSP#/GPIO0B
ICH_PWROK/GPXO06
104
18
PBTN_OUT#/GPIO0C
GPO BKOFF#/GPXO08
105
19
EC_PME#/GPIO0D
GPIO
WL_OFF#/GPXO09
106
25
EC_THERM#/GPIO11
GPXO10
107
28
FAN_SPEED1/FANFB1/GPIO14
GPXO11
108
29
E51TXD_P80DATA
FANFB2/GPIO15
30
E51RXD_P80CLK
EC_TX/GPIO16
31
EC_RX/GPIO17
PM_SLP_S4#/GPXID1
110
32
ON_OFF/GPIO18
ENBKL/GPXID2
112
34
PWR_LED#/GPIO19
GPXID3
114
36
NUMLED#/GPIO1A
GPI
GPXID4
115
GPXID5
116
GPXID6
117
EC_CRY1
GPXID7
118
122
EC_CRY2
XCLK1
123
XCLK0
V18R 124
GND
GND
GND
GND
GND
11
24
35
94
113
AVCC 67
AGND
69
KB926QFD2_LQFP128_14X14
L69
ECAGND 1 2
FBMA-L11-160808-800LMT_0603
BATT_TEMP
BATT_OVP
AD_BID0
AD_PID0
EC_MUTE#
TP_CLK
TP_DATA
LID_SW#
FSTCHG
ACIN
EC_RSMRST#
BATT_OVP
BATT_TEMP
ACIN
TP_LOCK_LED#
EC_THERM#_R
Please close to EC pin
1
C674
4.7U_0805_10V4Z
2
C672 1 2
C673 1 2
C676 1 2
EC_INVT_PWM <24>
BEEP# <35>
FANPWM <6>
ACOFF <40>
BATT_TEMP <41>
BATT_OVP <40>
ADP_I <40>
DAC_BRIG <24>
EN_DFAN1 <6>
IREF <40>
CALIBRATE# <40>
EC_MUTE# <36>
TP_LOCK_LED# <34>
TP_CLK <29>
TP_DATA <29>
3S/4S# <40>
65W/90W# <40>
EC_VLDT_EN <33>
LID_SW# <34>
EC_SI_SPI_SO <30>
EC_SO_SPI_SI <30>
EC_SPICLK <30>
EC_SPICS#/FSEL# <30>
FSTCHG <40>
BATT_GRN_LED# <34>
CAPS_LED# <34>
BATT_AMB_LED# <34>
PWR_LED <34>
SYSON <37,44>
VR_ON <45>
ACIN <19,37,38,40>
EC_LID_OUT# <18>
EC_ON <33>
EC_SWI# <18>
EC_PWROK <33>
BKOFF# <24>
WL_OFF# <31>
VGATE <45>
ENBKL <13>
EAPD <35>
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
SUSP# <33,37,43>
PBTN_OUT# <18>
EC_PME# <25>
EC_RSMRST#
1
@
C762
0.1U_0402_16V4Z
2
For EC Tools
JP37
1
1
2
2
3
3
4
4
ACES_85205-0400
CONN@
1
2
Ra
Rb
Ra
Rb
+3VALW
1 2
17@
R186
100K_0402_5%
+3VALW
1 2
AD_PID0
AD_BID0
+3VALW
R219
@
100K_0402_5%
E51RXD_P80CLK
E51TXD_P80DATA
R656
1 2
0_0402_5%
Project ID
Please see page 3.
Board ID <VB support>
Please see page 3.
Place on MiniCard
+3VALW
U45
2
B
RSMRST#
Y 4
1
A
@NC7SZ08P5X_NL_SC70-5
R657
R740
@
10K_0402_5%
@
10K_0402_5%
1 2
P 5
G
3
1
2
0--NCWG0
3--NAL00
7--NCWH0
1
15@
R534
100K_0402_5%
C309
0.1U_0402_16V4Z
2
1 2
R215
8.2K_0402_5%
1
C306
0.1U_0402_16V4Z
2
E51RXD_P80CLK <31>
E51TXD_P80DATA <31>
RSMRST# <18>
D
C
B
A
2
3
Y1
32.768KHZ_12.5P_MC-306
WWW.AliSaler.Com
5
4
Security Classification
Compal Secret Data
Issued Date
2007/5/18 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
C
401743 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 28 of
47
3
2
1
For 17"
For 15"
Left
Right
Left
Right
BTN_L
SW4
17@SMT1-05-A_4P
3
1
BTN_R
SW5
17@SMT1-05-A_4P
3
1
BTN_L
SW2
15@SMT1-05-A_4P
3
1
BTN_R
SW3
15@SMT1-05-A_4P
3
1
4
2
4
2
4
2
4
2
5
6
TP_CLK
TP_DATA
BTN_R
BTN_L
3
2
TP_DATA
D14
TP_CLK
C174 1 2
100P_0402_50V8J
PJDLC05_SOT23-3
1
3
2
5
6
5
6
C169 1 2
100P_0402_50V8J
D15
PJDLC05_SOT23-3
1
5
6
To TP/B Conn.
Change to SCA00000200
<28>
<28>
TP_CLK
TP_DATA
+5VS
TP_CLK
TP_DATA
BTN_L
BTN_R
JTP1
6
5
4
3
2
1
ACES_85201-0605
CONN@
+5VS
C137
0.1U_0402_16V4Z
KALA0 used
INT_KBD Conn.
KSI[0..7]
KSO[0..17]
KSI[0..7] <28,34>
KSO[0..17] <28,34>
KB1 for 15"
KB2 for 17"
KSO15
KSO14
KSO13
KSO12
KSI0
KSO11
KSO10
KSI1
KSI2
KSO9
KSI3
KSO8
KSO16
C243 1 2
C242 1 2
C241 1 2
C240 1 2
C239 1 2
C238 1 2
C237 1 2
C236 1 2
C235 1 2
C234 1 2
C233 1 2
C232 1 2
C245 1 2
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
KSO7
KSO6
KSO5
KSO4
KSO3
KSI4
KSO2
KSO1
KSO0
KSI5
KSI6
KSI7
C231 1 2
C230 1 2
C229 1 2
C228 1 2
C227 1 2
C226 1 2
C225 1 2
C224 1 2
C223 1 2
C222 1 2
C221 1 2
C220 1 2
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
(Left)
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
(Right)
JKB1
26
KSO0 G2
28
25
KSO1 G1
27
24
KSO2
23
KSO3
22
KSO4
21
KSO5
20
KSO6
19
KSO7
18
KSO8
17
KSO9
16
KSO10
15
KSO11
14
KSO12
13
KSO13
12
KSO14
11
KSO15
10
KSO16
9
KSO17
8
KSI0
7
KSI1
6
KSI2
5
KSI3
4
KSI4
3
KSI5
2
KSI6
1
KSI7
ACES_88747-2601
CONN@
(Left)
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
(Right)
JKB2
26
KSO0 G2
28
25
KSO1 G1
27
24
KSO2
23
KSO3
22
KSO4
21
KSO5
20
KSO6
19
KSO7
18
KSO8
17
KSO9
16
KSO10
15
KSO11
14
KSO12
13
KSO13
12
KSO14
11
KSO15
10
KSO16
9
KSO17
8
KSI0
7
KSI1
6
KSI2
5
KSI3
4
KSI4
3
KSI5
2
KSI6
1
KSI7
ACES_88747-2601
CONN@
KSO17
C244 1 2
100P_0402_50V8J
Security Classification
Compal Secret Data
Issued Date
2005/03/08 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
C
401743 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 29 of
47
+3VALW
1 2
R618
0_0603_5%
C675 1 2
0.1U_0402_16V4Z
+SPI_VCC
U17
<28> EC_SPICS#/FSEL#
+3VALW
2
R619 2
R621
1
SPI_WP#
CE# VDD 8
1
3
SPI_HOLD#
WP# SCK 6
1
4.7K_0402_5%
7
HOLD# SI
5
4.7K_0402_5%
4
VSS
SO 2
MX25L8005M2C-15G_SOP8
EC_SPICLK_R
R620 1 2
0_0402_5%
EC_SO_SPI_SI_R
R622 1
EC_SI_SPI_SO_R
R623 1
2
0_0402_5%
2
0_0402_5%
EC_SPICLK <28>
EC_SO_SPI_SI <28>
EC_SI_SPI_SO <28>
EC_SPICS#/FSEL#
SPI_WP#
SPI_HOLD#
SA00000XT00 : S IC FL 8M MX25L8005M2C-15G SOP 8P
ENE suggestion SPI Frequency over 66MHz
SST: 50MHz
MXIC: 70MHz
ST: 40MHz
ONLY MXIC used in this project (66MHz)
U44
1
CS#
3
WP#
7
HOLD#
4
GND
MX25L512AMC-12G_SO8
@
R257
EC_SPICLK_R 1 2
@22_0402_5%
+SPI_VCC
VCC 8 EC_SPICLK_R
SCLK 6
EC_SO_SPI_SI
SI
5
EC_SI_SPI_SO
SO 2
Reserved for BIOS simulator.
Footprint SO8
SPI ROM Footprint 150mil
C296
1 2
@10P_0402_50V8J
WWW.AliSaler.Com
Security Classification
Compal Secret Data
Issued Date
2005/03/08 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
C
401743 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 30 of
47
A
B
C
D
E
1 1
+3VS_WLAN
+1.5VS
+3VALW
1
C442
1
C441
1
C439
1
C438
1
C440
1
C437
4.7U_0805_10V4Z
0.1U_0402_16V4Z
2
2
4.7U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
0.1U_0402_16V4Z
2
+3VS_WLAN
R487 1 2
0_1206_5%
+3VS
R653
0_0402_5%
JMINI2
<18> SB_PCIE_WAKE#
1 2
1
+3VS_WLAN
@
1
2
2
3
3
4
4
5
5
6
6
+1.5VS
<16> MINI1_CLKREQ#
7
7
8
8
9
9 10
10
<16> CLK_PCIE_MINI1#
11
11 12
12
2 <16> CLK_PCIE_MINI1
13
13 14
14
2
15
15 16
16
Mini Card Power Rating
<12> PCIE_PTX_C_IRX_N0
<12> PCIE_PTX_C_IRX_P0
<12> PCIE_ITX_C_PRX_N0
<12> PCIE_ITX_C_PRX_P0
<28> E51TXD_P80DATA
<28> E51RXD_P80CLK
E51TXD_P80DATA
E51RXD_P80CLK
+3VS_WLAN
R654 1 2
0_0402_5% E51TXD_P80DATA_R
For MINICARD Port80 Debug
H:9.9mm
For Wireless LAN
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
G1
G2
G3
G3
53
54
55
56
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
(MINI1_LED#)
FOX_AS0B226-S99N-7F
CONN@
R655
0_0402_5%
WL_OFF#_R 1 2
PLT_RST#
R246 1 2
0_0603_5%
R243 1 2
0_0603_5%
@
1
2
+3VALW
1 2
R752
0_0402_5%
R550
@100K_0402_5%
WL_OFF# <28>
PLT_RST# <13,15,17,25,28>
+3VS
+3VALW
SB_CK_SCLK <10,11,16,18>
SB_CK_SDAT <10,11,16,18>
USB20_N5 <18>
USB20_P5 <18>
WL_ON_LED# <34>
Power
+3VS
+3VALW
+1.5VS
Primary Power (mA)
Peak Normal
1000 750
330 250
500 375
Auxiliary Power (mA)
Normal
250 (wake enable)
5 (Not wake enable)
3 3
4 4
A
B
Security Classification
Compal Secret Data
Issued Date
2005/06/20 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
401743 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 31 of
47
C
D
E
A
B
C
D
E
1 1
USB CONN. 1 & 2
<18> USB20_N0
<18> USB20_P0
USB20_N0
USB20_P0
+USB_VCCA
1
C478+
150U_D2_6.3VM
2
R598 1 @ 2
0_0402_5%
R600 1 2
0_0402_5%
@
L67
4
4
3
1
1
2
2
SUYIN_020173MR004G565ZR
1
1
2
2
SUYIN_020173MR004G565ZR
CONN@ KALA0 used
CONN@ KALA0 used
WCM2012F2S-900T04_0805
WCM2012F2S-900T04_0805
2 2
3
W=80mils
1
C474
470P_0402_50V7K
2
USB20_N0_R
USB20_P0_R
JUSB1
1
VCC
2
D-
3
D+
4
GND
5
GND1
6
GND2
7
GND3
8
GND4
<18> USB20_N1
<18> USB20_P1
USB20_N1
USB20_P1
+USB_VCCA
1
C1
+
@
150U_D2_6.3VM
2
R599 1 @ 2
0_0402_5%
R601 1 2
0_0402_5%
@
L68
4
4
3
3
W=80mils
1
C2
470P_0402_50V7K
2
USB20_N1_R
USB20_P1_R
JUSB2
1
VCC
2
D-
3
D+
4
GND
5
GND1
6
GND2
7
GND3
8
GND4
+3VALW
USB20_N0_R
6
D31
CH3
CH2
3
USB20_N1_R
+5VALW
1
C111
4.7U_0805_10V4Z
2
U4
1
GND OUT
8
2
IN OUT
7
3
IN OUT
6
4
EN# FLG 5
TPS2061DRG4_SO8
+USB_VCCA
1
2
R42
100K_0402_5%
2 1
R171
10K_0402_5%
R677
0_0402_5%
1 2
1
C133
0.1U_0402_16V4Z
2
USB_OC#1 <18>
USB_OC#0 <18>
+USB_VCCA
USB20_P1_R
5
Vp
Vn
2
4
CH4 CH1
1
CM1293-04SO_SOT23-6
USB20_P0_R
<37,43> SYSON#
3 3
4 4
WWW.AliSaler.Com
A
B
Security Classification
Compal Secret Data
Issued Date
2005/06/20 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
401743 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 32 of
47
C
D
E
A
B
C
D
E
Power ON Circuit
For South Bridge
1 +3VALW
+3VALW
1
<37>
SUSP
2
G
Q11
2N7002_SOT23
1
3
D
S
R192
180K_0402_5%
+3VS
1
2
1
C322
1U_0603_10V4Z
2
+3VS
1
+3VALW
+3VALW
<28> EC_PWROK
1 2
R198
SB_PWRGD <8,18>
note:T1 minimum 15ms,T2 minimum 33ms/maximum 500ms,
SUSP# goes to low after SB_PWRGD goes to low for power
down.
R195
U13C
U13D
10K_0402_1%
SN74LVC14APWLE_TSSOP14
SN74LVC14APWLE_TSSOP14
D12
SUSP#
<28,37,43> SUSP#
1 2
5
I O 6
9
I O 8
1 2
VLDT_EN <37,42>
2
R180
@
0_0402_5%
CH751H-40PT_SOD323-2
C321
0.1U_0402_16V4Z 1 <28> EC_VLDT_EN
1 2
R183
0_0402_5%
2 2
2
1
I
P 14
G
7
P 14
3
I
U13B
SN74LVC14APWLE_TSSOP14
O 4
1 2
R191
@
0_0402_5%
0_0402_5%
For +1.2HT
VLDT_EN
NB_PWRGD
SB_PWRGD
SUSP#
+1.8VS
T1
T2
+3VALW
+3VALW
11
I
P 14
7
G
U13E
SN74LVC14APWLE_TSSOP14
O 10
13
I
P 14
7
G
U13F
SN74LVC14APWLE_TSSOP14
O 12
<34> ON/OFFBTN#
TOP Side
2
@ 1
R765
10K_0603_5%
2
@ 1
R766
10K_0603_5%
Bottom Side
ON/OFFBTN#
1
D10
2
3
+3VALW
Power Button
DAN202UT106_SC70-3
3 3
2
EC_ON
<28> EC_ON
2
G
R290
10K_0402_5%
@SW10
SMT1-05-A_4P
1
3
2
4
ON/OFFBTN#
6
5
G
7
U13A
SN74LVC14APWLE_TSSOP14
O 2
P 14
G
7
P 14
G
7
1 2
R281
100K_0402_5%
ON/OFF <28>
51ON#
51ON# <38>
C358
D11
1000P_0402_50V7K
RLZ20A_LL34
1
D
Q17
3
S
2N7002_SOT23
1
1
2
MP would remove
4 4
A
B
Security Classification
Compal Secret Data
Issued Date
2005/03/08 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
C
401743 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 33 of
47
C
D
E
PWR_LED#
MDC Conn.
<28>
PWR_LED
1
R291
100K_0402_5%
2
<18> HDA_SDOUT_MDC
<18> HDA_SYNC_MDC
<18> HDA_SDIN1
<18> HDA_RST_MDC#
HDA_SDOUT_MDC
HDA_SYNC_MDC
R357 1 2
33_0402_5%
HDA_RST_MDC#
R254
0_0402_5%
1 2
20mil
HDA_BITCLK_MDC
1
R256
+3VALW
HDA_BITCLK_MDC <18>
PWR_SUSP_LED#
2
<28> PWR_SUSP_LED
1
3
5
4
Q68B
2N7002DW-T/R7_SOT363-6
JMDC1
1
GND1
RES0
3
IAC_SDATA_OUT RES1
5
GND2
3.3V
7
IAC_SYNC
GND3
9
IAC_SDATA_IN GND4
11
IAC_RESET# IAC_BITCLK
GND
GND
GND
GND
GND
GND
2
4
6
8
10
12
+3VALW
1
C3
1U_0603_10V4Z
2
6
For EMI
R292
100K_0402_5%
2
ACES_88018-124G
0_0402_5%
CONN@
1
Connector for MDC Rev1.5
C432
13
14
15
16
17
18
2
Q68A
2N7002DW-T/R7_SOT363-6
22P_0402_50V8J
2
1
+5VS
LED1
R251
1K_0402_5%
1 2 2 YG 1
PWR_LED#
To PWR LED/B
+5VS +3VALW +5VALW +3VS
+5VALW
+5VALW
+5VALW
R250
1.2K_0402_5%
1 2 4 PWR_SUSP_LED#
A 3
HT-297UD/CB BLUE/AMB
HARVATEK
LED2
R253
1K_0402_5%
1 2 2 BATT_GRN_LED#
YG 1
R252
1.2K_0402_5%
1 2 4 BATT_AMB_LED#
A 3
HT-297UD/CB BLUE/AMB
HARVATEK
BLUE/AMB LED
BATT_GRN_LED# <28>
BATT_AMB_LED# <28>
JP14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
ACES_85201-20051
CONN@
LID_SW#
TP_LOCK_LED#
KSO0
KSI2
PWR_SUSP_LED#
PWR_LED#
ON/OFFBTN#
KSI1
WL_ON_LED#
MEDIA_LED#
NUM_LED#
CAPS_LED#
LID_SW# <28>
TP_LOCK_LED# <28>
KSO0 <28,29>
KSI2 <28,29>
ON/OFFBTN# <33>
KSI1 <28,29>
WL_ON_LED# <31>
NUM_LED# <28>
CAPS_LED# <28>
+5VALW +5VS +3VS
+3VALW
C435
C436
C444
C445
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSO0
WL_BTN#
TP_LOCK_BTN#
+3VS
6 1
5IN1_LED# <27>
MEDIA_LED# 3
4
SATA_LED# <19>
Q67B
2N7002DW-T/R7_SOT363-6
2
5
Q67A
2N7002DW-T/R7_SOT363-6
+3VS
WWW.AliSaler.Com
Security Classification
Compal Secret Data
Issued Date
2005/06/20 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Document Number Rev
R&D
B
401743 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 34 of
47
A
B
C
D
E
F
G
H
+3VS
+VDDA
1 2
R784
0_0805_5%
D38
+5VS
L80 1 2
1
R783
FBMA-L11-201209-221LMA30T_0805
IN
OUT
5
20K_0402_1%
2
R789
L81
GND
1 2
1 1 1
+VDDA 4.75V
RB751V_SOD323
10K_0402_5%
FBMA-L11-201209-221LMA30T_0805
3
SHDN BYP 4
1 C902
C901
2
1 1
1 2
MONO_IN
@
@G9191-475T1U_SOT23-5
0.01U_0402_25V7K
1U_0402_6.3V4Z
2 2 2
<28>
BEEP#
C903
1U_0402_6.3V4Z
2 1
R787
1 2
560_0402_5%
1
2
2
B
1
2
C
1
Q72
E
2SC2411KT146_SOT23-3
3
1 2
R786
2.4K_0402_1%
HD Audio Codec
+5VAMP
C106 22U_0805_6.3V6M
C899 0.1U_0402_16V4Z
C900 0.1U_0402_16V4Z
60mil
U81
(output = 300 mA)
40mil
<18>
SB_SPKR
1U_0402_6.3V4Z 1 2 C916 4.7U_0805_6.3V6K
C904
1U_0402_6.3V4Z 1 2
R788
1 2
560_0402_5%
2 1
D37
RB751V_SOD323
10mil
0.1U_0402_16V4Z
+3VS_DVDD
L82
MBK1608121YZF_0603
1 2
+3VS
1
1
1
C905
C906
C907
+AVDD_HDA
10U_0805_10V4Z
2
2
2
L83
40mil
+VDDA 1 2
0.1U_0402_16V4Z
FBM-L11-160808-800LMT_0603 1
1
1
0.1U_0402_16V4Z
C909
C910
C908
2 2
10U_0805_10V4Z
2
2
2
U82
0.1U_0402_16V4Z
14
15
16
25
AVDD1
38
LINE2_L
LINE2_R
MIC2_L
AVDD2
DVDD 1
LOUT1_L
17
MIC2_R
LOUT2_R 41
23
LINE1_L
SPDIFO2
45
24
LINE1_R
DMIC_CLK1/2
46
18
LINE1_VREFO
NC 43
20
1 2
C914
LINE2_VREFO DMIC_CLK3/4
44
1 2
R792
0_0402_5%
22P_0402_50V8J For EMI
19
MIC2_VREFO
<36> MIC1_L
MIC1_L 1 2 MIC1_C_L 21
C915
4.7U_0805_6.3V6K
MIC1_L
BITCLK
6
HDA_BITCLK_AUDIO <18>
<36> MIC1_R
MIC1_R 1 2 MIC1_C_R 22
C916
4.7U_0805_6.3V6K
MIC1_R
SDATA_IN 8
1 2
R793
33_0402_5%
HDA_SDIN0 <18>
MONO_IN 12
PCBEEP_IN MONO_OUT
37
CBP 29
<18> HDA_RST_AUDIO#
11
2.2U_0402_6.3V6M
RESET#
C917
CPVEE 31
1 2
<18> HDA_SYNC_AUDIO
10
SYNC
10mil
1
3 3
MIC1_VREFO 28
MIC1_VREFO_L
<18> HDA_SDOUT_AUDIO
5
C918
HP_RIGHT
SDATA_OUT
HP_RIGHT <36>
HP_RIGHT
HPOUT_R 32
2.2U_0402_6.3V6M
2
2
HP_LEFT
GPIO0/DMIC_DATA1/2
HP_LEFT <36>
3
R794
20K_0402_1% SENSE_A
GPIO1/DMIC_DATA3/4 CBN 30
<36> MIC_PLUG#
2 1
13
10mil
R795
5.11K_0402_1% SENSE_B
SENSE A
CODEC_VREF
<36> HP_PLUG#
2 1
34
SENSE B
VREF
27
1
1
<28> EAPD
1 R796
2
0_0402_5%
47
EAPD
JDREF
40
update this table
48
SPDIFO1
HPOUT_L
33 HP_LEFT
2
2
4
DVSS1
AVSS1
26
7
DVSS2
AVSS2
42
ALC272-VA2-GR_LQFP48_7X7
Sense Pin Impedance Codec Signals
1 2
1 2
Change to ALC272X
R798
0_0805_5%
R799
0_0805_5%
39.2K PORT-A (PIN 39, 41)
DGND
AGND
1 2
1 2
R800
0_0805_5%
R801
0_0805_5%
SENSE A
20K PORT-B (PIN 21, 22)
1 2
1 2
10K PORT-C (PIN 23, 24)
R802
0_0805_5%
R803
0_0805_5%
DVDD_IO 9
35
LOUT_R 36
LOUT2_L
39
AMP_LEFT
AMP_RIGHT
R797
1
2
20K_0402_1%
C919
10U_0805_10V4Z
C920
AMP_LEFT <36>
AMP_RIGHT <36>
0.1U_0402_16V4Z
5.1K PORT-D (PIN 35, 36)
4 4
39.2K PORT-E (PIN 14, 15)
GND
GNDA
GND
GNDA
SENSE B
A
20K
10K
5.1K
PORT-F (PIN 16, 17)
PORT-G (PIN 43, 44)
PORT-H (PIN 45, 46)
B
C
D
Security Classification
Compal Secret Data
Issued Date
2007/09/20 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Document Number Rev
R&D
B
401743
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 35 of
47
E
F
G
H
A
B
C
D
E
+5VAMP
0.1U_0402_16V4Z
Int. Speaker Conn.
C921
C922
JSPK1
1 1
10U_0805_10V4Z
SPKL+
R804 1 2
0_0603_5% SPK_L+ 1
2
2
SPKL-
R805
SPK_L-
1
1 2
0_0603_5%
2
2
<35> AMP_RIGHT
<35> AMP_LEFT
C923 1 2
0.47U_0603_10V7K
1 2
1 2 AMP_C_LEFT
C971
3900P_0402_50V7K
R813
0_0603_5%
U83
RIN+
C925 1 2
0.47U_0603_10V7K
7
9
5
LIN+
ROUT-
LIN-
VDD 16
PVDD1
15
PVDD2
6
GAIN0
GAIN1
ROUT+
LOUT-
LOUT+
SPKL-
1 2
1 2 AMP_C_RIGHT 17
C924
3900P_0402_50V7K
R808
0_0603_5%
RIN-
2
3
18
14
4
8
1
1
GAIN0
GAIN1
SPKR+
SPKL+
SPKR-
1
R809
100K_0402_5%
2
1
@
R811
100K_0402_5%
2
10 dB
1
2
+5VAMP
20mil
SPKR+
SPKR-
20mil
R810 1 2
0_0603_5%
R807 1 2
0_0603_5%
SPK_R+
SPK_R-
3
G1
4
G2
Left
ACES_88266-02001
CONN@
Right
2 2
<28> EC_MUTE#
EC_MUTE#
19
SHUTDOWN
GND5
GND1
GND2
GND3
GND4
21
20
13
11
1
NC 12
BYPASS 10
TPA6017A2_TSSOP20
Keep 10 mil width
2
C927
0.47U_0603_10V7K
1
<35> HP_RIGHT
<35> HP_LEFT
HP_RIGHT
HP_LEFT
20mil
2
C928
1 2 HPOUT_R_1 1 2
R814
56.2_0402_1%
L84
FBM-11-160808-700T_0603
1 2 HPOUT_L_1 1 2
R815
56.2_0402_1%
L85
FBM-11-160808-700T_0603
<35> HP_PLUG#
330P_0402_50V7K
330P_0402_50V7K
1
1
HPOUT_R_2
HPOUT_L_2
LINE Out/Headphone Out
HP_PLUG#
JHP1
8
7
5
4
3
6
2
1
SINGA_2SJ-E351-S03
CONN@
3 3
MIC1_VREFO_L
MIC1_VREFO_L
2
MIC JACK
1
RB751V_SOD323
D42
1
@
R806
100K_0402_5%
JSPK2
1
1
2
2
3
G1
4
G2
ACES_88266-02001
CONN@
2
1
RB751V_SOD323
D41
1
1
2
R812
100K_0402_5%
D39
@
PJDLC05_SOT23-3
D40
@
PJDLC05_SOT23-3
3
3
1
1
2
2
2
C929
JMIC1
8
7
R816
4.7K_0402_5%
R817
4.7K_0402_5%
<35> MIC_PLUG#
MIC_PLUG# 5
4
<35>
<35>
MIC1_R
MIC1_L
1 2
R818
1K_0603_1%
1 2
R819
1K_0603_1%
1 2
FBM-11-160808-700T_0603
L86
1 2
FBM-11-160808-700T_0603
L87
1
1
C930
C931
220P_0402_50V7K
220P_0402_50V7K
2
2
2
2
MIC2_R_1
MIC2_L_1
3
6
2
1
SINGA_2SJ-E351-S01
CONN@
(HDA Jack)
4 4
WWW.AliSaler.Com
A
B
Security Classification
Compal Secret Data
Issued Date
2007/09/20 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Document Number Rev
R&D
B
401743 C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 36 of
47
C
D
E
A
B
C
D
E
+3VALW TO +3VS
+5VALW TO +5VS
+3VS
R167
10K_0402_5%
+5VALW
+5VS
1
1
U7
+3VALW
C559
C562
8
SUSP
D S 1
<33> SUSP
7
10U_0805_10V4Z
1U_0603_10V4Z
D S 2
U41
6
2
2
S 1
D S 3
1
1
8
D
5
C166
C165
D
1 7
Q12
1
S 2
R508
D G 4
D
6
D S 3
100K_0402_5%
<28,33,43> SUSP#
2
5
5VS_GATE
+VSB
G
2N7002_SOT23
D G 4
1
AO4468_SO8
10U_0805_10V4Z
1U_0603_10V4Z
2
2
1 2
1 2
R562
20K_0402_1%
C143
S
AO4468_SO8
4.7U_0805_10V4Z
R586
2
10K_0402_5%
1
Q29
R728
0_0402_5%
C560
D
1 2 5VS_GATE
C570
2 SUSP
10U_0805_10V4Z
0.1U_0603_25V7K
G
2
R500
S
2N7002_SOT23-3
@
C658
0.1U_0603_25V7K
1 2
1
2
100K_0402_5%
1
3
1 2
1
2
+5VALW
1 2
1
3
+5VALW
<19,28,38,40> ACIN
ACIN
<32,43> SYSON#
D
Q5
+1.8V TO +1.8VS
+1.2V_HT
SYSON
<28,44> SYSON
2
G
S
2N7002_SOT23
2 2
+1.8V
+1.2VALW
R589
U37
1
1
100K_0402_5%
8
+1.8VS
C756
C757
D S 1
7
D S 2
6
U46
1U_0603_10V4Z
10U_0805_10V4Z
R698
+1.2VALW
D S 3
8
D S 1
2
2
5
470_0805_5%
D G 4
1
1
C447
C446
7
AO4430_SOIC8
D S 2
6
D S 3
5
D G 4
1
1
10U_0805_10V4Z
1U_0603_10V4Z
1 2
2
2
+VSB
1
R699
+ C30
C443
AO4430_SOIC8
33K_0402_5%
220U_B2_2.5VM_R25M
+5VALW
4.7U_0805_10V4Z
D
D
1
Q63
Q64
2
C759
VLDT_EN#
2
2
2
0.1U_0603_25V7K 2
G
G
2N7002_SOT23-3
1 C758
S
2N7002_SOT23-3
S
R725
2
R563
5VS_GATE
2
For PWR request
10K_0402_5%
60.4K_0402_1%
4.7U_0805_10V4Z
1 2
C632
0.1U_0603_25V7K
2
G
@
1
3
D
S
Q58
2N7002_SOT23-3
12/30 Change R563 to 60.4K
+1.2VALW TO +1.2V_HT
1
2
1
<33,42> VLDT_EN
ACIN 2
Q65
R726
G
2N7002_SOT23
100K_0402_5%
3 3
S
3
D
1
3
R700
33K_0402_5%
1 2
1
3
1
2
VLDT_EN
1
2
SYSON#
VLDT_EN#
2
G
1 2
1
3
1 2
1
3
D
S
R31
10K_0402_5%
Q66
2N7002_SOT23
+0.9V
+2.5VS
+1.5VS
+1.8V
+3VS
+1.8VS
+5VS
+NB_CORE
+1.1VS
1 2
R604
470_0402_5%
1 2
R587
470_0402_5%
1 2
R588
470_0402_5%
1 2
R26
470_0402_5%
1 2
R224
470_0402_5%
1 2
R270
470_0402_5%
1 2
R181
470_0402_5%
1 2
R184
470_0402_5%
1 2
R185
470_0402_5%
D
1
S
3
2 SYSON#
G
Q34
2N7002_SOT23
D
1
S
3
2 SUSP
G
Q35
2N7002_SOT23
D
1
S
3
2 SUSP
G
Q36
2N7002_SOT23
D
1
S
3
D
D
D
2 SYSON# 2 SUSP
2
SUSP 2 SUSP
2 VLDT_EN# 2 SUSP
G
G
G
G
G
G
Q6
S
Q14
S
Q15
S
Q10
S
Q13
S
Q16
2N7002_SOT23
2N7002_SOT23
2N7002_SOT23
2N7002_SOT23
2N7002_SOT23
2N7002_SOT23
3
3
3
D
D
3
3
1
1
1
1
1
4 4
A
B
Security Classification
Compal Secret Data
Issued Date
2005/03/08 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
C
401743 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 37 of
47
C
D
E
A
B
C
D
DC231000500
PJP1
PR1
SINGA_2DC-G756I200
ADPIN
PL1
VIN
1M_0402_5%
SMB3025500YA_2P
1 2
1
1 2
VIN
VS
VIN
G
G
2
3
1 1
PC1
2 1
560P_0402_50V7K
PC2
2 1
12P_0402_50V8J
PC3
2 1
12P_0402_50V8J
1 2
1 2 1
<19,28,37,40> ACIN
0
PU1A
LM358DT_SO8
PR8
PD3
10K_0402_5%
GLZ4.3B_LL34-2
2
2
PR6
22K_0402_5%
+
3 1 2
-
2
1
1
1
1 2
RTCVREF
- PBJ1
+
2
1
+RTCBATT
+RTCBATT
Vin Dectector
Min. Typ Max.
H-->L 16.976V 17.525V 17.728V
L-->H 17.430V 17.901V 18.384V
2 2
VIN
BATT+
1
+3VALWP
+3VALW
+1.5VSP
PJ2
2
2 1
1
JUMP_43X118
+1.5VS
PR12
200_0603_5%
CHGRTCP 1 2
PR10
PQ1
68_1206_5%
TP0610K-T1-E3_SOT23-3
N1 3
1
2
PR11
68_1206_5%
VS
+5VALWP
+5VALW
+0.9VP
PJ4
2
2 1
1
JUMP_43X79
+0.9V
PR13
100K_0402_1%
3 3
PR14
22K_0402_1%
1 2
<33> 51ON#
2
2
2
2
PJ5
PJ6
+VSBP
2
2 1
1
+VSB
+1.8VP
2
2 1
1
JUMP_43X39
JUMP_43X118
+1.8V
+CHGRTC
RTCVREF
1
2
3.3V
PU2
G920AT24U_SOT89-3
3
OUT IN 2
GND
PC9
10U_0805_10V4Z 1
N2
1 2 1
2
1
PC4
2 1
560P_0402_50V7K
@PR3
10K_0402_5%
PR5
PR160
0_0402_5%
10K_0402_5%
P 8
4
G
PC6
0.1U_0603_25V7K
2
2 1
PR9
10K_0402_5%
1
1
2
2
PR4
84.5K_0402_1%
PR7
20K_0402_1%
2 1
PC5
1000P_0402_50V7K
ML1220T13RE
45@
PD5
LL4148_LL34-2
2 1
1 1 2
PD4
LL4148_LL34-2
PJ1
2
2 1
1
JUMP_43X118
2
PJ3
2
2 1
1
JUMP_43X118
PC7
0.22U_1206_25V7K
1
1
PC8
0.1U_0603_25V7K
PR16
560_0603_5%
1 2
PR17
560_0603_5%
1 2
PR15
200_0603_5%
PC10
1U_0805_25V4Z
+1.2VALWP
+NB_COREP
PJ7
2
2 1
1
JUMP_43X118
PJ21
2
2 1
1
JUMP_43X118
+1.2VALW
+NB_CORE
+1.1VSP
+2.5VSP
PJ8
2
2 1
1
JUMP_43X118
PJ10
2
2 1
1
JUMP_43X118
+1.1VS
+2.5VS
4 4
WWW.AliSaler.Com
A
B
Security Classification
Compal Secret Data
Issued Date
2008/06/11 Deciphered Date
2010/03/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
C
401743
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 38 of
47
C
D
Compal Electronics, Inc.
SCHEMATIC, MB A5481
A
B
C
D
ISL6237_B+
ISL6237_B+
1 1
+3VALWP
B+
@PC203
680P_0402_50V7K
PC25
330U_6.3V_M
<BOM Structure>
PJ17
JUMP_43X118
2
2 1
1
PC15
4.7U_1206_25V6K
DH3
PR20
2
BST3A
2.2_0603_5% 1
LX3
DL3
2 2
+3.3VALWP Ipeak=4.26A ; Then set Imax=4.26A
Choke DCRmax=26.5m ohm, DCRtyp=23m ohm
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Vlimit=(5E-06 * 316K)/10=158mV
Ilimit=158mV/(18m*1.2) ~ 158mV/15m
=7.31A~10.53A
Iocp=Ilimit+Delta I/2
VS
=7.76A~10.98A
Delta I=0.908A (Freq=300KHz)
1
+
2
1
2
1 2
1 2
PR22
0_0402_5%
@PR25
10K_0402_1%
1
2
PL5
10UH_MSCDRI-104A-100M-E_4.6A_20%
1 2
FB3
3 3
check this part
PC16
4.7U_1206_25V6K
1SS355_SOD323-2
PC17
2200P_0402_50V7K
1
2
PC28
680P_0402_50V7K
PD7
1
2
PR19
4.7_1206_5%
2 1
1
2
1
2
PD6
GLZ5.1B_LL34-2
1 2
<8,41> MAINPWON
2
3 6
3 6
8
7
1
2
5
5
PR29
100K_0402_1%
1 2
8
7
1
2
PQ4
AO4712_SO8
4
PR30
200K_0402_5%
1 2
PR37
0_0402_5%
2 1
1 3
PQ2
AO4466_SO8
4
1 2
VL
1 2
PR35
806K_0603_1%
1 2
PQ6
TP0610K-T1-E3_SOT23-3
PR18
0_0805_5%
1 2
PC26
0.1U_0603_25V7K
PC31
PC32
0.22U_0603_25V7K
1
2
@PR33
0_0402_5%
PC21
0.1U_0603_25V7K
VL
2VREF_ISL6237
1 2
@PR38
47K_0402_5%
1 2
PC34
0.047U_0603_16V7K
1 2
PR34
0_0402_5%
1 2
1
2
2VREF_ISL6237
33
26
24
25
23
30
32
@PC35
0.047U_0402_16V7K
DH5
PR21
2.2_0603_5%
BST5A 2 1
4 4
1
0.22U_0603_10V7K
8
20
4
14
27
1 2
TP
UGATE2
BOOT2
PHASE2
LGATE2
OUT2
REFIN2
REF
LDOREFIN
NC
EN_LDO
EN1
EN2
VIN 6
NC
5
PC33
1U_0603_10V6K
1 2
PC22
1U_0603_10V6K
1 2
TON
2
1
2
2VREF_ISL6237
VCC 3
LDO 7
GND
21
VL
PC23
4.7U_0805_6.3V6K
POK2
POK1
1
2
PVCC 19
UGATE1
BOOT1
PHASE1
LGATE1
PR36
0_0402_5%
PGND 22
OUT1
FB1
BYP 9
SKIP 29
ILIM1
ILIM2
15
17
16
18
10
11
28
13
12
31
PC27
0.1U_0603_25V7K
LX5
DL5
FB5
ILM1
ILIM2
PC24
1U_0603_10V6K
1 2
@PR27
2
PU3
ISL6237IRZ-T_QFN32_5X5
1 2
0_0402_5%
1
PR28
0_0402_5%
1 2
PQ5
AO4712_SO8
PR31
365K_0402_1%
2 1
2
PQ3
AO4466_SO8
4
1
PR32
316K_0402_1%
4
5
5
3 6
3 6
VL
7
8
2
1
7
8
2
1
PR23
4.7_1206_5%
PC29
680P_0402_50V7K
PC18
4.7U_1206_25V6K
1
2
1
2
SPOK <41,44>
+5VALWP
+5VALWP Ipeak=6.87A ; Imax=4.81A
Choke DCRmax=26.5m ohm, DCRtyp=23m ohm
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Vlimit=(5E-06 * 365K)/10=182.5mV
Ilimit=182.5mV/(18m*1.2) ~ 182.5mV/15m
=8.44A ~ 12.16A
Iocp=Ilimit+Delta I/2
=8.90A ~ 12.62A
Delta I=0.921A (Freq=400KHz)
1
2
PC19
4.7U_1206_25V6K
1
2
PC20
2200P_0402_50V7K
1
2
PL4
10UH_MSCDRI-104A-100M-E_4.6A_20%
2
1
PR24
63.4K_0402_1%
1 2
PR26
10K_0402_1%
1 2
1
+ PC30
330U_6.3V_M
2
A
B
Security Classification
Compal Secret Data
Issued Date
2008/06/11 Deciphered Date
2010/03/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
C
401743
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 39 of
47
C
D
Compal Electronics, Inc.
SCHEMATIC, MB A5481
A
B
C
D
E
VIN
PC41
PC45
0.1U_0402_16V7K
PU4
1U_0805_25V6K
1 1
1 2
1
PVCC
PQ9
CHGEN
PVCC 28
1 2
@
AO4407A_SO8
PR43
PR44
/BATDRV
4
3.3_1210_5%
PC42
PC43
2.2_0603_5%
PQ10
0.1U_0603_25V7K
0.1U_0603_25V7K
BTST
27 BTST 1 2
4
AO4466_SO8
PR45
@PD11
340K_0402_1%
1 2
ACN 2
DH_CHG
PR274
ACP
ACN
HIDRV 26
3
PC44
RLZ24B_LL34
0_0805_5%
ACP
PR46
2.2U_0805_25V6K
1 2
4
LX_CHG
ACDET
ACDRV
PH 25
PL6
0.02_2512_1%
5
PD8
10UH_PCMB104T-100MS_6A_20%
ACDET
2 1 1 2
1 2 1
4
BATT+
Place close to back to back MOS
LL4148_LL34-2
PC46
2
3
0.1U_0603_25V7K
24751_VREF
PR47
PC47
CELLS GND 3 Cell
54.9K_0402_1%
ACSET 6
ACSET
10U_1206_25V6M
VREF 4 Cell
REGN 24
PC49
PQ11
@PR49
1U_0603_10V6K
4
AO4466_SO8
100K_0402_1%
PR50
PC51
PR48
0_0402_5%
0.47U_0603_16V7K
4.7_1206_5%
1 2
1 2 7
PR51
ACOP
340K_0402_1%
LODRV
23 DL_CHG
CELLS
@
PQ12
OVPSET
PGND 22
PC50
D
8
680P_0402_50V7K
PC52
2N7002W-T/R7_SOT323-3
OVPSET
0.1U_0402_16V7K
2
3S/4S# <28>
1 2
G
9
AGND
LEARN 21
ACOFF <28>
S
2 2
PR52
54.9K_0402_1%
PC53
PC54
24751_VREF
CELLS
20 CELLS
0.1U_0603_25V7K
0.1U_0603_25V7K
1 2
1
3
24751_VREF
PC55
10
VREF
1U_0603_10V6K
+3VALWP
PR53
SE_CHG+
100K_0402_1%
SRP 19
1 2 PQ13_GATE 2
11
SE_CHG-
PQ13
VDAC
SRN 18
Input OVP : 22.3V
SI2301BDS-T1-E3_SOT23-3
BAT
17
Input UVP : 17.26V
LI-4S :18.0V----BATT-OVP=2.001V
PC56
VADJ
0.1U_0603_25V7K
12
VADJ
PC57
BATT-OVP=0.1112*VMB
ACSET
0.1U_0603_25V7K
Icharge Setting
Fsw : 300KHz
ACGOOD#
TP
29
LI-3S :13.5V----BATT-OVP=1.5012V
13
ACGOOD
ICHG setting
PR55
For 2200mA, Icharge=0.8C=0.8*2*2.2=3.52A
BATT-OVP=0.1112*VMB
17.4K_0402_1%
Icharge=(Vsrset/Vdac)*(0.1/PR46)
VMB
SRSET
Per cell=3.5V
/BATDRV
SRSET
16
2 1 IREF <28>
14
BATDRV
IREF=((100k/(100K+17.4K))/3.3)*(0.1/0.02)=Icharge
PR56
10_0603_5%
PR57
IADAPT
15 1 2 100K_0402_1% @PC58
0.01U_0402_25V7K
IREF=0.7748*Icharge
VS
PR58
BQ24751ARHDR_QFN28_5X5
24751_VREF
CP Point Setting
340K_0402_1%
RTCVREF
3 3
CP point=Iadapter*85%
PC59
100P_0402_50V8J
@PR59
65W adapter R=(100K*100K)/(100K+100K)=50K
100K_0402_1%
Vacset=3.3*(50K/(50K+64.9K))=1.436V
24751_VREF
24751_VREF
ADP_I <28>
@PR61
0_0402_5%
24751_VREF
PR60
1 2
CP POINT=(1.436V/3.3V)*(0.1/0.015)=2.901A
499K_0402_1%
ACIN <19,28,37,38>
PQ13_GATE
@PR64
D
<28> BATT_OVP
PR65
PU1B
887K_0402_1% ACGOOD#
10K_0402_1%
LM358DT_SO8
D
2
@
PQ14
+
5
@
PQ16
G
2N7002W-T/R7_SOT323-3
1 2
7
SI2301BDS-T1-E3_SOT23-3 @PR66
0
2
PQ15
S
-
6
PC61
G
SSM3K7002F_SC59-3
0_0402_5%
0.1U_0402_16V7K
D
S
REGN
3
1
1 2
VADJ
ACOFF
24751_VREF
1 2
2
PR67
G
105K_0402_1%
S
PQ17
@PR69
SSM3K7002F_SC59-3
100K_0402_1%
@PC63
PR72
PR70
1000P_0402_50V7K
100K_0402_5%
PR73
210K_0402_0.1%
64.9K_0402_1%
24751_VREF1 2
ACSET
CHGEN#
D
@
PQ18
D
2
<28> CALIBRATE#
G
2N7002W-T/R7_SOT323-3
<28> FSTCHG
2
PQ19
PR74
S
G
2N7002W-T/R7_SOT323-3
100K_0402_1%
S
PR75
4 100K_0402_1%
4
D
<28> 65W/90W# 2
G
PQ20
S
2N7002W-T/R7_SOT323-3
CP setting
Cells selector
1
2
1
3
1
PR40
3.3_1210_5%
1
2
2
1
2
1
2
Charger ADJ
WWW.AliSaler.Com
A
1 2
1 2
1 2
1 2
8
7
6
5
PQ7
AO4407A_SO8
8
P
G
4
4
1
2
1 2
PC40
0.01U_0402_25V7K
1
2
1
2
3
PC60
0.01U_0402_25V7K
B
Calibrate#
4.0V L=0
4.2V
4.3V
4.35V
PQ8
AO4407A_SO8
1
8
2
7
3 6
5
1
2
1
2
1
2
1
2
PR42
100K_0402_1%
4
G
1 3
D
S
1.8755V
2.8132V
H=3.3V
1
2
1
2
PC62
0.01U_0402_25V7K
1
2
1
2
PR39
0.015_2512_1%
4
3
1
2
PR62
100K_0402_1%
PR68
340K_0402_1%
CHGEN#
1
2
1
2
1
3
PR63
200K_0402_1%
1
2
Security Classification
Issued Date
REGN
1
2
1
2
1
3
B+
1
2
PJ11
2
2 1
1
JUMP_43X118
1
2
CHG_B+
Compal Secret Data
2008/06/11 Deciphered Date
2010/03/12
5
5
1
2
3 6
3 6
1
2
7
8
2
1
7
8
2
1
S
1 2
PC37
4.7U_1206_25V6K
G
2
1
3
1
2
1
2
D
1 2
PC38
4.7U_1206_25V6K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Document Number Rev
R&D
B
401743
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 40 of
47
C
D
E
1 2
PC39
2200P_0402_25V7K
1
2
1
2
PC36
0.01U_0402_25V7K
1 2
1
2
Title
PR71
499K_0402_0.1%
1
2
1 2
1
2
1
2
PR244
100K_0402_5%
1 2
1
2
PR41
100K_0402_1%
1 2
1
3
1
2
3
2
1
5
6
7
8
PC137
10U_1206_25V6M
1 2
1
3
PC48
10U_1206_25V6M
Compal Electronics, Inc.
SCHEMATIC, MB A5481
1
2
A
B
C
D
PH1 under CPU botten side :
CPU thermal protection at 92 degree C
1 1
PJP2
SUYIN_250133MR007G115ZL
BATT_S1
EC_SMCA
EC_SMDA
2 2
EC_SMCA
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
1
3
5
7
9
11
13
15
17
19
PJP3
1
3
5
7
9
11
13
15
17
19
PR79
100_0402_1%
EC_SMDA
BATT_TEMP <28>
VMB
EC_SMB_CK1 <28>
EC_SMB_DA1 <28>
BATT+
3 3
VL
1 2
SUYIN_200109MS020G209ZR
2
4
6
8
10
12
14
16
18
20
2
4
6
8
10
12
14
16
18
20
1 2
PR80
100_0402_1%
1
2
PR85
1K_0402_1%
PC65
1000P_0402_50V7K
+3VALWP
3
1
B+ +VSBP
1
PR88
100K_0402_1%
PR90
22K_0402_1%
1 2
2
PR83
6.49K_0402_1%
2 1
1
2
PC69
0.22U_1206_25V7K
@
1
2
PQ22
TP0610K-T1-E3_SOT23-3
2
PL7
SMB3025500YA_2P
1 2
1
2
PC70
0.1U_0603_25V7K
@
1
2
PC66
0.01U_0402_25V7K
PH1
100K_0603_1%_TSM1A104F4361RZ
PC67
0.22U_0603_16V7K
<BOM Structure>
VL
VL
TM_REF1
PH2 near main Battery CONN :
BAT. thermal protection at 75 degree C
@PH2
100K_0603_1%_TH11-4H104FT
@PC71
0.22U_0603_16V7K
1
2
1
2
1
2
1
1
2
1
2
PR81
13.3K_0402_1%
PC64
0.1U_0603_25V7K
@PR89
6.49K_0402_1%
1 2
@PR91
22.1K_0402_1%
PR78
11.3K_0402_1%
1 2
1
2
PC68
1000P_0402_50V7K
1
2
TM_REF1
1
2
3
2
+
-
VL
PR82
100K_0402_1%
2 1 VL
PR84
100K_0402_1%
5
6
P 8
G
4
PR77
47K_0402_1%
1 2
@PR87
47K_0402_1%
1 2
+
-
VL
P 8
G
4
O 1
O 7
VL
1 2
PU5A
LM393DG_SO8
VL
1 2
PU5B
LM393DG_SO8
PR76
47K_0402_1%
PD9
2
@PR86
47K_0402_1%
1
2
LL4148_LL34-2
@PD10
LL4148_LL34-2
2 1
1
3
MAINPWON <8,39>
PQ21
DTC115EUA_SC70-3
1 2
PR92
100K_0402_1%
PR93
0_0402_5%
1 2
<39,44> SPOK
2
PC72
0.1U_0402_16V7K
@
1
D
2
PQ23
G
2N7002W-T/R7_SOT323-3
S
1
3
4 4
2
A
B
Security Classification
Compal Secret Data
Issued Date
2008/06/11 Deciphered Date
2010/03/12
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
C
401743
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 41 of
47
C
D
Compal Electronics, Inc.
SCHEMATIC, MB A5481
5
4
3
2
1
D
5
1
2
NB_51117_B+
PC206
10U_1206_25VAK
PL16
FBMA-L11-322513-151LMA50T_1210
1 2
B+
1
+ @
PC300
68U_25V_M_R0.44
2
D
C
<33,37> VLDT_EN
+5VALW
PR247
1.3K_0402_5%
1 2
1
PR249
47K_0402_5%
2
2 1
PR251
300_0603_5%
1 2
PC214
1U_0603_10V6K
1
2
PC208
0.1U_0402_16V7K
@PC213
47P_0402_50V8J
1 2
PR246
267K_0402_1%
1 2
PU12
2
TON
EN_PSV
1
3
VOUT
4
V5FILT
5
VFB
6
PGOOD
7
GND
15
14
TP
PGND
VBST
8
BST_NBCOREP
DRVH 13
LL
12
TRIP
11
4
PC209
PR248
0.1U_0603_25V7K
0_0603_5%
1 2BST_NBCOREP_11 2
DH_NBCOREP
LX_NBCOREP
+5VALW
DL_NBCOREP
4
TPS51117RGYR_QFN14_3.5x3.5
2 1
PR252
12K_0402_1%
2 1
PC212
4.7U_0805_10V6K
3
2
1
PQ35
SIS412DN-T1-GE3_POWERPAK8-5
PL13
1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%
1 2
PR250
4.7_1206_5%
+NB_COREP
C
1
2
PR254
10K_0402_1%
1 2
PR255
30K_0402_1%
+3VS
B
D
PR257
10K_0402_1%
PQ37
2
1 2
2N7002W-T/R7_SOT323-3
G
VFB=0.75V
S
@
PR258
Rton=267K, Freq=298KHz
10K_0402_1%
PC215
Ipeak=7A Imax=5.32A
0.1U_0402_16V7K
Delta I=((19-1.1)*(1.1/19))/(1.8U*298K)=1.93A
Rtrip=12K
1/2DeltaI=0.96A
Rdson=9m~11.5m
BOM control (R*C>1ms)
Iocp=9.05A~14.30A
D
H
L
1.017V
1.1V
1
3
1 2
PR260
10K_0402_1%
2 1 2
G
1 2
+3VS
+5VALW
+1.2VALW
+1.1VSP
B
A
1
<BOM Structure>
PR271
3.24K_0402_1%
A
2
V5DRV
10
DRVL
9
D 5
D 6
D 7
D 8
G
S
S
S
1
2
1
2
PQ36
FDS6670AS_NL_SO8
3
2
1
PC211
680P_0603_50V8J
1
+ PC210
330U_D2E_6.3VM_R25M
2
PR253
3.57K_0402_1%
1 2
1
2
PQ38
2N7002W-T/R7_SOT323-3
1
S
3
1 2
PR256
10K_0402_5%
1 2
@PR259
10K_0402_5%
PC227
1U_0402_6.3V6K
POWER_SEL
POWER_SEL <13>
PU15
@PR261
10K_0402_1%
7
POK
PR273
12_0402_5%
<33,37> VLDT_EN
VLDT_EN 1 2
8
EN
PC228
1U_0603_10V6K
1
2 1
1
2
PR270
10K_0402_5%
6
VCNTL
GND
2
1
VIN 5
VOUT
4
VOUT
3
FB
2
VIN 9
APL5912-KAC-TRL_SO8
2 1
1
2 1 2
PJ22
JUMP_43X79
@
PC230
4.7U_0805_6.3V6K
1
PR272
1.3K_0402_1%
2
PC226
0.01U_0402_25V7K
2 1
PC229
2 1
22U_0805_6.3V6M
WWW.AliSaler.Com
5
4
Security Classification
Compal Secret Data
Issued Date
2008/11/03
Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
401743
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 42 of
47
3
2
1
5
4
3
2
1
+1.8V
1
PJ12
JUMP_43X79
D
2
2
PU6
1
VIN
VCNTL
6
+3VALW
D
<32,37> SYSON#
@PR95
0_0402_5%
1 2
@PC77
0.1U_0402_16V7K
PC73
4.7U_0805_6.3V6K
@
PQ24
2N7002W-T/R7_SOT323-3
2
G
1
2
1 2
1
3
D
S
1
PR94
1K_0402_1%
1 2
+0.9VP
PC76
10U_0805_6.3V6M
1
2
PC74
1U_0402_6.3V6K
+3VS
2 1
@PR98
150_1206_5%
+2.5VSP
C
C
+1.8V
+5VALW
B
1
PC83
1U_0402_6.3V6K
B
2
1
2
2
GND NC 5
3
REFEN NC 7
4
VOUT NC 8
GND 9
RT9173DPSP_SO8
6
1
2
2
1
1
PR96
1K_0402_1%
2
PC75
0.1U_0402_16V7K
PU7
APL5508-25DC-TRL_SOT89-3
2
IN OUT
3
GND
PC78
1U_0402_6.3V6K
1
PC79
4.7U_0805_6.3V6K
PJ14
JUMP_43X79
<28,33,37> SUSP#
PR101
100K_0402_5%
1 2
PR103
1 2
47K_0402_5%
2 1
7
POK
8
EN
PC86
0.1U_0402_16V7K
1
GND VCNTL
VIN 5
VOUT
4
VOUT
3
FB
2
VIN 9 PR102
PC85
1.54K_0402_1%
0.01U_0402_25V7K
PU8
APL5915KAI-TRL_SO8
1
PC84
4.7U_0805_6.3V6K
2
1
1
2
2
1
PR104
1.74K_0402_1%
1
2
PC87
22U_0805_6.3V6M
+1.5VSP
2
2 1
2 1
1
2
A
A
5
4
Security Classification
Compal Secret Data
Issued Date
2008/06/11 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Document Number Rev
R&D
Custom
401743
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 43 of
47
3
2
1
5
4
3
2
1
D
<28,37> SYSON
PR107
0_0402_5%
1 2
PR106
267K_0402_1%
1 2
PR200
0_0603_5%
1 2 4
5
3 6
7
8
2
1
1.8_51117_B+
PQ25
AO4466_SO8
2 1
PL14
FBMA-L11-322513-151LMA50T_1210
1 2
PC88
10U_1206_25VAK
2 1
B+
@PC204
680P_0402_50V7K
D
C
VFB=0.75V
Vo=VFB*(1+PR111/PR112)=0.75*(1+14K/10K)=1.8V
Rton=267K=>Faw=297KHz
+5VALW
Cout ESR=15m ohm
Ipeak=11.96A, Imax=8.372A
Delta I=((19-1.8)*(1.8/19))/(L*Fsw)
((19-1.8)*(1.8/19))/(1.8u*297000)=3.048A
=>1/2DeltaI=1.524A
PR109
300_0603_5%
1 2
PC94
1U_0603_10V6K
1
2
1
2
@PC89
0.1U_0402_16V7K
1
@PC93
47P_0402_50V8J
1 2
PR111
14K_0402_1%
1 2
PU9
EN_PSV 1
2
TON
DRVH 13
3
VOUT
LL
12
4
V5FILT VFB=0.75V TRIP 11
5
VFB
V5DRV 10
6
PGOOD
DRVL
9
GND
7
TP 15
PGND
8
14
VBST
BST_1.8V
DH_1.8V
LX_1.8V
DL_1.8V
TPS51117RGYR_QFN14_3.5x3.5
PR108
PC90
0_0603_5%
0.1U_0603_25V7K
1 2BST_1.8V-1
1 2
1
2
PR110
16.2K_0402_1%
1
2
+5VALW
PC92
4.7U_0805_10V6K
PQ26
FDS6670AS_NL_SO8
4
G
D 5
D 6
D 7
D 8
3
2
1
S
S
S
2 1 2 1
PL8
1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%
1 2
1
@PR201
4.7_1206_5%
+ PC91
330U_6.3V_M
2
@PC171
680P_0402_50V7K
+1.8VP
C
PR112
10K_0402_1%
2
Rtrip=16.2K
Iocp=12.39A~20.69A
1.2_51117_B+
PL15
FBMA-L11-322513-151LMA50T_1210
1 2
B+
B
A
<39,41> SPOK
VFB=0.75V
Vo=VFB*(1+PR119/PR120)=0.75*(1+6.04K/10K)=1.203V
Rton=267K=>Fsw=298KHz
+5VALW
PR115
0_0402_5%
1 2
1.2VP Ipeak=7.4A ; Imax=5.180A
Delta I=((19-1.2)*(1.2/19))/(L*Fsw)
((19-1.2)*(1.2/19))/(1.8u*298000)=2.10A
=>1/2DeltaI=1.05A
Rdson=11.5m/9m ohm
set Rtrip=12K
Icop_min=9.11A
Iocp_max=14.38A
@PC96
0.1U_0402_16V7K
PR120
10K_0402_1%
WWW.AliSaler.Com
5
4
1
2
PR117
300_0603_5%
1 2 @PC100
47P_0402_50V8J
1 2
PC101
1U_0603_10V6K
1
2
1
2
PR119
6.34K_0402_1%
1 2
PR114
267K_0402_1%
1 2
PU10
EN_PSV 1
2
TON
DRVH 13
3
VOUT
LL
12
4
V5FILT VFB=0.75V TRIP 11
5
VFB
V5DRV 10
6
PGOOD
DRVL
9
GND
7
TP 15
PGND
8
14
VBST
Security Classification
Issued Date
BST_1.2V
DH_1.2V
LX_1.2V
DL_1.2V
TPS51117RGYR_QFN14_3.5x3.5
PR116
PC97
0_0603_5%
0.1U_0603_25V7K
1 2BST_1.2V-1
1 2
1
2
PR118
12K_0402_1%
1
2
+5VALW
PC99
4.7U_0805_10V6K
Compal Secret Data
PQ40
FDS6670AS_NL_SO8
PQ39
AO4466_SO8
2008/06/11 Title
Deciphered Date
2010/03/12
4
PC95
10U_1206_25VAK
PL9
1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%
1 2
+1.2VALWP
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
C
401743
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 44 of
47
3
2
1
4
D 5
D 6
D 7
D 8
G
3
2
1
S
S
S
5
3 6
1
2
1
2
7
8
2
1
@PR203
4.7_1206_5%
@PC172
680P_0402_50V7K
1
2
1
1
2
+ PC98
330U_D2E_2.5VM
2
@PC205
680P_0402_50V7K
B
A
5
4
3
2
1
D
C
B
<8> CPU_VCC_SENSE
+CPU_CORE
行 from output Bulk Cap
<8> CPU_VSS_SENSE
PR224
PC181
97.6K_0402_1%
470P_0402_50V7K
1 2
1 2
PC184
220P_0402_50V8J
1 2
PR226
1K_0402_1%
2 1
PR227
255_0402_1%
PC185
1000P_0402_50V7K
1 2
1 2
PR229
10_0402_5%
2 1
PR232
10_0402_5%
1 2
2
PR228
0_0402_5%
Rn=(PR241+PH3)//(PR236)=5.875k, Rseuq=Rs/2=1.825K
Vdcrequ=Io*(DCR/2),
Vn=Vdcrequ*(Rn/(Rsequ+Rn))
=Io*(DCR/2)*(Rn/(Rsequ+Rn))
=Io*(DCR/2)*G1
Vdroop=Vn/Rdroop1*(Rdroop1+Rdroop2)
=Vn*(1+(Rdroop2/Rdroop1))
=Vn*(1+(PR231/PR230))
=Vn*G2
=>Vdroop=Vn*(1+(PR231/PR230))=Io*Rdroop
=>Io*(DCR/2)*G1*G2=Io*Rdroop
=>Rdroop=1.007m ohm
1
PC177
1000P_0402_50V7K
1 2
2
PR216
6.81K_0402_1%
1 2 @PC178
1000P_0402_50V7K
1 2
@PC187
1000P_0402_50V7K
1 2
1
@
PR234
0_0402_5%
@
<28> VGATE
VCC_PRM
PR217
4.02K_0402_1%
1 2
PC179
0.047U_0402_16V7K
1 2
1 2
1 2
@PC192
1000P_0402_50V7K
@
PC193
0.22U_0402_6.3V6K
1 2
PR218
36.5K_0402_1%
1 2
PR215
150K_0402_1%
1 2
@PC186
0.068U_0402_16V7K
PC194
0.022U_0402_16V7K
1 2
@PD100
RB751V-40TE17_SOD323-2
2 1
+3VS
+3VS
1 2
PR204
10K_0402_5%
PSI_L
VR_ON
Close to Phase1 Choke PL11
VCC_PRM
LG_CPU1
UG_CPU1
PC188
0.22U_0603_25V7K
CPU_ISEN1
`'?'`''
~'0~'''''P|'
|''@}'
{''`z'z'`{'Py'
y''`x' 勵 '
w'0w'''x''Pu'
u''@v'''`s's'`t't'
r''`q'0p''pr'?'`??'?'P? PQ32
??'??'p?`??`???'?'`??'p? ??'?'??'p?
??'@??'?'P??`???'p?`??'@'?'p? ??'??'p? ??
180P_0402_50V8J
SI7686DP-T1-E3_SO8
1 2
CPU_ISEN2
PR230
PR231
1K_0402_1%
1.4K_0402_1%
4
2 1 1 2
+5VS
PC195
0.22U_0402_6.3V6K
1 2
1 2
PR210
10K_0402_5%
1
2
3
4
5
6
7
8
9
10
41
1 2
@PR212
10K_0402_5%
@
SET
RBIAS
OFS
SOFT
OCSET
VW
COMP
FB
VDIFF
VSEN
PR236
11K_0402_1%
1 2
PR206 0_0402_5%
1 2
GND PAD
PGOOD 40
RTN
11
1 2
PR241
2.61K_0402_1%
1 2
Rn
39
PSI_L
DROOP
12
1 2
PR205 0_0402_5%
VR_ON 38
VSUM
<8>
1 2
PR213 0_0402_5%
1 2
PR245 0_0402_5%
<28>
CPU_VID5 <8>
B+
PC196
0.01U_0402_50V7K
1 2
1
2
CPU_VID4 <8>
PR208 0_0402_5%
PU11
ISL6264CRZ-T_QFN40_6X6
DFB
13
PH3
10K_0603_5%_TSM1A103J4302RE
1 2
37
VID5
VO
14
PR211 0_0402_5%
36
VID4
VSUM
15
35
VID3
VIN
16
1 2
34
VID2
GND
17
PR214 0_0402_5%
33
VID1
VDD
18
1 2
PR235
10_0603_5%
1 2
PR209 0_0402_5%
32
VID0
ISEN2
19
CPU_VID3 <8>
31
BOOT1
ISEN1
20
PR233
10_0402_5%
1 2
PC197
1U_0402_6.3V6K
1
2
CPU_VID2 <8>
CPU_VID1 <8>
UGATE1
PHASE1
PGND1
LGATE1
LGATE2
PGND2
PHASE2
UGATE2
BOOT2
CPU_VID0 <8>
1
PR207
2.2_0603_5%
30
29
28
27
PVCC 26
25
24
23
22
21
2
1 2
UG_CPU2
2 1
PR225
2.2_0603_5%
PC176
0.22U_0603_25V7K
PR223 0_0402_5%
2 1
2 1
PC182
4.7U_0603_6.3V6K
1 2
+5VS
PHASE_CPU1
PHASE_CPU2
LG_CPU2
5
PQ30
AO4456_SO8
5
PQ33
AO4456_SO8
4
4
4
3 5
3 6
3 5
3 6
2
1
7
8
2
1
2
1
7
8
2
1
PQ29
SI7686DP-T1-E3_SO8
5
PQ31
AO4456_SO8
5
PQ34
AO4456_SO8
4
4
3 6
3 6
7
8
2
1
7
8
2
1
PC202
2200P_0402_50V7K
1
2
1
2
1 2
PR219
4.7_1206_5%
1
2
1 2
PR237
4.7_1206_5%
PC199
680P_0603_50V8J
PC200
2200P_0402_50V7K
PC183
680P_0603_50V8J
1 2
1
2
VSUM
VSUM
1 2
1 2
PR220
3.65K_0805_1%
1 2
PR221
10K_0402_1%
CPU_ISEN1
Rs
CPU_ISEN2
PC174
10U_1206_25V6M
1 2
CPU_B+
PC180
0.22U_0603_16V7K
1 2
VCC_PRM
CPU_B+
PL12
0.36UH_PCMC104T-R36MN1R17_30A_20%
1 2
1 2
PR238
3.65K_0805_1%
1 2
PR239
10K_0402_1%
PL11
0.36UH_PCMC104T-R36MN1R17_30A_20%
1 2
PC190
10U_1206_25V6M
1 2
PC191
10U_1206_25V6M
PC175
10U_1206_25V6M
1 2
PR240
1_0402_5%
PC198
0.22U_0603_16V7K
1 2
1 2
PR222
1_0402_5%
VCC_PRM
PL10
FBMA-L18-453215-900LMA90T_1812
1 2
1 2
1 2
1
CPU_ISEN2
CPU_ISEN1
B+
+ PC201
220U_25V_M
2
+CPU_CORE
PR242
10K_0402_1%
+CPU_CORE
PR243
10K_0402_1%
D
C
B
A
Iocp_min*Rdroop>Rocset*10uA
=>25A*1.007m ohm>Rocset*10uA
=>choose Rocset=2.74K
=>Iocp_min*1.007m ohm>2.74K*10u
=Iocp_min>27.209A
A
Iocp_max*Rdroop>Rocset*10.4uA
=>Icop_max>28.297A
Iocp=~27.209A~28.297A
5
4
Security Classification
Compal Secret Data
Issued Date
2008/06/11 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
401743
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 45 of
47
3
2
1
5
4
3
2
1
Item
Version change list (P.I.R. List) Page 1 of 1
for PWR
Reason for change Rev. PG# Modify List Date Phase
Fixed Issue
D
1
HW required to adjust from 1.14V to
1.12V
HW required to adjust from 1.14V to
1.12V
Change PR271 from SD034300180 (S RES 1/16W 3K +-1%
0.1 42 0402) to SD034324180 (S RES 1/16W 3.24K 0402 1%) 09, 05/07 to PVT
D
2
Power sequense adjust. HW required to adjust power sequense. 0.1 42 Add PC208 SE076104K80 (S CER CAP .1U 16V K X7R 0402) 09, 05/07
to PVT
3
4
5
Power sequense adjust. HW required to adjust power sequense. 0.1 42
NB_COREP working frequency has
issue.
Because NB_COREP working frequency will be gitter
while system at heavy loading. Change to larger ESR
Cap will be solve.
0.1 42
Change PR247 from SD028000080 (S RES 1/16W 0 +-5%
0402) to SD028130180 (S RES 1/16W 1.3K 0402 5%)
Change PC210 from SGA19331D00 (S POLY C 330U 2.5V M
D2 TPE LESR15M H1.8) to SGA00002B00 (S POLY C 330U
6.3V M D2E ESR25M TPE H1.8)
09, 05/07
09, 05/07
BOM error BOM error
0.1 42 Add PR270 SD28100280(S RES 1/16W 10K 0402 5%) 09, 05/07 to PVT
to PVT
to PVT
6
BOM error BOM error
0.1 42
Change PR103 from SD028470280(S RES 1/16W 47K 0402 5%)
to SD028100280(S RES 1/16W 10K 0402
09, 05/07 to PVT
5%)
C
7
C
8
9
10
11
B
12
B
13
14
A
15
16
17
18
A
WWW.AliSaler.Com
5
4
Security Classification
Compal Secret Data
Issued Date
2008/06/11 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
401743
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 46 of
46
3
2
1
5
4
3
2
1
Version change list (P.I.R. List) for HW
Item
Reason for change
Modify List
PG#
Date
Item
Reason for change Modify List
Rev. PG#
D
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PWR update circuit 4/9
BOM change
BOM change
R118 reserve P.18 4/9
Change R178, R179 to 90.9/158 ohm P.16 4/9
BOM change R30, R39 reserve P.24 4/9
BOM change Add C30 P.38 4/9
BOM change Add R634, R639 P.28 4/9
BOM change C383 Reserve P.24 4/9
PWR update circuit
Pop R419 P.20 4/10
For Panel flash issue R1,D2 Reserve, pop R763 P.24
For Panel flash issue Add R414 and non-pop P.24
Lid_SW intial issue Add R19 P.28
HPET timer issue Change C288,C290 to 33P P.16
5/15
5/18
5/18
5/18
5/18
BOM change change C276,C279 10P to 27P P.19 5/19
26
27
28
29
30
31
32
33
D
C
16
17
18
19
20
B
21
B
22
23
24
25
A
A
5
4
Security Classification
Compal Secret Data
Issued Date
2005/03/08 Deciphered Date
2010/03/12
Title
Compal Electronics, Inc.
SCHEMATIC, MB A5481
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
C
401743 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, June 24, 2009
Sheet 47 of
47
3
2
1
Change language