my current CV - University of Windsor

EDUCATION:
RÉSUMÉ
Dr. Mohammed A. S. Khalid
Associate Professor
Dept of Electrical and Computer Engineering
University of Windsor, 401 Sunset Avenue
Windsor, Ontario, Canada N9B 3P4
Tel: (519) 253-3000, Ext. 2611, Fax: (519) 971-3695
Email: mkhalid@uwindsor.ca
Web: http://www.vlsi.uwindsor.ca/~mkhalid
1999 University of Toronto Toronto, Ontario, Canada
Ph.D. in Computer Engineering, University of Toronto, Canada.
Thesis Title: Routing Architecture and Layout Synthesis for Multi-FPGA
Systems.
Advisor: Professor Jonathan Rose.
1986 Louisiana State University Louisiana, USA
M.S.E.E., 1986, Computer Engineering, Louisiana State University, U.S.A
1984 Osmania University Hyderabad, India
B.E., 1984, Electronics and Communication Engineering, Osmania University,
Hyderabad, India.
WORK EXPERIENCE:
Since 07/09 University of Windsor Windsor, Ontario, Canada
Associate Professor in the Electrical and Computer Engineering Department.
Research interests include architectures and CAD tools for rapid prototyping,
verification acceleration and reconfigurable computing, physical design
automation for VLSI and FPGAs, embedded system design.
08/03-06/09 University of Windsor Windsor, Ontario, Canada
Assistant Professor in the Electrical and Computer Engineering Department.
01/99-07/03 Cadence Design Systems San Jose, California, USA
Senior member of technical staff, Verification Acceleration Group (former
Quickturn). As a key member of the Core Emulation Design Compiler Group,

developed efficient algorithms and CAD tools for multi-way partitioning and
board level routing. Participated in development of the next generation of
emulation CAD tools and field programmable system architectures. Interacted
with design verification teams from leading semiconductor and electronic
systems vendors (Intel, Nokia) to obtain end user feedback and improve the
quality of emulation CAD tools and architectures.
09/93-12/98 University of Toronto Toronto, Ontario, Canada
Instructor, Research and Teaching Assistant, Electrical and Computer
Engineering Department. Taught a course in Computer Organization with a
class size of more than 100 students and supervised three teaching assistants
(Summer of 1994). Teaching assistant for courses on Algorithms and Data
Structures, Digital Systems, Microprocessor Systems and VLSI Systems. Coordinated
the digital system modeling lab (using VHDL) in the VLSI Systems
Course.
08/87-07/93 King Fahd Univ. of Petroleum & Minerals (KFUPM), Dhahran, Saudi Arabia
Lecturer, Computer Engineering Department. Taught undergraduate level
courses in Computer Organization, Digital Logic Design, and Microprocessor
System Design and Interfacing. Conducted research in VLSI layout design
automation. Supervised senior projects in digital system design and
interfacing which involved the design and implementation of functional PC
interface cards for applications such as data communication (modem) and data
acquisition.
PERSONAL BACKGROUND :
CAREER HIGHLIGHTS:
Canadian Citizen, born in Hyderabad, India on Nov. 30, 1961. Studied,
worked or traveled in South Asia, Middle East, North America and Europe.
Fluent in English and Urdu.
1998 Proposed a new routing architecture for Multi-FPGA Systems which was
licensed to Quickturn Design Systems (San Jose, California) by the University
of Toronto. In return, the University of Toronto received substantial research
funding from Quickturn. A U.S. patent was also granted for this invention in
2003.
1998 Best Paper Award in the Systems Category, MICRONET Annual Workshop,
April 1998, Ottawa, Canada.
1984 Overseas Travel Award for Higher Studies, H. E. H. The Nizam’s Trust,
Hyderabad, India.

1980 Ranked 95 th out of about 60,000 students in the Joint Engineering Entrance
Exam, Hyderabad, India.
INVITED TALKS :
1. NoC Prototyping on FPGAs, Hubert Curien Lab, Jean Monnet University, St. Etienne,
France, July 2009.
2. Reconfigurable Computing Systems: Challenges and Opportunities, Department of
Computer Science and Engineering, Osmania University, Hyderabad, India, September
2006.
3. Introduction to Embedded Systems Design, ICUE’05, Windsor, Canada, May, 2005.
4. An Overview of Reconfigurable Computing Systems, Ryerson University, Toronto,
Canada, May 13, 2004.
5. Introduction to Field Programmable Chips and Systems, IEEE Student Branch S-PAC,
University of Windsor, November 15, 2003.
6. Field-Programmable Chips and Systems: Current Status and Future Directions,
Computer Society of India, Hyderabad Chapter, July 8, 2000.
7. Experimental Evaluation of Routing Architectures for Multi-FPGA Systems, Quickturn
Design Systems, San Jose, California, February 25, 1998.
SERVICES IN PROFESSIONAL SOCIETIES AND RESEARCH ORGANIZATIONS
1. Served on the program committee of IEEE sponsored Reconfigurable Architectures
Workshop (RAW) from 1999 to 2004.
2. Served as a reviewer for IEEE Trans. on CAD, IEEE Trans. on VLSI, and several other
IEEE/ACM sponsored conferences and workshops.
3. Served as a Session Chair in RAW’99 and FPL’2005.
4. Served as a reviewer for the Natural Sciences and Engineering Research Council of
Canada (NSERC), Canada Foundation for Innovation (CFI) and Research Grants Council
(RGC) of Hong Kong.
5. Served as Conference General Chair for 2009 IEEE International Conference on
Electro/Information Technology, held at Windsor, Ontario, Canada from June 7 to 9,
2009.
SERVICE AT THE UNIVERSITY OF WINDSOR :
2003- 2004: ECE dept. Graduate Assistantship Committee and Undergraduate Curriculum
Committee.

2004- 2009: ECE dept. Undergraduate Curriculum Committee, Undergraduate Advising
Committee and Scholarship Committee.
2004-2006: Member of Faculty of Engineering’s Faculty Coordination Council (FCC)
2006: ECE dept. representative in Faculty of Engineering’s Winter Term Curriculum Task
Force.
2005-2009: ECE dept. faculty representative and liaison for Co-op Office.
UNIVERSITY COURSES TAUGHT :
At the University of Windsor
Undergraduate Courses
85-124 Electric Circuits I, 85-211 Computer-Aided Analysis II (C++ and Numerical
Methods), 88-226 Electronics I, 88-330 Digital Logic Design II, 88-441 Software
Engineering, 88-443 Embedded System Design.
Graduate Courses
88-559 Physical Design Automation for VLSI & FPGAs. 88-560 Reconfigurable Computing,
88-590-76 Embedded System Design.
At the University of Toronto
CSC 258, Computer Organization.
At King Fahd University of Petroleum & Minerals (KFUPM)
• COE 201 Digital Logic Design I
• COE 352 Microprocessors
• COE 454 Digital System Design
GRADUATE STUDENTS SUPERVISED
1. Yonghong Xu, Efficient Quadratic Placement for FPGAs, MASc thesis completed April
2005.
2. Kevin Banovic, Blind Adaptive Equalization for QAM Signals: New Algorithms and
FPGA Implementation, MASc thesis completed January 2006 (co-supervised with Dr.
Esam Abdel-Raheem).
3. Muqeeth Ali Syed, M. Eng. completed August 2006.
4. Amir Ali Yazdashenas, Hardware Design and CAD for Processor-Based Logic
Emulation Systems, MASc thesis completed December 2006.
5. Ian Anderson, A CAD Tool for Design Space Exploration of Embedded CPU Cores for
FPGAs, MASc thesis completed January 2007.
6. Raymond Lee, DNLMS-Based Adaptive Filters for Echo Cancellation, MASc thesis
completed January 2007 (co-supervised with Dr. Esam Abdel-Raheem).

7. Jason Tong, Software Profiling for an FPGA-Based CPU Core, MASc thesis completed
February 2007.
8. Marwan Kanaan, A Low Cost Processor Based Logic Emulation System Using FPGAs,
MASc thesis completed August 2007.
9. Junsong Liao, FPGA Implementation of a Wireless Sensor Network, MASc thesis
completed December 2007.
10. Hongmei Zhong, Low Power Two-Channel PR QMF Bank using CSD Coefficients and
FPGA Implementation, MASc thesis completed August 2008.
11. Omar Al-Rayahi, A CAD Tool for Synthesizing Variants of Altera NIOS-II Soft Core
Processor, MASc thesis completed August 2008.
12. Thuan Le, Implementation and Evaluation of an NoC Architecture for FPGAs MASc
thesis completed January 2009.
13. Mike Brugge, Design and Evaluation of a Parameterizable NoC Router for FPGAs,
MASc thesis completed September 2009.
Visiting Research Scholars Supervised
• Linlin Zhang, PhD student at the Hubert Curien Lab, Jean Monnet University, St.
Etienne, France. Research topic: NoC architectures for implementation of multispectral
image processing architectures. March to September, 2008.
Visiting Research Positions Held
• Invited Professor at the Hubert Curien Lab, Jean Monnet University, St. Etienne,
France. Research topic: NoC Prototyping on FPGAs, July 16 to 31, 2009.
PUBLICATIONS :
Journal Papers(9)
Linlin Zhang, Virginie Fresse, Mohammed Khalid, Dominique Houzet and Anne-Claire
Legrand, Evaluation and Design Space Exploration of a Time-Division Multiplexed NoC on
FPGA for Multispectral Image Data Communication, EURASIP Journal on Embedded
Systems, Accepted for publication, November 17, 2009.
Anderson, Ian, D.; Khalid, Mohammed, A., SCBuild: A CAD Tool for Design Space
Exploration of Embedded CPU Cores for FPGAs, IET Computers and Digital Techniques,
3(1), 24-32, January 2009.
Tong, Jason, G; Khalid, Mohammed, A., Profiling Tools for FPGA-Based Embedded
Systems: Survey and Quantitative Comparison, Journal of Computers, Academy Publisher,
3(6), 1-14, June 2008.

Xu, Yonghong; Khalid, Mohammed, A Fast and Effective Timing-Driven Placement Tool
for FPGAs, Journal of Circuits,Systems and Computers, World Scientific, 17(4), 663-673,
August 2008.
Banovic, Kevin; Abdel-Raheem, Esam; Khalid, Mohammed, Computationally Efficient
Methods for Blind Decision Feedback Equalization of QAM Signals, AEU International
Journal of Electronics and Communication, 62(5), 474-485, May 2008.
Banovic, Kevin; Khalid, Mohammed; Abdel-Raheem, Esam, A Configurable Fractionally-
Spaced Blind Equalizer for QAM Demodulators, Digital Signal Processing, 17(6), 1071-
1088, November, 2007.
Lee, Raymond; Abdel-Raheem, Esam; Khalid, Mohammed A. S., Computationally-Efficient
DNLMS-Based Adaptive Algorithms for Echo Cancellation Application, Journal of
Communication, 1(7), 1-8, November 2006.
Banovic, Kevin; Abdel-Raheem, Esam; Khalid, Mohammed A. S., A Novel Radius-Adjusted
Approach for Blind Adaptive Equalization, IEEE Signal Processing Letters, 13(1), 37-40,
January 2006.
Khalid, Mohammed, A; Rose, Jonathan, A Novel and Efficient Routing Architecture for
Multi-FPGA Systems, IEEE Transactions on VLSI Systems, 8(1), 30-39, February 2000.
Patents(1)
M. A. S. Khalid and J. Rose, “Multi-logic Device Systems Having Partial Crossbar and
Direct Interconnection Architectures,” U.S. Patent #6604230, filed Feb. 9, 1999, issued
August 5, 2003.
Conference Papers(20)
Brugge, Mike; Khalid, Mohammed, Design and Evaluation of a Parameterizable NoC Router
for FPGAs, 18 th ACM/SIGDA International Symposium on FPGAs, FPGA 2010, Feb. 21-23,
2010, Monterey, California, Accepted for Presentation and Publication, Nov. 14, 2009.
Le, Thuan; Khalid, Mohammed, NoC Prototyping on FPGAs: A Case Study Using an Image
Processing Benchmark, Proc. of IEEE International Conference on Electro/Information
Technology, pp. 441-445, June 2009 .
Al Rayahi, Omar; Khalid, Mohammed, UWindsor Nios II: A Soft-Core Processor for Design
Space Exploration, Proceedings of IEEE International Conference on Electro/Information
Technology, pp. 451-457, June 2009.

Zhang, Linlin; Fresse, Virginie; Khalid, Mohammed; Houzet, Dominique, Evaluation of NoC
Dedicated to Multispectral Image Data Communication, Proceedings of IEEE International
Symposium on Signals Circuits and Systems, July 2009.
Zhang, Linlin; Fresse, Virginie; Legrand, Anne-Claire; Khalid, Mohammed, GALS Noc
Architectures on FPGA Dedicated to Multispectral Image Applications, Proceedings of
European Signal Processing Conference, 2009, In Press.
Kevin Banovic, Mohammed A. S. Khalid, and Esam Abdel-Raheem, FPGA Implementation
of Fractionally-Spaced Complex Blind Adaptive Equalizer, Proc. of IEEE Int. Symp. On
Signal processing and Information Tech. (ISSPIT), 2007.
Tong, Jason, G; Khalid, Mohammed, A.S., A Comparison of Profiling Tools for FPGA-
Based Embedded Systems, Proceedings of Canadian Conference on Electrical and computer
Engineering, 2007.
Yazdanshenas, Amir; Khalid, Mohammed, A New Scheduling Algorithm for Processor-
Based Logic Emulation Systems, Proceedings of Midwest Symposium on Circuits and
Systems, 2007.
Tong, Jason, G; Khalid, Mohammed, A.S., Profiling CAD Tools: A Proposed Classification,
International Conference on Microelectronics, 2007.
Anderson, Ian; Khalid, Mohammed, Design Space Exploration Using Parameterized Cores:
A Case Study, Proceedings of Canadian Conference on Electrical and computer Engineering,
2006.
Khalid, Mohammed, A. S.; Salitrennik, Viktor, Scalability Evaluation of a Hybrid Routing
Architecture for Multi FPGA systems, Proc. of International Conference on
Microelectronics, 2006.
Tong, Jason, G; Anderson, Ian, D.L., Khalid, Mohammed, A.S., Soft-core Processors for
Embedded Systems, Proc. of International Conference on Microelectronics, 2006.
Banovic, Kevin; Lee, Raymond; Abdel-Raheem; Khalid Mohammed, Computationally
Efficient Methods for Blind Adaptive Equalization, Proc of /Midwest Symposiumm on
Circuits and Systems, 2005.
Banovic, Kevin; Khalid, Mohammed; Abdel-Raheem, Esam, FPGA Based Rapid
Prototyping of Digital Signal Processing Systems, Proc. of Midwest Symposiumon Circuits
and Systems, 2005.

Banovic, Kevin; Abdel-Raheem, Esam; Khalid, Mohammed, Hybrid Methods for Blind
Adaptive Equalization; New Results and comparisons, proc. of 10 th IEEE Symposium on
Computers and Communications 2005.
Xu, Yonghong; Khalid, Mohammed, QPF: Efficient Quadratic Placement for FPGAs, Proc.
of 15 th International Conference on Field-Programmable Logic and Applications, 2005.
Khalid, Mohammed, A; Rose, Jonathan, Hardwired Clusters Partial Crossbar A hierarchical
routing architecture for multi FPGA systems, proceedings of sixth reconfigurable
architectures workshop, 597-695, 1999.
Khalid, Mohammed, A: Rose, Jonathan, A hybrid complete- graph partial crossbar routing
architectures for multi FPGA systems , Proceedings of the Sixth ACM International
Symposium on FPGAS, 45-54, 1998.
Khalid, Mohammed , A: Rose, Jonathan, Experimental Evaluation of Mesh and Partial
Crossbar Routing Architectures for Multi-FPGA Systems, proc of the sixth IFIP International
workshop on logic and architecture synthesis, 119-127, 1997.
Khalid, Mohammed A; Rose, Jonathan, the effect of fixed i/o pin positioning on the
routability and speed of fpgas, proc of third Canadian workshop on field programmable
devices, 92-104, 1995.
Cadence Internal Publications
[1] M. A. S. Khalid and V. Salitrennik, “On the Scalability of a Hybrid Routing
Architecture for Multi-FPGA Systems,” Cadence Technical Conference 2002
(Cadence Confidential, refereed publication).
[2] M. A. S. Khalid, “EBPART: A Multi-way Partitioning Tool for the Real World,”
Cadence Technical Conference, 2001 (Cadence Confidential, refereed publication).
[3] A. Kfir and M. A. S. Khalid, “Overview of Quickturn’s Emulation Technology, Part
I: Hardware Architecture and Design Compilation,” The Regatta, Cadence R & D
Newsletter, vol. 13, issue 1, March 2002 (Cadence Confidential, invited paper).
[4] A. Kfir and M. A. S. Khalid, “Overview of Quickturn’s Emulation Technology, Part
II: Emulation and Debug Environment,” The Regatta, Cadence R & D Newsletter,
vol. 13, issue 2, June 2002 (Cadence Confidential, invited paper).
RESEARCH GRANTS :
Title: Architecture and CAD for Field Programmable Chips and Systems
Principal Investigator: M. A. S. Khalid
Sponsor: University of Windsor (Start-up Grant)
Period: 2003-2008
Amount: CAD $30,000

Title: Architecture and CAD for Field Programmable Systems
Principal Investigator: M. A. S. Khalid
Sponsor: Natural Sciences and Engineering Research Council, Canada (NSERC)
Period: 2004 - 2009
Amount: CAD $100,000