Applications for Maskless E-Beam Lithography between ... - Sematech

Applications for Mask-less E-Beam Lithography 

between R&D and Manufacturing 

May 24, 2006 

Johannes Kretz 

Lithography Forum

Table of Contents 

E-Beam Lithography at Qimonda in Dresden 

Project Environment (Qimonda, Fraunhofer, VISTEC, IMS) 

Technical Results 

Future: ML2 

Qimonda · Johannes Kretz · QD P RDC EBEAM · May 24, 2006 · Page 2 Confidential





Future: ML2 


Motivation 

• Decision Mid 2004 for acquisition of a Variable Shaped Electron Beam 

Lithography in Dresden for shared use of Infineon and AMD 

• E-Beam Business Cases for support of R&D existing 

• E-Beam has great potential to facilitate optical litho, technology 

development and product engineering (mask cost, time to silicon) 

• Further, more sophisticated applications to a later date conceivable 

� Therefore participation of Infineon/Qimonda in European Programs 

for Mask less Lithograph (ML2) 

• Manufacturing Lithography Strategy of Qimonda unchanged 


Center of Competence E-Beam at QD P RDC 

• Own Group at Qimonda Dresden Research & Development Center 

(Head: Berndt Tropper) with additional resources from optical litho 

department, integration and etch (total: 9 persons) 

• Main objective: device learning

E-Beam Direct Write: Possible Applications 

Test Structures for technology learning and tool qualification 

Personalization 

ASIC Structuring 

Ground rule, cell concept and device learning 

Metal fix applications for 130nm and 90nm technologies 

Chip shuttle for macro verification 

Main focus Qimonda Main focus for logic companies 

Qimonda · Johannes Kretz · QD P RDC EBEAM · May 24, 2006 · Page 6 Confidential 

Increasing complexity

2005 

Timeline E-Beam Project 

4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 

Site Accept E-Beam 

Tool Delivery CNT 

Transfer Resist Process 

Final Acceptance 

2006 2007 

Support Device 1 layer 

Ready for Service Center for (external) customers 

Column Upgrade 

Support Device >1 layer 

45nm node capability 32nm node capability 


E-Beam Cluster in CNT Clean room 






Future: ML2 


Project Construct 

• Collaboration between Qimonda, CNT and external Partners 

• Resist benchmarking & process development @ IMS Chips 

• Timeframe: October 04 – Mid 08 

• National Funding (BMBF with Fraunhofer: SWITCH, SOHAR) 

• European Programs (FOREMOST) 

• Synergies to other (NGL) technologies 

– Mask applications 

– Nano-imprint (resist process) 

–EUV 

Qimonda · Johannes Kretz · QD P RDC EBEAM · May 24, 2006 · Page 10 Confidential 

S 

J 

DD

Mission or Fraunhofer CNT 

Center 

Nanoelectronic 

Technologies 

� a public-private partnership 

� the most efficient platform to develop 

� innovative processing solutions 

� for fast implementation in microelectronic devices 

� in the nanoelectronic era in Germany / Europe 

page 11

Research Challenge: … Fast Integration of Innovative 

Processes/Technologies and Equipment into Manufacturing 

Sequential 

Basic Research 

Integrated 

Basic 

Research 

Applied Research 

> 5 years 

Applied Research 

~ 3 years 

Development 

Product 

Technology 

CNT 

Development 

Product 

Technology 

Pilot 

Product 

Pilot 

Product 

Volume 

Ramp 

Volume 

Ramp 

• No Feedback 

• Independent 

• Technology driven 

• Fast Feedback 

from market 

• Interacting 

• Application driven 

page 12

European Nanotechnology Platform - Concept 

page 13

CNT Competence Areas 

for High-Performance Data Processing and Logic 

Materials 

Unit Process & 

Modules 

Areas Competence Reference Fab 

Equipment 

� New materials 

- storage cell 

- isolation concepts 

- conductor 

-transistor 

� Metrology and Analytics 

� Innovative Process Solutions 

� Enabling Patterning 

AMD Fab 36 

300mm 

IFX SC300 

300mm 

page 14

CNT Layout 

acces to 

CNT offices 

page 15





Future: ML2 


Resist Benchmarking at IMS Chips 

Extensive benchmarking of >30 positive and negative chemically amplified 

resists for direct write applications performed at IMS Chips 

• Multiple (small volume) samples supplied by all major resist vendors 

• Identification of p& n-CARs for 50nm DRAM node applications meeting basic 

resist requirements 

• Resist improvement clearly visible 

– Multiple learning cycles observed with several suppliers 

– Commercialization of most advanced samples 


P-CAR Benchmarking Result (dense 

pattern) 

Resist 

F 

Resist 

G 

Resist 

I 

Resist 

J 

Resist 

K 

50nm 55nm 60nm 70nm 100nm 


Status Exposure Results: Negative Resist 

50nm 

L/S 

70nm 

Dots 

iso dense (7-lines) dense (wide lines) 

(Pitch 180nm) 


Status Exposure Results: Positive Resist 

50nm 

L/S 

70nm 

CH 

iso dense (7-lines) dense (wide lines) 

(Pitch 180nm) 






Future: ML2 


IMS 

Nanofabrication 

PML2 Project Status 

IMS-Jena

PML2 

SEMATECH Litho Forum 

Vancouver, 22-May-2005 

E - beam evolution at Vistec 

Device engineering Fast prototyping Low volume production 

Litho ++ Litho+ Litho 

VB6 SB350DW PML2 R&D Project 

Gaussian Beam 

1 Gaussian pixel / flash Beam 

Shaped Shaped Beam Beam 

100 pixels / flash 

Multi Beam Array 

Multi Beam 

> 10,000 pixels / flash 

Increasing throughput 

Increasing complexity 

IMS 


23

PML2 



Multi e-beam, single column 

5keV 

100keV 

Single Electron source 

Condenser Optics 

Programmable Aperture Plate 

System (APS) 

200x Reduction Projection 

Electrostatic / Magnetic Optics 

Scanning Wafer Stage 

IMS 


24

PML2 



Throughput estimation 

Feature POC tool Beta tool 

Technology node 45 nm 45 nm 

Resist 36 µC/cm² 18 µC/cm² 

APS size 20x20 mm² 40x40 mm² 

aperture size/ number 5µm/ 0.3Mio 5µm/ 1.2Mio 

Blanking rate 

Current in column 

1 MHz 8 MHz 

50% beams on 0.45 µA 3.5 µA 

Total blur < 10 nm 13 nm 

v-stage 

Throughput 

0.025 m/s 0.2 m/s 

(12” wafer) 

0.1 WPH 1.3 WPH 

Results are based on: 

- 0.1s stage turn-around time, 120s overhead/ wafer 

- calculation of 3rd / 5th order electron optical aberrations 

- Monte Carlo simulation of all space charge effects (ray tracing) 

IMS 


Potential: 5 WPH 

Potential: 5 WPH 

sophisticated stage 

required (0.5…1m/s) 

25

Summary 

• VSB E-Beam Lithography established in Dresden 

• Patterning Ready for Internal and External Customers 

• Use for 300mm applications for future device and technology 

learning 

• Use of FhG network and National / European funding for 

process development 

• Process-learning for future mask-less litho tools 

• Strong potential for mask-less lithography in R&D 


Acknowledgement 

The Qimonda part of the work for this paper was partly supported by 

the EFRE fund of the European Community and by funding of the 

State Saxony of the Federal Republic of Germany (project number 

10746) and partly by the Federal Ministry of Education and Research 

of the Federal Republic of Germany (Project No 01M3167A). The 

authors are responsible for the content of the paper. 

Thanks to: 

• Center of Competence E-Beam, Frank-Michael Kamm 

• VISTEC Jena 

• Karl-Heinz Kliem, Elke Kilgus, Monika Böttcher, Uli Denker, Lutz Bettin, Bernd 

Brendel, Dirk Beyer, Hans-Joachim Döring 

• IMS Chips 

• Mathias Irmscher, Anatol Schwersenz, Holger Sailer 

• Fraunhofer CNT 

• Peter Kücher 


Team of E-Beam Competence Center 

• Christian Arndt (optical litho) 

• Maik Bootsmann (integration) 

• Kang-Hoon Choi (resist, track, metrology) 

• Christoph Hohle (resist screening and process) 

• Katja Keil, PhD 

• Johannes Kretz (project manager) 

• Tarek Lutz (device, alignment, proximity, tool) 

• M. Tesauro (etch) 

• Frank Thrum (Data Prep, KERF, fracturing) 


Thank you 

The World’s Leading 

Creative Memory Company 

Johannes Kretz

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