GaN devices

Unipolar Devices III:
GaN Electronic Devices
Tutorial in the frame of the TARGET network
Joachim Würfl
Ferdinand-Braun-Institut für
Höchstfrequenztechnik
Gustav-Kirchhoff-Straße 4
12489 Berlin
Participating institutions:
� Fraunhofer Institut für angewandte
Festkörperphysik, Freiburg, Germany
� Technical University Vienna, Austria
� AMS, Rome, Italy
...Translating ideas into innovation
IAF
Fraunhofer Institut
Angewandte
Festkörperphysik

Outline
GaN electronic devices –
An introduction
Device fabrication
Understanding device
operation
Design of high power
microwave GaN devices
Future GaN devices
Conclusions
� Comparison to other device families
� Applications
� Principles of operation
� Epitaxy
� Processing
� Performance limitations and how to get rid of it
� Reliability
� Field plate devices
� Power bar designs
� State of the art results
� Novel epitaxial approaches
� GaN HBTs

GaN electronic devices
– An introduction

Semiconductor microwave power devices
maximale maximale Leistung Leistung (Watt) (Watt)
Maximum power (W)
1000
100
10
1
SiC GaN HFET
SiC GaN HFET
Si LDMOS GaAs HBT, HEMT
Si LDMOS GaAs HBT, HEMT
0,1
0,1 1 10 100 1000
Frequency Frequenz (GHz) (GHz)
InP HBT, HEMT
InP HBT, HEMT
Device classes and frequency vs. maximum possible
microwave power

Comparison of semiconductor materials
Band Gap (eV)
Electron mobility
(cm²/Vs)
Electric breakdown field
(10 6 V/cm)
Saturation velocity
(10 7 cm/s)
Thermal conductivity
(W/Kcm)
Johnsons Figure of Merit
(~V Br ² x v sat ²)
Maximum estimated operation
temperature (°C)
Si
1.1
ind.
1500
0.3
1.0
1.5
1
200
GaAs
1.43
dir.
8500
0.4
2.0
0.46
7
300
4H-SiC
3.26
ind.
1000
2.0
2.0
4.9
180
500
6H SiC
3.0
ind.
500
2.4
2.0
4.9
260
500
GaN/
AlGaN
3.42
dir.
1250*
3.3
2.7
1.3
760
500
* 2DEG mobility up to 2000 cm²/Vs

Applications
Oscillator
1/f noise
Distortion
RF noise
High power amplifier
Low noise amplifier
Breakdown
Voltage
High speed communication Gate array
f max
Power
Handling
f T
P diss
ADC ASIC Air cooled LSI
g m
σVT
GaAs - HEMT
GaAs - HBT
Si - BJT
GaN - HEMT

GaN high power devices: Applications
Demands from system
applications
More demanding
requirements regarding:
� Linearity
� Output power
� Efficiency
� Heat sinking
� Total system noise factor
To be expected in future:
Realization in GaN technology
GaN devices for
„Enabling microwave components“
� High power microwave amplifier (HPA)
� Highly linear amplifiers
� Robust low noise amplifiers (LNA)
� Power switches
Civil applications
� Base stations for mobile communications
� Satellite communication
Military applications
� Phased array radar systems

Advantages of GaN-HFETs in power amplifiers
conventional technology GaN technology
T T
T
T
T T
T T
input T T
output input output
T
T T
T
Higher operation voltage leads to:
� Higher power densities
� Higher impedance level
� Higher linearity
� Less complex transformation and power combining networks
Less complex circuit design
� Small chip areas
� Higher reliability

III-Nitride hetero structures for
microwave power transistors
R.J.. Trew, MTT-S 2004
Bandgap-Engineering
� Realization of HEMTs
Spontaneous and
piezoelectric polarization
Advantages:
� Reduced Coulomb-
Scattering in 2DEG
� Higher mobility
� Higher carrier
concentration in 2DEG

High Electron Mobility Transistors (HEMT):
How does it work?
Source
AlGaAs
Gate
Drain
GaAs 2-DEG
spacer
AlGaAs GaAs
Distribution
of 2DEG carriers
Additional
features
Example: GaAs/AlGaAs HEMTs
� Electrons from AlGaAs drift to
AlGaAs/GaAs interface
� There: Formation of 2DEG
� Extremely high electron mobility
along interface
� 2DEG concentration controllable by
Gate electrode
Speciality: GaN/AlGaN HEMT
� Parameters controlling 2DEG
concentration:
-Doping of AlGaN barrier
-Spontaneous polarization
-Piezoelectric polarization

Spontaneous and piezoelectric polarization
Relaxed
Substrate
Compressive
strain
Substrate

Mechanism of spontaneous polarization
Charge distribution of
valence electrons (e/ų)
Ionic character of
Ga-N compound
+
Deviation from ideal
c/a ratio
Resulting
polarization
Spontaneous
polarization

c/a ratio
c/a-ratio and spontaneous polarization
Spont. polarization (C/m²)
� c/a ratio always smaller as in ideal case
� Spontaneous polarization increases in the order GaN, InN, AlGaN
� Relevant for high power GaN microwave transistors:
Difference between GaN and AlGaN

Principles of 2DEG formation in AlGaN/GaN structures
E F
Al x Ga 1-x N
P piezo
∆P 0
2DEG
GaN
∇
∆P 0 = P 0 (GaN)- P 0 (AlGaN)
differential spontaneous polarization at the
junction
P piezo
Gauss theorem: -ρ total = . (P piezo + P 0 )
positive polarization-induced charge ρtotal to compensate ρtotal tensile strain in the
AlGaN lattice-matched to GaN
2DEG accumulation
polarization doping no intentional doping necessary !

2DEG formation in AlGaN/GaN HFET-structures
GaN
AlGaN
GaN
Saphir
P SP
P SP
P SP
P PE
-
+
ρ+
N
Ga
O
Al
E F
[0001]
E C
2DEG
[0001]
Ga-face polarity N-face polarity
P SP
P SP
P SP
P PE
+
-
ρ+
Ga
N
O
Al
E F
E C
2DEG

Device fabrication

Epitaxy on non-lattice matched substrates (1)
Possible substrate solutions for GaN FETs:
Lattice mismatch (%)
Availability / Price (2“, $)
Thermal Conductivity
(W/cmK)
Sapphire
13
100
0.3
n-type
SiC
3.1
500
4
s.i.
SiC
3.1
3000
4
GaN bulk
0
not
available
1.3
IAF
Fraunhofer Institut
Angewandte
Festkörperphysik
Si
17
100
1.48

Epitaxy on non-lattice matched substrates (2)
Analysis of dislocations and epitaxial quality
dislocations � TEM image
Non-lattice matched substrate (sapphire)
IAF
Fraunhofer Institut
Angewandte
Festkörperphysik
� PEC: photo enhanced etching
� Dislocations are etched slower than
defect free areas
� Dislocation rich area up to a thickness
of 500 nm

Epitaxy on non-lattice matched substrates (3)
Metal Organic Chemical
Vapour Deposition (MOCVD)
Both types deliver similar epitaxial quality
MOCVD:
� Faster growth
� Mass production
Molecular Beam Epitaxy
(MBE)
MBE:
� More options for polarity of
interfaces
IAF
Fraunhofer Institut
Angewandte
Festkörperphysik

Impact of epitaxy on polar heterodevices
� Material composition x:
Increasing n s while
preserving mobility µ
� No/little doping required
Source
Al x Ga 1-x N
Al x Ga 1-x N
Gate
Drain
Si-doping
GaN 2-DEG
Mobility (cm 2 / Vs)
Sheet Carrier Concentration (1E13 cm -2 )
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1600
1400
1200
1000
800
600
400
200
0
25 30
Al content (%)
35
HEMT on Sapphire
Al=25%
Al=30%
Al=35%
0.4 0.6 0.8 1.0 1.2 1.4 1.6
Sheet Carrier Concentration (1E13 cm -2 )
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Fraunhofer Institut
Angewandte
Festkörperphysik

Technology of AlGaN/GaN HFETs (1)
S D
S D
Ti-reflector layer on transparent wafer
� Structuring of reflector layer
� Definition of alignment marks
Deposition of Source-/Drain contacts
(Ti/Al/Ti/Au/WSiN)
� Removal of reflector layer
� Annealing at 850°C in N 2
On chip isolation:
� Dry etching of active layers
� RIE-process, BCl 3 :Cl 2 :Ar

Technology of AlGaN/GaN HFETs (2)
Dielectric
passivation
S G D
S G D
MIM-capacitor
Resistor
Gate-Technology (Pt-Au):
� Electron beam lithography:
Gate length 0.3 µm
Passivation and dry etching of contact
windows
1 st interconnect (Ti-Pt-Au, 500nm)
Passive components:
� MIM-capacitor
� NiCr-resistor
� Electroplated Au air bridge
(6 µm)

Technology of Power Cells
WSiN x -Diffusionbarrier
encapsulats ohmic contact
Power cell with common Source Design
(connected by airbridge)

Backend Processing
Wafer thinning
Via etching and
metalization
Chip dicing

Backend Processing (1)
Thinning of SiC-Substrate to 100 µm
� Lapping with different diamond
pastes
� Polishing
Via technology
� Dry chemical via process
� Laser micro-machining
Via metallization
� Plating base: Ti/Au 30/1000 nm
Electroplating

Backend Processing (2)
Definition of dicing streets
� Lithography and etching
� Laser micro-machining
Wafer dicing
� Sawing and cleaving
Chip delivery:
� Diced chips on dicing frame

L-Band Powerbars based on laser-vias
� Full wafer thickness
(Wafer not thinned)
� Via-diameter 90 µm
� Technological specialty
Through-Vias

Chip Dicing
Laser scribe lines
Laser induced removal of Au in
dicing streets
(focus on backside)
Dicing street
Dicing street after wafer sawing
and cleaning
(focus on front side)

GaN-HFETs:
Power devices on transparent wafers

16x250 µm power cells
Device data at 2 GHz:
� P max = 12.3 W
� PAE = 59%
� Linear gain: 19 dB
� Gain at P max : 16 dB
dB MSG
Po(dBm); G(dB); PAE
(%)
40
30
20
10
0
60
50
40
30
20
10
0
0,1 1 10 100
Pout
G
PAE
ID
f (GHz)
Pmax=12.3W
-10 0 10 20 30
Pin (dBm)
0,8
0,7
0,6
0,5
0,4
0,3
0,2
0,1
0
ID (A)

Understanding device operation

I D (A)
DC-characteristics
Device:
GaN-HFET 2x50 µm,
L g = 0.3 µm
0.12
0.1
0.08
0.06
0.04
0.02
0
I D (A)
0.12
0.1
0.08
0.06
0.04
0.02
0 5 10 15 20 25 30
V DS (V)
0
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2
V GS (V)
Typical GaN-HFET I/Vcharacteristics:
� I DSS_max = 1.1 A/mm
� g m = 220 mS/mm
� Slight hysteresis in output
characteristics

I (mA) ds
Compression of drain current: Gate lag conditions
140
120
100
80
60
40
20
0
0 5 10 15 20 25 30
V (V)
ds V = 0.0 V, V = 0.0 V
gs ds
V = -3.0 V, V = 0.0 V
gs ds
I (mA)
ds 140
120
100
80
60
40
20
0
0 5 10 15 20 25 30
V (V) ds
V = 0.0 V, V = 0.0 V
gs ds
V = -3.0 V, V = 0.0 V
gs ds
Biasing point for pulse measurements: V GS = -3 V, (pinch off); V DS = 0 V
Before passivation:
� Drain current reduction
After passivation
� Slight recovery of drain current

Reduction of power dispersion (3)
5. Field plate structures
� Suppressing surface/interface traps
� Field plate flattens electric field distribution
G
� High electric field
� Trapped electrons
form virtual gate
AlGaN
+ + + + + + + + + + + + + + + + + + +
GaN
Without field plate
D
� Electric field
maximum reduced
� Modulation of
carriers due to F.P
AlGaN
+ + + + + + + + + + + + + + + + + +
GaN
With field plate
D

I (mA)
ds Compression of drain current: Drain lag conditions
140
120
100
80
60
40
20
0
0 5 10 15 20 25 30
V (V) ds
V gs = -3.0 V, V ds = 0.0 V
V gs = -3.0 V, V ds = 26.0 V
I (mA) ds
140
120
100
80
60
40
20
V gs = -3.0 V, V ds = 0.0 V
V gs = -3.0 V, V ds = 26.0 V
0
0 5 10 15 20 25 30
V (V)
ds Biasing point for pulse measurements: V GS = -3 V, (pinch off); V DS = 26 V
Before passivation:
� Very pronounced drain lag
After passivation:
� Strong recovery of drain lag

Maximum obtainable output power
I DS
V P
g m
I max
V GS
V K
R opt = (V DSmax –V K ) / I max
V GS =0
V GS =V P
P max = 1/2 · (V DSmax –V K ) · I max
V DD
V DSmax
V DS
Ohmic Saturation Breakdown
∆I
Optimum output impedance for
max. output amplitude given by:
� Voltage knee V K
� Breakdown onset
� Saturation current

If current compression:
Strong reduction of maximum obtainable output power
I DS
V P
g m
Therefore:
I max
V GS
V K
Current compression has to
reduced by any means
V DSmax
V DS
Ohmic Saturation Breakdown
Not accessible
∆I
Maximum power swing reduced by:
� Surface traps
� Buffer layer traps

I ds (mA)
Dependency of output power density
on current compression
120
100
80
60
40
20
0
0
0
0 5 10 15 20 25 30
0 5 10 15 20 25 30
0 5 10 15 20 25 30
V ds (V)
Static
Dynamic
0
0
0
0
0
0
V ds (V)
Static
Dynamic
P out = 5.2 W/mm P out = 3.9 W/mm P out = 1.8 W/mm
� Transistor geometry: 2x50 µm
� Frequency: 2 GHz
0
0
0
0
0
0
V ds (V)
RF-power performance
Static
Dynamic

Physical background of current compression
Main cause of current compression
� Electron/hole traps due to
surface/interface states & material
defects
Location of traps
� AlGaN surface / interface (I)
� AlGaN layer (II)
� GaN buffer (III)
� Interface substrate / buffer (IV)
Causes of trap formation
� Impurity addition during growth
� Threading dislocation due to lattice
mismatch & defects
� Excess of carrier gasses & uncontrolled
growth parameters
� Increasing Al mole fraction and AlGaN
relaxation
� Surface exposure & damage during
device processing
S
G
D
(I) (I)
AlGaN (II)
GaN (III)
IV
Substrate

Current compression:
An analogue from every days world
� A parallelism could be made for a choked tap, that
cannot modulate the flowing liquid (the Drain current)
because of a throttling (the virtual Gate due to the
charged traps) in the tube (the channel) before
and/or after it.

Gate lag
I ds (mA)
Experimental observation Explanation
70
60
50
40
30
20
10
0
0 5 10 15 20
V ds (V)
Bias points: V ds = 0.0 V; V gs = 0.0 V
V ds = 0.0 V; V gs = -7.0 V
Open channel: V ds = 0.0 V ; V gs = 0.0 V
S D
G
AlGaN
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
GaN
Depleted channel: V ds = 0.0 V ; V gs = -7.0 V
� Pulsing the gate: ē are trapped in surface
states, negative charging.
S G
D
AlGaN
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
GaN
Traps

I ds (mA)
Drain lag
Experimental observation Explanation
70
60
50
40
30
20
10
0
0 5 10 15 20
V ds (V)
Bias points: V ds = 0.0 V; V gs = -7.0 V
V ds = 20.0 V; V gs = -7.0 V
Depleted channel: V ds = 0.0 V ; V gs = -7.0 V
S D
G
AlGaN
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
GaN
More Depleted channel:
V ds = 20.0 V ; V gs = -7.0 V
Traps
Pulsing the drain: ē are also trapped in
buffer traps due to high V ds.
S G
D
AlGaN
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Traps

Reduction of power dispersion (1)
1. Surface passivation
2. n- type GaN cap
Mechanism:
� Neutralizing surface / interface traps by n + -donors (n-doped GaN
cap) & shallow donors (SiN x )
� Therefore: No virtual gate formation
G
AlGaN
Trapped electrons
form virtual gate
+ + + + + + + + + + + + + + + + + + +
GaN
D
G
AlGaN
Removal of virtual
gate due to SiN x
+ + + + + + + + + + + + + + + + + + +
GaN
D
AlGaN
G
Removal of virtual gate
due to n-doped cap
+ + + + + + + + + + + + + + + + + + +
GaN
D

Reduction of power dispersion (2)
3. Recessed gate process
4. Light stimulation
� Suppression of surface/interface traps
� No effective charging of surface states and therefore removal of virtual gate
� De-trapping of carriers
G
GaN
Trapped electrons
form virtual gate
AlGaN
+ + + + + + + + + + + + + + + + + + +
D
No trapping of
electrons leaking
from the gate
D
G
AlGaN
+ + + + + + + + + + + + + + + + + + +
GaN
Ec
Ev
Traps
Electron
hole
hν

Design and realization of
high power microwave GaN devices

Field plates: Output power increase
Psat [W/mm]
8,0
7,5
7,0
6,5
6,0
5,5
5,0
4,5
4,0
3,5
3,0
A2: G-D=2µm
A6: G-D=6µm
A6L: G-D=6µm, FP=1µm
A6M: G-D=6µm, FP=2µm
A6N: G-D=6µm, FP=3µm
24 26 30 36 42 48 54 60
Vds [V]
GaN 707-4 (Wg=2*125µm)
Power density vs. bias voltage
� Systematically higher output power level
� Power density can be increased by 100%
S
G
D
FP
Field plate
Field plate connected to
gate at gate pad

Field plates: Trade-offs
MSG [dB]
24
22
20
18
16
14
12
10
24 26 30 36 42
Vds [V]
A2: G-D=2µm
A6: G-D=6µm
A6L: G-D=6µm, FP=1µm
A6M: G-D=6µm, FP=2µm
A6N: G-D=6µm, FP=3µm
GaN 707-4 (Wg=2*125µm)
Maximum stable gain (MSG) vs. bias voltage
� Reduced gain (MSG) due
to field plate. Increase of
- Base/collector
capacitance
- Effective gate length
� Trade-off between
maximum achievable
power level and speed

High power transistors: Power bar structures
S
G
S
S
G
S
S
G
S
S
G
S
S
G
S
D
S
S
D
S
S
D
S
S
D
S
S
D
S S
� Bonding areas according to device current
and mounting requirements
� Sub-cells separated on chip
- Avoid odd mode oscillations
- On chip measurability
� Inter sub-cell connection by power bar
bonding

Thermal management
Flip chip technology:
� Flip chip bonding of GaN HEMT discrete devices on AlN substrates could
be used to improve devices thermal management. It can be be also used
as an alternative solution to via holes for MMIC ground connection.
AlN Carrier Substrate GaN Chip
Au/Sn
bumps

Breakdown in GaN HEMTs
+
S
EF
G
+
breakdowns
Reduction of break down:
D
AlGaN
GaN
� Highly resistive buffer
� Dislocation-free surface
� field plate (eliminates impact
ionisation in the channel)
S-D breakdown
� Complex avalanche-injection process
- Highly resistive buffer layer needed !
G-D breakdown
� Through the surface
� Impact ionisation in the channel
� Schottky barrier breakdown
Literature
� Vaschenko et.al.; Microelectron. Reliab. 37
(1997), 1137-1141
� Kuzmik et.al.; Appl. Phys. Letters 83 (2003),
4655-4657)
� Nakano et.al; phys. stat. sol. (c) 0 (2003)
2335
� Dayakonova et.al; Appl. Phys. Lett. 72 (1998)
2562

Pout (dBm)
GaN-Amplifier Module
45
40
35
30
25
20
22.4 W
Pout
PAE
Gain
28V D , 1A , 1.87GHz
N0713-1 5x8X250 _16R10_4S3
0 5 10 15 20 25 30 35 0
Pin (dBm)
Single stage amplifier
� In- and output matching
� 10 mm Gate width
� 43,5dBm (22.4 W) @ 1.87GHz
50
40
30
20
10
PAE (%), Gain (dB)

Power bar devices: Performance
Gain (dB) /Output Power (dBm)
45
40
35
30
25
20
15
Gain
Output Power
PAE
10
0
0 5 10 15 20 25 30 35
Input Power (dBm)
Device in test fixture
� P max = 32 W
� PAE = 42%
� Linear gain: 17 dB
� Gain at P max : 15 dB
45
40
35
30
25
20
15
10
5
PAE (%)
2 GHz test fixture

Bench marking of GaN power devices
P (W) bzw. P/WG (W/mm)
1000
100
10
1
0,1
NEC
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DC
FBH IAF
TRW
Frequenz (GHz)
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Future GaN devices

New structures for high-power performance
Energy gap at 300 K (eV)
7
6
5
4
3
2
AlN
AlGaN
GaN
In 0.17 Al 0.83 N
InAlN
InGaN
InN
3,1 3,2 3,3 3,4 3,5 3,6
Lattice constant, at 300 K (Angstrom)
Therefore:
Goals:
� Better carrier confinement in 2DEG
� Increase 2 DEG concentration
Conventional approach: Increase of
Al mole-fraction in AlGaN
� Increase of strain in AlGaN
� Increase of spontaneous polarization
� Increase of 2DEG density
Problem:
InAlN/(In)GaN QW new approach
� Relaxation of the AlGaN layer

New structures for high-power performance
In x Al 1-x N
(lattice
matched,
x= 0.17, or
tensile
strain)
Al0.2Ga0.8N/GaN
(conventional)
E F
P piezo
DP 0
2DEG
PpiezoDP0 GaN
In y Ga 1-y N
(lattice matched
(y= 0) or
compressive
strain)
∆ P0 (Ccm -2 ) Ppiezo (Ccm -2 ) ntotal (cm -2 ) ∆EC (eV)
-1.04 x 10 -6
In0.17Al0.83N/GaN -4.37 x 10 -6
In0.17Al0.83N/ In0.10Ga0.90N -4.34 x 10 -6
-6.9 x 10 -7
1.08 x 10 13
0 2.73 x 10 13
1.6 x 10 -6
3.71 x 10 13
0.3 (0.75∆Eg)
0.68
>0.68

New structures for high-power performance
Advantages
� Very high 2 DEG density expected (� high power HEMTs), controlled
strain
Disadvantages
� InAlN growth is difficult
Literature
� J. Kuzmik; IEEE El.Dev.Letters 22, 510-512 (2001)
� M. Higashiwaki; Jap. J. Applied Physics 43, L768-770 (2004)

MOS GaN HEMT
Advantages of MOS/MIS-Structures:
� Low gate leakage
� reduced current collapse
� lower noise
� positive sweep on gate (higher power, normally off device possible)
Requirements on dielectric layers:
� High electrical strength, no bulk traps
� Good insulation,
� Low interface state density
Literature:
� Khan et.al.; IEEE Trans. On Microw. Th. and Tech.51 (2003) 624-633.
� Khan et.al.; phys. stat. sol. (a) 200 (2003) 155.
� Adivarahan et.al.; IEEE Electron Dev. Lett. 24 (2003) 541

GaN-HBT: Main advantages
Property
Eg (eV)
v sat (cm/s)
E crit (MV/cm)
χ (W/cmK)
GaN
3.4
3x10 7
3.3
1.3
4H-SiC
3.3
2x10 7
2.0
4.9
GaAs
1.4
2x10 7
GaN wide-band-gap-material (Eg) as collector layer:
� High RF-power
� High operating voltage
� Operation at high temperatures (300 - 500°C)
Advantages of GaN:
� Highest saturation velocity v sat gives lowest transit time
0.4
0.5
� Highest breakdown field E crit allows highest bias voltage
� Good thermal conductivity (SiC better!)
Si
1.1
0.6x10 7
0.3
1.5
GaN HBTs:
Extremely high power
at high frequency

GaN-HBT: Comparison with GaAs-HBT [2,3]
Structure:
GaN-HBT
50 nm base
100 nm collector
GaN-HBT
200 nm base
7000 nm collector
GaAs-HBT
100 nm base
3000 nm collector
Breakdown
voltage (V)
15
1000
70
Current gain
cut-off
frequency f T
200
6
20
Power gain
cut-off
frequency f max
200
300
~100
Superior RF-power performance expected for GaN-HBTs!

GaN-HBT: Main world-wide activities
Research
group:
J. Pankove
Astralux Inc.,
USA [4,5]
U.K. Mishra,
et.al., UCSB
USA [2,6,7,8]
T. Makimoto,
et.al., NTT
Japan [9,10]
S. Estrada,
et.al., UCSB
USA [11]
Structure:
emtter/base/
collector
n-GaN/p-SiC/
n-SiC
n-AlGaN/p-GaN/
n-GaN
n-GaN/p-InGaN/
n-GaN
n-AlGaAs/
p-GaAs/n-GaN
Current gain at
room or higher
temperature
β~10000000 (RT)
β~100 (535°C)
β ~ 3 - 35 (RT)
β~ 20 - 2000 (RT)
β~ 0.2 - 0.5 (RT)
Remarks,
drawbacks
Differential current gain
due to high leakage
SiC-purity issue
first GaN-HBT in 1998
base doping issue
processing issues
double hetorojunction
base regrowth optimized
4 W DC-power obtained
GaAs-GaN-hetero-
interface by wafer fusion
(1 h at 750°C and 2 Mpa)

GaN-HBT: Technological challenges (a few…)
Highly p-doped and high quality p-GaN base not yet available:
� shallowest acceptor Mg is a deep acceptor (E A -E V ~110-200 meV)
� low activation at RT: N A ~5x10 19 cm -3 gives p~8x10 17 cm -3 (2 % activation!)
� high base sheet resistance: 100 kΩ/ for 100 nm base (200 Ω/ for GaAs)
� Mg-dopant memory effect during growth and out-diffusion of Mg into emitter
� high density of point defects in the base leads to low minority lifetime
and thus low current gain
Lack of GaN-substrates: heteroepitaxy on sapphire or SiC
� large lattice mismatch leads to high dislocation density in grown layers
� threading dislocations identified as source of collector-emitter leakage current
� GaN templates or LEO/ELO growth as possible improvements
GaN-emitter definition:
� Cl 2 RIE is primarily physical etching causing damage to extrinsic base
� high contact resistance on RIE etched base leads to high offset voltage (~10 V)
� selective extrinsic base regrowth as possible solution
or selective area emitter growth using AlN or SiN mask

AlGaN/GaN-HBT: Towards an RF device…
Development of the UCSB AlGaN/GaN-HBT device:
� Offset voltage reduced from >10 V to 1-5 V by using regrown extrinsic base
� Current gain increased from 3 to 10 due to improvement in dislocation density
(LEO substrate)
� Main issues: current leakage due to threading dislocations and low minority
carrier lifetime in the base
� Current gain cut-off frequency of 2 GHz reported

GaN/InGaN-DHBT: Better epi gives a better device…
Improvements of the NTT GaN/InGaN-HBT device:
� p-InGaN: 10% base dopant activation (N A ~2x10 19 cm -3 gives p~2x10 18 cm -3 )
� Offset voltage reduced from 5 V to 1 V due to improved base contacts (optimized
regrown extrinsic base): high current gain > 2000 obtained
� Output characteristics indicates electron blocking "spike" at base-collector junction
� Current limitation due to Kirk-effect at 7 kA/cm 2 (70 kA/cm 2 for GaAs-HBT [13])
� 50x30 µm 2 DHBT operating up to 50 V gives 4 W of DC-power corresponding to
DC power density of 270 kW/cm 2 (375 kW/cm 2 for GaAs-HBT [13])

GaN/SiC-HBT: Pankove´s approach
Cross section of the GaN/SiC transistor Common-base I-V-characteristics
Pankove´s (Astralux, Univ. of Colorado, USA) GaN/SiC-HBT device:
� LPE grown SiC base and MBE grown GaN emitter
� 100,000 of differential current gain obtained from common base characteristics
� Poor RIE etch selectivity GaN-to-SiC causing high leakage current at V CB > 10V
� Improvement with selectively grown GaN emitter:
current gain of 1,000,000 at RT and 100 at 535°C reported
� Not reproduced due to parasitic deep level defects in p-type 6H-SiC
� Work in progress using purer 4H-SiC (β~15@ RT) but lack of production quantities

AlGaAs/GaAs/GaN-HBT: Fused-wafer approach
Development of the UCSB fused-HBT device:
� Joining the best of two worlds: high quality and highly doped p-GaAs base with
high breakdown voltage of n-GaN collector
� AlGaAs/GaAs fused with GaN: 1 h at 750°C in N 2 under 2 MPa pressure giving
mechanically stable junction with good structural quality (

GaN-HBT: Perspectives
Show-stoppers: a number of outstanding material and processing issues
� Base layer: large acceptor ionization energies and low hole mobilities
� Growth of GaN layers: still a high defect density
� Base ohmic contacts: high resistance causes high offset voltage
� Emitter definition: etching damage or base regrowth to be further optimized
Possible solutions:
� Improved substrates for GaN growth like HVPE-grown GaN templates
� Further optimization of base layer regrowth
� Direct wafer bonding (wafer-fusion): structural improvement
References GaN-HBTs
[1] S.J. Pearton et.al., Mater. Sci. Eng. 250 (2000) 1-158
[2] L.S. McCarthy et.al., Trans. Electron Dev. 48 (2001) 543-551
[3] P. Kurpas et.al., Technical Digest IEDM 2002 (2002) 682-684
[4] http://www.mdatechnology.net/ (Tech Search, Spinoff Technology: #321)
[5] L.S. McCarthy et.al., Electron Dev. Lett. 20 (1999) 277-279
[6] H. Xing et.al., J. Phys.: Condens. Matter. 13 (2001) 7139-7157
[7] T. Makimoto et.al., Proc. Int. Workshop on Nitride Semic. 2000 (2000) 969-972
[8] http://www2.electrochem.org/cgi-bin/ abs?mtg=206&abs=1255&type=pdf
[9] S. Estrada et.al., Appl. Phys. Lett. 82 (2003) 820-822

Conclusions

Conclusions (1)
Material and
manufacturing
Device results
Material continuously improves
� High mobility structures
� Reduced power compression
� High voltage capability
� GaN on Si substrates
Established device processes available
� Special process modules for suppression of power
dispersion
� Via and backside technology
� Developments towards higher bias voltages
Transition to larger wafers 2“ � 3“, 4“
Promising results from S- to Q-Band
� Power cells and power bars up to 250 W (L-Band)
� GaN MMICs
� Low noise applications

Conclusions (2)
Present Challenges
Future perspectives
Still a problem: Power dispersion
� Adapted technological solutions
High voltage operation
Reliability issues unsolved
� Required: >10 6 h at 125 °C and 48 V
Further optimization of conventional approaches
New technologies on the horizon:
� GaN-MOS devices
� GaN HBTs