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410<br />

AM, FM, and Digital Modulated Systems Chap. 5<br />

5–59 Assume that 4,800-bits random data are sent over a bandpass channel by BPSK signaling. Find<br />

the transmission bandwidth B T such that the spectral envelope is down at least 35 dB outside this<br />

band.<br />

5–60 As indicated in Fig. 5–22a, a BPSK signal can be demodulated by using a coherent detector<br />

wherein the carrier reference is provided by a Costas loop for the case of h = 1.0. Alternatively,<br />

the carrier reference can be provided by a squaring loop that uses a × 2 frequency multiplier.<br />

A block diagram for a squaring loop is shown in Fig. P5–60.<br />

(a) Using the squaring loop, draw an overall block diagram for a BPSK receiver.<br />

(b) By using mathematics to represent the waveforms, show how the squaring loop recovers the<br />

carrier reference.<br />

(c) Demonstrate that the squaring loop does or does not have a 180 phase ambiguity problem.<br />

BPSK<br />

signal<br />

input<br />

Frequency<br />

multiplier<br />

× 2<br />

Phase-locked loop<br />

Loop<br />

filter<br />

VCO<br />

Frequency<br />

divider<br />

2<br />

Carrier<br />

reference output<br />

Figure P5–60<br />

5–61 A binary data signal is differentially encoded and modulates a PM transmitter to produce a<br />

differentially encoded phase-shift-keyed signal (DPSK). The peak-to-peak phase deviation is<br />

180 and f c is harmonically related to the bit rate R.<br />

(a) Draw a block diagram for the transmitter, including the differential encoder.<br />

(b) Show typical waveforms at various points on the block diagram if the input data sequence is<br />

01011000101.<br />

(c) Assume that the receiver consists of a superheterodyne circuit. The detector that is used is<br />

shown in Fig. P5-61, where T = 1R. If the DPSK IF signal v 1 (t) has a peak value of A c volts,<br />

determine the appropriate value for the threshold voltage setting V T .<br />

From IF<br />

v 1 (t)<br />

v 3 (t)<br />

Integrator<br />

(n + 1) T<br />

( ) dt<br />

nT<br />

<br />

Unipolar<br />

Threshold device<br />

binary<br />

output<br />

v<br />

v 4 (t) Sample v 5 (t) 6<br />

v 6 (t)<br />

& hold<br />

t=nT<br />

V T v 5<br />

One-bit<br />

delay, T<br />

v 2 (t)<br />

Matched filter<br />

Figure P5–61

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