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Sec. 4–14 Phase-Locked Loops and Frequency Synthesizers 285
where K m is the gain of the multiplier circuit. The sum frequency term does not pass through
the LPF, so the LPF output is
where
v 2 (t) = K d [sin u e (t)] * f(t)
u e (t) ! u i (t) - u 0 (t)
K d = K mA i A 0
2
(4–96)
(4–97)
(4–98)
and f(t) is the impulse response of the LPF. u e (t) is called the phase error; K d is the equivalent
PD constant, which, for the multiplier-type PD, depends on the levels of the input signal A i
and the level of the VCO signal A 0 .
The overall equation describing the operation of the PLL may be obtained by taking the
derivative of Eqs. (4–94) and (4–97) and combining the result by the use of Eq. (4–96). The
resulting nonlinear equation that describes the PLL becomes
du e (t)
dt
= du i(t)
dt
t
- K d K v [sin u e (l)]f(t - l) dl
L
0
(4–99)
where u e (t) is the unknown and u i (t) is the forcing function.
In general, this PLL equation is difficult to solve. However, it may be reduced to a linear
equation if the gain K d is large, so that the loop is locked and the error u e (t) is small. In this
case, sin u e (t) ≈ u e (t), and the resulting linear equation is
du e (t)
dt
= du i(t)
dt
(4–100)
A block diagram based on this linear equation is shown in Fig. 4–22. In this linear PLL model
(Fig. 4–22), the phase of the input signal and the phase of the VCO output signal are used
instead of the actual signals themselves (Fig. 4–21). The closed-loop transfer function
Θ 0 (f)Θ i (f) is
H(f) = ® 0(f)
® i (f)
=
- K d K v u e (t) * f(t)
K d K v F(f)
j2pf + K d K v F(f)
(4–101)
¨i(t)
¨e(t)
LPF
F 1 (f)=F(f)
v 2 (t)
K d
K v
¨0(t)
VCO
F 2 (f)=–––
j2∏f
¨0(t)
Figure 4–22
Linear model of the analog PLL.