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Sec. 4–14 Phase-Locked Loops and Frequency Synthesizers 283
low-pass filter (LPF) is a narrowband filter. In this operating mode, the frequency of the VCO
will become that of one of the line components of the input signal spectrum, so that, in effect,
the VCO output signal is a periodic signal with a frequency equal to the average frequency of
this input signal component. Once the VCO has acquired the frequency component, the frequency
of the VCO will track the input signal component if it changes slightly in frequency.
In another mode of operation, the bandwidth of the LPF is wider so that the VCO can track
the instantaneous frequency of the whole input signal. When the PLL tracks the input signal
in either of these ways, the PLL is said to be “locked.”
If the applied signal has an initial frequency of f 0 , the PLL will acquire a lock and the
VCO will track the input signal frequency over some range, provided that the input frequency
changes slowly. However, the loop will remain locked only over some finite range of
frequency shift. This range is called the hold-in (or lock) range. The hold-in range depends
on the overall DC gain of the loop, which includes the DC gain of the LPF. On the other
hand, if the applied signal has an initial frequency different from f 0 , the loop may not acquire
lock even though the input frequency is within the hold-in range. The frequency range over
which the applied input will cause the loop to lock is called the pull-in (or capture) range.
This range is determined primarily by the loop filter characteristics, and it is never greater
than the hold-in range. (See Fig. 4–23.) Another important PLL specification is the
maximum locked sweep rate, which is defined as the maximum rate of change of the input
frequency for which the loop will remain locked. If the input frequency changes faster than
this rate, the loop will drop out of lock.
If the PLL is built using analog circuits, it is said to be an analog phase-locked loop
(APLL). Conversely, if digital circuits and signals are used, the PLL is said to be a digital
phase-locked loop (DPLL). For example, the phase detection (PD) characteristic depends on
the exact implementation used. Some PD characteristics are shown in Fig. 4–20. The sinusoidal
characteristic is obtained if an (analog circuit) multiplier is used and the periodic
signals are sinusoids. The multiplier may be implemented by using a double-balanced mixer.
The triangle and sawtooth PD characteristics are obtained by using digital circuits. In addition
to using digital VCO and PD circuits, the DPLL may incorporate a digital loop filter and
signal-processing techniques that use microprocessors. Gupta [1975] published a fine tutorial
paper on analog phase-locked loops in the IEEE Proceedings, and Lindsey and Chie [1981]
followed with a survey paper on digital PLL techniques. In addition, there are excellent books
available [Blanchard, 1976; Gardner, 1979; Best, 1999].
The PLL may be studied by examining the APLL, as shown in Fig. 4–21. In this figure,
a multiplier (sinusoidal PD characteristic) is used. Assume that the input signal is
v in (t) = A i sin[v 0 t + u i (t)]
(4–92)
and that the VCO output signal is
where
v 0 (t) = A 0 cos[v 0 t + u 0 (t)]
t
u 0 (t) = K v v 2 (t) dt
L
-q
(4–93)
(4–94)