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Baseband Pulse and Digital Signaling Chap. 3
Synchronous and Asynchronous Lines
For bit sync, data transmission systems are designed to operate with either synchronous or
asynchronous serial data lines. In a synchronous system, each device is designed so that its
internal clock is relatively stable for a long period of time, and the device clock is synchronized
to a system master clock. Each bit of data is clocked in synchronism with the master
clock. The synchronizing signal may be provided by a separate clocking line or may be
embedded in the data signal (e.g., by the use of Manchester line codes). In addition,
synchronous transmission requires a higher level of synchronization to allow the receiver to
determine the beginning and ending of blocks of data. This is achieved by the use of frame
sync as discussed previously.
In asynchronous systems, the timing is precise only for the bits within each character (or
word). This is also called start–stop signaling, because each character consists of a “start bit”
that starts the receiver clock and concludes with one or two “stop bits” that terminate the clocking.
Usually, two stop bits are used with terminals that signal at rates less than 300 bitss,
and one stop bit is used if R > 300 bitss. Thus, with asynchronous lines, the receiver clock is
started aperiodically and no synchronization with a master clock is required. The frequency of
the receiver clock is sufficiently accurate that correct bit timing is maintained for the duration
of one word. This aperiodic mode of operation is ideal for keyboard terminals, at which the
typist does not type at an even pace and whose input rate is much slower than that of the data
communication system. These asynchronous terminals often use a 7-bit ASCII code, and
the complete character consists of one start bit, 7 bits of the ASCII code, one parity bit, and one
stop bit (for R Ú 300 bitss). This gives a total character length of 10 bits. In TDM of
the asynchronous type, the different sources are multiplexed on a character-interleaved (i.e.,
character-by-character) basis instead of interleaving on a bit-by-bit basis. The synchronous
transmission system is more efficient, because start and stop bits are not required. However, the
synchronous mode of transmission requires that the clocking signal be passed along with the
data and that the receiver synchronize to the clocking signal.
“Intelligent” TDMs may be used to concentrate data arriving from many different terminals
or sources. These TDMs are capable of providing speed, code, and protocol conversion.
At the input to a large mainframe computer, they are called front-end processors. The
hardware in the intelligent TDM consists of microprocessors or minicomputers. Usually, they
connect “on the fly” to the input data lines that have data present and momentarily disconnect
the lines that do not have data present. For example, a keyboard terminal is disconnected from
the system while it is inactive (although to the user, it does not appear to be disconnected) and
is connected as each character or block of data is sent. Thus the output data rate of the multiplexer
is much less than the sum of the data capacities of the input lines. This technique is
called statistical multiplexing; it allows many more terminals to be connected on line to the
system.
Multiplexers can also be classified into three general types. The first TDM type consists
of those that connect to synchronous lines. The second TDM type consists of those
that connect to quasi-synchronous lines. In this case, the individual clocks of the input data
sources are not exactly synchronized in frequency. Consequently, there will be some variation
in the bit rates between the data arriving from different sources. In addition, in some