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01.05.2017 Views

Low-level distorted TDM input Amplifer and filter Sampler and decision circuit Regenerated TDM data Frame synchronizer Bit synchronizer Bit sync Clock Data Stage 1 Stage 1 Shift register Stage 1 • •• • •• Stage K s 1 s 2 s 3 s K Frame sync Coincident detector T b T f Figure 3–37 Frame synchronizer with TDM receiver front end. 209

Low-level<br />

distorted<br />

TDM<br />

input<br />

Amplifer<br />

and filter<br />

Sampler and<br />

decision circuit<br />

Regenerated TDM data<br />

Frame synchronizer<br />

Bit<br />

synchronizer<br />

Bit<br />

sync<br />

Clock<br />

Data<br />

Stage<br />

1<br />

Stage<br />

1<br />

Shift register<br />

Stage<br />

1<br />

• ••<br />

• ••<br />

Stage<br />

K<br />

s 1 s 2 s 3 s K<br />

Frame sync<br />

Coincident detector<br />

T b<br />

T f<br />

Figure 3–37<br />

Frame synchronizer with TDM receiver front end.<br />

209

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