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Baseband Pulse and Digital Signaling Chap. 3
Channel N
data
s 1 s 2 s Channel 1 Channel 2 Channel N
K s 1 s 2
data data
data
• ••
• ••
• ••
• ••
Information
words
Sync word
Information words
Frame
Sync word
Figure 3–36 TDM frame sync format.
each frame. As illustrated in Fig. 3–37, the frame sync is recovered from the corrupted TDM
signal by using a frame synchronizer circuit that cross-correlates the regenerated TDM signal
with the expected unique sync word s = (s 1 , s 2 , ... , s K ). The elements of the unique sync word
vector s, denoted by s 1 , s 2 , ... s j , ... s k , are binary 1’s or 0’s (which, for TTL logic would represent
+5 V or 0 V, respectively). The current bit of the regenerated TDM signal is clocked into
the first stage of the shift register and then shifted to the next stage on the next clock pulse
so that the most immediate K bits are always stored in the shift register. The s j ’s within the
triangles below the shift register denote the presence or absence of an inverter. That is, if s j is a
binary 0, then there is an inverter in the jth leg. If s j is a binary 1, there is no inverter. The
coincident detector is a K-input AND gate.
If the unique sync word happens to be present in the shift register, all the inputs to the
coincident detector will be binary 1’s, and the output of the coincident detector will be a binary
1 (i.e., a high level). Otherwise, the output of the coincident detector is a binary 0 (i.e., a low
level). Consequently, the coincident detector output will go high only during the T b -s interval
when the sync word is perfectly aligned in the shift register. Thus, the frame synchronizer
recovers the frame sync signal.
False sync output pulses will occur if K successive information bits happen to match the
bits in the sync word. For equally likely TDM data, the probability of this false sync occurring
is equal to the probability of obtaining the unique sync word, which is
P f = a 1 2 b K
= 2 -K
(3–90)
In frame synchronizer design, this equation may be used to determine the number of
bits, K, needed in the sync word so that the false lock probability will meet specifications.
Alternatively, more sophisticated techniques such as aperture windows can be used to suppress
false lock pulses [Ha, 1986]. The information words may also be encoded so that they
are not allowed to have the bit strings that match the unique sync word.
Since the output of the coincident detector is a digitized crosscorrelation of the sync
word with the passing K-bit word stored in the shift register, the sync word needs to be
chosen so that its autocorrelation function, R s (k), has the desirable properties: R s (0) = 1 and
R(k) ≈ 0 for k Z 0. The PN codes (studied in Sec. 5–13) are almost ideal in this regard. For
example, if P f = 4 × 10 -5 is the allowed probability of false sync, then, from Eq. (3–90), a
(K = 15)-bit sync word is required. Consequently, a 15-stage shift register is needed for
the frame synchronizer in the receiver. The 15-bit PN sync word can be generated at the
transmitter using a four-stage shift register.