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Sec. 3–8 Delta Modulation 199
DM transmitter
Analog input
signal
Low-pass
filter
w(t)
Sampler
Flat-topped
PAM
+
Comparator
y(t)
DM
–
Clock
f s
z(t)
Integrator or
accumulator
Channel
DM receiver
Integrator
Analog output
signal
Figure 3–31
DM system.
In the DM circuit shown in Fig. 3–31, the operations of the subtractor and two-level quantizer
are implemented by using a comparator so that the output is ±V c (binary). In this case, the
DM signal is a polar signal. A set of waveforms associated with the delta modulator is shown in
Fig. 3–32. In Fig. 3–32a, an assumed analog input waveform is illustrated. If the instantaneous
samples of the flat-topped PAM signal are taken at the beginning of each sampling period, the
corresponding accumulator output signal is shown. † Here the integrator is assumed to act as an
accumulator (e.g., integrating impulses) so that the integrator output at time t = nT s is given by
z n = 1 n
(3–81)
V a dyi
c i=0
where y i = y(iT s ) and d is the accumulator gain or step size. The corresponding DM output
waveform is shown in Fig. 3–32b.
At the receiver, the DM signal may be converted back to an analog signal approximation
to the analog signal at the system input. This is accomplished by using an integrator for
the receiver that produces a smoothed waveform corresponding to a smoothed version of the
accumulator output waveform that is present in the transmitter (Fig. 3–32a).
† The sampling frequency, f s = 1T s , is selected to be within the range 2B in 6 f s 6 2B channel , where B in is the
bandwidth of the input analog signal and B channel is the bandwidth of the channel. The lower limit prevents aliasing of
the analog signal, and the upper limit prevents ISI in the DM signal at the receiver. (See Example 3–16 for further
restrictions on the selection of f s .)