AMSV Newsletter 2016
AMSV Newsletter 2016
AMSV Newsletter 2016
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An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-<br />
SAR ADC in 65 nm CMOS<br />
Yan Zhu, Chi-Hang Chan, Seng-Pan U and R. P. Martins<br />
In IEEE JSSC <strong>2016</strong><br />
From Data Conversion and Signal Processing research line<br />
Motivation<br />
Architecture<br />
Software-defined Radio application.<br />
Multiple shared elements among the TI<br />
channel optimize the area.<br />
Offset and gain calibrations are fully integrated<br />
on-chip and achieve small area.<br />
Error-decision-correction logic enhances the<br />
robustness of the SA logic.<br />
Hybrid pipeline, flash and SAR architecture<br />
optimize the energy efficiency.<br />
Implementation<br />
Verification