AMSV Newsletter 2016

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In IEEE ISSCC <strong>2016</strong> and JSSC 2017 A Handheld 50pM-Sensitivity Micro-NMR CMOS Platform with B- Field Stabilization for Multi-Type Biological/Chemical Assays Ka-Meng Lei, Hadi Heidari, Pui-In Mak, Man-Kay Law, F. Maloberti and R. P. Martins From Wireless research line Motivation This is a micro-Nuclear Magnetic Resonance (NMR) system compatible with multi-type biological/chemical lab-on-a-chip assays. Unified in a handheld scale, the system is capable to detect
Vcal,P Vcal,N Off_N Off_P R R Off_P Off_N CAL-LogicR Off_P 6b Enable Off_P Off_N Vcal,P Vcal,N In IEEE ISSCC 2017 A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with Background Offset Calibration Chi-Hang Chan, Yan Zhu, Iok-Meng Ho, Wai-Hong Zhang, Seng-Pan U and R. P. Martins From Data Conversion and Signal Processing research line Motivation Architecture Wireless communication and Ethernet networks system. Multi-bit SAR ADC can achieve better energy efficiency than 1-b/ cycle at high speed. Pre-charge operation not only leads to larger power consumption but also makes the performance of multi-bit SAR ADCs more sensitive to PVT variation. Pre-charge operation is merged with the proposed switching scheme and a segmented DAC arrangement. Offset is calibrated in the background, embedded in the ADC operation, and low overhead. Performance is stable across a wide range of Voltage and Temperature variation. CLk.Gen. Ch.2 Φ S,main Common Clk Self-time Ch.1 Φ S,ch1 S,ch2 Bootstrapped loop DAC1 VIP Φ ST1,ch1 DAC1,P QP 1 VIN DAC1,N QN 1 V DD , QP 2 G nd QN 2 DAC2,P QP 3 QN DAC2,N 3 DAC2 Register w/ Mux Φ S,ch1 Φ S,main 1b+background Φ ST1,ch1 offset Cal. 2b 2b 2b Background Offset Calibration Decoder and Multiplexer 7b Implementation Verification SNDR (dB) SNDR (dB) SNDR (dB) 40 39 38 37 36 35 40 39.5 39 38.5 38 40 39.5 39 38.5 38 Chip #3 fs = 2.4 GHz fin = 10.1 MHz -40 -20 0 20 40 60 80 100 120 Temperature (°C) Chip #3 fs = 2.4 GHz fin = 10.1 MHz Chip #3 fs = 2 GHz fin = 10.1 MHz 0.58 0.6 0.62 0.64 0.66 0.68 Input Common-mode (V) 0.84 0.86 0.88 0.9 0.92 0.94 0.96 Supply Voltage (V) FoM@Nyquist (fJ/conv.-step) 100 MCAL,P MCAL,N CAL_enable D QP Dff1 CLK CAL_enable D QP Dff2 CLK MUX DAC Counter Flip Detection 7b design >8x improved CAL_enable fS ≥1GS/s,
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Page 9 and 10: ISSCC Results for Academia in China
Page 11 and 12: Design of a Collapse-Mode CMUT With
Page 13 and 14: In RSC Lab on a Chip 2016 Sub-7-Sec
Page 15 and 16: Events and Visits Visits Visit by D

AMSV Newsletter 2016

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