AMSV Newsletter 2016

Selected works from each research line
In IEEE ISSCC 2016 and JSSC 2016
A 0.003mm 2 1.7-to-3.5GHz Dual-Mode Time-Interleaved Ring-VCO
Achieving 90-to-150kHz 1/f 3 Phase Noise Corner
Jun Yin, Pui-In Mak, F. Maloberti and R. P. Martins
From Wireless research line
Motivation
Architecture
This work is a time-interleaved (TI) ring-VCO
(RVCO) exhibiting an improved figure-of-merit
(FoM) over a wide range of frequency offsets,
an extended tuning range and an inherent divided
output. Such features are achieved by substantially
increasing the number of delay stages
in a RVCO, such that the rich multi-phase suboutputs
can be combined time-interleavedly, to
generate a high-frequency output with a significantly
lowered 1/f 3 phase noise corner (f 1∕f3 ). The
critical block is the phase combiner, which features
a timing window to minimize the delay offset
and mismatch. A reconfigurable TI factor
extends the tuning range over the same range
of supply voltage (V DD ). The prototype is a 35-
stage dual-mode TI-RVCO occupying 0.003
mm 2 in 65-nm CMOS, and has a selectable TI
factor of 5 and 7. The measured f 1∕f3 is 150 kHz
at 3.47 GHz, which is 6.2x less than that of a
typical 5-stage RVCO, and is comparable with
those of the state-of-the-art LC-VCOs.
Result I
Result II