AMSV Newsletter 2016
AMSV Newsletter 2016
AMSV Newsletter 2016
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State Key Lab of Analog and Mixed-Signal VLSI (SKL AMS-VLSI)<br />
<strong>Newsletter</strong><br />
Motto: “Locally, from (World) Quality towards (National) Quantity”<br />
座 右 銘 : 立 足 本 土 、 人 才 培 養 , 以 世 界 級 質 量 創 建 國 家 級 規 模<br />
Year 6<br />
No . 6<br />
<strong>2016</strong> Milestones<br />
March 2017<br />
Co-Funded by<br />
Macao Science and Technology<br />
Development Fund (FDCT)<br />
Events<br />
Prof. Rui Martins gave a talk on nurturing talents in Science as part of the University Lecture Series and the<br />
Collegiate Learning Day, March 16, <strong>2016</strong>.<br />
State Key Laboratory of Analog and Mixed-Signal VLSI (SKL AMS-VLSI) received the Second and Third Prizes of<br />
Natural Science Award in Technological Invention attributed by Macao Science and Technology Development<br />
Fund (FDCT), October 12, <strong>2016</strong>.<br />
State Key Laboratory of Analog and Mixed-Signal VLSI (SKL AMS-VLSI) participated in the 10th Annual Meeting of<br />
the Committee for China and Macao Cooperation in Science and Technology held in Changzhou, China, October 18,<br />
<strong>2016</strong>.
State-of-the-Art Chips - Designed and Tested in <strong>2016</strong> (24 chips)<br />
190 μm<br />
580 μm<br />
1 st Integrator<br />
CLK<br />
Generator<br />
2 nd Integrator<br />
0.35μm, 0.18μm, 65nm and for the first time 6 28nm chips<br />
ISSCC 2017<br />
A team of faculty members and students from the SKL AMS-VLSI and ECE/FST, University of Macau (UM) attended the IEEE 64 th<br />
International Solid-State Circuits Conference (ISSCC) in February 2017, considered the ‘Chip Olympics’, the most competitive<br />
conference in the world in the field of chip design.<br />
This year SKL AMS-VLSI had a record acceptance of 6 papers/chips with the following titles, "A 5mW 7b 2.4GS/s 1-then-2b/cycle<br />
SAR ADC with Background Offset Calibration", "An Output-Capacitor-Free Analog-Assisted Digital Low-Dropout Regulator with Tri<br />
-Loop Control", "A Dual-Symmetrical-Output Switched-Capacitor Converter with Dynamic Power Cells and Minimized Cross Regulation for<br />
Application Processors in 28nm CMOS", "A 1.7mm 2 Inductorless Fully Integrated Flipping-Capacitor Rectifier (FCR) for Piezoelectric Energy<br />
Harvesting with 483% Power-Extraction Enhancement", "A Reconfigurable<br />
Bidirectional Wireless Power Transceiver with Maximum-Current<br />
Charging Mode and 58.6% Battery-to-Battery Efficiency", and "A 0.18V<br />
382μW Bluetooth Low-Energy (BLE) Receiver with 1.33nW Sleep Power<br />
for Energy-Harvesting Applications in 28nm CMOS". Besides, the SKLab<br />
PhD students received 1 Pre-doctoral Achievement Award and presented<br />
2 Student Research Previews.<br />
Prof. Seng-Pan U and Prof. Pui-In Mak, deputy director and associate<br />
director (research) of SKL AMS-VLSI , were invited to serve as members<br />
of the Technical Program Committee of the ISSCC. In addition, Prof. U is<br />
currently the China Representative of the ISSCC Technical Program<br />
Committee, responsible for coordination of ISSCC activities in China.<br />
Prof. Seng-Pan U became the 1st member<br />
of Ministry of Education’s Science and<br />
Technology Commission from Macao<br />
Prof. Seng-Pan U and Prof. Pui-In Mak<br />
participated in a China Press Conference<br />
held in Shanghai as members of the TPC of<br />
ISSCC 2017<br />
UM’s first ‘Macao Fellow’ appointed visiting<br />
scholar at Harvard and received IEEE<br />
SSCS Predoctoral Achievement Award<br />
Prof. Ben U Seng Pan from the University of<br />
Macau (UM) Faculty of Science and Technology,<br />
who is also the deputy director of SKL<br />
AMS-VLSI, was appointed a member of the<br />
Seventh Science and Technology Commission<br />
of the Ministry of Education. Prof U is the<br />
first and only scholar from Macao to be<br />
appointed as member of such commission.<br />
SKL AMS-VLSI student supervised by Prof.<br />
Yan Lu won 2nd prize at National University<br />
Integrated Circuit Design Contest (NUICDC)<br />
Dr. Ka-Meng Lei, a lecturer under the<br />
‘Macao Fellow’ program at the University of<br />
Macau, will be a visiting scholar at the<br />
Harvard University for a two-year term<br />
starting in mid-2017. During his stay, Dr Lei<br />
will explore a parallel nuclear magnetic<br />
resonance (NMR) platform combining advanced<br />
microfluidic, magnetic-sensing and<br />
integrated circuits technologies, with the<br />
aim of substantially reducing the cost and<br />
time of NMR experiments.<br />
4 New PhD Graduates<br />
4. Jianyu Zhong, High-resolution Power-efficient SAR-<br />
Type ADCs, Sep. <strong>2016</strong>.<br />
3. Ka-Meng Lei, Handheld CMOS-Based NMR Devices<br />
for Biological/Chemical Diagnosis, Sep. <strong>2016</strong>.<br />
2. Tianlan Chen, Thermal Digital Microfluidic Devices<br />
for Rapid DNA Analysis, Sep. <strong>2016</strong>.<br />
1. Chio-In Ieong, Low-Power CMOS Processors Design<br />
for ECG QRS Wave Detection and Data Compression,<br />
Mar. <strong>2016</strong>.<br />
A Book by Springer<br />
A Book by IEEE CASS<br />
http://ieee-cas.org/short-history-circuits-and-systems
Selected works from each research line<br />
In IEEE ISSCC <strong>2016</strong> and JSSC <strong>2016</strong><br />
A 0.003mm 2 1.7-to-3.5GHz Dual-Mode Time-Interleaved Ring-VCO<br />
Achieving 90-to-150kHz 1/f 3 Phase Noise Corner<br />
Jun Yin, Pui-In Mak, F. Maloberti and R. P. Martins<br />
From Wireless research line<br />
Motivation<br />
Architecture<br />
This work is a time-interleaved (TI) ring-VCO<br />
(RVCO) exhibiting an improved figure-of-merit<br />
(FoM) over a wide range of frequency offsets,<br />
an extended tuning range and an inherent divided<br />
output. Such features are achieved by substantially<br />
increasing the number of delay stages<br />
in a RVCO, such that the rich multi-phase suboutputs<br />
can be combined time-interleavedly, to<br />
generate a high-frequency output with a significantly<br />
lowered 1/f 3 phase noise corner (f 1∕f3 ). The<br />
critical block is the phase combiner, which features<br />
a timing window to minimize the delay offset<br />
and mismatch. A reconfigurable TI factor<br />
extends the tuning range over the same range<br />
of supply voltage (V DD ). The prototype is a 35-<br />
stage dual-mode TI-RVCO occupying 0.003<br />
mm 2 in 65-nm CMOS, and has a selectable TI<br />
factor of 5 and 7. The measured f 1∕f3 is 150 kHz<br />
at 3.47 GHz, which is 6.2x less than that of a<br />
typical 5-stage RVCO, and is comparable with<br />
those of the state-of-the-art LC-VCOs.<br />
Result I<br />
Result II
In IEEE ISSCC <strong>2016</strong> and JSSC 2017<br />
A Handheld 50pM-Sensitivity Micro-NMR CMOS Platform with B-<br />
Field Stabilization for Multi-Type Biological/Chemical Assays<br />
Ka-Meng Lei, Hadi Heidari, Pui-In Mak, Man-Kay Law, F. Maloberti and R. P. Martins<br />
From Wireless research line<br />
Motivation<br />
This is a micro-Nuclear Magnetic Resonance<br />
(NMR) system compatible with multi-type biological/chemical<br />
lab-on-a-chip assays. Unified in a<br />
handheld scale, the system is capable to detect<br />
Vcal,P<br />
Vcal,N<br />
Off_N<br />
Off_P<br />
R<br />
R<br />
Off_P<br />
Off_N<br />
CAL-LogicR<br />
Off_P<br />
6b<br />
Enable<br />
Off_P<br />
Off_N<br />
Vcal,P<br />
Vcal,N<br />
In IEEE ISSCC 2017<br />
A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with Background Offset<br />
Calibration<br />
Chi-Hang Chan, Yan Zhu, Iok-Meng Ho, Wai-Hong Zhang, Seng-Pan U and R. P. Martins<br />
From Data Conversion and Signal Processing research line<br />
Motivation<br />
Architecture<br />
Wireless communication and Ethernet networks<br />
system. Multi-bit SAR ADC can<br />
achieve better energy efficiency than 1-b/<br />
cycle at high speed.<br />
Pre-charge operation not only leads to larger<br />
power consumption but also makes the<br />
performance of multi-bit SAR ADCs more<br />
sensitive to PVT variation.<br />
Pre-charge operation is merged with the<br />
proposed switching scheme and a segmented<br />
DAC arrangement.<br />
Offset is calibrated in the background, embedded<br />
in the ADC operation, and low<br />
overhead.<br />
Performance is stable across a wide range<br />
of Voltage and Temperature variation.<br />
CLk.Gen.<br />
Ch.2<br />
Φ S,main Common Clk<br />
Self-time Ch.1<br />
Φ S,ch1 S,ch2 Bootstrapped<br />
loop<br />
DAC1<br />
VIP<br />
Φ ST1,ch1<br />
DAC1,P<br />
QP 1<br />
VIN<br />
DAC1,N<br />
QN 1<br />
V DD ,<br />
QP 2<br />
G nd<br />
QN 2<br />
DAC2,P<br />
QP 3<br />
QN<br />
DAC2,N<br />
3<br />
DAC2<br />
Register w/ Mux<br />
Φ S,ch1<br />
Φ S,main<br />
1b+background<br />
Φ ST1,ch1 offset Cal. 2b 2b 2b<br />
Background Offset Calibration<br />
Decoder and Multiplexer<br />
7b<br />
Implementation<br />
Verification<br />
SNDR (dB)<br />
SNDR (dB)<br />
SNDR (dB)<br />
40<br />
39<br />
38<br />
37<br />
36<br />
35<br />
40<br />
39.5<br />
39<br />
38.5<br />
38<br />
40<br />
39.5<br />
39<br />
38.5<br />
38<br />
Chip #3<br />
fs = 2.4 GHz<br />
fin = 10.1 MHz<br />
-40 -20 0 20 40 60 80 100 120<br />
Temperature (°C)<br />
Chip #3<br />
fs = 2.4 GHz<br />
fin = 10.1 MHz<br />
Chip #3<br />
fs = 2 GHz<br />
fin = 10.1 MHz<br />
0.58 0.6 0.62 0.64 0.66 0.68<br />
Input Common-mode (V)<br />
0.84 0.86 0.88 0.9 0.92 0.94 0.96<br />
Supply Voltage (V)<br />
FoM@Nyquist<br />
(fJ/conv.-step)<br />
100<br />
MCAL,P<br />
MCAL,N<br />
CAL_enable<br />
D QP<br />
Dff1<br />
CLK<br />
CAL_enable<br />
D<br />
QP<br />
Dff2<br />
CLK<br />
MUX<br />
DAC<br />
Counter<br />
Flip<br />
Detection<br />
7b<br />
design >8x<br />
improved<br />
CAL_enable<br />
fS ≥1GS/s,
An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-<br />
SAR ADC in 65 nm CMOS<br />
Yan Zhu, Chi-Hang Chan, Seng-Pan U and R. P. Martins<br />
In IEEE JSSC <strong>2016</strong><br />
From Data Conversion and Signal Processing research line<br />
Motivation<br />
Architecture<br />
Software-defined Radio application.<br />
Multiple shared elements among the TI<br />
channel optimize the area.<br />
Offset and gain calibrations are fully integrated<br />
on-chip and achieve small area.<br />
Error-decision-correction logic enhances the<br />
robustness of the SA logic.<br />
Hybrid pipeline, flash and SAR architecture<br />
optimize the energy efficiency.<br />
Implementation<br />
Verification
ISSCC / 2002 - 2017 — 21 papers/chips<br />
ISSCC 2017<br />
21<br />
ISSCC 2017<br />
CMOS<br />
0.18 μm<br />
CMOS<br />
28 nm<br />
A 1.7mm 2 Inductor-less Fully-Integrated Capacitive-Flip<br />
Rectifier (CFR) for Piezoelectric Energy Harvesting with<br />
483% Power Extraction Improvement<br />
20<br />
A 0.18V 382µW Bluetooth Low-Energy (BLE) Receiver<br />
with 1.33nW Sleep Power for Energy-Harvesting<br />
Applications in 28nm CMOS<br />
ISSCC 2017<br />
19<br />
ISSCC 2017<br />
CMOS<br />
28 nm<br />
CMOS<br />
28 nm<br />
A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with<br />
Background Offset Calibration<br />
18<br />
A Dual-Symmetrical-Output Switched-Capacitor Converter<br />
with Dynamic Power Cells and Minimized Cross<br />
Regulation for Application Processors in 28nm CMOS<br />
ISSCC 2017<br />
17<br />
ISSCC 2017<br />
CMOS<br />
65 nm<br />
CMOS<br />
0.35 μm<br />
An Output-Capacitor-Free Analog-Assisted Digital<br />
Low-Dropout Regulator with Tri-Loop Control<br />
16<br />
A Reconfigurable Bidirectional Wireless Power<br />
Transceiver with Maximum-Current Charging Mode<br />
and 58.6% Battery-to-Battery Efficiency<br />
ISSCC <strong>2016</strong><br />
15<br />
ISSCC <strong>2016</strong><br />
CMOS<br />
0.18 μm<br />
CMOS<br />
65 nm<br />
A Handheld 50pM-Sensitivity Micro-NMR CMOS<br />
Platform with B-Field Stabilization for Multi-Type<br />
Biological/Chemical Assays<br />
14<br />
A 0.003mm 2 1.7-to-3.5GHz Dual-Mode Time-Interleaved<br />
Ring-VCO Achieving 90-to-150kHz 1/f 3 Phase Noise<br />
Corner<br />
ISSCC <strong>2016</strong><br />
13<br />
ISSCC 2015<br />
CMOS<br />
65 nm<br />
CMOS<br />
65 nm<br />
A 0.038mm 2 SAW-less Multi-Band Transceiver Using an<br />
N-Path SC Gain Loop<br />
12<br />
A 0.028mm 2 11mW Single-Mixing Blocker-Tolerant<br />
Receiver with Double-RF N-Path Filtering, S11 Centering,<br />
+13dBm OB-IIP3 and 1.5-to-2.9dB NF
ISSCC / 2002 - 2017 — 21 papers/chips<br />
ISSCC 2015<br />
11<br />
ISSCC 2015<br />
CMOS<br />
65 nm<br />
CMOS<br />
65 nm<br />
A 123-Phase DC-DC Converter-Ring with Fast-DVS for<br />
Microprocessors<br />
10<br />
A 2-/3-Phase Fully Integrated Switched-Capacitor DC-DC<br />
Converter in Bulk CMOS for Energy-Efficient Digital<br />
Circuits with 14% Efficiency Improvement<br />
9<br />
ISSCC 2015 ISSCC 2014<br />
CMOS<br />
65 nm<br />
CMOS<br />
65 nm<br />
A 5.5mW 6b 5GS/s 4×-Interleaved 3b/cycle SAR ADC in<br />
65nm CMOS<br />
8<br />
A 0.5V 1.15mW 0.2mm 2 Sub-GHz ZigBee Receiver<br />
Supporting 433/860/915/960MHz ISM Bands with<br />
Zero External Components<br />
ISSCC 2014<br />
7<br />
ISSCC 2014<br />
CMOS<br />
65 nm<br />
CMOS<br />
0.18 μm<br />
An RF-to-BB-Current-Reuse Wideband Receiver<br />
with Parallel N-Path Active/Passive Mixers and<br />
a Single-MOS Pole-Zero LPF<br />
6<br />
A 0.0013mm 2 3.6μW Nested-Current-Mirror Single-Stage<br />
Amplifier Driving 0.15-to-15nF Capacitive Loads<br />
with >62° Phase Margin<br />
ISSCC 2013<br />
5<br />
ISSCC 2012<br />
CMOS<br />
65 nm<br />
CMOS<br />
0.35 μm<br />
A 1.7mW 0.22mm 2 2.4GHz ZigBee RX Exploiting a<br />
Current-Reuse Blixer+Hybrid Filter Topology<br />
in 65nm CMOS<br />
4<br />
A 0.016mm 2 144µW Three-Stage Amplifier Capable of<br />
Driving 1-to-15nF Capacitive Load with >0.95MHz GBW<br />
ISSCC 2011<br />
2,3<br />
ISSCC 2002<br />
CMOS<br />
65 nm<br />
CMOS<br />
0.35 μm<br />
A 0.46mm 2 4-dB NF<br />
Unified Receiver<br />
Front-End for<br />
Full-Band Mobile TV<br />
A 0.024mm 2 8-bit 400<br />
MS/s SAR ADC with<br />
2-bit per Cycle and<br />
Resistive DAC<br />
1<br />
A 2.5V 57MHz 15-tap SC Bandpass Interpolating Filter<br />
with 320MHz Output Sampling Rate in 0.35μm CMOS
ISSCC Results for Academia in China (2011-2017)<br />
By First Affiliation of<br />
First Author<br />
2011 2012 2013 2014 2015 <strong>2016</strong> 2017 Total<br />
University of Macau 2 1 1 3 2 3 6 18<br />
Hong Kong University of<br />
Science and Technology<br />
1 1 2 3 4 3 4 18<br />
Fudan University 1 1 2 1 5<br />
Tsinghua University 1 2 1 4<br />
Institute of Microelectronics<br />
Chinese Academy of Science<br />
1 1 1 3<br />
Awards and Student Research Preview in 2011 - 2017:<br />
2 ISSCC Silk-Road Award<br />
4 SSCS Pre-Doctoral Achievement Award<br />
9 ISSCC Student Research Preview<br />
Industry/University/Institute Worldwide (2017)<br />
(First Author Affiliation)<br />
▓ Industry: 7<br />
◆MediaTek (9), IBM (5), Samsung Electronics (5), Intel (5),<br />
◆TSMC (3), Analog Devices (3), Xilinx (3).<br />
▓ University: 16<br />
◆Univ. of Michigan (11), Columbia Univ. (6), Delft Univ. (6),<br />
◆KAIST (6), U. Macau (6), Univ. of Texas @ Dallas (6),<br />
◆Georgia Inst. of Tech. (5), Pohang U. of Sci. & Tech. (5),<br />
◆UC San Diego (5), HK U. of S&T (4), MIT (4), UCLA (4),<br />
◆National Chiao Tung Univ.(3), Princeton Univ.(3),<br />
◆Stanford Univ. (3), Univ. of Illinois (3).<br />
▓ Institute: 1<br />
◆IMEC (4).
ISSCC - 15 PhD Students Awards and Research Previews<br />
ISSCC<br />
Silkroad Award<br />
Ka-Meng Lei<br />
(2017)<br />
ISSCC<br />
Silkroad Award<br />
He Gong Wei<br />
(2011)<br />
"A Handheld 50pM-Sensitivity Micro-NMR CMOS Platform with<br />
B-Field Stabilization for Multi-Type Biological/Chemical Assays"<br />
“A 0.024mm 2 8-bit 400 MS/s SAR ADC with 2-bit per Cycle and<br />
Resistive DAC in 65 nm CMOS”<br />
SSCC Pre-Doctoral Achievement Award (<strong>2016</strong>-2017) (Ka-Meng Lei)<br />
SSCC Pre-Doctoral Achievement Award (2013-2014) (Zushu Yan)<br />
SSCC Pre-Doctoral Achievement Award (2014-2015) (Zhicheng Lin)<br />
SSCC Pre-Doctoral Achievement Award (2014-2015) (Chi Hang Chan)<br />
Student Research<br />
Preview 2017<br />
Tan-Tan Zhang<br />
Student Research Preview 2017 (Yang Jiang)<br />
Student Research Preview <strong>2016</strong> (Liang Qi)<br />
Student Research Preview <strong>2016</strong> (Chio-In Ieong)<br />
Student Research Preview <strong>2016</strong> (Wei Han Yu)<br />
Student Research Preview 2015 (Ka-Meng Lei)<br />
Student Research<br />
Preview 2015<br />
Jianyu Zhong<br />
Student Research<br />
Preview 2014<br />
Yaohua Zhao<br />
Student Research Preview 2013 (Zushu Yan)
Design of a Collapse-Mode CMUT With an Embossed Membrane for<br />
Improving Output Pressure<br />
Yuanyu Yu, Sio Hang Pun, Peng Un Mak, Ching-Hsiang Cheng, Jiujiang Wang, Pui-In Mak, and<br />
Mang I Vai<br />
From Biomedical research line<br />
In IEEE Transactions on Ultrasonics, Ferroelectrics,<br />
and Frequency Control - TUFFC <strong>2016</strong><br />
Motivation<br />
Architecture<br />
Capacitive micromachined ultrasonic transducers<br />
(CMUTs) have emerged as a competitive<br />
alternative to piezoelectric ultrasonic transducers,<br />
especially in medical ultrasound imaging<br />
and therapeutic ultrasound applications, which<br />
require high output pressure. However, when<br />
compared with piezoelectric ultrasonic transducers,<br />
the output pressure capability of CMUTs<br />
needs still to be improved.<br />
In this work, a novel structure is proposed by<br />
forming an embossed vibrating membrane on a<br />
CMUT cell operating in the collapse mode to<br />
increase the maximum output pressure. By using<br />
a beam model in undamped conditions and<br />
finite-element analysis simulations, the proposed<br />
embossed structure showed improvement<br />
on the maximum output pressure of the<br />
CMUT cell when the embossed pattern was<br />
placed on the estimated location of the peak deflection.<br />
(a)<br />
(b)<br />
(a) 3-D outlook view and (b) 2-D axisymmetric cross-sectional view of<br />
the proposed collapse-mode CMUT with an embossed membrane.<br />
2-D axisymmetric view of the dual embossed patterns located<br />
symmetrically in the vibrating center.<br />
Principle<br />
Result<br />
Based on the analysis of the simply supported beam model,<br />
X = 0.481L is the optimal position for the embossed pattern.<br />
For a collapse-mode CMUT, the output pressure is improved<br />
and the center frequency is reduced with this embossed pattern.<br />
(a)<br />
(b)<br />
(a) Output pressure comparison between the uniform membrane and<br />
the embossed membrane CMUT in the collapse mode. (b) Thinning<br />
embossed membrane to tune center frequency.<br />
Relationship between pressure improvement and center frequency<br />
shift for various embossed positions.
A Dual-Output Wireless Power Transfer System with Active Rectifier<br />
and 3-Level Operation<br />
Yan Lu, Mo Huang, Lin Cheng, Wing-Hung Ki, Seng-Pan U, and R. P. Martins<br />
In IEEE TPEL 2017<br />
[Accepted in <strong>2016</strong>]<br />
From Integrated Power research line<br />
Motivation<br />
Architecture<br />
Wireless power transfer (WPT) systems for<br />
batteryless and wirelessly charged devices<br />
have attracted enormous attention in recent<br />
years.<br />
The 3-level DC-DC and the SIMO techniques are naturally<br />
merged with a 2X rectifier (voltage doubler) which readily<br />
has two DC supplies (three levels, including GND).<br />
To cut the last wire of the electronic devices,<br />
this work was designed for the wirelessly<br />
powered flash memory drives that<br />
need multiple supply levels with a total<br />
power consumption of sub-1W.<br />
For miniature size and small output ripple,<br />
multi-level operation and single-inductor<br />
multiple-output techniques are employed in<br />
this prototype.<br />
Implementation<br />
Verification<br />
The proposed WPT system was fabricated in a 0.35μm<br />
CMOS process, and measured with low-cost PCB coils.<br />
Measured voltage and inductor current waveforms of the<br />
WPT receiver.
In RSC Lab on a Chip <strong>2016</strong><br />
Sub-7-Second Genotyping of Single-Nucleotide Polymorphism by High-<br />
Resolution Melting Curve Analysis on a Thermal Digital Microfluidic Device<br />
Tianlan Chen, Yanwei Jia, Cheng Dong, Jie Gao, Pui-In Mak, and R. P. Martins<br />
From Multidisciplinary Research Area (Microfluidic)<br />
Motivation<br />
Architecture I<br />
We developed a thermal digital microfluidic<br />
(T-DMF) device enabling ultrafast DNA melting<br />
curve analysis (MCA). Within 7 seconds,<br />
the T-DMF device succeeded in differentiating<br />
a melting point difference down to 1.6 °C<br />
with a variation of 0.3 °C in a tiny droplet<br />
sample (1.2 μL), which was 300 times faster<br />
and with 20 times less sample spending<br />
than the standard MCA (35 minutes, 25 μL)<br />
run in a commercial qPCR machine. Such a<br />
performance makes it possible for a rapid<br />
discrimination of single-nucleotide mutation<br />
relevant to prompt clinical decision-making.<br />
Capable of thermally modulating DNA samples<br />
with ultrafast MCA, this T-DMF device<br />
has the potential for a wide variety of life science<br />
analyses, especially for disease diagnosis<br />
and prognosis.<br />
Architecture II<br />
Result
Technology Transfer Office and Starting of Commercialization Activity<br />
Technology Transfer Office<br />
In order to enhance the technology transfer supporting infrastructure, SKL AMS-VLSI Technology<br />
Transfer Office (TTO) was established in Feb <strong>2016</strong> led by Dr. Yong-Hsiang Hsieh (Alex) born in Macao.<br />
Dr. Alex Hsieh received the Ph.D. degree in Department of Electrical Engineering, National Taiwan<br />
University and has over 15 years extensive microelectronics industry experience in Taiwan and China.<br />
Partnership with Companies and Applied Research Institutes<br />
In the year of <strong>2016</strong>, the startup year of TTO, it has made tremendous efforts on establishing connection with industrial partners. The active interactions<br />
were with regional government fund IC incubation center (e.g., National IC Design ShenZhen industrial Centre and ZhuHai South IC Design Service<br />
Center), with research institutes (e.g., Institute of Microelectronics of Chinese Academy of Sciences and Hong Kong Applied Sciences and Technology<br />
Research Institute), and the leading fabless IC companies in China.(e.g., Hisilicon, Allwinner, etc.)<br />
A delegation led by Dr. Mei-Kei Ieong, CTO of Hong Kong Applied<br />
Science and Technology Research Institute, visited SKL AMS-VLSI to<br />
discuss potential collaboration.<br />
Visit by Mr. Hai-Yang Wang, Director of Huawei, China.<br />
US Patents Granted in <strong>2016</strong><br />
1. “Ultra-Low-Voltage Current-Reuse Voltage-Controlled Oscillator and Transconductance-Capacitor Filter,” US Patent, No. 9,444,431, Sep. <strong>2016</strong>.<br />
2. “Gain-Boosted N-Path Bandpass Filter,” US Patent, No. 9,374,063, Jun. <strong>2016</strong>.<br />
3. “An RF-to-BB-Current-Reuse Wideband Receiver with Parallel N-Path Active/Passive Mixers,” US Patent, No. 9,356,636, May <strong>2016</strong>.<br />
4. “IF-Noise-Shaping Transistorized Current-Mode Lowpass Filter Utilizing Cross-Coupled Transistors,” US Patent, No. 9,306,540, Apr. <strong>2016</strong>.<br />
5. “Non-recursive Digital Calibration for Joint-elimination of Transmitter and Receiver I/Q Imbalances with Minimized Add-on Hardware,” US Patent,<br />
No. 9,276,798, Mar. <strong>2016</strong>.<br />
6. “RF-to-BB-Current-Reuse Wideband Receiver with a Single-MOS Pole-Zero LPF,” US Patent, No. 9,270,314, Feb. <strong>2016</strong>.<br />
7. “ZigBee Receiver Exploiting an RF-to-BB Current-Reuse Blixer and Hybrid Filter Topology,” US Patent, No. 9,237,055, Jan. <strong>2016</strong>.<br />
Industrial-Academic Collaborative Projects<br />
Selected accomplished project: An ultra-low power high speed ADC collaborative project with Hisilicon, the China #1 fabless IC design company, has<br />
successfully closed in <strong>2016</strong>.<br />
Selected on-going projects: Two collaborative projects with Allwinner, a Pearl River Delta area local listed company and one project under negotiation<br />
with Synopsys, the world’s leading company in silicon IP.<br />
Possible Spin-off Projects<br />
SKL AMS-VLSI explores DNA kinetic limitation<br />
on microchips with the duration of the DNA<br />
melting curve analysis shortened to 7 seconds.<br />
CBBio under SKL AMS-VLSI achieves new<br />
breakthrough in biochip research.<br />
SKL AMS-VLSI developed a T-DMF device<br />
enabling ultrafast DNA melting curve analysis.
Events and Visits<br />
Visits<br />
Visit by Du Qinglin, Vice-Chairman of the Chinese People's<br />
Political Consultative Conference.<br />
Visit by Du Zhanyuan, Vice-Minister, Ministry of Education.<br />
Visit by Prof. António Cunha, Rector of University of Minho,<br />
President of the Council of Rectors of Portugal.<br />
Distinguished Lectures and Workshops<br />
Visit by a Delegation from The Institute for Systems and Computer<br />
Engineering, Technology and Science (INESC-TEC), Portugal.<br />
4-Day Workshop in Advanced IC Design by<br />
Prof. Willy Sansen,<br />
IEEE Life Fellow, Professor at the<br />
Catholic University of Leuven, in Belgium<br />
Distinguished Workshop<br />
“From Flatland Electrodynamics<br />
to Molecular<br />
Spectroscope and Neurotechnology<br />
with Solid-<br />
State Chips” by<br />
Prof. Donhee Ham,<br />
Gordon McKay Prof.,<br />
Harvard University<br />
Distinguished Lecture<br />
"Innovative Entrepreneurship<br />
and Youth<br />
Development" by<br />
Dr. Carter Tseng,<br />
Chairman & CEO of<br />
Little Dragon Foundation<br />
, Director USA<br />
“Committee100”<br />
2-Day Distinguished Workshop<br />
with INESCTEC,<br />
Porto, Portugal, by<br />
Prof. Vítor Grade Tavares,<br />
Senior Researcher,<br />
INESC-TEC and other<br />
INESC-TEC related<br />
members<br />
New Academic Joined SKL AMS-VLSI<br />
SKL AMS-VLSI New Cleanroom for Biochip<br />
Research and Commercialization<br />
Lecturer (Macao Fellow)<br />
Ka-Meng Lei received the B.Sc. degree in electrical<br />
and electronics engineering and Ph.D.<br />
degree from the University of Macau (UM),<br />
Macao, China, in 2012 and <strong>2016</strong>, respectively.<br />
He is currently a lecturer (Macao Fellow) at SKL<br />
AMS-VLSI and will visit Harvard University as a<br />
Visiting Researcher for 2 years.<br />
Research Interests: Microfluidics, Mixed-Signal integrated circuits<br />
design, Wireless integrated circuits design.
▓<br />
Book<br />
“Ultra-Low-Power and Ultra-Low-Cost Short-Range Wireless Receivers in Nanoscale CMOS”, ISBN 978-3-319-21524-2, Series of Analog Circuits and Signal Processing<br />
(ACSP), Springer Press, USA, Jan. <strong>2016</strong>.<br />
SCI Journals – 38 Papers (3 in 2017)<br />
▓ “A Handheld High Sensitivity Micro-NMR CMOS Platform with B-Field Stabilization for Multi-Type Biological/Chemical Assays,” IEEE Journal of Solid-State Circuits, Jan. 2017.<br />
[Invited Paper]<br />
▓ “Design of a Thyristor Controlled LC Compensator for Wind Farm Dynamic Reactive Power Compensation in Smart Grid,” IEEE Transactions on Smart Grid, Jan. 2017.<br />
▓ “Active-Passive ΔΣ Modulator for High-Resolution and Low-Power Applications,” IEEE Transactions on Very Large Scale Integration Systems, Jan. 2017.<br />
▓ “A Time-Interleaved Ring-VCO with Reduced 1/f 3 Phase Noise Corner, Extended Tuning Range and Inherent Divided Output,” IEEE Journal of Solid-State Circuits, Dec. <strong>2016</strong>.<br />
▓ “Wireless Power Transfer System Architectures for Portable or Implantable Applications,” Energies, Dec. <strong>2016</strong>.<br />
▓ “An 18-Gb/s Fully Integrated Optical Receiver with Adaptive Cascaded Equalizer,” IEEE Journal of Selected Topics in Quantum Electronics, vol. 22, no. 6, Nov.-Dec. <strong>2016</strong>.<br />
▓ “A μNMR CMOS Transceiver Using a Butterfly-Coil Input for Integration with a Digital Microfluidic Device inside a Portable Magnet,” IEEE Journal of Solid-State Circuits, Oct.<br />
<strong>2016</strong>. [Invited Paper]<br />
▓ “Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial V cm-Based Switching,” IEEE Transactions on Very Large Scale Integration Systems, online on Oct.<br />
<strong>2016</strong>.<br />
▓ “Wide Input Range Supply Voltage Tolerant Capacitive Sensor Readout Using On-Chip Solar Cell,” World Scientific Journal of Circuits, Systems, and Computers, Oct.<br />
▓<br />
<strong>2016</strong>.<br />
“Analysis, Design and Implementation of a Quasi-Proportional-Resonant Controller for Multi-Functional Capacitive-Coupling Grid-Connected Inverter,” IEEE Transactions on<br />
Industry Application, Sep. <strong>2016</strong>.<br />
▓ “CMOS Biosensors for In Vitro Diagnosis - Transducing Mechanisms and Applications,” RSC Lab on a Chip, Sep. <strong>2016</strong>.<br />
▓ “Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators,” IEEE Transactions on CAS – Part II: Express Briefs, Sep. <strong>2016</strong>.<br />
▓ “Improved Analytical Modeling of Membrane Large Deflection with Lateral Force for the Underwater CMUT Based on Von Kármán Equations,” IEEE Sensors Journal, Sep. <strong>2016</strong>.<br />
▓ “ProtPOS: a Python Package for the Prediction of Protein Preferred Orientation on a Surface,” Oxford University Press - Bioinformatics, Aug. <strong>2016</strong>.<br />
▓ “A 312 ps Response-Time LDO with Enhanced Super Source Follower in 28 nm CMOS,” IET Electronics Letters, Aug. <strong>2016</strong>.<br />
▓ “A Multi-Channel Power-Supply Modulated Micro-Stimulator With Energy Recycling,” IEEE Design and Test, Aug. <strong>2016</strong>.<br />
▓ “A 4x Time-Domain Interpolation 6-bit 3.4 GS/s 12.6 mW Flash ADC in 65 nm CMOS”, Journal of Semiconductor Technology and Science (South Korea), Aug. <strong>2016</strong>.<br />
▓ “A Fully-Integrated Digital LDO with Coarse-Fine-Tuning and Burst-Mode Operation,” IEEE Transactions on CAS – Part II: Express Briefs, Jul. <strong>2016</strong>.<br />
▓ “Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC,” IEEE Transactions on Very Large Scale Integration Systems, Jul. <strong>2016</strong>.<br />
▓ “Development of a Calibration Strip for Immunochromatographic Assay Detection Systems,” Sensors, Jul. <strong>2016</strong>.<br />
▓ “A Hybrid STATCOM with Wide Compensation Range and Low DC-Link Voltage,” IEEE Transactions on Industrial Electronics, Jun. <strong>2016</strong>.<br />
▓<br />
▓<br />
▓<br />
“Design of a Collapse-Mode CMUT with an Embossed Membrane for Improving Output Pressure,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency<br />
Control, Jun. <strong>2016</strong>.<br />
“Joint-Digital-Predistortion for Wireless Transmitter's I/Q Imbalance and PA Nonlinearities Using an Asymmetrical Complexity-Reduced Volterra Series Model,” Springer Analog<br />
Integrated Circuits and Signal Processing, Apr. <strong>2016</strong>.<br />
“A 2 µW 45 nV/√Hz Readout Frontend With Multiple Chopping, Active-High-Pass Ripple Reduction Loop and Pseudo-Feedback DC Servo Loop,” IEEE Transactions on Circuits<br />
and Systems – II, Apr. <strong>2016</strong>.<br />
▓ “Metastablility in SAR ADCs,” IEEE Transactions on CAS – Part II: Express Briefs, online on Apr. <strong>2016</strong>.<br />
▓ “A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting,” IEEE Transactions on CAS – Part II: Express Briefs, online on Apr. <strong>2016</strong>.<br />
▓ “A Novel Field-Circuit FEM Modeling and Channel Gain Estimation for Galvanic Coupling Real IBC Measurements,” Sensors, Apr. <strong>2016</strong>.<br />
▓ “A 1.1 µW CMOS Smart Temperature Sensor with an Inaccuracy of ±0.2 o C (3σ) for Clinical Temperature Monitoring,” IEEE Sensors Journal, Apr. <strong>2016</strong>.<br />
▓ “Adaptive On/Off Delay-Compensated Active Rectifiers for Wireless Power Transfer Systems,” IEEE Journal of Solid-State Circuits, Mar. <strong>2016</strong>.<br />
▓ “Switching Loss Reduction Technique in Active Power Filters without Auxiliary Circuits,” IET Power Electronics, Mar. <strong>2016</strong>.<br />
▓ “Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC”, IEEE Transactions on Very Large Scale Integration Systems, Mar. <strong>2016</strong>.<br />
▓ “An NMOS-LDO Regulated Switched-Capacitor DC-DC Converter with Fast Response Adaptive Phase Digital Control,” IEEE Transactions on Power Electronics, Feb. <strong>2016</strong>.<br />
▓<br />
“Analysis of DC Link Operation Voltage of a Hybrid Railway Power Quality Conditioner and its PQ Compensation Capability in High Speed Co-Phase Traction Power Supply,” IEEE<br />
Transactions on Power Electronics, Feb. <strong>2016</strong>.<br />
▓ “A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC,” IEEE Journal of Solid-State Circuits, Feb. <strong>2016</strong>.<br />
▓ “Low-power CMOS Laser Doppler Imaging using Non-CDS Pixel Readout and 13.6-bit SAR ADC,” IEEE Transactions on Biomedical Circuits and Systems, Feb. <strong>2016</strong>.<br />
▓ “Sub-7-second genotyping of single-nucleotide polymorphism by high-resolution melting curve analysis on a thermal digital microfluidic device”, RSC Lab on a Chip, Jan. <strong>2016</strong>.<br />
▓<br />
▓<br />
“The dispersal analysis on basis construction of digital pre-distortion techniques for power amplifiers”, Springer Analog Integrated Circuits and Signal Processing, Jan.<br />
<strong>2016</strong>.<br />
“A 2-µm InGaP/GaAs Class-J Power Amplifier for Multi-Band LTE Achieving 35.8-dB Gain, 40.5% to 55.8% PAE and 28-dBm Linear Output Power”, IEEE Transactions on<br />
Microwave Theory and Techniques, Jan. <strong>2016</strong>.<br />
Conferences – 25 Papers<br />
Major IEEE solid-state circuits conferences:<br />
IEEE International Solid-State Circuits Conference (ISSCC) <strong>2016</strong>, San Francisco, CA, USA, Feb. <strong>2016</strong><br />
▓ “A Handheld 50pM-Sensitivity Micro-NMR CMOS Platform with B-Field Stabilization for Multi-Type Biological/Chemical Assays” [ISSCC Silkroad Award]<br />
▓ “A 0.003mm 2 1.7-to-3.5GHz Dual-Mode Time-Interleaved Ring-VCO Achieving 90-to-150kHz 1/f 3 Phase Noise Corner”<br />
▓ “A 0.038mm 2 SAW-less Multi-Band Transceiver Using an N-Path SC Gain Loop”<br />
▓ “A 2.4-GHz Digitally-Modulated Class-D Polar PA Using Power-Gating, Interactive AM-AM Modulation and a Dynamic Matching Network for Battery Lifetime Extension” [Student<br />
Research Preview]<br />
▓ “A 0.45V 147-to-375nW Hardware-Efficient Real-Time ECG Processor with Lossless-to-Lossy Data Compression for Wireless Healthcare Wearables” [Student Research Preview]<br />
▓ “A 12.5-ENOB 5MHz BW 4.2mW DT Multirate 2-1 Mash ΔΣ Modulator with Horizontal/Vertical Opamp Sharing in 65nm CMOS” [Student Research Preview]<br />
IEEE Asian Solid-State Circuits Conference (A-SSCC), Toyama, Japan, Nov. <strong>2016</strong><br />
▓ “A High DR Multi-Channel Stage-Shared Hybrid Front-End for Integrated Power Electronics Controller”<br />
IEEE European Solid-State Circuits Conference (ESSCIRC) <strong>2016</strong>, Lausanne, Switzerland, Sep. <strong>2016</strong><br />
▓ “An 8-bit 0.7-GS/s Single Channel Flash-SAR ADC in 65-nm CMOS Technology”<br />
▓ “A 12b 180MS/s 0.068mm 2 Pipelined-SAR ADC with Merged-residue DAC for Noise Reduction”<br />
▓ “A Digitally-Controlled 2-/3-Phase 6-Ratio Switched-Capacitor DC-DC Converter with Adaptive Ripple Reduction and Efficiency Improvements”<br />
Other IEEE conferences:<br />
International Symposium on Integrated Circuits (ISIC), Singapore, Dec. <strong>2016</strong><br />
▓ “A Mixed-Signal Sigma-Delta Interface circuit for Navigation System Applications”<br />
Lab on a Chip International Symposium: Droplet-based Microfluidics, HangZhou, China , Nov. <strong>2016</strong><br />
▓ “A Thermal Digital Microfluidic Device and Its Application to Disease Diagnostics”<br />
▓ “Digital Microfluidic System for LAMP-based Detection of Trypanosoma Brucei Using Molecular Beacon Probes”<br />
International Conference on Miniaturized Systems for Chemistry and Life Sciences (MicroTAS), Dublin, Ireland, Oct. <strong>2016</strong><br />
▓ “Digital Microfluidic Chip with Blade Structures for Precise Droplet Splitting”<br />
▓ “A Calibration-Free Thermal Digital Microfluidic Device for Ultrafast DNA Melting Curve Analysis”<br />
IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Jeju Province, Korea, Oct. <strong>2016</strong><br />
▓ “A Digital LDO with Transient Enhancement and Limit Cycle Oscillation Reduction”<br />
▓ “Digitally Assisted Low Dropout Regulator Design for Low Duty Cycle IoT Applications”<br />
IEEE International Ultrasonics Symposium (IUS), Tours, France, Sep. <strong>2016</strong><br />
▓ “Analytical model with lateral force for conventional CMUT membranes under large deflection using Von Kármán equations”<br />
IEEE Ph.D. Research In Micro-electronics and Electronics (PRIME), Lisbon, Portugal, Jun. <strong>2016</strong><br />
▓ “A High Resolution Multi-Bit Incremental Converter Insensitive to DAC Mismatch Error”<br />
IEEE International Symposium on Circuits and Systems (ISCAS), Quebec, Canada , May <strong>2016</strong><br />
▓ “A High-Q Spiral Inductor with Dual-Layer Patterned Floating Shield in a Class-B VCO Achieving a 190.5-dBc/Hz FoM”<br />
International Symposium on Microchemistry and Microsystems (ISMM <strong>2016</strong>), Hong Kong, China, May <strong>2016</strong><br />
▓ “Digital Microfluidic System with Intelligent Control for Ultrafast DNA Analysis”<br />
The Qatar Foundation Annual Research Conference <strong>2016</strong> (ARC'16), Doha, Qatar, Mar. <strong>2016</strong><br />
▓ “A Digitally Controlled Pseudo-Hysteretic Buck Converter for Low Power Biomedical Implants”<br />
21st Asia and South Pacific Design Automation Conference (ASP-DAC <strong>2016</strong>), Macao, China, Jan. <strong>2016</strong><br />
▓ “Sub-threshold VLSI-Logic Family Exploiting Unbalanced Pull-up/down Network, Logical Effort and Inverse-Narrow-Width Techniques”<br />
▓ “Sub-µW QRS Detection Processor Using Quadratic Spline Wavelet Transform and Maxima Modulus Pair Recognition for Power-Efficient Wireless Arrhythmia Monitoring”<br />
▓ “Time-Domain I/Q-LOFT Compensator Using a Simple Envelope Detector for a Sub-GHz IEEE 802.11af WLAN Transmitter”<br />
State Key Laboratory of Analog and Mixed-Signal VLSI / UM<br />
http://www.amsv.umac.mo