AMSV Newsletter 2016

State Key Lab of Analog and Mixed-Signal VLSI (SKL AMS-VLSI)
Newsletter
Motto: “Locally, from (World) Quality towards (National) Quantity”
座 右 銘 : 立 足 本 土 、 人 才 培 養 , 以 世 界 級 質 量 創 建 國 家 級 規 模
Year 6
No . 6
2016 Milestones
March 2017
Co-Funded by
Macao Science and Technology
Development Fund (FDCT)
Events
Prof. Rui Martins gave a talk on nurturing talents in Science as part of the University Lecture Series and the
Collegiate Learning Day, March 16, 2016.
State Key Laboratory of Analog and Mixed-Signal VLSI (SKL AMS-VLSI) received the Second and Third Prizes of
Natural Science Award in Technological Invention attributed by Macao Science and Technology Development
Fund (FDCT), October 12, 2016.
State Key Laboratory of Analog and Mixed-Signal VLSI (SKL AMS-VLSI) participated in the 10th Annual Meeting of
the Committee for China and Macao Cooperation in Science and Technology held in Changzhou, China, October 18,
2016.

State-of-the-Art Chips - Designed and Tested in 2016 (24 chips)
190 μm
580 μm
1 st Integrator
CLK
Generator
2 nd Integrator
0.35μm, 0.18μm, 65nm and for the first time 6 28nm chips
ISSCC 2017
A team of faculty members and students from the SKL AMS-VLSI and ECE/FST, University of Macau (UM) attended the IEEE 64 th
International Solid-State Circuits Conference (ISSCC) in February 2017, considered the ‘Chip Olympics’, the most competitive
conference in the world in the field of chip design.
This year SKL AMS-VLSI had a record acceptance of 6 papers/chips with the following titles, "A 5mW 7b 2.4GS/s 1-then-2b/cycle
SAR ADC with Background Offset Calibration", "An Output-Capacitor-Free Analog-Assisted Digital Low-Dropout Regulator with Tri
-Loop Control", "A Dual-Symmetrical-Output Switched-Capacitor Converter with Dynamic Power Cells and Minimized Cross Regulation for
Application Processors in 28nm CMOS", "A 1.7mm 2 Inductorless Fully Integrated Flipping-Capacitor Rectifier (FCR) for Piezoelectric Energy
Harvesting with 483% Power-Extraction Enhancement", "A Reconfigurable
Bidirectional Wireless Power Transceiver with Maximum-Current
Charging Mode and 58.6% Battery-to-Battery Efficiency", and "A 0.18V
382μW Bluetooth Low-Energy (BLE) Receiver with 1.33nW Sleep Power
for Energy-Harvesting Applications in 28nm CMOS". Besides, the SKLab
PhD students received 1 Pre-doctoral Achievement Award and presented
2 Student Research Previews.
Prof. Seng-Pan U and Prof. Pui-In Mak, deputy director and associate
director (research) of SKL AMS-VLSI , were invited to serve as members
of the Technical Program Committee of the ISSCC. In addition, Prof. U is
currently the China Representative of the ISSCC Technical Program
Committee, responsible for coordination of ISSCC activities in China.
Prof. Seng-Pan U became the 1st member
of Ministry of Education’s Science and
Technology Commission from Macao
Prof. Seng-Pan U and Prof. Pui-In Mak
participated in a China Press Conference
held in Shanghai as members of the TPC of
ISSCC 2017
UM’s first ‘Macao Fellow’ appointed visiting
scholar at Harvard and received IEEE
SSCS Predoctoral Achievement Award
Prof. Ben U Seng Pan from the University of
Macau (UM) Faculty of Science and Technology,
who is also the deputy director of SKL
AMS-VLSI, was appointed a member of the
Seventh Science and Technology Commission
of the Ministry of Education. Prof U is the
first and only scholar from Macao to be
appointed as member of such commission.
SKL AMS-VLSI student supervised by Prof.
Yan Lu won 2nd prize at National University
Integrated Circuit Design Contest (NUICDC)
Dr. Ka-Meng Lei, a lecturer under the
‘Macao Fellow’ program at the University of
Macau, will be a visiting scholar at the
Harvard University for a two-year term
starting in mid-2017. During his stay, Dr Lei
will explore a parallel nuclear magnetic
resonance (NMR) platform combining advanced
microfluidic, magnetic-sensing and
integrated circuits technologies, with the
aim of substantially reducing the cost and
time of NMR experiments.
4 New PhD Graduates
4. Jianyu Zhong, High-resolution Power-efficient SAR-
Type ADCs, Sep. 2016.
3. Ka-Meng Lei, Handheld CMOS-Based NMR Devices
for Biological/Chemical Diagnosis, Sep. 2016.
2. Tianlan Chen, Thermal Digital Microfluidic Devices
for Rapid DNA Analysis, Sep. 2016.
1. Chio-In Ieong, Low-Power CMOS Processors Design
for ECG QRS Wave Detection and Data Compression,
Mar. 2016.
A Book by Springer
A Book by IEEE CASS
http://ieee-cas.org/short-history-circuits-and-systems

Selected works from each research line
In IEEE ISSCC 2016 and JSSC 2016
A 0.003mm 2 1.7-to-3.5GHz Dual-Mode Time-Interleaved Ring-VCO
Achieving 90-to-150kHz 1/f 3 Phase Noise Corner
Jun Yin, Pui-In Mak, F. Maloberti and R. P. Martins
From Wireless research line
Motivation
Architecture
This work is a time-interleaved (TI) ring-VCO
(RVCO) exhibiting an improved figure-of-merit
(FoM) over a wide range of frequency offsets,
an extended tuning range and an inherent divided
output. Such features are achieved by substantially
increasing the number of delay stages
in a RVCO, such that the rich multi-phase suboutputs
can be combined time-interleavedly, to
generate a high-frequency output with a significantly
lowered 1/f 3 phase noise corner (f 1∕f3 ). The
critical block is the phase combiner, which features
a timing window to minimize the delay offset
and mismatch. A reconfigurable TI factor
extends the tuning range over the same range
of supply voltage (V DD ). The prototype is a 35-
stage dual-mode TI-RVCO occupying 0.003
mm 2 in 65-nm CMOS, and has a selectable TI
factor of 5 and 7. The measured f 1∕f3 is 150 kHz
at 3.47 GHz, which is 6.2x less than that of a
typical 5-stage RVCO, and is comparable with
those of the state-of-the-art LC-VCOs.
Result I
Result II

In IEEE ISSCC 2016 and JSSC 2017
A Handheld 50pM-Sensitivity Micro-NMR CMOS Platform with B-
Field Stabilization for Multi-Type Biological/Chemical Assays
Ka-Meng Lei, Hadi Heidari, Pui-In Mak, Man-Kay Law, F. Maloberti and R. P. Martins
From Wireless research line
Motivation
This is a micro-Nuclear Magnetic Resonance
(NMR) system compatible with multi-type biological/chemical
lab-on-a-chip assays. Unified in a
handheld scale, the system is capable to detect

Vcal,P
Vcal,N
Off_N
Off_P
R
R
Off_P
Off_N
CAL-LogicR
Off_P
6b
Enable
Off_P
Off_N
Vcal,P
Vcal,N
In IEEE ISSCC 2017
A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with Background Offset
Calibration
Chi-Hang Chan, Yan Zhu, Iok-Meng Ho, Wai-Hong Zhang, Seng-Pan U and R. P. Martins
From Data Conversion and Signal Processing research line
Motivation
Architecture
Wireless communication and Ethernet networks
system. Multi-bit SAR ADC can
achieve better energy efficiency than 1-b/
cycle at high speed.
Pre-charge operation not only leads to larger
power consumption but also makes the
performance of multi-bit SAR ADCs more
sensitive to PVT variation.
Pre-charge operation is merged with the
proposed switching scheme and a segmented
DAC arrangement.
Offset is calibrated in the background, embedded
in the ADC operation, and low
overhead.
Performance is stable across a wide range
of Voltage and Temperature variation.
CLk.Gen.
Ch.2
Φ S,main Common Clk
Self-time Ch.1
Φ S,ch1 S,ch2 Bootstrapped
loop
DAC1
VIP
Φ ST1,ch1
DAC1,P
QP 1
VIN
DAC1,N
QN 1
V DD ,
QP 2
G nd
QN 2
DAC2,P
QP 3
QN
DAC2,N
3
DAC2
Register w/ Mux
Φ S,ch1
Φ S,main
1b+background
Φ ST1,ch1 offset Cal. 2b 2b 2b
Background Offset Calibration
Decoder and Multiplexer
7b
Implementation
Verification
SNDR (dB)
SNDR (dB)
SNDR (dB)
40
39
38
37
36
35
40
39.5
39
38.5
38
40
39.5
39
38.5
38
Chip #3
fs = 2.4 GHz
fin = 10.1 MHz
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
Chip #3
fs = 2.4 GHz
fin = 10.1 MHz
Chip #3
fs = 2 GHz
fin = 10.1 MHz
0.58 0.6 0.62 0.64 0.66 0.68
Input Common-mode (V)
0.84 0.86 0.88 0.9 0.92 0.94 0.96
Supply Voltage (V)
FoM@Nyquist
(fJ/conv.-step)
100
MCAL,P
MCAL,N
CAL_enable
D QP
Dff1
CLK
CAL_enable
D
QP
Dff2
CLK
MUX
DAC
Counter
Flip
Detection
7b
design >8x
improved
CAL_enable
fS ≥1GS/s,

An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-
SAR ADC in 65 nm CMOS
Yan Zhu, Chi-Hang Chan, Seng-Pan U and R. P. Martins
In IEEE JSSC 2016
From Data Conversion and Signal Processing research line
Motivation
Architecture
Software-defined Radio application.
Multiple shared elements among the TI
channel optimize the area.
Offset and gain calibrations are fully integrated
on-chip and achieve small area.
Error-decision-correction logic enhances the
robustness of the SA logic.
Hybrid pipeline, flash and SAR architecture
optimize the energy efficiency.
Implementation
Verification

ISSCC / 2002 - 2017 — 21 papers/chips
ISSCC 2017
21
ISSCC 2017
CMOS
0.18 μm
CMOS
28 nm
A 1.7mm 2 Inductor-less Fully-Integrated Capacitive-Flip
Rectifier (CFR) for Piezoelectric Energy Harvesting with
483% Power Extraction Improvement
20
A 0.18V 382µW Bluetooth Low-Energy (BLE) Receiver
with 1.33nW Sleep Power for Energy-Harvesting
Applications in 28nm CMOS
ISSCC 2017
19
ISSCC 2017
CMOS
28 nm
CMOS
28 nm
A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with
Background Offset Calibration
18
A Dual-Symmetrical-Output Switched-Capacitor Converter
with Dynamic Power Cells and Minimized Cross
Regulation for Application Processors in 28nm CMOS
ISSCC 2017
17
ISSCC 2017
CMOS
65 nm
CMOS
0.35 μm
An Output-Capacitor-Free Analog-Assisted Digital
Low-Dropout Regulator with Tri-Loop Control
16
A Reconfigurable Bidirectional Wireless Power
Transceiver with Maximum-Current Charging Mode
and 58.6% Battery-to-Battery Efficiency
ISSCC 2016
15
ISSCC 2016
CMOS
0.18 μm
CMOS
65 nm
A Handheld 50pM-Sensitivity Micro-NMR CMOS
Platform with B-Field Stabilization for Multi-Type
Biological/Chemical Assays
14
A 0.003mm 2 1.7-to-3.5GHz Dual-Mode Time-Interleaved
Ring-VCO Achieving 90-to-150kHz 1/f 3 Phase Noise
Corner
ISSCC 2016
13
ISSCC 2015
CMOS
65 nm
CMOS
65 nm
A 0.038mm 2 SAW-less Multi-Band Transceiver Using an
N-Path SC Gain Loop
12
A 0.028mm 2 11mW Single-Mixing Blocker-Tolerant
Receiver with Double-RF N-Path Filtering, S11 Centering,
+13dBm OB-IIP3 and 1.5-to-2.9dB NF

ISSCC / 2002 - 2017 — 21 papers/chips
ISSCC 2015
11
ISSCC 2015
CMOS
65 nm
CMOS
65 nm
A 123-Phase DC-DC Converter-Ring with Fast-DVS for
Microprocessors
10
A 2-/3-Phase Fully Integrated Switched-Capacitor DC-DC
Converter in Bulk CMOS for Energy-Efficient Digital
Circuits with 14% Efficiency Improvement
9
ISSCC 2015 ISSCC 2014
CMOS
65 nm
CMOS
65 nm
A 5.5mW 6b 5GS/s 4×-Interleaved 3b/cycle SAR ADC in
65nm CMOS
8
A 0.5V 1.15mW 0.2mm 2 Sub-GHz ZigBee Receiver
Supporting 433/860/915/960MHz ISM Bands with
Zero External Components
ISSCC 2014
7
ISSCC 2014
CMOS
65 nm
CMOS
0.18 μm
An RF-to-BB-Current-Reuse Wideband Receiver
with Parallel N-Path Active/Passive Mixers and
a Single-MOS Pole-Zero LPF
6
A 0.0013mm 2 3.6μW Nested-Current-Mirror Single-Stage
Amplifier Driving 0.15-to-15nF Capacitive Loads
with >62° Phase Margin
ISSCC 2013
5
ISSCC 2012
CMOS
65 nm
CMOS
0.35 μm
A 1.7mW 0.22mm 2 2.4GHz ZigBee RX Exploiting a
Current-Reuse Blixer+Hybrid Filter Topology
in 65nm CMOS
4
A 0.016mm 2 144µW Three-Stage Amplifier Capable of
Driving 1-to-15nF Capacitive Load with >0.95MHz GBW
ISSCC 2011
2,3
ISSCC 2002
CMOS
65 nm
CMOS
0.35 μm
A 0.46mm 2 4-dB NF
Unified Receiver
Front-End for
Full-Band Mobile TV
A 0.024mm 2 8-bit 400
MS/s SAR ADC with
2-bit per Cycle and
Resistive DAC
1
A 2.5V 57MHz 15-tap SC Bandpass Interpolating Filter
with 320MHz Output Sampling Rate in 0.35μm CMOS

ISSCC Results for Academia in China (2011-2017)
By First Affiliation of
First Author
2011 2012 2013 2014 2015 2016 2017 Total
University of Macau 2 1 1 3 2 3 6 18
Hong Kong University of
Science and Technology
1 1 2 3 4 3 4 18
Fudan University 1 1 2 1 5
Tsinghua University 1 2 1 4
Institute of Microelectronics
Chinese Academy of Science
1 1 1 3
Awards and Student Research Preview in 2011 - 2017:
2 ISSCC Silk-Road Award
4 SSCS Pre-Doctoral Achievement Award
9 ISSCC Student Research Preview
Industry/University/Institute Worldwide (2017)
(First Author Affiliation)
▓ Industry: 7
◆MediaTek (9), IBM (5), Samsung Electronics (5), Intel (5),
◆TSMC (3), Analog Devices (3), Xilinx (3).
▓ University: 16
◆Univ. of Michigan (11), Columbia Univ. (6), Delft Univ. (6),
◆KAIST (6), U. Macau (6), Univ. of Texas @ Dallas (6),
◆Georgia Inst. of Tech. (5), Pohang U. of Sci. & Tech. (5),
◆UC San Diego (5), HK U. of S&T (4), MIT (4), UCLA (4),
◆National Chiao Tung Univ.(3), Princeton Univ.(3),
◆Stanford Univ. (3), Univ. of Illinois (3).
▓ Institute: 1
◆IMEC (4).

ISSCC - 15 PhD Students Awards and Research Previews
ISSCC
Silkroad Award
Ka-Meng Lei
(2017)
ISSCC
Silkroad Award
He Gong Wei
(2011)
"A Handheld 50pM-Sensitivity Micro-NMR CMOS Platform with
B-Field Stabilization for Multi-Type Biological/Chemical Assays"
“A 0.024mm 2 8-bit 400 MS/s SAR ADC with 2-bit per Cycle and
Resistive DAC in 65 nm CMOS”
SSCC Pre-Doctoral Achievement Award (2016-2017) (Ka-Meng Lei)
SSCC Pre-Doctoral Achievement Award (2013-2014) (Zushu Yan)
SSCC Pre-Doctoral Achievement Award (2014-2015) (Zhicheng Lin)
SSCC Pre-Doctoral Achievement Award (2014-2015) (Chi Hang Chan)
Student Research
Preview 2017
Tan-Tan Zhang
Student Research Preview 2017 (Yang Jiang)
Student Research Preview 2016 (Liang Qi)
Student Research Preview 2016 (Chio-In Ieong)
Student Research Preview 2016 (Wei Han Yu)
Student Research Preview 2015 (Ka-Meng Lei)
Student Research
Preview 2015
Jianyu Zhong
Student Research
Preview 2014
Yaohua Zhao
Student Research Preview 2013 (Zushu Yan)

Design of a Collapse-Mode CMUT With an Embossed Membrane for
Improving Output Pressure
Yuanyu Yu, Sio Hang Pun, Peng Un Mak, Ching-Hsiang Cheng, Jiujiang Wang, Pui-In Mak, and
Mang I Vai
From Biomedical research line
In IEEE Transactions on Ultrasonics, Ferroelectrics,
and Frequency Control - TUFFC 2016
Motivation
Architecture
Capacitive micromachined ultrasonic transducers
(CMUTs) have emerged as a competitive
alternative to piezoelectric ultrasonic transducers,
especially in medical ultrasound imaging
and therapeutic ultrasound applications, which
require high output pressure. However, when
compared with piezoelectric ultrasonic transducers,
the output pressure capability of CMUTs
needs still to be improved.
In this work, a novel structure is proposed by
forming an embossed vibrating membrane on a
CMUT cell operating in the collapse mode to
increase the maximum output pressure. By using
a beam model in undamped conditions and
finite-element analysis simulations, the proposed
embossed structure showed improvement
on the maximum output pressure of the
CMUT cell when the embossed pattern was
placed on the estimated location of the peak deflection.
(a)
(b)
(a) 3-D outlook view and (b) 2-D axisymmetric cross-sectional view of
the proposed collapse-mode CMUT with an embossed membrane.
2-D axisymmetric view of the dual embossed patterns located
symmetrically in the vibrating center.
Principle
Result
Based on the analysis of the simply supported beam model,
X = 0.481L is the optimal position for the embossed pattern.
For a collapse-mode CMUT, the output pressure is improved
and the center frequency is reduced with this embossed pattern.
(a)
(b)
(a) Output pressure comparison between the uniform membrane and
the embossed membrane CMUT in the collapse mode. (b) Thinning
embossed membrane to tune center frequency.
Relationship between pressure improvement and center frequency
shift for various embossed positions.

A Dual-Output Wireless Power Transfer System with Active Rectifier
and 3-Level Operation
Yan Lu, Mo Huang, Lin Cheng, Wing-Hung Ki, Seng-Pan U, and R. P. Martins
In IEEE TPEL 2017
[Accepted in 2016]
From Integrated Power research line
Motivation
Architecture
Wireless power transfer (WPT) systems for
batteryless and wirelessly charged devices
have attracted enormous attention in recent
years.
The 3-level DC-DC and the SIMO techniques are naturally
merged with a 2X rectifier (voltage doubler) which readily
has two DC supplies (three levels, including GND).
To cut the last wire of the electronic devices,
this work was designed for the wirelessly
powered flash memory drives that
need multiple supply levels with a total
power consumption of sub-1W.
For miniature size and small output ripple,
multi-level operation and single-inductor
multiple-output techniques are employed in
this prototype.
Implementation
Verification
The proposed WPT system was fabricated in a 0.35μm
CMOS process, and measured with low-cost PCB coils.
Measured voltage and inductor current waveforms of the
WPT receiver.

In RSC Lab on a Chip 2016
Sub-7-Second Genotyping of Single-Nucleotide Polymorphism by High-
Resolution Melting Curve Analysis on a Thermal Digital Microfluidic Device
Tianlan Chen, Yanwei Jia, Cheng Dong, Jie Gao, Pui-In Mak, and R. P. Martins
From Multidisciplinary Research Area (Microfluidic)
Motivation
Architecture I
We developed a thermal digital microfluidic
(T-DMF) device enabling ultrafast DNA melting
curve analysis (MCA). Within 7 seconds,
the T-DMF device succeeded in differentiating
a melting point difference down to 1.6 °C
with a variation of 0.3 °C in a tiny droplet
sample (1.2 μL), which was 300 times faster
and with 20 times less sample spending
than the standard MCA (35 minutes, 25 μL)
run in a commercial qPCR machine. Such a
performance makes it possible for a rapid
discrimination of single-nucleotide mutation
relevant to prompt clinical decision-making.
Capable of thermally modulating DNA samples
with ultrafast MCA, this T-DMF device
has the potential for a wide variety of life science
analyses, especially for disease diagnosis
and prognosis.
Architecture II
Result

Technology Transfer Office and Starting of Commercialization Activity
Technology Transfer Office
In order to enhance the technology transfer supporting infrastructure, SKL AMS-VLSI Technology
Transfer Office (TTO) was established in Feb 2016 led by Dr. Yong-Hsiang Hsieh (Alex) born in Macao.
Dr. Alex Hsieh received the Ph.D. degree in Department of Electrical Engineering, National Taiwan
University and has over 15 years extensive microelectronics industry experience in Taiwan and China.
Partnership with Companies and Applied Research Institutes
In the year of 2016, the startup year of TTO, it has made tremendous efforts on establishing connection with industrial partners. The active interactions
were with regional government fund IC incubation center (e.g., National IC Design ShenZhen industrial Centre and ZhuHai South IC Design Service
Center), with research institutes (e.g., Institute of Microelectronics of Chinese Academy of Sciences and Hong Kong Applied Sciences and Technology
Research Institute), and the leading fabless IC companies in China.(e.g., Hisilicon, Allwinner, etc.)
A delegation led by Dr. Mei-Kei Ieong, CTO of Hong Kong Applied
Science and Technology Research Institute, visited SKL AMS-VLSI to
discuss potential collaboration.
Visit by Mr. Hai-Yang Wang, Director of Huawei, China.
US Patents Granted in 2016
1. “Ultra-Low-Voltage Current-Reuse Voltage-Controlled Oscillator and Transconductance-Capacitor Filter,” US Patent, No. 9,444,431, Sep. 2016.
2. “Gain-Boosted N-Path Bandpass Filter,” US Patent, No. 9,374,063, Jun. 2016.
3. “An RF-to-BB-Current-Reuse Wideband Receiver with Parallel N-Path Active/Passive Mixers,” US Patent, No. 9,356,636, May 2016.
4. “IF-Noise-Shaping Transistorized Current-Mode Lowpass Filter Utilizing Cross-Coupled Transistors,” US Patent, No. 9,306,540, Apr. 2016.
5. “Non-recursive Digital Calibration for Joint-elimination of Transmitter and Receiver I/Q Imbalances with Minimized Add-on Hardware,” US Patent,
No. 9,276,798, Mar. 2016.
6. “RF-to-BB-Current-Reuse Wideband Receiver with a Single-MOS Pole-Zero LPF,” US Patent, No. 9,270,314, Feb. 2016.
7. “ZigBee Receiver Exploiting an RF-to-BB Current-Reuse Blixer and Hybrid Filter Topology,” US Patent, No. 9,237,055, Jan. 2016.
Industrial-Academic Collaborative Projects
Selected accomplished project: An ultra-low power high speed ADC collaborative project with Hisilicon, the China #1 fabless IC design company, has
successfully closed in 2016.
Selected on-going projects: Two collaborative projects with Allwinner, a Pearl River Delta area local listed company and one project under negotiation
with Synopsys, the world’s leading company in silicon IP.
Possible Spin-off Projects
SKL AMS-VLSI explores DNA kinetic limitation
on microchips with the duration of the DNA
melting curve analysis shortened to 7 seconds.
CBBio under SKL AMS-VLSI achieves new
breakthrough in biochip research.
SKL AMS-VLSI developed a T-DMF device
enabling ultrafast DNA melting curve analysis.

Events and Visits
Visits
Visit by Du Qinglin, Vice-Chairman of the Chinese People's
Political Consultative Conference.
Visit by Du Zhanyuan, Vice-Minister, Ministry of Education.
Visit by Prof. António Cunha, Rector of University of Minho,
President of the Council of Rectors of Portugal.
Distinguished Lectures and Workshops
Visit by a Delegation from The Institute for Systems and Computer
Engineering, Technology and Science (INESC-TEC), Portugal.
4-Day Workshop in Advanced IC Design by
Prof. Willy Sansen,
IEEE Life Fellow, Professor at the
Catholic University of Leuven, in Belgium
Distinguished Workshop
“From Flatland Electrodynamics
to Molecular
Spectroscope and Neurotechnology
with Solid-
State Chips” by
Prof. Donhee Ham,
Gordon McKay Prof.,
Harvard University
Distinguished Lecture
"Innovative Entrepreneurship
and Youth
Development" by
Dr. Carter Tseng,
Chairman & CEO of
Little Dragon Foundation
, Director USA
“Committee100”
2-Day Distinguished Workshop
with INESCTEC,
Porto, Portugal, by
Prof. Vítor Grade Tavares,
Senior Researcher,
INESC-TEC and other
INESC-TEC related
members
New Academic Joined SKL AMS-VLSI
SKL AMS-VLSI New Cleanroom for Biochip
Research and Commercialization
Lecturer (Macao Fellow)
Ka-Meng Lei received the B.Sc. degree in electrical
and electronics engineering and Ph.D.
degree from the University of Macau (UM),
Macao, China, in 2012 and 2016, respectively.
He is currently a lecturer (Macao Fellow) at SKL
AMS-VLSI and will visit Harvard University as a
Visiting Researcher for 2 years.
Research Interests: Microfluidics, Mixed-Signal integrated circuits
design, Wireless integrated circuits design.

▓
Book
“Ultra-Low-Power and Ultra-Low-Cost Short-Range Wireless Receivers in Nanoscale CMOS”, ISBN 978-3-319-21524-2, Series of Analog Circuits and Signal Processing
(ACSP), Springer Press, USA, Jan. 2016.
SCI Journals – 38 Papers (3 in 2017)
▓ “A Handheld High Sensitivity Micro-NMR CMOS Platform with B-Field Stabilization for Multi-Type Biological/Chemical Assays,” IEEE Journal of Solid-State Circuits, Jan. 2017.
[Invited Paper]
▓ “Design of a Thyristor Controlled LC Compensator for Wind Farm Dynamic Reactive Power Compensation in Smart Grid,” IEEE Transactions on Smart Grid, Jan. 2017.
▓ “Active-Passive ΔΣ Modulator for High-Resolution and Low-Power Applications,” IEEE Transactions on Very Large Scale Integration Systems, Jan. 2017.
▓ “A Time-Interleaved Ring-VCO with Reduced 1/f 3 Phase Noise Corner, Extended Tuning Range and Inherent Divided Output,” IEEE Journal of Solid-State Circuits, Dec. 2016.
▓ “Wireless Power Transfer System Architectures for Portable or Implantable Applications,” Energies, Dec. 2016.
▓ “An 18-Gb/s Fully Integrated Optical Receiver with Adaptive Cascaded Equalizer,” IEEE Journal of Selected Topics in Quantum Electronics, vol. 22, no. 6, Nov.-Dec. 2016.
▓ “A μNMR CMOS Transceiver Using a Butterfly-Coil Input for Integration with a Digital Microfluidic Device inside a Portable Magnet,” IEEE Journal of Solid-State Circuits, Oct.
2016. [Invited Paper]
▓ “Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial V cm-Based Switching,” IEEE Transactions on Very Large Scale Integration Systems, online on Oct.
2016.
▓ “Wide Input Range Supply Voltage Tolerant Capacitive Sensor Readout Using On-Chip Solar Cell,” World Scientific Journal of Circuits, Systems, and Computers, Oct.
▓
2016.
“Analysis, Design and Implementation of a Quasi-Proportional-Resonant Controller for Multi-Functional Capacitive-Coupling Grid-Connected Inverter,” IEEE Transactions on
Industry Application, Sep. 2016.
▓ “CMOS Biosensors for In Vitro Diagnosis - Transducing Mechanisms and Applications,” RSC Lab on a Chip, Sep. 2016.
▓ “Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators,” IEEE Transactions on CAS – Part II: Express Briefs, Sep. 2016.
▓ “Improved Analytical Modeling of Membrane Large Deflection with Lateral Force for the Underwater CMUT Based on Von Kármán Equations,” IEEE Sensors Journal, Sep. 2016.
▓ “ProtPOS: a Python Package for the Prediction of Protein Preferred Orientation on a Surface,” Oxford University Press - Bioinformatics, Aug. 2016.
▓ “A 312 ps Response-Time LDO with Enhanced Super Source Follower in 28 nm CMOS,” IET Electronics Letters, Aug. 2016.
▓ “A Multi-Channel Power-Supply Modulated Micro-Stimulator With Energy Recycling,” IEEE Design and Test, Aug. 2016.
▓ “A 4x Time-Domain Interpolation 6-bit 3.4 GS/s 12.6 mW Flash ADC in 65 nm CMOS”, Journal of Semiconductor Technology and Science (South Korea), Aug. 2016.
▓ “A Fully-Integrated Digital LDO with Coarse-Fine-Tuning and Burst-Mode Operation,” IEEE Transactions on CAS – Part II: Express Briefs, Jul. 2016.
▓ “Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC,” IEEE Transactions on Very Large Scale Integration Systems, Jul. 2016.
▓ “Development of a Calibration Strip for Immunochromatographic Assay Detection Systems,” Sensors, Jul. 2016.
▓ “A Hybrid STATCOM with Wide Compensation Range and Low DC-Link Voltage,” IEEE Transactions on Industrial Electronics, Jun. 2016.
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“Design of a Collapse-Mode CMUT with an Embossed Membrane for Improving Output Pressure,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency
Control, Jun. 2016.
“Joint-Digital-Predistortion for Wireless Transmitter's I/Q Imbalance and PA Nonlinearities Using an Asymmetrical Complexity-Reduced Volterra Series Model,” Springer Analog
Integrated Circuits and Signal Processing, Apr. 2016.
“A 2 µW 45 nV/√Hz Readout Frontend With Multiple Chopping, Active-High-Pass Ripple Reduction Loop and Pseudo-Feedback DC Servo Loop,” IEEE Transactions on Circuits
and Systems – II, Apr. 2016.
▓ “Metastablility in SAR ADCs,” IEEE Transactions on CAS – Part II: Express Briefs, online on Apr. 2016.
▓ “A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting,” IEEE Transactions on CAS – Part II: Express Briefs, online on Apr. 2016.
▓ “A Novel Field-Circuit FEM Modeling and Channel Gain Estimation for Galvanic Coupling Real IBC Measurements,” Sensors, Apr. 2016.
▓ “A 1.1 µW CMOS Smart Temperature Sensor with an Inaccuracy of ±0.2 o C (3σ) for Clinical Temperature Monitoring,” IEEE Sensors Journal, Apr. 2016.
▓ “Adaptive On/Off Delay-Compensated Active Rectifiers for Wireless Power Transfer Systems,” IEEE Journal of Solid-State Circuits, Mar. 2016.
▓ “Switching Loss Reduction Technique in Active Power Filters without Auxiliary Circuits,” IET Power Electronics, Mar. 2016.
▓ “Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC”, IEEE Transactions on Very Large Scale Integration Systems, Mar. 2016.
▓ “An NMOS-LDO Regulated Switched-Capacitor DC-DC Converter with Fast Response Adaptive Phase Digital Control,” IEEE Transactions on Power Electronics, Feb. 2016.
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“Analysis of DC Link Operation Voltage of a Hybrid Railway Power Quality Conditioner and its PQ Compensation Capability in High Speed Co-Phase Traction Power Supply,” IEEE
Transactions on Power Electronics, Feb. 2016.
▓ “A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC,” IEEE Journal of Solid-State Circuits, Feb. 2016.
▓ “Low-power CMOS Laser Doppler Imaging using Non-CDS Pixel Readout and 13.6-bit SAR ADC,” IEEE Transactions on Biomedical Circuits and Systems, Feb. 2016.
▓ “Sub-7-second genotyping of single-nucleotide polymorphism by high-resolution melting curve analysis on a thermal digital microfluidic device”, RSC Lab on a Chip, Jan. 2016.
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“The dispersal analysis on basis construction of digital pre-distortion techniques for power amplifiers”, Springer Analog Integrated Circuits and Signal Processing, Jan.
2016.
“A 2-µm InGaP/GaAs Class-J Power Amplifier for Multi-Band LTE Achieving 35.8-dB Gain, 40.5% to 55.8% PAE and 28-dBm Linear Output Power”, IEEE Transactions on
Microwave Theory and Techniques, Jan. 2016.
Conferences – 25 Papers
Major IEEE solid-state circuits conferences:
IEEE International Solid-State Circuits Conference (ISSCC) 2016, San Francisco, CA, USA, Feb. 2016
▓ “A Handheld 50pM-Sensitivity Micro-NMR CMOS Platform with B-Field Stabilization for Multi-Type Biological/Chemical Assays” [ISSCC Silkroad Award]
▓ “A 0.003mm 2 1.7-to-3.5GHz Dual-Mode Time-Interleaved Ring-VCO Achieving 90-to-150kHz 1/f 3 Phase Noise Corner”
▓ “A 0.038mm 2 SAW-less Multi-Band Transceiver Using an N-Path SC Gain Loop”
▓ “A 2.4-GHz Digitally-Modulated Class-D Polar PA Using Power-Gating, Interactive AM-AM Modulation and a Dynamic Matching Network for Battery Lifetime Extension” [Student
Research Preview]
▓ “A 0.45V 147-to-375nW Hardware-Efficient Real-Time ECG Processor with Lossless-to-Lossy Data Compression for Wireless Healthcare Wearables” [Student Research Preview]
▓ “A 12.5-ENOB 5MHz BW 4.2mW DT Multirate 2-1 Mash ΔΣ Modulator with Horizontal/Vertical Opamp Sharing in 65nm CMOS” [Student Research Preview]
IEEE Asian Solid-State Circuits Conference (A-SSCC), Toyama, Japan, Nov. 2016
▓ “A High DR Multi-Channel Stage-Shared Hybrid Front-End for Integrated Power Electronics Controller”
IEEE European Solid-State Circuits Conference (ESSCIRC) 2016, Lausanne, Switzerland, Sep. 2016
▓ “An 8-bit 0.7-GS/s Single Channel Flash-SAR ADC in 65-nm CMOS Technology”
▓ “A 12b 180MS/s 0.068mm 2 Pipelined-SAR ADC with Merged-residue DAC for Noise Reduction”
▓ “A Digitally-Controlled 2-/3-Phase 6-Ratio Switched-Capacitor DC-DC Converter with Adaptive Ripple Reduction and Efficiency Improvements”
Other IEEE conferences:
International Symposium on Integrated Circuits (ISIC), Singapore, Dec. 2016
▓ “A Mixed-Signal Sigma-Delta Interface circuit for Navigation System Applications”
Lab on a Chip International Symposium: Droplet-based Microfluidics, HangZhou, China , Nov. 2016
▓ “A Thermal Digital Microfluidic Device and Its Application to Disease Diagnostics”
▓ “Digital Microfluidic System for LAMP-based Detection of Trypanosoma Brucei Using Molecular Beacon Probes”
International Conference on Miniaturized Systems for Chemistry and Life Sciences (MicroTAS), Dublin, Ireland, Oct. 2016
▓ “Digital Microfluidic Chip with Blade Structures for Precise Droplet Splitting”
▓ “A Calibration-Free Thermal Digital Microfluidic Device for Ultrafast DNA Melting Curve Analysis”
IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Jeju Province, Korea, Oct. 2016
▓ “A Digital LDO with Transient Enhancement and Limit Cycle Oscillation Reduction”
▓ “Digitally Assisted Low Dropout Regulator Design for Low Duty Cycle IoT Applications”
IEEE International Ultrasonics Symposium (IUS), Tours, France, Sep. 2016
▓ “Analytical model with lateral force for conventional CMUT membranes under large deflection using Von Kármán equations”
IEEE Ph.D. Research In Micro-electronics and Electronics (PRIME), Lisbon, Portugal, Jun. 2016
▓ “A High Resolution Multi-Bit Incremental Converter Insensitive to DAC Mismatch Error”
IEEE International Symposium on Circuits and Systems (ISCAS), Quebec, Canada , May 2016
▓ “A High-Q Spiral Inductor with Dual-Layer Patterned Floating Shield in a Class-B VCO Achieving a 190.5-dBc/Hz FoM”
International Symposium on Microchemistry and Microsystems (ISMM 2016), Hong Kong, China, May 2016
▓ “Digital Microfluidic System with Intelligent Control for Ultrafast DNA Analysis”
The Qatar Foundation Annual Research Conference 2016 (ARC'16), Doha, Qatar, Mar. 2016
▓ “A Digitally Controlled Pseudo-Hysteretic Buck Converter for Low Power Biomedical Implants”
21st Asia and South Pacific Design Automation Conference (ASP-DAC 2016), Macao, China, Jan. 2016
▓ “Sub-threshold VLSI-Logic Family Exploiting Unbalanced Pull-up/down Network, Logical Effort and Inverse-Narrow-Width Techniques”
▓ “Sub-µW QRS Detection Processor Using Quadratic Spline Wavelet Transform and Maxima Modulus Pair Recognition for Power-Efficient Wireless Arrhythmia Monitoring”
▓ “Time-Domain I/Q-LOFT Compensator Using a Simple Envelope Detector for a Sub-GHz IEEE 802.11af WLAN Transmitter”
State Key Laboratory of Analog and Mixed-Signal VLSI / UM
http://www.amsv.umac.mo